* [PATCH RESEND v7 0/9] target/arm: Allow CONFIG_TCG=n builds
@ 2023-02-28 19:26 Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 1/9] target/arm: Move cortex sysregs into a separate file Fabiano Rosas
` (8 more replies)
0 siblings, 9 replies; 25+ messages in thread
From: Fabiano Rosas @ 2023-02-28 19:26 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
Resending with the remaining patches now that arm next was merged.
CI run: https://gitlab.com/farosas/qemu/-/pipelines/791478895
v7:
https://lore.kernel.org/r/20230223130841.25916-1-farosas@suse.de
Changes since v6:
Now using the same feature set for -cpu max for both qtests and
TCG. This requires a slightly awkward code movement to expose
aa32_max_features to non-tcg code, but we gain by not having a
different environment for the tests.
Also applied Richard's suggestion of creating a new cortex-regs.c
file.
CI run: https://gitlab.com/farosas/qemu/-/pipelines/786195517
v6:
https://lore.kernel.org/r/20230217201150.22032-1-farosas@suse.de
v5 resend:
https://lore.kernel.org/r/20230213202927.28992-1-farosas@suse.de
v5:
https://lore.kernel.org/r/20230120184825.31626-1-farosas@suse.de
v4:
https://lore.kernel.org/r/20230119135424.5417-1-farosas@suse.de
v3:
https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de
v2:
https://lore.kernel.org/r/20230109224232.11661-1-farosas@suse.de
v1:
https://lore.kernel.org/r/20230104215835.24692-1-farosas@suse.de
Claudio Fontana (1):
target/arm: move cpu_tcg to tcg/cpu32.c
Fabiano Rosas (7):
target/arm: Move cortex sysregs into a separate file
target/arm: Move 64-bit TCG CPUs into tcg/
target/arm: Move aa32_max_features out of cpu_tcg.c
tests/avocado: Pass parameters to migration test
arm/Kconfig: Always select SEMIHOSTING when TCG is present
arm/Kconfig: Do not build TCG-only boards on a KVM-only build
tests/qtest: Fix tests when no KVM or TCG are present
Philippe Mathieu-Daudé (1):
gitlab-ci: Check building KVM-only aarch64 target
.gitlab-ci.d/crossbuilds.yml | 11 +
.../custom-runners/ubuntu-22.04-aarch64.yml | 4 -
configs/devices/aarch64-softmmu/default.mak | 4 -
configs/devices/arm-softmmu/default.mak | 39 --
hw/arm/Kconfig | 43 +-
hw/arm/virt.c | 6 +-
target/arm/Kconfig | 7 +
target/arm/cortex-regs.c | 69 +++
target/arm/cpregs.h | 6 +
target/arm/cpu.c | 69 +++
target/arm/cpu64.c | 399 +---------------
target/arm/internals.h | 7 +-
target/arm/meson.build | 2 +-
target/arm/{cpu_tcg.c => tcg/cpu32.c} | 141 +-----
target/arm/tcg/cpu64.c | 438 ++++++++++++++++++
target/arm/tcg/meson.build | 2 +
tests/avocado/migration.py | 83 +++-
tests/qtest/arm-cpu-features.c | 12 +-
tests/qtest/bios-tables-test.c | 4 +
tests/qtest/boot-serial-test.c | 10 +
tests/qtest/migration-test.c | 5 +
tests/qtest/pxe-test.c | 6 +
tests/qtest/vmgenid-test.c | 6 +
23 files changed, 772 insertions(+), 601 deletions(-)
create mode 100644 target/arm/cortex-regs.c
rename target/arm/{cpu_tcg.c => tcg/cpu32.c} (87%)
create mode 100644 target/arm/tcg/cpu64.c
--
2.35.3
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH RESEND v7 1/9] target/arm: Move cortex sysregs into a separate file
2023-02-28 19:26 [PATCH RESEND v7 0/9] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
@ 2023-02-28 19:26 ` Fabiano Rosas
2023-03-01 1:21 ` Richard Henderson
2023-02-28 19:26 ` [PATCH RESEND v7 2/9] target/arm: Move 64-bit TCG CPUs into tcg/ Fabiano Rosas
` (7 subsequent siblings)
8 siblings, 1 reply; 25+ messages in thread
From: Fabiano Rosas @ 2023-02-28 19:26 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
The file cpu_tcg.c is about to be moved into the tcg/ directory, so
move the register definitions into a new file.
Also move the function declaration to the more appropriate cpregs.h.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
target/arm/cortex-regs.c | 69 ++++++++++++++++++++++++++++++++++++++++
target/arm/cpregs.h | 6 ++++
target/arm/cpu64.c | 1 +
target/arm/cpu_tcg.c | 59 ----------------------------------
target/arm/internals.h | 6 ----
target/arm/meson.build | 1 +
6 files changed, 77 insertions(+), 65 deletions(-)
create mode 100644 target/arm/cortex-regs.c
diff --git a/target/arm/cortex-regs.c b/target/arm/cortex-regs.c
new file mode 100644
index 0000000000..17708480e7
--- /dev/null
+++ b/target/arm/cortex-regs.c
@@ -0,0 +1,69 @@
+/*
+ * ARM Cortex-A registers
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpregs.h"
+
+
+static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ ARMCPU *cpu = env_archcpu(env);
+
+ /* Number of cores is in [25:24]; otherwise we RAZ */
+ return (cpu->core_count - 1) << 24;
+}
+
+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
+ { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
+ .access = PL1_RW, .readfn = l2ctlr_read,
+ .writefn = arm_cp_write_ignore },
+ { .name = "L2CTLR",
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
+ .access = PL1_RW, .readfn = l2ctlr_read,
+ .writefn = arm_cp_write_ignore },
+ { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "L2ECTLR",
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUACTLR",
+ .cp = 15, .opc1 = 0, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUECTLR",
+ .cp = 15, .opc1 = 1, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUMERRSR",
+ .cp = 15, .opc1 = 2, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "L2MERRSR",
+ .cp = 15, .opc1 = 3, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+};
+
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
+{
+ define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+}
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 1ee64e99de..b04d344a9f 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -1071,4 +1071,10 @@ static inline bool arm_cpreg_in_idspace(const ARMCPRegInfo *ri)
ri->crn, ri->crm);
}
+#ifdef CONFIG_USER_ONLY
+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+#else
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+#endif
+
#endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 4066950da1..9f193927d8 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -29,6 +29,7 @@
#include "qapi/visitor.h"
#include "hw/qdev-properties.h"
#include "internals.h"
+#include "cpregs.h"
static void aarch64_a35_initfn(Object *obj)
{
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index df0c45e523..6ce728134f 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -93,65 +93,6 @@ void aa32_max_features(ARMCPU *cpu)
cpu->isar.id_dfr0 = t;
}
-#ifndef CONFIG_USER_ONLY
-static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
-{
- ARMCPU *cpu = env_archcpu(env);
-
- /* Number of cores is in [25:24]; otherwise we RAZ */
- return (cpu->core_count - 1) << 24;
-}
-
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
- { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
- .access = PL1_RW, .readfn = l2ctlr_read,
- .writefn = arm_cp_write_ignore },
- { .name = "L2CTLR",
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
- .access = PL1_RW, .readfn = l2ctlr_read,
- .writefn = arm_cp_write_ignore },
- { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2ECTLR",
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUACTLR",
- .cp = 15, .opc1 = 0, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUECTLR",
- .cp = 15, .opc1 = 1, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUMERRSR",
- .cp = 15, .opc1 = 2, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2MERRSR",
- .cp = 15, .opc1 = 3, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-};
-
-void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
-{
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
-}
-#endif /* !CONFIG_USER_ONLY */
-
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 680c574717..9a033daa28 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1352,12 +1352,6 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
#endif
-#ifdef CONFIG_USER_ONLY
-static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
-#else
-void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
-#endif
-
bool el_is_in_host(CPUARMState *env, int el);
void aa32_max_features(ARMCPU *cpu);
diff --git a/target/arm/meson.build b/target/arm/meson.build
index a5191b57e1..d236112684 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -20,6 +20,7 @@ arm_softmmu_ss = ss.source_set()
arm_softmmu_ss.add(files(
'arch_dump.c',
'arm-powerctl.c',
+ 'cortex-regs.c',
'machine.c',
'monitor.c',
'ptw.c',
--
2.35.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH RESEND v7 2/9] target/arm: Move 64-bit TCG CPUs into tcg/
2023-02-28 19:26 [PATCH RESEND v7 0/9] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 1/9] target/arm: Move cortex sysregs into a separate file Fabiano Rosas
@ 2023-02-28 19:26 ` Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 3/9] target/arm: Move aa32_max_features out of cpu_tcg.c Fabiano Rosas
` (6 subsequent siblings)
8 siblings, 0 replies; 25+ messages in thread
From: Fabiano Rosas @ 2023-02-28 19:26 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
Move the 64-bit CPUs that are TCG-only:
- cortex-a35
- cortex-a55
- cortex-a72
- cortex-a76
- a64fx
- neoverse-n1
Keep the CPUs that can be used with KVM:
- cortex-a57
- cortex-a53
- max
- host
For the special case "max" CPU, there's a nuance that while KVM/HVF
use the "host" model instead, we still cannot move all of the TCG code
into the tcg directory because the qtests might reach the !kvm && !hvf
branch.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/arm/virt.c | 6 +-
target/arm/cpu64.c | 398 +--------------------------------
target/arm/internals.h | 1 +
target/arm/tcg/cpu64.c | 438 +++++++++++++++++++++++++++++++++++++
target/arm/tcg/meson.build | 1 +
5 files changed, 445 insertions(+), 399 deletions(-)
create mode 100644 target/arm/tcg/cpu64.c
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index ac626b3bef..999c1ada79 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -206,14 +206,16 @@ static const int a15irqmap[] = {
static const char *valid_cpus[] = {
ARM_CPU_TYPE_NAME("cortex-a7"),
ARM_CPU_TYPE_NAME("cortex-a15"),
+#ifdef CONFIG_TCG
ARM_CPU_TYPE_NAME("cortex-a35"),
- ARM_CPU_TYPE_NAME("cortex-a53"),
ARM_CPU_TYPE_NAME("cortex-a55"),
- ARM_CPU_TYPE_NAME("cortex-a57"),
ARM_CPU_TYPE_NAME("cortex-a72"),
ARM_CPU_TYPE_NAME("cortex-a76"),
ARM_CPU_TYPE_NAME("a64fx"),
ARM_CPU_TYPE_NAME("neoverse-n1"),
+#endif
+ ARM_CPU_TYPE_NAME("cortex-a53"),
+ ARM_CPU_TYPE_NAME("cortex-a57"),
ARM_CPU_TYPE_NAME("host"),
ARM_CPU_TYPE_NAME("max"),
};
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 9f193927d8..0b55598f9d 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -31,86 +31,6 @@
#include "internals.h"
#include "cpregs.h"
-static void aarch64_a35_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,cortex-a35";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
-
- /* From B2.2 AArch64 identification registers. */
- cpu->midr = 0x411fd040;
- cpu->revidr = 0;
- cpu->ctr = 0x84448004;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
- cpu->isar.id_dfr0 = 0x03010066;
- cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_aa64pfr0 = 0x00002222;
- cpu->isar.id_aa64pfr1 = 0;
- cpu->isar.id_aa64dfr0 = 0x10305106;
- cpu->isar.id_aa64dfr1 = 0;
- cpu->isar.id_aa64isar0 = 0x00011120;
- cpu->isar.id_aa64isar1 = 0;
- cpu->isar.id_aa64mmfr0 = 0x00101122;
- cpu->isar.id_aa64mmfr1 = 0;
- cpu->clidr = 0x0a200023;
- cpu->dcz_blocksize = 4;
-
- /* From B2.4 AArch64 Virtual Memory control registers */
- cpu->reset_sctlr = 0x00c50838;
-
- /* From B2.10 AArch64 performance monitor registers */
- cpu->isar.reset_pmcr_el0 = 0x410a3000;
-
- /* From B2.29 Cache ID registers */
- cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
- cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
- cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */
-
- /* From B3.5 VGIC Type register */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
-
- /* From C6.4 Debug ID Register */
- cpu->isar.dbgdidr = 0x3516d000;
- /* From C6.5 Debug Device ID Register */
- cpu->isar.dbgdevid = 0x00110f13;
- /* From C6.6 Debug Device ID Register 1 */
- cpu->isar.dbgdevid1 = 0x2;
-
- /* From Cortex-A35 SIMD and Floating-point Support r1p0 */
- /* From 3.2 AArch32 register summary */
- cpu->reset_fpsid = 0x41034043;
-
- /* From 2.2 AArch64 register summary */
- cpu->isar.mvfr0 = 0x10110222;
- cpu->isar.mvfr1 = 0x12111111;
- cpu->isar.mvfr2 = 0x00000043;
-
- /* These values are the same with A53/A57/A72. */
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
-}
-
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
{
/*
@@ -541,7 +461,7 @@ static void cpu_arm_get_default_vec_len(Object *obj, Visitor *v,
}
#endif
-static void aarch64_add_sve_properties(Object *obj)
+void aarch64_add_sve_properties(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
uint32_t vq;
@@ -787,316 +707,6 @@ static void aarch64_a53_initfn(Object *obj)
define_cortex_a72_a57_a53_cp_reginfo(cpu);
}
-static void aarch64_a55_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,cortex-a55";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
-
- /* Ordered by B2.4 AArch64 registers by functional group */
- cpu->clidr = 0x82000023;
- cpu->ctr = 0x84448004; /* L1Ip = VIPT */
- cpu->dcz_blocksize = 4; /* 64 bytes */
- cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
- cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
- cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
- cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x01011121;
- cpu->isar.id_isar6 = 0x00000010;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x00021110;
- cpu->isar.id_pfr0 = 0x10010131;
- cpu->isar.id_pfr1 = 0x00011011;
- cpu->isar.id_pfr2 = 0x00000011;
- cpu->midr = 0x412FD050; /* r2p0 */
- cpu->revidr = 0;
-
- /* From B2.23 CCSIDR_EL1 */
- cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
- cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
- cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
-
- /* From B2.96 SCTLR_EL3 */
- cpu->reset_sctlr = 0x30c50838;
-
- /* From B4.45 ICH_VTR_EL2 */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
-
- cpu->isar.mvfr0 = 0x10110222;
- cpu->isar.mvfr1 = 0x13211111;
- cpu->isar.mvfr2 = 0x00000043;
-
- /* From D5.4 AArch64 PMU register summary */
- cpu->isar.reset_pmcr_el0 = 0x410b3000;
-}
-
-static void aarch64_a72_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,cortex-a72";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
- cpu->midr = 0x410fd083;
- cpu->revidr = 0x00000000;
- cpu->reset_fpsid = 0x41034080;
- cpu->isar.mvfr0 = 0x10110222;
- cpu->isar.mvfr1 = 0x12111111;
- cpu->isar.mvfr2 = 0x00000043;
- cpu->ctr = 0x8444c004;
- cpu->reset_sctlr = 0x00c50838;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
- cpu->isar.id_dfr0 = 0x03010066;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_aa64pfr0 = 0x00002222;
- cpu->isar.id_aa64dfr0 = 0x10305106;
- cpu->isar.id_aa64isar0 = 0x00011120;
- cpu->isar.id_aa64mmfr0 = 0x00001124;
- cpu->isar.dbgdidr = 0x3516d000;
- cpu->isar.dbgdevid = 0x01110f13;
- cpu->isar.dbgdevid1 = 0x2;
- cpu->isar.reset_pmcr_el0 = 0x41023000;
- cpu->clidr = 0x0a200023;
- cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
- cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
- cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
- cpu->dcz_blocksize = 4; /* 64 bytes */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
-}
-
-static void aarch64_a76_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,cortex-a76";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
-
- /* Ordered by B2.4 AArch64 registers by functional group */
- cpu->clidr = 0x82000023;
- cpu->ctr = 0x8444C004;
- cpu->dcz_blocksize = 4;
- cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
- cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x01011121;
- cpu->isar.id_isar6 = 0x00000010;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x00021110;
- cpu->isar.id_pfr0 = 0x10010131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
- cpu->isar.id_pfr2 = 0x00000011;
- cpu->midr = 0x414fd0b1; /* r4p1 */
- cpu->revidr = 0;
-
- /* From B2.18 CCSIDR_EL1 */
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
- cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
-
- /* From B2.93 SCTLR_EL3 */
- cpu->reset_sctlr = 0x30c50838;
-
- /* From B4.23 ICH_VTR_EL2 */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
-
- /* From B5.1 AdvSIMD AArch64 register summary */
- cpu->isar.mvfr0 = 0x10110222;
- cpu->isar.mvfr1 = 0x13211111;
- cpu->isar.mvfr2 = 0x00000043;
-
- /* From D5.1 AArch64 PMU register summary */
- cpu->isar.reset_pmcr_el0 = 0x410b3000;
-}
-
-static void aarch64_a64fx_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,a64fx";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
- cpu->midr = 0x461f0010;
- cpu->revidr = 0x00000000;
- cpu->ctr = 0x86668006;
- cpu->reset_sctlr = 0x30000180;
- cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
- cpu->isar.id_aa64pfr1 = 0x0000000000000000;
- cpu->isar.id_aa64dfr0 = 0x0000000010305408;
- cpu->isar.id_aa64dfr1 = 0x0000000000000000;
- cpu->id_aa64afr0 = 0x0000000000000000;
- cpu->id_aa64afr1 = 0x0000000000000000;
- cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
- cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
- cpu->isar.id_aa64isar0 = 0x0000000010211120;
- cpu->isar.id_aa64isar1 = 0x0000000000010001;
- cpu->isar.id_aa64zfr0 = 0x0000000000000000;
- cpu->clidr = 0x0000000080000023;
- cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
- cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
- cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
- cpu->dcz_blocksize = 6; /* 256 bytes */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
-
- /* The A64FX supports only 128, 256 and 512 bit vector lengths */
- aarch64_add_sve_properties(obj);
- cpu->sve_vq.supported = (1 << 0) /* 128bit */
- | (1 << 1) /* 256bit */
- | (1 << 3); /* 512bit */
-
- cpu->isar.reset_pmcr_el0 = 0x46014040;
-
- /* TODO: Add A64FX specific HPC extension registers */
-}
-
-static void aarch64_neoverse_n1_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,neoverse-n1";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
-
- /* Ordered by B2.4 AArch64 registers by functional group */
- cpu->clidr = 0x82000023;
- cpu->ctr = 0x8444c004;
- cpu->dcz_blocksize = 4;
- cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
- cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x01011121;
- cpu->isar.id_isar6 = 0x00000010;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x00021110;
- cpu->isar.id_pfr0 = 0x10010131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
- cpu->isar.id_pfr2 = 0x00000011;
- cpu->midr = 0x414fd0c1; /* r4p1 */
- cpu->revidr = 0;
-
- /* From B2.23 CCSIDR_EL1 */
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
- cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
-
- /* From B2.98 SCTLR_EL3 */
- cpu->reset_sctlr = 0x30c50838;
-
- /* From B4.23 ICH_VTR_EL2 */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
-
- /* From B5.1 AdvSIMD AArch64 register summary */
- cpu->isar.mvfr0 = 0x10110222;
- cpu->isar.mvfr1 = 0x13211111;
- cpu->isar.mvfr2 = 0x00000043;
-
- /* From D5.1 AArch64 PMU register summary */
- cpu->isar.reset_pmcr_el0 = 0x410c3000;
-}
-
static void aarch64_host_initfn(Object *obj)
{
#if defined(CONFIG_KVM)
@@ -1305,14 +915,8 @@ static void aarch64_max_initfn(Object *obj)
}
static const ARMCPUInfo aarch64_cpus[] = {
- { .name = "cortex-a35", .initfn = aarch64_a35_initfn },
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
- { .name = "cortex-a55", .initfn = aarch64_a55_initfn },
- { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
- { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
- { .name = "a64fx", .initfn = aarch64_a64fx_initfn },
- { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
{ .name = "max", .initfn = aarch64_max_initfn },
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
{ .name = "host", .initfn = aarch64_host_initfn },
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 9a033daa28..b82be52506 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1350,6 +1350,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
+void aarch64_add_sve_properties(Object *obj);
#endif
bool el_is_in_host(CPUARMState *env, int el);
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
new file mode 100644
index 0000000000..4cbae9293d
--- /dev/null
+++ b/target/arm/tcg/cpu64.c
@@ -0,0 +1,438 @@
+/*
+ * QEMU AArch64 TCG CPUs
+ *
+ * Copyright (c) 2013 Linaro Ltd
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "qemu/module.h"
+#include "qapi/visitor.h"
+#include "hw/qdev-properties.h"
+#include "internals.h"
+#include "cpregs.h"
+
+static void aarch64_a35_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a35";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+ /* From B2.2 AArch64 identification registers. */
+ cpu->midr = 0x411fd040;
+ cpu->revidr = 0;
+ cpu->ctr = 0x84448004;
+ cpu->isar.id_pfr0 = 0x00000131;
+ cpu->isar.id_pfr1 = 0x00011011;
+ cpu->isar.id_dfr0 = 0x03010066;
+ cpu->id_afr0 = 0;
+ cpu->isar.id_mmfr0 = 0x10201105;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01260000;
+ cpu->isar.id_mmfr3 = 0x02102211;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232042;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00011142;
+ cpu->isar.id_isar5 = 0x00011121;
+ cpu->isar.id_aa64pfr0 = 0x00002222;
+ cpu->isar.id_aa64pfr1 = 0;
+ cpu->isar.id_aa64dfr0 = 0x10305106;
+ cpu->isar.id_aa64dfr1 = 0;
+ cpu->isar.id_aa64isar0 = 0x00011120;
+ cpu->isar.id_aa64isar1 = 0;
+ cpu->isar.id_aa64mmfr0 = 0x00101122;
+ cpu->isar.id_aa64mmfr1 = 0;
+ cpu->clidr = 0x0a200023;
+ cpu->dcz_blocksize = 4;
+
+ /* From B2.4 AArch64 Virtual Memory control registers */
+ cpu->reset_sctlr = 0x00c50838;
+
+ /* From B2.10 AArch64 performance monitor registers */
+ cpu->isar.reset_pmcr_el0 = 0x410a3000;
+
+ /* From B2.29 Cache ID registers */
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
+ cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */
+
+ /* From B3.5 VGIC Type register */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+
+ /* From C6.4 Debug ID Register */
+ cpu->isar.dbgdidr = 0x3516d000;
+ /* From C6.5 Debug Device ID Register */
+ cpu->isar.dbgdevid = 0x00110f13;
+ /* From C6.6 Debug Device ID Register 1 */
+ cpu->isar.dbgdevid1 = 0x2;
+
+ /* From Cortex-A35 SIMD and Floating-point Support r1p0 */
+ /* From 3.2 AArch32 register summary */
+ cpu->reset_fpsid = 0x41034043;
+
+ /* From 2.2 AArch64 register summary */
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x12111111;
+ cpu->isar.mvfr2 = 0x00000043;
+
+ /* These values are the same with A53/A57/A72. */
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
+}
+
+static void aarch64_a55_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a55";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+ /* Ordered by B2.4 AArch64 registers by functional group */
+ cpu->clidr = 0x82000023;
+ cpu->ctr = 0x84448004; /* L1Ip = VIPT */
+ cpu->dcz_blocksize = 4; /* 64 bytes */
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+ cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_dfr0 = 0x04010088;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232042;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00011142;
+ cpu->isar.id_isar5 = 0x01011121;
+ cpu->isar.id_isar6 = 0x00000010;
+ cpu->isar.id_mmfr0 = 0x10201105;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01260000;
+ cpu->isar.id_mmfr3 = 0x02122211;
+ cpu->isar.id_mmfr4 = 0x00021110;
+ cpu->isar.id_pfr0 = 0x10010131;
+ cpu->isar.id_pfr1 = 0x00011011;
+ cpu->isar.id_pfr2 = 0x00000011;
+ cpu->midr = 0x412FD050; /* r2p0 */
+ cpu->revidr = 0;
+
+ /* From B2.23 CCSIDR_EL1 */
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
+ cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
+ cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
+
+ /* From B2.96 SCTLR_EL3 */
+ cpu->reset_sctlr = 0x30c50838;
+
+ /* From B4.45 ICH_VTR_EL2 */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x13211111;
+ cpu->isar.mvfr2 = 0x00000043;
+
+ /* From D5.4 AArch64 PMU register summary */
+ cpu->isar.reset_pmcr_el0 = 0x410b3000;
+}
+
+static void aarch64_a72_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a72";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+ cpu->midr = 0x410fd083;
+ cpu->revidr = 0x00000000;
+ cpu->reset_fpsid = 0x41034080;
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x12111111;
+ cpu->isar.mvfr2 = 0x00000043;
+ cpu->ctr = 0x8444c004;
+ cpu->reset_sctlr = 0x00c50838;
+ cpu->isar.id_pfr0 = 0x00000131;
+ cpu->isar.id_pfr1 = 0x00011011;
+ cpu->isar.id_dfr0 = 0x03010066;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x10201105;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01260000;
+ cpu->isar.id_mmfr3 = 0x02102211;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232042;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00011142;
+ cpu->isar.id_isar5 = 0x00011121;
+ cpu->isar.id_aa64pfr0 = 0x00002222;
+ cpu->isar.id_aa64dfr0 = 0x10305106;
+ cpu->isar.id_aa64isar0 = 0x00011120;
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
+ cpu->isar.dbgdidr = 0x3516d000;
+ cpu->isar.dbgdevid = 0x01110f13;
+ cpu->isar.dbgdevid1 = 0x2;
+ cpu->isar.reset_pmcr_el0 = 0x41023000;
+ cpu->clidr = 0x0a200023;
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+ cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
+ cpu->dcz_blocksize = 4; /* 64 bytes */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
+}
+
+static void aarch64_a76_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a76";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+ /* Ordered by B2.4 AArch64 registers by functional group */
+ cpu->clidr = 0x82000023;
+ cpu->ctr = 0x8444C004;
+ cpu->dcz_blocksize = 4;
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_dfr0 = 0x04010088;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232042;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00010142;
+ cpu->isar.id_isar5 = 0x01011121;
+ cpu->isar.id_isar6 = 0x00000010;
+ cpu->isar.id_mmfr0 = 0x10201105;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01260000;
+ cpu->isar.id_mmfr3 = 0x02122211;
+ cpu->isar.id_mmfr4 = 0x00021110;
+ cpu->isar.id_pfr0 = 0x10010131;
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
+ cpu->isar.id_pfr2 = 0x00000011;
+ cpu->midr = 0x414fd0b1; /* r4p1 */
+ cpu->revidr = 0;
+
+ /* From B2.18 CCSIDR_EL1 */
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+ cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
+
+ /* From B2.93 SCTLR_EL3 */
+ cpu->reset_sctlr = 0x30c50838;
+
+ /* From B4.23 ICH_VTR_EL2 */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+
+ /* From B5.1 AdvSIMD AArch64 register summary */
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x13211111;
+ cpu->isar.mvfr2 = 0x00000043;
+
+ /* From D5.1 AArch64 PMU register summary */
+ cpu->isar.reset_pmcr_el0 = 0x410b3000;
+}
+
+static void aarch64_a64fx_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,a64fx";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+ cpu->midr = 0x461f0010;
+ cpu->revidr = 0x00000000;
+ cpu->ctr = 0x86668006;
+ cpu->reset_sctlr = 0x30000180;
+ cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
+ cpu->isar.id_aa64pfr1 = 0x0000000000000000;
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408;
+ cpu->isar.id_aa64dfr1 = 0x0000000000000000;
+ cpu->id_aa64afr0 = 0x0000000000000000;
+ cpu->id_aa64afr1 = 0x0000000000000000;
+ cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
+ cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
+ cpu->isar.id_aa64isar0 = 0x0000000010211120;
+ cpu->isar.id_aa64isar1 = 0x0000000000010001;
+ cpu->isar.id_aa64zfr0 = 0x0000000000000000;
+ cpu->clidr = 0x0000000080000023;
+ cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
+ cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
+ cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
+ cpu->dcz_blocksize = 6; /* 256 bytes */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+
+ /* The A64FX supports only 128, 256 and 512 bit vector lengths */
+ aarch64_add_sve_properties(obj);
+ cpu->sve_vq.supported = (1 << 0) /* 128bit */
+ | (1 << 1) /* 256bit */
+ | (1 << 3); /* 512bit */
+
+ cpu->isar.reset_pmcr_el0 = 0x46014040;
+
+ /* TODO: Add A64FX specific HPC extension registers */
+}
+
+static void aarch64_neoverse_n1_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,neoverse-n1";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+ /* Ordered by B2.4 AArch64 registers by functional group */
+ cpu->clidr = 0x82000023;
+ cpu->ctr = 0x8444c004;
+ cpu->dcz_blocksize = 4;
+ cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
+ cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_dfr0 = 0x04010088;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232042;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00010142;
+ cpu->isar.id_isar5 = 0x01011121;
+ cpu->isar.id_isar6 = 0x00000010;
+ cpu->isar.id_mmfr0 = 0x10201105;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01260000;
+ cpu->isar.id_mmfr3 = 0x02122211;
+ cpu->isar.id_mmfr4 = 0x00021110;
+ cpu->isar.id_pfr0 = 0x10010131;
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
+ cpu->isar.id_pfr2 = 0x00000011;
+ cpu->midr = 0x414fd0c1; /* r4p1 */
+ cpu->revidr = 0;
+
+ /* From B2.23 CCSIDR_EL1 */
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+ cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
+
+ /* From B2.98 SCTLR_EL3 */
+ cpu->reset_sctlr = 0x30c50838;
+
+ /* From B4.23 ICH_VTR_EL2 */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+
+ /* From B5.1 AdvSIMD AArch64 register summary */
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x13211111;
+ cpu->isar.mvfr2 = 0x00000043;
+
+ /* From D5.1 AArch64 PMU register summary */
+ cpu->isar.reset_pmcr_el0 = 0x410c3000;
+}
+
+static const ARMCPUInfo aarch64_cpus[] = {
+ { .name = "cortex-a35", .initfn = aarch64_a35_initfn },
+ { .name = "cortex-a55", .initfn = aarch64_a55_initfn },
+ { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
+ { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
+ { .name = "a64fx", .initfn = aarch64_a64fx_initfn },
+ { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
+};
+
+static void aarch64_cpu_register_types(void)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
+ aarch64_cpu_register(&aarch64_cpus[i]);
+ }
+}
+
+type_init(aarch64_cpu_register_types)
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index d27e76af6c..128f782816 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -35,6 +35,7 @@ arm_ss.add(files(
))
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
+ 'cpu64.c',
'translate-a64.c',
'translate-sve.c',
'translate-sme.c',
--
2.35.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH RESEND v7 3/9] target/arm: Move aa32_max_features out of cpu_tcg.c
2023-02-28 19:26 [PATCH RESEND v7 0/9] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 1/9] target/arm: Move cortex sysregs into a separate file Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 2/9] target/arm: Move 64-bit TCG CPUs into tcg/ Fabiano Rosas
@ 2023-02-28 19:26 ` Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 4/9] target/arm: move cpu_tcg to tcg/cpu32.c Fabiano Rosas
` (5 subsequent siblings)
8 siblings, 0 replies; 25+ messages in thread
From: Fabiano Rosas @ 2023-02-28 19:26 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
In preparation to moving the cpu_tcg.c code into a 32-bit, tcg-only
file, move the aa32_max_features function which is shared between
32/64/tcg/non-tcg into cpu.c.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
target/arm/cpu.c | 69 ++++++++++++++++++++++++++++++++++++++++++++
target/arm/cpu_tcg.c | 69 --------------------------------------------
2 files changed, 69 insertions(+), 69 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0b333a749f..1d0837ae12 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2153,6 +2153,75 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
acc->parent_realize(dev, errp);
}
+/* Share AArch32 -cpu max features with AArch64. */
+void aa32_max_features(ARMCPU *cpu)
+{
+ uint32_t t;
+
+ /* Add additional features supported by QEMU */
+ t = cpu->isar.id_isar5;
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
+ cpu->isar.id_isar5 = t;
+
+ t = cpu->isar.id_isar6;
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
+ cpu->isar.id_isar6 = t;
+
+ t = cpu->isar.mvfr1;
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
+ cpu->isar.mvfr1 = t;
+
+ t = cpu->isar.mvfr2;
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
+ cpu->isar.mvfr2 = t;
+
+ t = cpu->isar.id_mmfr3;
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
+ cpu->isar.id_mmfr3 = t;
+
+ t = cpu->isar.id_mmfr4;
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
+ t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
+ cpu->isar.id_mmfr4 = t;
+
+ t = cpu->isar.id_mmfr5;
+ t = FIELD_DP32(t, ID_MMFR5, ETS, 1); /* FEAT_ETS */
+ cpu->isar.id_mmfr5 = t;
+
+ t = cpu->isar.id_pfr0;
+ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
+ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
+ cpu->isar.id_pfr0 = t;
+
+ t = cpu->isar.id_pfr2;
+ t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
+ cpu->isar.id_pfr2 = t;
+
+ t = cpu->isar.id_dfr0;
+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
+ cpu->isar.id_dfr0 = t;
+}
+
static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 6ce728134f..5a2690f56e 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -24,75 +24,6 @@
#endif
-/* Share AArch32 -cpu max features with AArch64. */
-void aa32_max_features(ARMCPU *cpu)
-{
- uint32_t t;
-
- /* Add additional features supported by QEMU */
- t = cpu->isar.id_isar5;
- t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
- t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
- cpu->isar.id_isar5 = t;
-
- t = cpu->isar.id_isar6;
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
- t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
- t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
- cpu->isar.id_isar6 = t;
-
- t = cpu->isar.mvfr1;
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
- cpu->isar.mvfr1 = t;
-
- t = cpu->isar.mvfr2;
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
- cpu->isar.mvfr2 = t;
-
- t = cpu->isar.id_mmfr3;
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
- cpu->isar.id_mmfr3 = t;
-
- t = cpu->isar.id_mmfr4;
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
- t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
- cpu->isar.id_mmfr4 = t;
-
- t = cpu->isar.id_mmfr5;
- t = FIELD_DP32(t, ID_MMFR5, ETS, 1); /* FEAT_ETS */
- cpu->isar.id_mmfr5 = t;
-
- t = cpu->isar.id_pfr0;
- t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
- t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
- t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
- cpu->isar.id_pfr0 = t;
-
- t = cpu->isar.id_pfr2;
- t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
- cpu->isar.id_pfr2 = t;
-
- t = cpu->isar.id_dfr0;
- t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
- t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
- t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
- cpu->isar.id_dfr0 = t;
-}
-
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
--
2.35.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH RESEND v7 4/9] target/arm: move cpu_tcg to tcg/cpu32.c
2023-02-28 19:26 [PATCH RESEND v7 0/9] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (2 preceding siblings ...)
2023-02-28 19:26 ` [PATCH RESEND v7 3/9] target/arm: Move aa32_max_features out of cpu_tcg.c Fabiano Rosas
@ 2023-02-28 19:26 ` Fabiano Rosas
2023-03-01 13:06 ` Thomas Huth
2023-02-28 19:26 ` [PATCH RESEND v7 5/9] tests/avocado: Pass parameters to migration test Fabiano Rosas
` (4 subsequent siblings)
8 siblings, 1 reply; 25+ messages in thread
From: Fabiano Rosas @ 2023-02-28 19:26 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth, Laurent Vivier
From: Claudio Fontana <cfontana@suse.de>
move the module containing cpu models definitions
for 32bit TCG-only CPUs to tcg/ and rename it for clarity.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/arm/virt.c | 2 +-
target/arm/meson.build | 1 -
target/arm/{cpu_tcg.c => tcg/cpu32.c} | 13 +++----------
target/arm/tcg/meson.build | 1 +
tests/qtest/arm-cpu-features.c | 12 +++++++++---
5 files changed, 14 insertions(+), 15 deletions(-)
rename target/arm/{cpu_tcg.c => tcg/cpu32.c} (99%)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 999c1ada79..b661b8d91b 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -204,9 +204,9 @@ static const int a15irqmap[] = {
};
static const char *valid_cpus[] = {
+#ifdef CONFIG_TCG
ARM_CPU_TYPE_NAME("cortex-a7"),
ARM_CPU_TYPE_NAME("cortex-a15"),
-#ifdef CONFIG_TCG
ARM_CPU_TYPE_NAME("cortex-a35"),
ARM_CPU_TYPE_NAME("cortex-a55"),
ARM_CPU_TYPE_NAME("cortex-a72"),
diff --git a/target/arm/meson.build b/target/arm/meson.build
index d236112684..85a884808e 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -5,7 +5,6 @@ arm_ss.add(files(
'gdbstub.c',
'helper.c',
'vfp_helper.c',
- 'cpu_tcg.c',
))
arm_ss.add(zlib)
diff --git a/target/arm/cpu_tcg.c b/target/arm/tcg/cpu32.c
similarity index 99%
rename from target/arm/cpu_tcg.c
rename to target/arm/tcg/cpu32.c
index 5a2690f56e..4cbd7d68fb 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/tcg/cpu32.c
@@ -1,5 +1,5 @@
/*
- * QEMU ARM TCG CPUs.
+ * QEMU ARM TCG-only CPUs.
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@@ -10,9 +10,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
-#endif /* CONFIG_TCG */
#include "internals.h"
#include "target/arm/idau.h"
#if !defined(CONFIG_USER_ONLY)
@@ -27,7 +25,7 @@
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+#if !defined(CONFIG_USER_ONLY)
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -51,7 +49,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
return ret;
}
-#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
+#endif /* !CONFIG_USER_ONLY */
static void arm926_initfn(Object *obj)
{
@@ -947,7 +945,6 @@ static void pxa270c5_initfn(Object *obj)
cpu->reset_sctlr = 0x00000078;
}
-#ifdef CONFIG_TCG
static const struct TCGCPUOps arm_v7m_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
@@ -968,7 +965,6 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = {
.debug_check_breakpoint = arm_debug_check_breakpoint,
#endif /* !CONFIG_USER_ONLY */
};
-#endif /* CONFIG_TCG */
static void arm_v7m_class_init(ObjectClass *oc, void *data)
{
@@ -976,10 +972,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
acc->info = data;
-#ifdef CONFIG_TCG
cc->tcg_ops = &arm_v7m_tcg_ops;
-#endif /* CONFIG_TCG */
-
cc->gdb_core_xml_file = "arm-m-profile.xml";
}
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index 128f782816..4d99f6dacb 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -18,6 +18,7 @@ gen = [
arm_ss.add(gen)
arm_ss.add(files(
+ 'cpu32.c',
'translate.c',
'translate-m-nocp.c',
'translate-mve.c',
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 1cb08138ad..1555b0bab8 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -506,9 +506,15 @@ static void test_query_cpu_model_expansion_kvm(const void *data)
QDict *resp;
char *error;
- assert_error(qts, "cortex-a15",
- "We cannot guarantee the CPU type 'cortex-a15' works "
- "with KVM on this host", NULL);
+ if (qtest_has_accel("tcg")) {
+ assert_error(qts, "cortex-a15",
+ "We cannot guarantee the CPU type 'cortex-a15' works "
+ "with KVM on this host", NULL);
+ } else {
+ assert_error(qts, "cortex-a15",
+ "The CPU type 'cortex-a15' is not a "
+ "recognized ARM CPU type", NULL);
+ }
assert_has_feature_enabled(qts, "host", "aarch64");
--
2.35.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH RESEND v7 5/9] tests/avocado: Pass parameters to migration test
2023-02-28 19:26 [PATCH RESEND v7 0/9] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (3 preceding siblings ...)
2023-02-28 19:26 ` [PATCH RESEND v7 4/9] target/arm: move cpu_tcg to tcg/cpu32.c Fabiano Rosas
@ 2023-02-28 19:26 ` Fabiano Rosas
2023-03-03 16:22 ` Peter Maydell
2023-02-28 19:26 ` [PATCH RESEND v7 6/9] arm/Kconfig: Always select SEMIHOSTING when TCG is present Fabiano Rosas
` (3 subsequent siblings)
8 siblings, 1 reply; 25+ messages in thread
From: Fabiano Rosas @ 2023-02-28 19:26 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Cleber Rosa, Wainer dos Santos Moschetta, Beraldo Leal
The migration tests are currently broken for an aarch64 host because
the tests pass no 'machine' and 'cpu' options on the QEMU command
line.
Add a separate class to each architecture so that we can specify
'machine' and 'cpu' options instead of relying on defaults.
Add a skip decorator to keep the current behavior of only running
migration tests when the qemu target matches the host architecture.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
tests/avocado/migration.py | 83 +++++++++++++++++++++++++++++++++++---
1 file changed, 78 insertions(+), 5 deletions(-)
diff --git a/tests/avocado/migration.py b/tests/avocado/migration.py
index 4b25680c50..8b2ec0e3c4 100644
--- a/tests/avocado/migration.py
+++ b/tests/avocado/migration.py
@@ -11,6 +11,8 @@
import tempfile
+import os
+
from avocado_qemu import QemuSystemTest
from avocado import skipUnless
@@ -19,7 +21,7 @@
from avocado.utils.path import find_command
-class Migration(QemuSystemTest):
+class MigrationTest(QemuSystemTest):
"""
:avocado: tags=migration
"""
@@ -62,20 +64,91 @@ def _get_free_port(self):
self.cancel('Failed to find a free port')
return port
-
- def test_migration_with_tcp_localhost(self):
+ def migration_with_tcp_localhost(self):
dest_uri = 'tcp:localhost:%u' % self._get_free_port()
self.do_migrate(dest_uri)
- def test_migration_with_unix(self):
+ def migration_with_unix(self):
with tempfile.TemporaryDirectory(prefix='socket_') as socket_path:
dest_uri = 'unix:%s/qemu-test.sock' % socket_path
self.do_migrate(dest_uri)
@skipUnless(find_command('nc', default=False), "'nc' command not found")
- def test_migration_with_exec(self):
+ def migration_with_exec(self):
"""The test works for both netcat-traditional and netcat-openbsd packages."""
free_port = self._get_free_port()
dest_uri = 'exec:nc -l localhost %u' % free_port
src_uri = 'exec:nc localhost %u' % free_port
self.do_migrate(dest_uri, src_uri)
+
+
+@skipUnless('aarch64' in os.uname()[4], "host != target")
+class Aarch64(MigrationTest):
+ """
+ :avocado: tags=arch:aarch64
+ :avocado: tags=machine:virt
+ :avocado: tags=cpu:max
+ """
+
+ def test_migration_with_tcp_localhost(self):
+ self.migration_with_tcp_localhost()
+
+ def test_migration_with_unix(self):
+ self.migration_with_unix()
+
+ def test_migration_with_exec(self):
+ self.migration_with_exec()
+
+
+@skipUnless('x86_64' in os.uname()[4], "host != target")
+class X86_64(MigrationTest):
+ """
+ :avocado: tags=arch:x86_64
+ :avocado: tags=machine:pc
+ :avocado: tags=cpu:qemu64
+ """
+
+ def test_migration_with_tcp_localhost(self):
+ self.migration_with_tcp_localhost()
+
+ def test_migration_with_unix(self):
+ self.migration_with_unix()
+
+ def test_migration_with_exec(self):
+ self.migration_with_exec()
+
+
+@skipUnless('ppc64le' in os.uname()[4], "host != target")
+class PPC64(MigrationTest):
+ """
+ :avocado: tags=arch:ppc64
+ :avocado: tags=machine:pseries
+ :avocado: tags=cpu:power9_v2.0
+ """
+
+ def test_migration_with_tcp_localhost(self):
+ self.migration_with_tcp_localhost()
+
+ def test_migration_with_unix(self):
+ self.migration_with_unix()
+
+ def test_migration_with_exec(self):
+ self.migration_with_exec()
+
+
+@skipUnless('s390x' in os.uname()[4], "host != target")
+class S390X(MigrationTest):
+ """
+ :avocado: tags=arch:s390x
+ :avocado: tags=machine:s390-ccw-virtio
+ :avocado: tags=cpu:qemu
+ """
+
+ def test_migration_with_tcp_localhost(self):
+ self.migration_with_tcp_localhost()
+
+ def test_migration_with_unix(self):
+ self.migration_with_unix()
+
+ def test_migration_with_exec(self):
+ self.migration_with_exec()
--
2.35.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH RESEND v7 6/9] arm/Kconfig: Always select SEMIHOSTING when TCG is present
2023-02-28 19:26 [PATCH RESEND v7 0/9] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (4 preceding siblings ...)
2023-02-28 19:26 ` [PATCH RESEND v7 5/9] tests/avocado: Pass parameters to migration test Fabiano Rosas
@ 2023-02-28 19:26 ` Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 7/9] arm/Kconfig: Do not build TCG-only boards on a KVM-only build Fabiano Rosas
` (2 subsequent siblings)
8 siblings, 0 replies; 25+ messages in thread
From: Fabiano Rosas @ 2023-02-28 19:26 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
We are about to enable the build without TCG, so CONFIG_SEMIHOSTING
and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in
default.mak anymore. So reflect the change in a Kconfig.
Instead of using semihosting/Kconfig, use a target-specific file, so
that the change doesn't affect other architectures which might
implement semihosting in a way compatible with KVM.
The selection from ARM_v7M needs to be removed to avoid a cycle during
parsing.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
configs/devices/arm-softmmu/default.mak | 2 --
hw/arm/Kconfig | 1 -
target/arm/Kconfig | 7 +++++++
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
index 1b49a7830c..cb3e5aea65 100644
--- a/configs/devices/arm-softmmu/default.mak
+++ b/configs/devices/arm-softmmu/default.mak
@@ -40,6 +40,4 @@ CONFIG_MICROBIT=y
CONFIG_FSL_IMX25=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
-CONFIG_SEMIHOSTING=y
-CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
CONFIG_ALLWINNER_H3=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index b5aed4aff5..c0b213f42d 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -316,7 +316,6 @@ config ARM_V7M
# currently v7M must be included in a TCG build due to translate.c
default y if TCG && (ARM || AARCH64)
select PTIMER
- select ARM_COMPATIBLE_SEMIHOSTING
config ALLWINNER_A10
bool
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
index 3f3394a22b..39f05b6420 100644
--- a/target/arm/Kconfig
+++ b/target/arm/Kconfig
@@ -4,3 +4,10 @@ config ARM
config AARCH64
bool
select ARM
+
+# This config exists just so we can make SEMIHOSTING default when TCG
+# is selected without also changing it for other architectures.
+config ARM_SEMIHOSTING
+ bool
+ default y if TCG && ARM
+ select ARM_COMPATIBLE_SEMIHOSTING
--
2.35.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH RESEND v7 7/9] arm/Kconfig: Do not build TCG-only boards on a KVM-only build
2023-02-28 19:26 [PATCH RESEND v7 0/9] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (5 preceding siblings ...)
2023-02-28 19:26 ` [PATCH RESEND v7 6/9] arm/Kconfig: Always select SEMIHOSTING when TCG is present Fabiano Rosas
@ 2023-02-28 19:26 ` Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 8/9] gitlab-ci: Check building KVM-only aarch64 target Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 9/9] tests/qtest: Fix tests when no KVM or TCG are present Fabiano Rosas
8 siblings, 0 replies; 25+ messages in thread
From: Fabiano Rosas @ 2023-02-28 19:26 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
Move all the CONFIG_FOO=y from default.mak into "default y if TCG"
statements in Kconfig. That way they won't be selected when
CONFIG_TCG=n.
I'm leaving CONFIG_ARM_VIRT in default.mak because it allows us to
keep the two default.mak files not empty and keep aarch64-default.mak
including arm-default.mak. That way we don't surprise anyone that's
used to altering these files.
With this change we can start building with --disable-tcg.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
configs/devices/aarch64-softmmu/default.mak | 4 --
configs/devices/arm-softmmu/default.mak | 37 ------------------
hw/arm/Kconfig | 42 ++++++++++++++++++++-
3 files changed, 41 insertions(+), 42 deletions(-)
diff --git a/configs/devices/aarch64-softmmu/default.mak b/configs/devices/aarch64-softmmu/default.mak
index cf43ac8da1..70e05a197d 100644
--- a/configs/devices/aarch64-softmmu/default.mak
+++ b/configs/devices/aarch64-softmmu/default.mak
@@ -2,7 +2,3 @@
# We support all the 32 bit boards so need all their config
include ../arm-softmmu/default.mak
-
-CONFIG_XLNX_ZYNQMP_ARM=y
-CONFIG_XLNX_VERSAL=y
-CONFIG_SBSA_REF=y
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
index cb3e5aea65..647fbce88d 100644
--- a/configs/devices/arm-softmmu/default.mak
+++ b/configs/devices/arm-softmmu/default.mak
@@ -4,40 +4,3 @@
# CONFIG_TEST_DEVICES=n
CONFIG_ARM_VIRT=y
-CONFIG_CUBIEBOARD=y
-CONFIG_EXYNOS4=y
-CONFIG_HIGHBANK=y
-CONFIG_INTEGRATOR=y
-CONFIG_FSL_IMX31=y
-CONFIG_MUSICPAL=y
-CONFIG_MUSCA=y
-CONFIG_CHEETAH=y
-CONFIG_SX1=y
-CONFIG_NSERIES=y
-CONFIG_STELLARIS=y
-CONFIG_STM32VLDISCOVERY=y
-CONFIG_REALVIEW=y
-CONFIG_VERSATILE=y
-CONFIG_VEXPRESS=y
-CONFIG_ZYNQ=y
-CONFIG_MAINSTONE=y
-CONFIG_GUMSTIX=y
-CONFIG_SPITZ=y
-CONFIG_TOSA=y
-CONFIG_Z2=y
-CONFIG_NPCM7XX=y
-CONFIG_COLLIE=y
-CONFIG_ASPEED_SOC=y
-CONFIG_NETDUINO2=y
-CONFIG_NETDUINOPLUS2=y
-CONFIG_OLIMEX_STM32_H405=y
-CONFIG_MPS2=y
-CONFIG_RASPI=y
-CONFIG_DIGIC=y
-CONFIG_SABRELITE=y
-CONFIG_EMCRAFT_SF2=y
-CONFIG_MICROBIT=y
-CONFIG_FSL_IMX25=y
-CONFIG_FSL_IMX7=y
-CONFIG_FSL_IMX6UL=y
-CONFIG_ALLWINNER_H3=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index c0b213f42d..dd189eae2b 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -34,20 +34,24 @@ config ARM_VIRT
config CHEETAH
bool
+ default y if TCG && ARM
select OMAP
select TSC210X
config CUBIEBOARD
bool
+ default y if TCG && ARM
select ALLWINNER_A10
config DIGIC
bool
+ default y if TCG && ARM
select PTIMER
select PFLASH_CFI02
config EXYNOS4
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select A9MPCORE
select I2C
@@ -60,6 +64,7 @@ config EXYNOS4
config HIGHBANK
bool
+ default y if TCG && ARM
select A9MPCORE
select A15MPCORE
select AHCI
@@ -74,6 +79,7 @@ config HIGHBANK
config INTEGRATOR
bool
+ default y if TCG && ARM
select ARM_TIMER
select INTEGRATOR_DEBUG
select PL011 # UART
@@ -86,12 +92,14 @@ config INTEGRATOR
config MAINSTONE
bool
+ default y if TCG && ARM
select PXA2XX
select PFLASH_CFI01
select SMC91C111
config MUSCA
bool
+ default y if TCG && ARM
select ARMSSE
select PL011
select PL031
@@ -103,6 +111,7 @@ config MARVELL_88W8618
config MUSICPAL
bool
+ default y if TCG && ARM
select OR_IRQ
select BITBANG_I2C
select MARVELL_88W8618
@@ -113,18 +122,22 @@ config MUSICPAL
config NETDUINO2
bool
+ default y if TCG && ARM
select STM32F205_SOC
config NETDUINOPLUS2
bool
+ default y if TCG && ARM
select STM32F405_SOC
config OLIMEX_STM32_H405
bool
+ default y if TCG && ARM
select STM32F405_SOC
config NSERIES
bool
+ default y if TCG && ARM
select OMAP
select TMP105 # tempature sensor
select BLIZZARD # LCD/TV controller
@@ -157,12 +170,14 @@ config PXA2XX
config GUMSTIX
bool
+ default y if TCG && ARM
select PFLASH_CFI01
select SMC91C111
select PXA2XX
config TOSA
bool
+ default y if TCG && ARM
select ZAURUS # scoop
select MICRODRIVE
select PXA2XX
@@ -170,6 +185,7 @@ config TOSA
config SPITZ
bool
+ default y if TCG && ARM
select ADS7846 # touch-screen controller
select MAX111X # A/D converter
select WM8750 # audio codec
@@ -182,6 +198,7 @@ config SPITZ
config Z2
bool
+ default y if TCG && ARM
select PFLASH_CFI01
select WM8750
select PL011 # UART
@@ -189,6 +206,7 @@ config Z2
config REALVIEW
bool
+ default y if TCG && ARM
imply PCI_DEVICES
imply PCI_TESTDEV
imply I2C_DEVICES
@@ -217,6 +235,7 @@ config REALVIEW
config SBSA_REF
bool
+ default y if TCG && AARCH64
imply PCI_DEVICES
select AHCI
select ARM_SMMUV3
@@ -232,11 +251,13 @@ config SBSA_REF
config SABRELITE
bool
+ default y if TCG && ARM
select FSL_IMX6
select SSI_M25P80
config STELLARIS
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select ARM_V7M
select CMSDK_APB_WATCHDOG
@@ -254,6 +275,7 @@ config STELLARIS
config STM32VLDISCOVERY
bool
+ default y if TCG && ARM
select STM32F100_SOC
config STRONGARM
@@ -262,16 +284,19 @@ config STRONGARM
config COLLIE
bool
+ default y if TCG && ARM
select PFLASH_CFI01
select ZAURUS # scoop
select STRONGARM
config SX1
bool
+ default y if TCG && ARM
select OMAP
config VERSATILE
bool
+ default y if TCG && ARM
select ARM_TIMER # sp804
select PFLASH_CFI01
select LSI_SCSI_PCI
@@ -283,6 +308,7 @@ config VERSATILE
config VEXPRESS
bool
+ default y if TCG && ARM
select A9MPCORE
select A15MPCORE
select ARM_MPTIMER
@@ -298,6 +324,7 @@ config VEXPRESS
config ZYNQ
bool
+ default y if TCG && ARM
select A9MPCORE
select CADENCE # UART
select PFLASH_CFI02
@@ -314,7 +341,7 @@ config ZYNQ
config ARM_V7M
bool
# currently v7M must be included in a TCG build due to translate.c
- default y if TCG && (ARM || AARCH64)
+ default y if TCG && ARM
select PTIMER
config ALLWINNER_A10
@@ -332,6 +359,7 @@ config ALLWINNER_A10
config ALLWINNER_H3
bool
+ default y if TCG && ARM
select ALLWINNER_A10_PIT
select ALLWINNER_SUN8I_EMAC
select ALLWINNER_I2C
@@ -345,6 +373,7 @@ config ALLWINNER_H3
config RASPI
bool
+ default y if TCG && ARM
select FRAMEBUFFER
select PL011 # UART
select SDHCI
@@ -375,6 +404,7 @@ config STM32F405_SOC
config XLNX_ZYNQMP_ARM
bool
+ default y if TCG && AARCH64
select AHCI
select ARM_GIC
select CADENCE
@@ -392,6 +422,7 @@ config XLNX_ZYNQMP_ARM
config XLNX_VERSAL
bool
+ default y if TCG && AARCH64
select ARM_GIC
select PL011
select CADENCE
@@ -405,6 +436,7 @@ config XLNX_VERSAL
config NPCM7XX
bool
+ default y if TCG && ARM
select A9MPCORE
select ADM1272
select ARM_GIC
@@ -421,6 +453,7 @@ config NPCM7XX
config FSL_IMX25
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select IMX
select IMX_FEC
@@ -430,6 +463,7 @@ config FSL_IMX25
config FSL_IMX31
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select SERIAL
select IMX
@@ -450,6 +484,7 @@ config FSL_IMX6
config ASPEED_SOC
bool
+ default y if TCG && ARM
select DS1338
select FTGMAC100
select I2C
@@ -470,6 +505,7 @@ config ASPEED_SOC
config MPS2
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select ARMSSE
select LAN9118
@@ -485,6 +521,7 @@ config MPS2
config FSL_IMX7
bool
+ default y if TCG && ARM
imply PCI_DEVICES
imply TEST_DEVICES
imply I2C_DEVICES
@@ -503,6 +540,7 @@ config ARM_SMMUV3
config FSL_IMX6UL
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select A15MPCORE
select IMX
@@ -514,6 +552,7 @@ config FSL_IMX6UL
config MICROBIT
bool
+ default y if TCG && ARM
select NRF51_SOC
config NRF51_SOC
@@ -525,6 +564,7 @@ config NRF51_SOC
config EMCRAFT_SF2
bool
+ default y if TCG && ARM
select MSF2
select SSI_M25P80
--
2.35.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH RESEND v7 8/9] gitlab-ci: Check building KVM-only aarch64 target
2023-02-28 19:26 [PATCH RESEND v7 0/9] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (6 preceding siblings ...)
2023-02-28 19:26 ` [PATCH RESEND v7 7/9] arm/Kconfig: Do not build TCG-only boards on a KVM-only build Fabiano Rosas
@ 2023-02-28 19:26 ` Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 9/9] tests/qtest: Fix tests when no KVM or TCG are present Fabiano Rosas
8 siblings, 0 replies; 25+ messages in thread
From: Fabiano Rosas @ 2023-02-28 19:26 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth, Wainer dos Santos Moschetta, Beraldo Leal
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Add a manual new job to cross-build the aarch64 target with
only the KVM accelerator enabled (in particular, no TCG).
Re-enable running the similar job on the project Aarch64
custom runner.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
---
.gitlab-ci.d/crossbuilds.yml | 11 +++++++++++
.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml | 4 ----
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml
index 101416080c..65678e2870 100644
--- a/.gitlab-ci.d/crossbuilds.yml
+++ b/.gitlab-ci.d/crossbuilds.yml
@@ -214,3 +214,14 @@ cross-arm64-xen-only:
IMAGE: debian-arm64-cross
ACCEL: xen
EXTRA_CONFIGURE_OPTS: --disable-tcg --disable-kvm
+
+# Similar job is run by qemu-project's custom runner by default
+cross-arm64-kvm-only:
+ extends: .cross_accel_build_job
+ needs:
+ job: arm64-debian-cross-container
+ variables:
+ QEMU_JOB_OPTIONAL: 1
+ IMAGE: debian-arm64-cross
+ ACCEL: kvm
+ EXTRA_CONFIGURE_OPTS: --disable-tcg --disable-xen --without-default-devices
diff --git a/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml b/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml
index 8ba85be440..770e596242 100644
--- a/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml
+++ b/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml
@@ -115,11 +115,7 @@ ubuntu-22.04-aarch64-notcg:
- aarch64
rules:
- if: '$CI_PROJECT_NAMESPACE == "qemu-project" && $CI_COMMIT_BRANCH =~ /^staging/'
- when: manual
- allow_failure: true
- if: "$AARCH64_RUNNER_AVAILABLE"
- when: manual
- allow_failure: true
script:
- mkdir build
- cd build
--
2.35.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH RESEND v7 9/9] tests/qtest: Fix tests when no KVM or TCG are present
2023-02-28 19:26 [PATCH RESEND v7 0/9] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (7 preceding siblings ...)
2023-02-28 19:26 ` [PATCH RESEND v7 8/9] gitlab-ci: Check building KVM-only aarch64 target Fabiano Rosas
@ 2023-02-28 19:26 ` Fabiano Rosas
2023-03-01 12:14 ` Juan Quintela
2023-03-01 13:04 ` Thomas Huth
8 siblings, 2 replies; 25+ messages in thread
From: Fabiano Rosas @ 2023-02-28 19:26 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Thomas Huth,
Laurent Vivier, Juan Quintela, Dr. David Alan Gilbert
It is possible to have a build with both TCG and KVM disabled due to
Xen requiring the i386 and x86_64 binaries to be present in an aarch64
host.
If we build with --disable-tcg on the aarch64 host, we will end-up
with a QEMU binary (x86) that does not support TCG nor KVM.
Fix tests that crash or hang in the above scenario. Do not include any
test cases if TCG and KVM are missing.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
This currently affects Arm, but will also affect x86 after the xenpvh
series gets merged. This patch fixes both scenarios.
---
tests/qtest/bios-tables-test.c | 4 ++++
tests/qtest/boot-serial-test.c | 10 ++++++++++
tests/qtest/migration-test.c | 5 +++++
tests/qtest/pxe-test.c | 6 ++++++
tests/qtest/vmgenid-test.c | 6 ++++++
5 files changed, 31 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index d29a4e47af..f6c2a010d2 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -2114,6 +2114,10 @@ int main(int argc, char *argv[])
char *v_env = getenv("V");
int ret;
+ if (!has_tcg && !has_kvm) {
+ return 0;
+ }
+
if (v_env) {
verbosity_level = atoi(v_env);
}
diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
index 3aef3a97a9..45490f5931 100644
--- a/tests/qtest/boot-serial-test.c
+++ b/tests/qtest/boot-serial-test.c
@@ -17,6 +17,9 @@
#include "libqtest.h"
#include "libqos/libqos-spapr.h"
+static bool has_tcg;
+static bool has_kvm;
+
static const uint8_t bios_avr[] = {
0x88, 0xe0, /* ldi r24, 0x08 */
0x80, 0x93, 0xc1, 0x00, /* sts 0x00C1, r24 ; Enable tx */
@@ -285,6 +288,13 @@ int main(int argc, char *argv[])
const char *arch = qtest_get_arch();
int i;
+ has_tcg = qtest_has_accel("tcg");
+ has_kvm = qtest_has_accel("kvm");
+
+ if (!has_tcg && !has_kvm) {
+ return 0;
+ }
+
g_test_init(&argc, &argv, NULL);
for (i = 0; tests[i].arch != NULL; i++) {
diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
index 109bc8e7b1..a6e3ca9f7d 100644
--- a/tests/qtest/migration-test.c
+++ b/tests/qtest/migration-test.c
@@ -2460,11 +2460,16 @@ static bool kvm_dirty_ring_supported(void)
int main(int argc, char **argv)
{
const bool has_kvm = qtest_has_accel("kvm");
+ const bool has_tcg = qtest_has_accel("tcg");
const bool has_uffd = ufd_version_check();
const char *arch = qtest_get_arch();
g_autoptr(GError) err = NULL;
int ret;
+ if (!has_tcg && !has_kvm) {
+ return 0;
+ }
+
g_test_init(&argc, &argv, NULL);
/*
diff --git a/tests/qtest/pxe-test.c b/tests/qtest/pxe-test.c
index 62b6eef464..05575f7687 100644
--- a/tests/qtest/pxe-test.c
+++ b/tests/qtest/pxe-test.c
@@ -130,6 +130,12 @@ int main(int argc, char *argv[])
{
int ret;
const char *arch = qtest_get_arch();
+ bool has_tcg = qtest_has_accel("tcg");
+ bool has_kvm = qtest_has_accel("kvm");
+
+ if (!has_tcg && !has_kvm) {
+ return 0;
+ }
ret = boot_sector_init(disk);
if(ret)
diff --git a/tests/qtest/vmgenid-test.c b/tests/qtest/vmgenid-test.c
index efba76e716..8045d3d706 100644
--- a/tests/qtest/vmgenid-test.c
+++ b/tests/qtest/vmgenid-test.c
@@ -164,6 +164,12 @@ static void vmgenid_query_monitor_test(void)
int main(int argc, char **argv)
{
int ret;
+ bool has_tcg = qtest_has_accel("tcg");
+ bool has_kvm = qtest_has_accel("kvm");
+
+ if (!has_tcg && !has_kvm) {
+ return 0;
+ }
ret = boot_sector_init(disk);
if (ret) {
--
2.35.3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH RESEND v7 1/9] target/arm: Move cortex sysregs into a separate file
2023-02-28 19:26 ` [PATCH RESEND v7 1/9] target/arm: Move cortex sysregs into a separate file Fabiano Rosas
@ 2023-03-01 1:21 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2023-03-01 1:21 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck
On 2/28/23 09:26, Fabiano Rosas wrote:
> The file cpu_tcg.c is about to be moved into the tcg/ directory, so
> move the register definitions into a new file.
>
> Also move the function declaration to the more appropriate cpregs.h.
>
> Signed-off-by: Fabiano Rosas<farosas@suse.de>
> ---
> target/arm/cortex-regs.c | 69 ++++++++++++++++++++++++++++++++++++++++
> target/arm/cpregs.h | 6 ++++
> target/arm/cpu64.c | 1 +
> target/arm/cpu_tcg.c | 59 ----------------------------------
> target/arm/internals.h | 6 ----
> target/arm/meson.build | 1 +
> 6 files changed, 77 insertions(+), 65 deletions(-)
> create mode 100644 target/arm/cortex-regs.c
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH RESEND v7 9/9] tests/qtest: Fix tests when no KVM or TCG are present
2023-02-28 19:26 ` [PATCH RESEND v7 9/9] tests/qtest: Fix tests when no KVM or TCG are present Fabiano Rosas
@ 2023-03-01 12:14 ` Juan Quintela
2023-03-01 12:25 ` Fabiano Rosas
2023-03-01 13:04 ` Thomas Huth
1 sibling, 1 reply; 25+ messages in thread
From: Juan Quintela @ 2023-03-01 12:14 UTC (permalink / raw)
To: Fabiano Rosas
Cc: qemu-devel, qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Thomas Huth,
Laurent Vivier, Dr. David Alan Gilbert
Fabiano Rosas <farosas@suse.de> wrote:
> It is possible to have a build with both TCG and KVM disabled due to
> Xen requiring the i386 and x86_64 binaries to be present in an aarch64
> host.
Ouch.
Just curious: why are they needed?
>
> If we build with --disable-tcg on the aarch64 host, we will end-up
> with a QEMU binary (x86) that does not support TCG nor KVM.
>
> Fix tests that crash or hang in the above scenario. Do not include any
> test cases if TCG and KVM are missing.
>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
> This currently affects Arm, but will also affect x86 after the xenpvh
> series gets merged. This patch fixes both scenarios.
Reviewed-by: Juan Quintela <quintela@redhat.com>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH RESEND v7 9/9] tests/qtest: Fix tests when no KVM or TCG are present
2023-03-01 12:14 ` Juan Quintela
@ 2023-03-01 12:25 ` Fabiano Rosas
2023-03-01 12:57 ` Alex Bennée
0 siblings, 1 reply; 25+ messages in thread
From: Fabiano Rosas @ 2023-03-01 12:25 UTC (permalink / raw)
To: quintela
Cc: qemu-devel, qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Thomas Huth,
Laurent Vivier, Dr. David Alan Gilbert
Juan Quintela <quintela@redhat.com> writes:
> Fabiano Rosas <farosas@suse.de> wrote:
>> It is possible to have a build with both TCG and KVM disabled due to
>> Xen requiring the i386 and x86_64 binaries to be present in an aarch64
>> host.
>
> Ouch.
>
> Just curious: why are they needed?
>
From https://wiki.xenproject.org/wiki/QEMU_Upstream:
Why is qemu-system-i386 used even on x86_64 and even non-x86?
QEMU in a Xen system only provides device model (DM) emulation and not
any CPU instruction emulation, so the nominal arch doesn't actually
matter and Xen builds i386 everywhere as a basically arbitrary choice.
It happens that the Xen DM part of QEMU is quite closely tied to the x86
scaffolding for various historical reasons, so we end up using
qemu-system-i386 even e.g. on ARM! There is no practical difference
between qemu-system-i386 and qemu-system-x86_64, they should be
interchangeable. However only qemu-system-i386 is regularly tested by
Xen Project (via osstest).
>>
>> If we build with --disable-tcg on the aarch64 host, we will end-up
>> with a QEMU binary (x86) that does not support TCG nor KVM.
>>
>> Fix tests that crash or hang in the above scenario. Do not include any
>> test cases if TCG and KVM are missing.
>>
>> Signed-off-by: Fabiano Rosas <farosas@suse.de>
>> ---
>> This currently affects Arm, but will also affect x86 after the xenpvh
>> series gets merged. This patch fixes both scenarios.
>
> Reviewed-by: Juan Quintela <quintela@redhat.com>
Thanks!
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH RESEND v7 9/9] tests/qtest: Fix tests when no KVM or TCG are present
2023-03-01 12:25 ` Fabiano Rosas
@ 2023-03-01 12:57 ` Alex Bennée
2023-03-01 13:34 ` Fabiano Rosas
0 siblings, 1 reply; 25+ messages in thread
From: Alex Bennée @ 2023-03-01 12:57 UTC (permalink / raw)
To: Fabiano Rosas
Cc: quintela, qemu-devel, qemu-arm, Peter Maydell,
Philippe Mathieu-Daudé,
Richard Henderson, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Thomas Huth,
Laurent Vivier, Dr. David Alan Gilbert
Fabiano Rosas <farosas@suse.de> writes:
> Juan Quintela <quintela@redhat.com> writes:
>
>> Fabiano Rosas <farosas@suse.de> wrote:
>>> It is possible to have a build with both TCG and KVM disabled due to
>>> Xen requiring the i386 and x86_64 binaries to be present in an aarch64
>>> host.
>>
>> Ouch.
>>
>> Just curious: why are they needed?
>>
>
> From https://wiki.xenproject.org/wiki/QEMU_Upstream:
>
> Why is qemu-system-i386 used even on x86_64 and even non-x86?
>
> QEMU in a Xen system only provides device model (DM) emulation and not
> any CPU instruction emulation, so the nominal arch doesn't actually
> matter and Xen builds i386 everywhere as a basically arbitrary choice.
>
> It happens that the Xen DM part of QEMU is quite closely tied to the x86
> scaffolding for various historical reasons, so we end up using
> qemu-system-i386 even e.g. on ARM! There is no practical difference
> between qemu-system-i386 and qemu-system-x86_64, they should be
> interchangeable. However only qemu-system-i386 is regularly tested by
> Xen Project (via osstest).
That said with the xenpvh model that was added recently we should be
able to finally build a Xen only qemu-system-aarch64 which while
functionally the same will be less head scratching for users.
>
>>>
>>> If we build with --disable-tcg on the aarch64 host, we will end-up
>>> with a QEMU binary (x86) that does not support TCG nor KVM.
>>>
>>> Fix tests that crash or hang in the above scenario. Do not include any
>>> test cases if TCG and KVM are missing.
>>>
>>> Signed-off-by: Fabiano Rosas <farosas@suse.de>
>>> ---
>>> This currently affects Arm, but will also affect x86 after the xenpvh
>>> series gets merged. This patch fixes both scenarios.
>>
>> Reviewed-by: Juan Quintela <quintela@redhat.com>
>
> Thanks!
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH RESEND v7 9/9] tests/qtest: Fix tests when no KVM or TCG are present
2023-02-28 19:26 ` [PATCH RESEND v7 9/9] tests/qtest: Fix tests when no KVM or TCG are present Fabiano Rosas
2023-03-01 12:14 ` Juan Quintela
@ 2023-03-01 13:04 ` Thomas Huth
2023-03-01 13:31 ` Fabiano Rosas
1 sibling, 1 reply; 25+ messages in thread
From: Thomas Huth @ 2023-03-01 13:04 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Laurent Vivier,
Juan Quintela, Dr. David Alan Gilbert
On 28/02/2023 20.26, Fabiano Rosas wrote:
> It is possible to have a build with both TCG and KVM disabled due to
> Xen requiring the i386 and x86_64 binaries to be present in an aarch64
> host.
>
> If we build with --disable-tcg on the aarch64 host, we will end-up
> with a QEMU binary (x86) that does not support TCG nor KVM.
>
> Fix tests that crash or hang in the above scenario. Do not include any
> test cases if TCG and KVM are missing.
>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
...
> diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
> index 3aef3a97a9..45490f5931 100644
> --- a/tests/qtest/boot-serial-test.c
> +++ b/tests/qtest/boot-serial-test.c
> @@ -17,6 +17,9 @@
> #include "libqtest.h"
> #include "libqos/libqos-spapr.h"
>
> +static bool has_tcg;
> +static bool has_kvm;
Any special reason for putting these here instead of making them local
variables in the main() function?
> static const uint8_t bios_avr[] = {
> 0x88, 0xe0, /* ldi r24, 0x08 */
> 0x80, 0x93, 0xc1, 0x00, /* sts 0x00C1, r24 ; Enable tx */
> @@ -285,6 +288,13 @@ int main(int argc, char *argv[])
> const char *arch = qtest_get_arch();
> int i;
>
> + has_tcg = qtest_has_accel("tcg");
> + has_kvm = qtest_has_accel("kvm");
> +
> + if (!has_tcg && !has_kvm) {
> + return 0;
> + }
> +
> g_test_init(&argc, &argv, NULL);
Could you please put the new code below the g_test_init() ?
Just to avoid the problem that has been reported here:
https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg08331.html
Thanks,
Thomas
> for (i = 0; tests[i].arch != NULL; i++) {
> diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
> index 109bc8e7b1..a6e3ca9f7d 100644
> --- a/tests/qtest/migration-test.c
> +++ b/tests/qtest/migration-test.c
> @@ -2460,11 +2460,16 @@ static bool kvm_dirty_ring_supported(void)
> int main(int argc, char **argv)
> {
> const bool has_kvm = qtest_has_accel("kvm");
> + const bool has_tcg = qtest_has_accel("tcg");
> const bool has_uffd = ufd_version_check();
> const char *arch = qtest_get_arch();
> g_autoptr(GError) err = NULL;
> int ret;
>
> + if (!has_tcg && !has_kvm) {
> + return 0;
> + }
> +
> g_test_init(&argc, &argv, NULL);
>
> /*
> diff --git a/tests/qtest/pxe-test.c b/tests/qtest/pxe-test.c
> index 62b6eef464..05575f7687 100644
> --- a/tests/qtest/pxe-test.c
> +++ b/tests/qtest/pxe-test.c
> @@ -130,6 +130,12 @@ int main(int argc, char *argv[])
> {
> int ret;
> const char *arch = qtest_get_arch();
> + bool has_tcg = qtest_has_accel("tcg");
> + bool has_kvm = qtest_has_accel("kvm");
> +
> + if (!has_tcg && !has_kvm) {
> + return 0;
> + }
>
> ret = boot_sector_init(disk);
> if(ret)
> diff --git a/tests/qtest/vmgenid-test.c b/tests/qtest/vmgenid-test.c
> index efba76e716..8045d3d706 100644
> --- a/tests/qtest/vmgenid-test.c
> +++ b/tests/qtest/vmgenid-test.c
> @@ -164,6 +164,12 @@ static void vmgenid_query_monitor_test(void)
> int main(int argc, char **argv)
> {
> int ret;
> + bool has_tcg = qtest_has_accel("tcg");
> + bool has_kvm = qtest_has_accel("kvm");
> +
> + if (!has_tcg && !has_kvm) {
> + return 0;
> + }
>
> ret = boot_sector_init(disk);
> if (ret) {
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH RESEND v7 4/9] target/arm: move cpu_tcg to tcg/cpu32.c
2023-02-28 19:26 ` [PATCH RESEND v7 4/9] target/arm: move cpu_tcg to tcg/cpu32.c Fabiano Rosas
@ 2023-03-01 13:06 ` Thomas Huth
0 siblings, 0 replies; 25+ messages in thread
From: Thomas Huth @ 2023-03-01 13:06 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Laurent Vivier
On 28/02/2023 20.26, Fabiano Rosas wrote:
> From: Claudio Fontana <cfontana@suse.de>
>
> move the module containing cpu models definitions
> for 32bit TCG-only CPUs to tcg/ and rename it for clarity.
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
...
> diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
> index 1cb08138ad..1555b0bab8 100644
> --- a/tests/qtest/arm-cpu-features.c
> +++ b/tests/qtest/arm-cpu-features.c
> @@ -506,9 +506,15 @@ static void test_query_cpu_model_expansion_kvm(const void *data)
> QDict *resp;
> char *error;
>
> - assert_error(qts, "cortex-a15",
> - "We cannot guarantee the CPU type 'cortex-a15' works "
> - "with KVM on this host", NULL);
> + if (qtest_has_accel("tcg")) {
> + assert_error(qts, "cortex-a15",
> + "We cannot guarantee the CPU type 'cortex-a15' works "
> + "with KVM on this host", NULL);
> + } else {
> + assert_error(qts, "cortex-a15",
> + "The CPU type 'cortex-a15' is not a "
> + "recognized ARM CPU type", NULL);
> + }
>
> assert_has_feature_enabled(qts, "host", "aarch64");
>
FWIW:
Acked-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH RESEND v7 9/9] tests/qtest: Fix tests when no KVM or TCG are present
2023-03-01 13:04 ` Thomas Huth
@ 2023-03-01 13:31 ` Fabiano Rosas
2023-03-01 13:43 ` Fabiano Rosas
0 siblings, 1 reply; 25+ messages in thread
From: Fabiano Rosas @ 2023-03-01 13:31 UTC (permalink / raw)
To: Thomas Huth, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Laurent Vivier,
Juan Quintela, Dr. David Alan Gilbert
Thomas Huth <thuth@redhat.com> writes:
> On 28/02/2023 20.26, Fabiano Rosas wrote:
>> It is possible to have a build with both TCG and KVM disabled due to
>> Xen requiring the i386 and x86_64 binaries to be present in an aarch64
>> host.
>>
>> If we build with --disable-tcg on the aarch64 host, we will end-up
>> with a QEMU binary (x86) that does not support TCG nor KVM.
>>
>> Fix tests that crash or hang in the above scenario. Do not include any
>> test cases if TCG and KVM are missing.
>>
>> Signed-off-by: Fabiano Rosas <farosas@suse.de>
>> ---
> ...
>> diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
>> index 3aef3a97a9..45490f5931 100644
>> --- a/tests/qtest/boot-serial-test.c
>> +++ b/tests/qtest/boot-serial-test.c
>> @@ -17,6 +17,9 @@
>> #include "libqtest.h"
>> #include "libqos/libqos-spapr.h"
>>
>> +static bool has_tcg;
>> +static bool has_kvm;
>
> Any special reason for putting these here instead of making them local
> variables in the main() function?
>
Yes, Phillipe was doing work in the same file and I put it here to
minimize conflicts.
https://lore.kernel.org/r/20230119145838.41835-5-philmd@linaro.org
>> static const uint8_t bios_avr[] = {
>> 0x88, 0xe0, /* ldi r24, 0x08 */
>> 0x80, 0x93, 0xc1, 0x00, /* sts 0x00C1, r24 ; Enable tx */
>> @@ -285,6 +288,13 @@ int main(int argc, char *argv[])
>> const char *arch = qtest_get_arch();
>> int i;
>>
>> + has_tcg = qtest_has_accel("tcg");
>> + has_kvm = qtest_has_accel("kvm");
>> +
>> + if (!has_tcg && !has_kvm) {
>> + return 0;
>> + }
>> +
>> g_test_init(&argc, &argv, NULL);
>
> Could you please put the new code below the g_test_init() ?
> Just to avoid the problem that has been reported here:
>
> https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg08331.html
>
I could, but I don't understand why we need this. What does having
"code" before g_test_init() causes? Should I move the qtest_get_arch()
that's already there as well?
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH RESEND v7 9/9] tests/qtest: Fix tests when no KVM or TCG are present
2023-03-01 12:57 ` Alex Bennée
@ 2023-03-01 13:34 ` Fabiano Rosas
0 siblings, 0 replies; 25+ messages in thread
From: Fabiano Rosas @ 2023-03-01 13:34 UTC (permalink / raw)
To: Alex Bennée
Cc: quintela, qemu-devel, qemu-arm, Peter Maydell,
Philippe Mathieu-Daudé,
Richard Henderson, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Thomas Huth,
Laurent Vivier, Dr. David Alan Gilbert
Alex Bennée <alex.bennee@linaro.org> writes:
> Fabiano Rosas <farosas@suse.de> writes:
>
>> Juan Quintela <quintela@redhat.com> writes:
>>
>>> Fabiano Rosas <farosas@suse.de> wrote:
>>>> It is possible to have a build with both TCG and KVM disabled due to
>>>> Xen requiring the i386 and x86_64 binaries to be present in an aarch64
>>>> host.
>>>
>>> Ouch.
>>>
>>> Just curious: why are they needed?
>>>
>>
>> From https://wiki.xenproject.org/wiki/QEMU_Upstream:
>>
>> Why is qemu-system-i386 used even on x86_64 and even non-x86?
>>
>> QEMU in a Xen system only provides device model (DM) emulation and not
>> any CPU instruction emulation, so the nominal arch doesn't actually
>> matter and Xen builds i386 everywhere as a basically arbitrary choice.
>>
>> It happens that the Xen DM part of QEMU is quite closely tied to the x86
>> scaffolding for various historical reasons, so we end up using
>> qemu-system-i386 even e.g. on ARM! There is no practical difference
>> between qemu-system-i386 and qemu-system-x86_64, they should be
>> interchangeable. However only qemu-system-i386 is regularly tested by
>> Xen Project (via osstest).
>
> That said with the xenpvh model that was added recently we should be
> able to finally build a Xen only qemu-system-aarch64 which while
> functionally the same will be less head scratching for users.
>
It would be nice if we could eventually restrict the x86 build to the
x86 host and the aarch64 build to the aarch64 host like we do for the
other HW accels.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH RESEND v7 9/9] tests/qtest: Fix tests when no KVM or TCG are present
2023-03-01 13:31 ` Fabiano Rosas
@ 2023-03-01 13:43 ` Fabiano Rosas
2023-03-01 13:50 ` Thomas Huth
0 siblings, 1 reply; 25+ messages in thread
From: Fabiano Rosas @ 2023-03-01 13:43 UTC (permalink / raw)
To: Thomas Huth, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Laurent Vivier,
Juan Quintela, Dr. David Alan Gilbert
Fabiano Rosas <farosas@suse.de> writes:
> Thomas Huth <thuth@redhat.com> writes:
>
>> On 28/02/2023 20.26, Fabiano Rosas wrote:
>>> It is possible to have a build with both TCG and KVM disabled due to
>>> Xen requiring the i386 and x86_64 binaries to be present in an aarch64
>>> host.
>>>
>>> If we build with --disable-tcg on the aarch64 host, we will end-up
>>> with a QEMU binary (x86) that does not support TCG nor KVM.
>>>
>>> Fix tests that crash or hang in the above scenario. Do not include any
>>> test cases if TCG and KVM are missing.
>>>
>>> Signed-off-by: Fabiano Rosas <farosas@suse.de>
>>> ---
>> ...
>>> diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
>>> index 3aef3a97a9..45490f5931 100644
>>> --- a/tests/qtest/boot-serial-test.c
>>> +++ b/tests/qtest/boot-serial-test.c
>>> @@ -17,6 +17,9 @@
>>> #include "libqtest.h"
>>> #include "libqos/libqos-spapr.h"
>>>
>>> +static bool has_tcg;
>>> +static bool has_kvm;
>>
>> Any special reason for putting these here instead of making them local
>> variables in the main() function?
>>
>
> Yes, Phillipe was doing work in the same file and I put it here to
> minimize conflicts.
>
> https://lore.kernel.org/r/20230119145838.41835-5-philmd@linaro.org
>
>>> static const uint8_t bios_avr[] = {
>>> 0x88, 0xe0, /* ldi r24, 0x08 */
>>> 0x80, 0x93, 0xc1, 0x00, /* sts 0x00C1, r24 ; Enable tx */
>>> @@ -285,6 +288,13 @@ int main(int argc, char *argv[])
>>> const char *arch = qtest_get_arch();
>>> int i;
>>>
>>> + has_tcg = qtest_has_accel("tcg");
>>> + has_kvm = qtest_has_accel("kvm");
>>> +
>>> + if (!has_tcg && !has_kvm) {
>>> + return 0;
>>> + }
>>> +
>>> g_test_init(&argc, &argv, NULL);
>>
>> Could you please put the new code below the g_test_init() ?
>> Just to avoid the problem that has been reported here:
>>
>> https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg08331.html
>>
>
> I could, but I don't understand why we need this. What does having
> "code" before g_test_init() causes? Should I move the qtest_get_arch()
> that's already there as well?
Oh, the issue is the early return? I guess it makes sense.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH RESEND v7 9/9] tests/qtest: Fix tests when no KVM or TCG are present
2023-03-01 13:43 ` Fabiano Rosas
@ 2023-03-01 13:50 ` Thomas Huth
0 siblings, 0 replies; 25+ messages in thread
From: Thomas Huth @ 2023-03-01 13:50 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Laurent Vivier,
Juan Quintela, Dr. David Alan Gilbert
On 01/03/2023 14.43, Fabiano Rosas wrote:
> Fabiano Rosas <farosas@suse.de> writes:
>
>> Thomas Huth <thuth@redhat.com> writes:
>>
>>> On 28/02/2023 20.26, Fabiano Rosas wrote:
>>>> It is possible to have a build with both TCG and KVM disabled due to
>>>> Xen requiring the i386 and x86_64 binaries to be present in an aarch64
>>>> host.
>>>>
>>>> If we build with --disable-tcg on the aarch64 host, we will end-up
>>>> with a QEMU binary (x86) that does not support TCG nor KVM.
>>>>
>>>> Fix tests that crash or hang in the above scenario. Do not include any
>>>> test cases if TCG and KVM are missing.
>>>>
>>>> Signed-off-by: Fabiano Rosas <farosas@suse.de>
>>>> ---
>>> ...
>>>> diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
>>>> index 3aef3a97a9..45490f5931 100644
>>>> --- a/tests/qtest/boot-serial-test.c
>>>> +++ b/tests/qtest/boot-serial-test.c
>>>> @@ -17,6 +17,9 @@
>>>> #include "libqtest.h"
>>>> #include "libqos/libqos-spapr.h"
>>>>
>>>> +static bool has_tcg;
>>>> +static bool has_kvm;
>>>
>>> Any special reason for putting these here instead of making them local
>>> variables in the main() function?
>>>
>>
>> Yes, Phillipe was doing work in the same file and I put it here to
>> minimize conflicts.
>>
>> https://lore.kernel.org/r/20230119145838.41835-5-philmd@linaro.org
>>
>>>> static const uint8_t bios_avr[] = {
>>>> 0x88, 0xe0, /* ldi r24, 0x08 */
>>>> 0x80, 0x93, 0xc1, 0x00, /* sts 0x00C1, r24 ; Enable tx */
>>>> @@ -285,6 +288,13 @@ int main(int argc, char *argv[])
>>>> const char *arch = qtest_get_arch();
>>>> int i;
>>>>
>>>> + has_tcg = qtest_has_accel("tcg");
>>>> + has_kvm = qtest_has_accel("kvm");
>>>> +
>>>> + if (!has_tcg && !has_kvm) {
>>>> + return 0;
>>>> + }
>>>> +
>>>> g_test_init(&argc, &argv, NULL);
>>>
>>> Could you please put the new code below the g_test_init() ?
>>> Just to avoid the problem that has been reported here:
>>>
>>> https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg08331.html
>>>
>>
>> I could, but I don't understand why we need this. What does having
>> "code" before g_test_init() causes? Should I move the qtest_get_arch()
>> that's already there as well?
>
> Oh, the issue is the early return? I guess it makes sense.
Yes, as far as I've undrestood the issue: If we call a function that starts
a QEMU subprocess (like qtest_has_device() or qtest_has_accel()), then this
could spoil the output since the TAP version from g_test_init() should come
first.
qtest_get_arch() is not a problem, since it does not start a QEMU subprocess.
Thomas
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH RESEND v7 5/9] tests/avocado: Pass parameters to migration test
2023-02-28 19:26 ` [PATCH RESEND v7 5/9] tests/avocado: Pass parameters to migration test Fabiano Rosas
@ 2023-03-03 16:22 ` Peter Maydell
2023-03-03 20:59 ` Fabiano Rosas
2023-03-06 13:14 ` Dr. David Alan Gilbert
0 siblings, 2 replies; 25+ messages in thread
From: Peter Maydell @ 2023-03-03 16:22 UTC (permalink / raw)
To: Fabiano Rosas, Dr. David Alan Gilbert
Cc: qemu-devel, qemu-arm, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Cleber Rosa, Wainer dos Santos Moschetta, Beraldo Leal
On Tue, 28 Feb 2023 at 19:28, Fabiano Rosas <farosas@suse.de> wrote:
>
> The migration tests are currently broken for an aarch64 host because
> the tests pass no 'machine' and 'cpu' options on the QEMU command
> line.
>
> Add a separate class to each architecture so that we can specify
> 'machine' and 'cpu' options instead of relying on defaults.
>
> Add a skip decorator to keep the current behavior of only running
> migration tests when the qemu target matches the host architecture.
I still don't understand this patch. Don't we run the
migration-test on all hosts already? David ?
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
> tests/avocado/migration.py | 83 +++++++++++++++++++++++++++++++++++---
> 1 file changed, 78 insertions(+), 5 deletions(-)
>
> diff --git a/tests/avocado/migration.py b/tests/avocado/migration.py
> index 4b25680c50..8b2ec0e3c4 100644
> --- a/tests/avocado/migration.py
> +++ b/tests/avocado/migration.py
> @@ -11,6 +11,8 @@
>
>
> import tempfile
> +import os
> +
> from avocado_qemu import QemuSystemTest
> from avocado import skipUnless
>
> @@ -19,7 +21,7 @@
> from avocado.utils.path import find_command
>
>
> -class Migration(QemuSystemTest):
> +class MigrationTest(QemuSystemTest):
> """
> :avocado: tags=migration
> """
> @@ -62,20 +64,91 @@ def _get_free_port(self):
> self.cancel('Failed to find a free port')
> return port
>
> -
> - def test_migration_with_tcp_localhost(self):
> + def migration_with_tcp_localhost(self):
> dest_uri = 'tcp:localhost:%u' % self._get_free_port()
> self.do_migrate(dest_uri)
>
> - def test_migration_with_unix(self):
> + def migration_with_unix(self):
> with tempfile.TemporaryDirectory(prefix='socket_') as socket_path:
> dest_uri = 'unix:%s/qemu-test.sock' % socket_path
> self.do_migrate(dest_uri)
>
> @skipUnless(find_command('nc', default=False), "'nc' command not found")
> - def test_migration_with_exec(self):
> + def migration_with_exec(self):
> """The test works for both netcat-traditional and netcat-openbsd packages."""
> free_port = self._get_free_port()
> dest_uri = 'exec:nc -l localhost %u' % free_port
> src_uri = 'exec:nc localhost %u' % free_port
> self.do_migrate(dest_uri, src_uri)
> +
> +
> +@skipUnless('aarch64' in os.uname()[4], "host != target")
> +class Aarch64(MigrationTest):
> + """
> + :avocado: tags=arch:aarch64
> + :avocado: tags=machine:virt
> + :avocado: tags=cpu:max
> + """
> +
> + def test_migration_with_tcp_localhost(self):
> + self.migration_with_tcp_localhost()
> +
> + def test_migration_with_unix(self):
> + self.migration_with_unix()
> +
> + def test_migration_with_exec(self):
> + self.migration_with_exec()
> +
> +
> +@skipUnless('x86_64' in os.uname()[4], "host != target")
> +class X86_64(MigrationTest):
> + """
> + :avocado: tags=arch:x86_64
> + :avocado: tags=machine:pc
> + :avocado: tags=cpu:qemu64
> + """
> +
> + def test_migration_with_tcp_localhost(self):
> + self.migration_with_tcp_localhost()
> +
> + def test_migration_with_unix(self):
> + self.migration_with_unix()
> +
> + def test_migration_with_exec(self):
> + self.migration_with_exec()
> +
> +
> +@skipUnless('ppc64le' in os.uname()[4], "host != target")
> +class PPC64(MigrationTest):
> + """
> + :avocado: tags=arch:ppc64
> + :avocado: tags=machine:pseries
> + :avocado: tags=cpu:power9_v2.0
> + """
> +
> + def test_migration_with_tcp_localhost(self):
> + self.migration_with_tcp_localhost()
> +
> + def test_migration_with_unix(self):
> + self.migration_with_unix()
> +
> + def test_migration_with_exec(self):
> + self.migration_with_exec()
> +
> +
> +@skipUnless('s390x' in os.uname()[4], "host != target")
> +class S390X(MigrationTest):
> + """
> + :avocado: tags=arch:s390x
> + :avocado: tags=machine:s390-ccw-virtio
> + :avocado: tags=cpu:qemu
> + """
> +
> + def test_migration_with_tcp_localhost(self):
> + self.migration_with_tcp_localhost()
> +
> + def test_migration_with_unix(self):
> + self.migration_with_unix()
> +
> + def test_migration_with_exec(self):
> + self.migration_with_exec()
> --
> 2.35.3
thanks
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH RESEND v7 5/9] tests/avocado: Pass parameters to migration test
2023-03-03 16:22 ` Peter Maydell
@ 2023-03-03 20:59 ` Fabiano Rosas
2023-03-04 14:10 ` Peter Maydell
2023-03-06 13:14 ` Dr. David Alan Gilbert
1 sibling, 1 reply; 25+ messages in thread
From: Fabiano Rosas @ 2023-03-03 20:59 UTC (permalink / raw)
To: Peter Maydell, Dr. David Alan Gilbert
Cc: qemu-devel, qemu-arm, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Cleber Rosa, Wainer dos Santos Moschetta, Beraldo Leal
Peter Maydell <peter.maydell@linaro.org> writes:
> On Tue, 28 Feb 2023 at 19:28, Fabiano Rosas <farosas@suse.de> wrote:
>>
>> The migration tests are currently broken for an aarch64 host because
>> the tests pass no 'machine' and 'cpu' options on the QEMU command
>> line.
>>
>> Add a separate class to each architecture so that we can specify
>> 'machine' and 'cpu' options instead of relying on defaults.
>>
>> Add a skip decorator to keep the current behavior of only running
>> migration tests when the qemu target matches the host architecture.
>
> I still don't understand this patch. Don't we run the
> migration-test on all hosts already? David ?
>
We run on all hosts but for each host we only take the QEMU binary that
matches the host architecture. So if you want to test aarch64 migration,
you need an aarch64 host.
If you run on an x86_64 host (without this patch):
$ ../configure #all targets
$ make check-avocado AVOCADO_TESTS=../tests/avocado/migration.py
You'll see:
(1/3) ... migration.py:Migration.test_migration_with_tcp_localhost: PASS (0.21 s)
(2/3) ... migration.py:Migration.test_migration_with_unix: PASS (0.18 s)
(3/3) ... migration.py:Migration.test_migration_with_exec: PASS (0.21 s)
All three tests ran using qemu-system-x86_64.
The issue I'm trying to solve is that when run on a aarch64 host, the
test will fail because (being generic) it doesn't pass the '-machine
virt' option and there is no architecture-specific information in it at
all.
If we need to pass '-machine virt' to the arm machine, then something
needs to change to add architecture-specific knowledge into the test. My
first version hardcoded the usual "if arch == foo". That was frowned
upon, so this version creates a class for each architecture like other
tests do (e.g. boot_linux.py).
The downside of this is that we need to explicitly enumerate the host
architectures on which we want the test to run. I chose a few of the
obvious, but we might need to add more.
The upside is that we could now enable the test to run with all the
targets present in the build. If we remove the @skip decorators from
this patch, we'd get (note the arch strings):
(01/12) ... migration.py:Aarch64.test_migration_with_tcp_localhost: PASS (0.19 s)
(02/12) ... migration.py:Aarch64.test_migration_with_unix: PASS (0.16 s)
(03/12) ... migration.py:Aarch64.test_migration_with_exec: PASS (0.20 s)
^
(04/12) ... migration.py:X86_64.test_migration_with_tcp_localhost: PASS (0.21 s)
(05/12) ... migration.py:X86_64.test_migration_with_unix: PASS (0.18 s)
(06/12) ... migration.py:X86_64.test_migration_with_exec: PASS (0.21 s)
^
(07/12) ... migration.py:PPC64.test_migration_with_tcp_localhost: PASS (0.20 s)
(08/12) ... migration.py:PPC64.test_migration_with_unix: PASS (0.17 s)
(09/12) ... migration.py:PPC64.test_migration_with_exec: PASS (0.20 s)
^
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH RESEND v7 5/9] tests/avocado: Pass parameters to migration test
2023-03-03 20:59 ` Fabiano Rosas
@ 2023-03-04 14:10 ` Peter Maydell
2023-03-06 17:06 ` Fabiano Rosas
0 siblings, 1 reply; 25+ messages in thread
From: Peter Maydell @ 2023-03-04 14:10 UTC (permalink / raw)
To: Fabiano Rosas
Cc: Dr. David Alan Gilbert, qemu-devel, qemu-arm,
Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Cleber Rosa, Wainer dos Santos Moschetta, Beraldo Leal
On Fri, 3 Mar 2023 at 20:59, Fabiano Rosas <farosas@suse.de> wrote:
>
> Peter Maydell <peter.maydell@linaro.org> writes:
>
> > On Tue, 28 Feb 2023 at 19:28, Fabiano Rosas <farosas@suse.de> wrote:
> >>
> >> The migration tests are currently broken for an aarch64 host because
> >> the tests pass no 'machine' and 'cpu' options on the QEMU command
> >> line.
> >>
> >> Add a separate class to each architecture so that we can specify
> >> 'machine' and 'cpu' options instead of relying on defaults.
> >>
> >> Add a skip decorator to keep the current behavior of only running
> >> migration tests when the qemu target matches the host architecture.
> >
> > I still don't understand this patch. Don't we run the
> > migration-test on all hosts already? David ?
> >
>
> We run on all hosts but for each host we only take the QEMU binary that
> matches the host architecture. So if you want to test aarch64 migration,
> you need an aarch64 host.
>
> If you run on an x86_64 host (without this patch):
> $ ../configure #all targets
> $ make check-avocado AVOCADO_TESTS=../tests/avocado/migration.py
>
> You'll see:
>
> (1/3) ... migration.py:Migration.test_migration_with_tcp_localhost: PASS (0.21 s)
> (2/3) ... migration.py:Migration.test_migration_with_unix: PASS (0.18 s)
> (3/3) ... migration.py:Migration.test_migration_with_exec: PASS (0.21 s)
>
> All three tests ran using qemu-system-x86_64.
>
> The issue I'm trying to solve is that when run on a aarch64 host, the
> test will fail because (being generic) it doesn't pass the '-machine
> virt' option and there is no architecture-specific information in it at
> all.
But my point is that we already CI on aarch64 hosts, so what is
happening there that means the test doesn't fail already ?
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH RESEND v7 5/9] tests/avocado: Pass parameters to migration test
2023-03-03 16:22 ` Peter Maydell
2023-03-03 20:59 ` Fabiano Rosas
@ 2023-03-06 13:14 ` Dr. David Alan Gilbert
1 sibling, 0 replies; 25+ messages in thread
From: Dr. David Alan Gilbert @ 2023-03-06 13:14 UTC (permalink / raw)
To: Peter Maydell
Cc: Fabiano Rosas, qemu-devel, qemu-arm, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Cleber Rosa, Wainer dos Santos Moschetta, Beraldo Leal
* Peter Maydell (peter.maydell@linaro.org) wrote:
> On Tue, 28 Feb 2023 at 19:28, Fabiano Rosas <farosas@suse.de> wrote:
> >
> > The migration tests are currently broken for an aarch64 host because
> > the tests pass no 'machine' and 'cpu' options on the QEMU command
> > line.
> >
> > Add a separate class to each architecture so that we can specify
> > 'machine' and 'cpu' options instead of relying on defaults.
> >
> > Add a skip decorator to keep the current behavior of only running
> > migration tests when the qemu target matches the host architecture.
>
> I still don't understand this patch. Don't we run the
> migration-test on all hosts already? David ?
I don't run the avocado tests.
Dave
> > Signed-off-by: Fabiano Rosas <farosas@suse.de>
> > ---
> > tests/avocado/migration.py | 83 +++++++++++++++++++++++++++++++++++---
> > 1 file changed, 78 insertions(+), 5 deletions(-)
> >
> > diff --git a/tests/avocado/migration.py b/tests/avocado/migration.py
> > index 4b25680c50..8b2ec0e3c4 100644
> > --- a/tests/avocado/migration.py
> > +++ b/tests/avocado/migration.py
> > @@ -11,6 +11,8 @@
> >
> >
> > import tempfile
> > +import os
> > +
> > from avocado_qemu import QemuSystemTest
> > from avocado import skipUnless
> >
> > @@ -19,7 +21,7 @@
> > from avocado.utils.path import find_command
> >
> >
> > -class Migration(QemuSystemTest):
> > +class MigrationTest(QemuSystemTest):
> > """
> > :avocado: tags=migration
> > """
> > @@ -62,20 +64,91 @@ def _get_free_port(self):
> > self.cancel('Failed to find a free port')
> > return port
> >
> > -
> > - def test_migration_with_tcp_localhost(self):
> > + def migration_with_tcp_localhost(self):
> > dest_uri = 'tcp:localhost:%u' % self._get_free_port()
> > self.do_migrate(dest_uri)
> >
> > - def test_migration_with_unix(self):
> > + def migration_with_unix(self):
> > with tempfile.TemporaryDirectory(prefix='socket_') as socket_path:
> > dest_uri = 'unix:%s/qemu-test.sock' % socket_path
> > self.do_migrate(dest_uri)
> >
> > @skipUnless(find_command('nc', default=False), "'nc' command not found")
> > - def test_migration_with_exec(self):
> > + def migration_with_exec(self):
> > """The test works for both netcat-traditional and netcat-openbsd packages."""
> > free_port = self._get_free_port()
> > dest_uri = 'exec:nc -l localhost %u' % free_port
> > src_uri = 'exec:nc localhost %u' % free_port
> > self.do_migrate(dest_uri, src_uri)
> > +
> > +
> > +@skipUnless('aarch64' in os.uname()[4], "host != target")
> > +class Aarch64(MigrationTest):
> > + """
> > + :avocado: tags=arch:aarch64
> > + :avocado: tags=machine:virt
> > + :avocado: tags=cpu:max
> > + """
> > +
> > + def test_migration_with_tcp_localhost(self):
> > + self.migration_with_tcp_localhost()
> > +
> > + def test_migration_with_unix(self):
> > + self.migration_with_unix()
> > +
> > + def test_migration_with_exec(self):
> > + self.migration_with_exec()
> > +
> > +
> > +@skipUnless('x86_64' in os.uname()[4], "host != target")
> > +class X86_64(MigrationTest):
> > + """
> > + :avocado: tags=arch:x86_64
> > + :avocado: tags=machine:pc
> > + :avocado: tags=cpu:qemu64
> > + """
> > +
> > + def test_migration_with_tcp_localhost(self):
> > + self.migration_with_tcp_localhost()
> > +
> > + def test_migration_with_unix(self):
> > + self.migration_with_unix()
> > +
> > + def test_migration_with_exec(self):
> > + self.migration_with_exec()
> > +
> > +
> > +@skipUnless('ppc64le' in os.uname()[4], "host != target")
> > +class PPC64(MigrationTest):
> > + """
> > + :avocado: tags=arch:ppc64
> > + :avocado: tags=machine:pseries
> > + :avocado: tags=cpu:power9_v2.0
> > + """
> > +
> > + def test_migration_with_tcp_localhost(self):
> > + self.migration_with_tcp_localhost()
> > +
> > + def test_migration_with_unix(self):
> > + self.migration_with_unix()
> > +
> > + def test_migration_with_exec(self):
> > + self.migration_with_exec()
> > +
> > +
> > +@skipUnless('s390x' in os.uname()[4], "host != target")
> > +class S390X(MigrationTest):
> > + """
> > + :avocado: tags=arch:s390x
> > + :avocado: tags=machine:s390-ccw-virtio
> > + :avocado: tags=cpu:qemu
> > + """
> > +
> > + def test_migration_with_tcp_localhost(self):
> > + self.migration_with_tcp_localhost()
> > +
> > + def test_migration_with_unix(self):
> > + self.migration_with_unix()
> > +
> > + def test_migration_with_exec(self):
> > + self.migration_with_exec()
> > --
> > 2.35.3
>
> thanks
> -- PMM
>
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH RESEND v7 5/9] tests/avocado: Pass parameters to migration test
2023-03-04 14:10 ` Peter Maydell
@ 2023-03-06 17:06 ` Fabiano Rosas
0 siblings, 0 replies; 25+ messages in thread
From: Fabiano Rosas @ 2023-03-06 17:06 UTC (permalink / raw)
To: Peter Maydell
Cc: Dr. David Alan Gilbert, qemu-devel, qemu-arm,
Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Cleber Rosa, Wainer dos Santos Moschetta, Beraldo Leal
Peter Maydell <peter.maydell@linaro.org> writes:
> On Fri, 3 Mar 2023 at 20:59, Fabiano Rosas <farosas@suse.de> wrote:
>>
>> Peter Maydell <peter.maydell@linaro.org> writes:
>>
>> > On Tue, 28 Feb 2023 at 19:28, Fabiano Rosas <farosas@suse.de> wrote:
>> >>
>> >> The migration tests are currently broken for an aarch64 host because
>> >> the tests pass no 'machine' and 'cpu' options on the QEMU command
>> >> line.
>> >>
>> >> Add a separate class to each architecture so that we can specify
>> >> 'machine' and 'cpu' options instead of relying on defaults.
>> >>
>> >> Add a skip decorator to keep the current behavior of only running
>> >> migration tests when the qemu target matches the host architecture.
>> >
>> > I still don't understand this patch. Don't we run the
>> > migration-test on all hosts already? David ?
>> >
>>
>> We run on all hosts but for each host we only take the QEMU binary that
>> matches the host architecture. So if you want to test aarch64 migration,
>> you need an aarch64 host.
>>
>> If you run on an x86_64 host (without this patch):
>> $ ../configure #all targets
>> $ make check-avocado AVOCADO_TESTS=../tests/avocado/migration.py
>>
>> You'll see:
>>
>> (1/3) ... migration.py:Migration.test_migration_with_tcp_localhost: PASS (0.21 s)
>> (2/3) ... migration.py:Migration.test_migration_with_unix: PASS (0.18 s)
>> (3/3) ... migration.py:Migration.test_migration_with_exec: PASS (0.21 s)
>>
>> All three tests ran using qemu-system-x86_64.
>>
>> The issue I'm trying to solve is that when run on a aarch64 host, the
>> test will fail because (being generic) it doesn't pass the '-machine
>> virt' option and there is no architecture-specific information in it at
>> all.
>
> But my point is that we already CI on aarch64 hosts, so what is
> happening there that means the test doesn't fail already ?
>
I don't see check-avocado on the custom runners job descriptions
(.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml). It seems we
don't run avocado there at all.
For the regular jobs, there's the avocado-cfi-aarch64 job which depends
on the build-cfi-aarch64 job that is being skipped at the moment. But
that wouldn't catch this bug because it runs on an x86 host and this
particular test gets skipped.
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2023-03-06 17:07 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-28 19:26 [PATCH RESEND v7 0/9] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 1/9] target/arm: Move cortex sysregs into a separate file Fabiano Rosas
2023-03-01 1:21 ` Richard Henderson
2023-02-28 19:26 ` [PATCH RESEND v7 2/9] target/arm: Move 64-bit TCG CPUs into tcg/ Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 3/9] target/arm: Move aa32_max_features out of cpu_tcg.c Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 4/9] target/arm: move cpu_tcg to tcg/cpu32.c Fabiano Rosas
2023-03-01 13:06 ` Thomas Huth
2023-02-28 19:26 ` [PATCH RESEND v7 5/9] tests/avocado: Pass parameters to migration test Fabiano Rosas
2023-03-03 16:22 ` Peter Maydell
2023-03-03 20:59 ` Fabiano Rosas
2023-03-04 14:10 ` Peter Maydell
2023-03-06 17:06 ` Fabiano Rosas
2023-03-06 13:14 ` Dr. David Alan Gilbert
2023-02-28 19:26 ` [PATCH RESEND v7 6/9] arm/Kconfig: Always select SEMIHOSTING when TCG is present Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 7/9] arm/Kconfig: Do not build TCG-only boards on a KVM-only build Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 8/9] gitlab-ci: Check building KVM-only aarch64 target Fabiano Rosas
2023-02-28 19:26 ` [PATCH RESEND v7 9/9] tests/qtest: Fix tests when no KVM or TCG are present Fabiano Rosas
2023-03-01 12:14 ` Juan Quintela
2023-03-01 12:25 ` Fabiano Rosas
2023-03-01 12:57 ` Alex Bennée
2023-03-01 13:34 ` Fabiano Rosas
2023-03-01 13:04 ` Thomas Huth
2023-03-01 13:31 ` Fabiano Rosas
2023-03-01 13:43 ` Fabiano Rosas
2023-03-01 13:50 ` Thomas Huth
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