[PATCH 0/2] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr

[PATCH 0/2] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr

[Philippe Mathieu-Daudé]

Raise Loongson-3A1000 SEGBITS from 40 to 48.

Philippe Mathieu-Daudé (2):
  target/mips: Document Loongson-3A CPU definitions
  target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr

 target/mips/cpu-defs.c.inc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

-- 
2.31.1

[PATCH 1/2] target/mips: Document Loongson-3A CPU definitions

[Philippe Mathieu-Daudé]

Document the cores on which each Loongson-3A CPU is based (see
commit af868995e1b, "target/mips: Add Loongson-3 CPU definition").

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu-defs.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index e03b2a998cd..c6ab3af190e 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -805,7 +805,7 @@ const mips_def_t mips_defs[] =
         .mmu_type = MMU_TYPE_R4000,
     },
     {
-        .name = "Loongson-3A1000",
+        .name = "Loongson-3A1000", /* Loongson-3A R1, GS464-based */
         .CP0_PRid = 0x6305,
         /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
@@ -835,7 +835,7 @@ const mips_def_t mips_defs[] =
         .mmu_type = MMU_TYPE_R4000,
     },
     {
-        .name = "Loongson-3A4000", /* GS464V-based */
+        .name = "Loongson-3A4000", /* Loongson-3A R4, GS464V-based */
         .CP0_PRid = 0x14C000,
         /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
-- 
2.31.1

[PATCH 2/2] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr

[Philippe Mathieu-Daudé]

Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter
1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements
48 virtual address bits in each 64-bit segment, not 40.

Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu-defs.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index c6ab3af190e..cbc45fcb0e8 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -828,7 +828,7 @@ const mips_def_t mips_defs[] =
                     (0x1 << FCR0_D) | (0x1 << FCR0_S),
         .CP1_fcr31 = 0,
         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
-        .SEGBITS = 42,
+        .SEGBITS = 48,
         .PABITS = 48,
         .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
                       ASE_LMMI | ASE_LEXT,
-- 
2.31.1

Re: [PATCH 1/2] target/mips: Document Loongson-3A CPU definitions

[Huacai Chen]

Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>

On Fri, Aug 13, 2021 at 7:01 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Document the cores on which each Loongson-3A CPU is based (see
> commit af868995e1b, "target/mips: Add Loongson-3 CPU definition").
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/cpu-defs.c.inc | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index e03b2a998cd..c6ab3af190e 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -805,7 +805,7 @@ const mips_def_t mips_defs[] =
>          .mmu_type = MMU_TYPE_R4000,
>      },
>      {
> -        .name = "Loongson-3A1000",
> +        .name = "Loongson-3A1000", /* Loongson-3A R1, GS464-based */
>          .CP0_PRid = 0x6305,
>          /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
>          .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
> @@ -835,7 +835,7 @@ const mips_def_t mips_defs[] =
>          .mmu_type = MMU_TYPE_R4000,
>      },
>      {
> -        .name = "Loongson-3A4000", /* GS464V-based */
> +        .name = "Loongson-3A4000", /* Loongson-3A R4, GS464V-based */
>          .CP0_PRid = 0x14C000,
>          /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
>          .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
> --
> 2.31.1
>

Re: [PATCH 2/2] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr

[Huacai Chen]

Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>

On Fri, Aug 13, 2021 at 7:02 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter
> 1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements
> 48 virtual address bits in each 64-bit segment, not 40.
>
> Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition")
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/cpu-defs.c.inc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index c6ab3af190e..cbc45fcb0e8 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -828,7 +828,7 @@ const mips_def_t mips_defs[] =
>                      (0x1 << FCR0_D) | (0x1 << FCR0_S),
>          .CP1_fcr31 = 0,
>          .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
> -        .SEGBITS = 42,
> +        .SEGBITS = 48,
>          .PABITS = 48,
>          .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
>                        ASE_LMMI | ASE_LEXT,
> --
> 2.31.1
>

Re: [PATCH 0/2] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr

[Philippe Mathieu-Daudé]

On 8/13/21 1:01 PM, Philippe Mathieu-Daudé wrote:
> Raise Loongson-3A1000 SEGBITS from 40 to 48.
> 
> Philippe Mathieu-Daudé (2):
>   target/mips: Document Loongson-3A CPU definitions
>   target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr

Thanks, applied to mips-next.