[v9,0/3] force hsa hbp hfp packets multiple of lanenum to avoid screen shift

[v9,0/3] force hsa hbp hfp packets multiple of lanenum to avoid screen shift

[Rex-BC Chen]

Changes since v8:
 - Use mode_flags to control this limitation instead of "hs_packet_end_aligned".
 - Add new bit definition "MIPI_DSI_HS_PKT_END_ALIGNED" for mode_flags.

Changes since v7:
 - Rebase to kernel 5.16
 - Add tags of reviewed-by and acked-by.
 - Add detailed commit message for flag "hs_packet_end_aligned" in DSI common driver.

Changes since v6:
 - Add "bool hs_packet_end_aligned" in "struct mipi_dsi_device" to control the dsi aligned.
 - Config the "hs_packet_end_aligned" in ANX7725 .attach().

Changes since v5:
 - Search the anx7625 compatible as flag to control dsi output aligned.

Changes since v4:
 - Move "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null" before
   "drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid".
 - Retitle "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null".

Rex-BC Chen (3):
  drm/dsi: transfer DSI HS packets ending at the same time
  drm/mediatek: implement the DSI hs packets aligned
  drm/bridge: anx7625: config hs packets end aligned to avoid screen shift

 drivers/gpu/drm/bridge/analogix/anx7625.c |  3 ++-
 drivers/gpu/drm/mediatek/mtk_dsi.c        | 12 ++++++++++++
 include/drm/drm_mipi_dsi.h                |  2 ++
 3 files changed, 16 insertions(+), 1 deletion(-)

-- 
2.18.0

[v9, 0/3] force hsa hbp hfp packets multiple of lanenum to avoid screen shift

[Rex-BC Chen]

Changes since v8:
 - Use mode_flags to control this limitation instead of "hs_packet_end_aligned".
 - Add new bit definition "MIPI_DSI_HS_PKT_END_ALIGNED" for mode_flags.

Changes since v7:
 - Rebase to kernel 5.16
 - Add tags of reviewed-by and acked-by.
 - Add detailed commit message for flag "hs_packet_end_aligned" in DSI common driver.

Changes since v6:
 - Add "bool hs_packet_end_aligned" in "struct mipi_dsi_device" to control the dsi aligned.
 - Config the "hs_packet_end_aligned" in ANX7725 .attach().

Changes since v5:
 - Search the anx7625 compatible as flag to control dsi output aligned.

Changes since v4:
 - Move "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null" before
   "drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid".
 - Retitle "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null".

Rex-BC Chen (3):
  drm/dsi: transfer DSI HS packets ending at the same time
  drm/mediatek: implement the DSI hs packets aligned
  drm/bridge: anx7625: config hs packets end aligned to avoid screen shift

 drivers/gpu/drm/bridge/analogix/anx7625.c |  3 ++-
 drivers/gpu/drm/mediatek/mtk_dsi.c        | 12 ++++++++++++
 include/drm/drm_mipi_dsi.h                |  2 ++
 3 files changed, 16 insertions(+), 1 deletion(-)

-- 
2.18.0


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[v9, 0/3] force hsa hbp hfp packets multiple of lanenum to avoid screen shift

[Rex-BC Chen]

Changes since v8:
 - Use mode_flags to control this limitation instead of "hs_packet_end_aligned".
 - Add new bit definition "MIPI_DSI_HS_PKT_END_ALIGNED" for mode_flags.

Changes since v7:
 - Rebase to kernel 5.16
 - Add tags of reviewed-by and acked-by.
 - Add detailed commit message for flag "hs_packet_end_aligned" in DSI common driver.

Changes since v6:
 - Add "bool hs_packet_end_aligned" in "struct mipi_dsi_device" to control the dsi aligned.
 - Config the "hs_packet_end_aligned" in ANX7725 .attach().

Changes since v5:
 - Search the anx7625 compatible as flag to control dsi output aligned.

Changes since v4:
 - Move "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null" before
   "drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid".
 - Retitle "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null".

Rex-BC Chen (3):
  drm/dsi: transfer DSI HS packets ending at the same time
  drm/mediatek: implement the DSI hs packets aligned
  drm/bridge: anx7625: config hs packets end aligned to avoid screen shift

 drivers/gpu/drm/bridge/analogix/anx7625.c |  3 ++-
 drivers/gpu/drm/mediatek/mtk_dsi.c        | 12 ++++++++++++
 include/drm/drm_mipi_dsi.h                |  2 ++
 3 files changed, 16 insertions(+), 1 deletion(-)

-- 
2.18.0


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[v9,1/3] drm/dsi: transfer DSI HS packets ending at the same time

[Rex-BC Chen]

Since a HS transmission is composed of an arbitrary number
of bytes that may not be an integer multiple of lanes, some
lanes may run out of data before others.
(Defined in 6.1.3 of mipi_DSI_specification_v.01-02-00)

However, for some DSI RX devices (for example, anx7625),
there is a limitation that packet number should be the same
on all DSI lanes. In other words, they need to end a HS at
the same time.

Because this limitation is for some specific DSI RX devices,
it is more reasonable to put the enable control in these
DSI RX drivers. If DSI TX driver knows the information,
they can adjust the setting for this situation.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 include/drm/drm_mipi_dsi.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 147e51b6d241..342dfe5a0874 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -137,6 +137,8 @@ struct mipi_dsi_host *of_find_mipi_dsi_host_by_node(struct device_node *node);
 #define MIPI_DSI_CLOCK_NON_CONTINUOUS	BIT(10)
 /* transmit data in low power */
 #define MIPI_DSI_MODE_LPM		BIT(11)
+/* transmit data ending in the same hsync for all lanes */
+#define MIPI_DSI_HS_PKT_END_ALIGNED	BIT(12)
 
 enum mipi_dsi_pixel_format {
 	MIPI_DSI_FMT_RGB888,
-- 
2.18.0

[v9,1/3] drm/dsi: transfer DSI HS packets ending at the same time

[Rex-BC Chen]

Since a HS transmission is composed of an arbitrary number
of bytes that may not be an integer multiple of lanes, some
lanes may run out of data before others.
(Defined in 6.1.3 of mipi_DSI_specification_v.01-02-00)

However, for some DSI RX devices (for example, anx7625),
there is a limitation that packet number should be the same
on all DSI lanes. In other words, they need to end a HS at
the same time.

Because this limitation is for some specific DSI RX devices,
it is more reasonable to put the enable control in these
DSI RX drivers. If DSI TX driver knows the information,
they can adjust the setting for this situation.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 include/drm/drm_mipi_dsi.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 147e51b6d241..342dfe5a0874 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -137,6 +137,8 @@ struct mipi_dsi_host *of_find_mipi_dsi_host_by_node(struct device_node *node);
 #define MIPI_DSI_CLOCK_NON_CONTINUOUS	BIT(10)
 /* transmit data in low power */
 #define MIPI_DSI_MODE_LPM		BIT(11)
+/* transmit data ending in the same hsync for all lanes */
+#define MIPI_DSI_HS_PKT_END_ALIGNED	BIT(12)
 
 enum mipi_dsi_pixel_format {
 	MIPI_DSI_FMT_RGB888,
-- 
2.18.0


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[v9,1/3] drm/dsi: transfer DSI HS packets ending at the same time

[Rex-BC Chen]

Since a HS transmission is composed of an arbitrary number
of bytes that may not be an integer multiple of lanes, some
lanes may run out of data before others.
(Defined in 6.1.3 of mipi_DSI_specification_v.01-02-00)

However, for some DSI RX devices (for example, anx7625),
there is a limitation that packet number should be the same
on all DSI lanes. In other words, they need to end a HS at
the same time.

Because this limitation is for some specific DSI RX devices,
it is more reasonable to put the enable control in these
DSI RX drivers. If DSI TX driver knows the information,
they can adjust the setting for this situation.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 include/drm/drm_mipi_dsi.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 147e51b6d241..342dfe5a0874 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -137,6 +137,8 @@ struct mipi_dsi_host *of_find_mipi_dsi_host_by_node(struct device_node *node);
 #define MIPI_DSI_CLOCK_NON_CONTINUOUS	BIT(10)
 /* transmit data in low power */
 #define MIPI_DSI_MODE_LPM		BIT(11)
+/* transmit data ending in the same hsync for all lanes */
+#define MIPI_DSI_HS_PKT_END_ALIGNED	BIT(12)
 
 enum mipi_dsi_pixel_format {
 	MIPI_DSI_FMT_RGB888,
-- 
2.18.0


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[v9,2/3] drm/mediatek: implement the DSI hs packets aligned

[Rex-BC Chen]

Some DSI RX devices require the packets on all lanes aligned at the end.
Otherwise, there will be some issues of shift or scroll for screen.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 5d90d2eb0019..ccdda15f5a66 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -195,6 +195,8 @@ struct mtk_dsi {
 	struct clk *hs_clk;
 
 	u32 data_rate;
+	/* force dsi line end without dsi_null data */
+	bool hs_packet_end_aligned;
 
 	unsigned long mode_flags;
 	enum mipi_dsi_pixel_format format;
@@ -500,6 +502,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
 		DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
 	}
 
+	if (dsi->hs_packet_end_aligned) {
+		horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
+		horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
+		horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2;
+		horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
+	}
+
 	writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
 	writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
 	writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
@@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
 	dsi->lanes = device->lanes;
 	dsi->format = device->format;
 	dsi->mode_flags = device->mode_flags;
+	dsi->hs_packet_end_aligned = (dsi->mode_flags &
+				      MIPI_DSI_HS_PKT_END_ALIGNED)
+				     ? true : false;
 
 	return 0;
 }
-- 
2.18.0

[v9,2/3] drm/mediatek: implement the DSI hs packets aligned

[Rex-BC Chen]

Some DSI RX devices require the packets on all lanes aligned at the end.
Otherwise, there will be some issues of shift or scroll for screen.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 5d90d2eb0019..ccdda15f5a66 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -195,6 +195,8 @@ struct mtk_dsi {
 	struct clk *hs_clk;
 
 	u32 data_rate;
+	/* force dsi line end without dsi_null data */
+	bool hs_packet_end_aligned;
 
 	unsigned long mode_flags;
 	enum mipi_dsi_pixel_format format;
@@ -500,6 +502,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
 		DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
 	}
 
+	if (dsi->hs_packet_end_aligned) {
+		horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
+		horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
+		horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2;
+		horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
+	}
+
 	writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
 	writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
 	writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
@@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
 	dsi->lanes = device->lanes;
 	dsi->format = device->format;
 	dsi->mode_flags = device->mode_flags;
+	dsi->hs_packet_end_aligned = (dsi->mode_flags &
+				      MIPI_DSI_HS_PKT_END_ALIGNED)
+				     ? true : false;
 
 	return 0;
 }
-- 
2.18.0


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[v9,2/3] drm/mediatek: implement the DSI hs packets aligned

[Rex-BC Chen]

Some DSI RX devices require the packets on all lanes aligned at the end.
Otherwise, there will be some issues of shift or scroll for screen.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 5d90d2eb0019..ccdda15f5a66 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -195,6 +195,8 @@ struct mtk_dsi {
 	struct clk *hs_clk;
 
 	u32 data_rate;
+	/* force dsi line end without dsi_null data */
+	bool hs_packet_end_aligned;
 
 	unsigned long mode_flags;
 	enum mipi_dsi_pixel_format format;
@@ -500,6 +502,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
 		DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
 	}
 
+	if (dsi->hs_packet_end_aligned) {
+		horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
+		horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
+		horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2;
+		horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
+	}
+
 	writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
 	writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
 	writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
@@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
 	dsi->lanes = device->lanes;
 	dsi->format = device->format;
 	dsi->mode_flags = device->mode_flags;
+	dsi->hs_packet_end_aligned = (dsi->mode_flags &
+				      MIPI_DSI_HS_PKT_END_ALIGNED)
+				     ? true : false;
 
 	return 0;
 }
-- 
2.18.0


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[v9,3/3] drm/bridge: anx7625: config hs packets end aligned to avoid screen shift

[Rex-BC Chen]

This device requires the packets on lanes aligned at the end to fix
screen shift or scroll.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/gpu/drm/bridge/analogix/anx7625.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
index 2346dbcc505f..fe32ab0878ae 100644
--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
@@ -1673,7 +1673,8 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
 	dsi->format = MIPI_DSI_FMT_RGB888;
 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO	|
 		MIPI_DSI_MODE_VIDEO_SYNC_PULSE	|
-		MIPI_DSI_MODE_VIDEO_HSE;
+		MIPI_DSI_MODE_VIDEO_HSE	|
+		MIPI_DSI_HS_PKT_END_ALIGNED;
 
 	ret = devm_mipi_dsi_attach(dev, dsi);
 	if (ret) {
-- 
2.18.0

[v9, 3/3] drm/bridge: anx7625: config hs packets end aligned to avoid screen shift

[Rex-BC Chen]

This device requires the packets on lanes aligned at the end to fix
screen shift or scroll.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/gpu/drm/bridge/analogix/anx7625.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
index 2346dbcc505f..fe32ab0878ae 100644
--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
@@ -1673,7 +1673,8 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
 	dsi->format = MIPI_DSI_FMT_RGB888;
 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO	|
 		MIPI_DSI_MODE_VIDEO_SYNC_PULSE	|
-		MIPI_DSI_MODE_VIDEO_HSE;
+		MIPI_DSI_MODE_VIDEO_HSE	|
+		MIPI_DSI_HS_PKT_END_ALIGNED;
 
 	ret = devm_mipi_dsi_attach(dev, dsi);
 	if (ret) {
-- 
2.18.0


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[v9, 3/3] drm/bridge: anx7625: config hs packets end aligned to avoid screen shift

[Rex-BC Chen]

This device requires the packets on lanes aligned at the end to fix
screen shift or scroll.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/gpu/drm/bridge/analogix/anx7625.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
index 2346dbcc505f..fe32ab0878ae 100644
--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
@@ -1673,7 +1673,8 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
 	dsi->format = MIPI_DSI_FMT_RGB888;
 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO	|
 		MIPI_DSI_MODE_VIDEO_SYNC_PULSE	|
-		MIPI_DSI_MODE_VIDEO_HSE;
+		MIPI_DSI_MODE_VIDEO_HSE	|
+		MIPI_DSI_HS_PKT_END_ALIGNED;
 
 	ret = devm_mipi_dsi_attach(dev, dsi);
 	if (ret) {
-- 
2.18.0


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Re: [v9,2/3] drm/mediatek: implement the DSI hs packets aligned

[AngeloGioacchino Del Regno]

Il 14/01/22 10:21, Rex-BC Chen ha scritto:
> Some DSI RX devices require the packets on all lanes aligned at the end.
> Otherwise, there will be some issues of shift or scroll for screen.
> 
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Hello,
thanks for the patch! However, there's something to improve...

> ---
>   drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 5d90d2eb0019..ccdda15f5a66 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -195,6 +195,8 @@ struct mtk_dsi {
>   	struct clk *hs_clk;
>   
>   	u32 data_rate;
> +	/* force dsi line end without dsi_null data */
> +	bool hs_packet_end_aligned;

There's no need to introduce a new variable here...

>   
>   	unsigned long mode_flags;
>   	enum mipi_dsi_pixel_format format;
> @@ -500,6 +502,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
>   		DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
>   	}
>   
> +	if (dsi->hs_packet_end_aligned) {

You can simply check mode_flags here:
	if (dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) {

> +		horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
> +		horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
> +		horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2;
> +		horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
> +	}
> +
>   	writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
>   	writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
>   	writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
> @@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
>   	dsi->lanes = device->lanes;
>   	dsi->format = device->format;
>   	dsi->mode_flags = device->mode_flags;
> +	dsi->hs_packet_end_aligned = (dsi->mode_flags &
> +				      MIPI_DSI_HS_PKT_END_ALIGNED)
> +				     ? true : false;

...so there's no need for this one, either.

>   
>   	return 0;
>   }
> 

Regards,
- Angelo

Re: [v9,2/3] drm/mediatek: implement the DSI hs packets aligned

[AngeloGioacchino Del Regno]

Il 14/01/22 10:21, Rex-BC Chen ha scritto:
> Some DSI RX devices require the packets on all lanes aligned at the end.
> Otherwise, there will be some issues of shift or scroll for screen.
> 
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Hello,
thanks for the patch! However, there's something to improve...

> ---
>   drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 5d90d2eb0019..ccdda15f5a66 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -195,6 +195,8 @@ struct mtk_dsi {
>   	struct clk *hs_clk;
>   
>   	u32 data_rate;
> +	/* force dsi line end without dsi_null data */
> +	bool hs_packet_end_aligned;

There's no need to introduce a new variable here...

>   
>   	unsigned long mode_flags;
>   	enum mipi_dsi_pixel_format format;
> @@ -500,6 +502,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
>   		DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
>   	}
>   
> +	if (dsi->hs_packet_end_aligned) {

You can simply check mode_flags here:
	if (dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) {

> +		horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
> +		horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
> +		horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2;
> +		horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
> +	}
> +
>   	writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
>   	writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
>   	writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
> @@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
>   	dsi->lanes = device->lanes;
>   	dsi->format = device->format;
>   	dsi->mode_flags = device->mode_flags;
> +	dsi->hs_packet_end_aligned = (dsi->mode_flags &
> +				      MIPI_DSI_HS_PKT_END_ALIGNED)
> +				     ? true : false;

...so there's no need for this one, either.

>   
>   	return 0;
>   }
> 

Regards,
- Angelo


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Re: [v9,2/3] drm/mediatek: implement the DSI hs packets aligned

[AngeloGioacchino Del Regno]

Il 14/01/22 10:21, Rex-BC Chen ha scritto:
> Some DSI RX devices require the packets on all lanes aligned at the end.
> Otherwise, there will be some issues of shift or scroll for screen.
> 
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Hello,
thanks for the patch! However, there's something to improve...

> ---
>   drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 5d90d2eb0019..ccdda15f5a66 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -195,6 +195,8 @@ struct mtk_dsi {
>   	struct clk *hs_clk;
>   
>   	u32 data_rate;
> +	/* force dsi line end without dsi_null data */
> +	bool hs_packet_end_aligned;

There's no need to introduce a new variable here...

>   
>   	unsigned long mode_flags;
>   	enum mipi_dsi_pixel_format format;
> @@ -500,6 +502,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
>   		DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
>   	}
>   
> +	if (dsi->hs_packet_end_aligned) {

You can simply check mode_flags here:
	if (dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) {

> +		horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
> +		horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
> +		horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2;
> +		horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
> +	}
> +
>   	writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
>   	writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
>   	writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
> @@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
>   	dsi->lanes = device->lanes;
>   	dsi->format = device->format;
>   	dsi->mode_flags = device->mode_flags;
> +	dsi->hs_packet_end_aligned = (dsi->mode_flags &
> +				      MIPI_DSI_HS_PKT_END_ALIGNED)
> +				     ? true : false;

...so there's no need for this one, either.

>   
>   	return 0;
>   }
> 

Regards,
- Angelo


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Re: [v9, 3/3] drm/bridge: anx7625: config hs packets end aligned to avoid screen shift

[AngeloGioacchino Del Regno]

Il 14/01/22 10:21, Rex-BC Chen ha scritto:
> This device requires the packets on lanes aligned at the end to fix
> screen shift or scroll.
> 
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   drivers/gpu/drm/bridge/analogix/anx7625.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
> index 2346dbcc505f..fe32ab0878ae 100644
> --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> @@ -1673,7 +1673,8 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
>   	dsi->format = MIPI_DSI_FMT_RGB888;
>   	dsi->mode_flags = MIPI_DSI_MODE_VIDEO	|
>   		MIPI_DSI_MODE_VIDEO_SYNC_PULSE	|
> -		MIPI_DSI_MODE_VIDEO_HSE;
> +		MIPI_DSI_MODE_VIDEO_HSE	|
> +		MIPI_DSI_HS_PKT_END_ALIGNED;
>   
>   	ret = devm_mipi_dsi_attach(dev, dsi);
>   	if (ret) {
> 

Re: [v9, 3/3] drm/bridge: anx7625: config hs packets end aligned to avoid screen shift

[AngeloGioacchino Del Regno]

Il 14/01/22 10:21, Rex-BC Chen ha scritto:
> This device requires the packets on lanes aligned at the end to fix
> screen shift or scroll.
> 
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   drivers/gpu/drm/bridge/analogix/anx7625.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
> index 2346dbcc505f..fe32ab0878ae 100644
> --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> @@ -1673,7 +1673,8 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
>   	dsi->format = MIPI_DSI_FMT_RGB888;
>   	dsi->mode_flags = MIPI_DSI_MODE_VIDEO	|
>   		MIPI_DSI_MODE_VIDEO_SYNC_PULSE	|
> -		MIPI_DSI_MODE_VIDEO_HSE;
> +		MIPI_DSI_MODE_VIDEO_HSE	|
> +		MIPI_DSI_HS_PKT_END_ALIGNED;
>   
>   	ret = devm_mipi_dsi_attach(dev, dsi);
>   	if (ret) {
> 


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Re: [v9, 3/3] drm/bridge: anx7625: config hs packets end aligned to avoid screen shift

[AngeloGioacchino Del Regno]

Il 14/01/22 10:21, Rex-BC Chen ha scritto:
> This device requires the packets on lanes aligned at the end to fix
> screen shift or scroll.
> 
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   drivers/gpu/drm/bridge/analogix/anx7625.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
> index 2346dbcc505f..fe32ab0878ae 100644
> --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> @@ -1673,7 +1673,8 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
>   	dsi->format = MIPI_DSI_FMT_RGB888;
>   	dsi->mode_flags = MIPI_DSI_MODE_VIDEO	|
>   		MIPI_DSI_MODE_VIDEO_SYNC_PULSE	|
> -		MIPI_DSI_MODE_VIDEO_HSE;
> +		MIPI_DSI_MODE_VIDEO_HSE	|
> +		MIPI_DSI_HS_PKT_END_ALIGNED;
>   
>   	ret = devm_mipi_dsi_attach(dev, dsi);
>   	if (ret) {
> 


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Re: [v9,1/3] drm/dsi: transfer DSI HS packets ending at the same time

[AngeloGioacchino Del Regno]

Il 14/01/22 10:21, Rex-BC Chen ha scritto:
> Since a HS transmission is composed of an arbitrary number
> of bytes that may not be an integer multiple of lanes, some
> lanes may run out of data before others.
> (Defined in 6.1.3 of mipi_DSI_specification_v.01-02-00)
> 
> However, for some DSI RX devices (for example, anx7625),
> there is a limitation that packet number should be the same
> on all DSI lanes. In other words, they need to end a HS at
> the same time.
> 
> Because this limitation is for some specific DSI RX devices,
> it is more reasonable to put the enable control in these
> DSI RX drivers. If DSI TX driver knows the information,
> they can adjust the setting for this situation.
> 
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   include/drm/drm_mipi_dsi.h | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
> index 147e51b6d241..342dfe5a0874 100644
> --- a/include/drm/drm_mipi_dsi.h
> +++ b/include/drm/drm_mipi_dsi.h
> @@ -137,6 +137,8 @@ struct mipi_dsi_host *of_find_mipi_dsi_host_by_node(struct device_node *node);
>   #define MIPI_DSI_CLOCK_NON_CONTINUOUS	BIT(10)
>   /* transmit data in low power */
>   #define MIPI_DSI_MODE_LPM		BIT(11)
> +/* transmit data ending in the same hsync for all lanes */
> +#define MIPI_DSI_HS_PKT_END_ALIGNED	BIT(12)
>   
>   enum mipi_dsi_pixel_format {
>   	MIPI_DSI_FMT_RGB888,
> 

Re: [v9, 1/3] drm/dsi: transfer DSI HS packets ending at the same time

[AngeloGioacchino Del Regno]

Il 14/01/22 10:21, Rex-BC Chen ha scritto:
> Since a HS transmission is composed of an arbitrary number
> of bytes that may not be an integer multiple of lanes, some
> lanes may run out of data before others.
> (Defined in 6.1.3 of mipi_DSI_specification_v.01-02-00)
> 
> However, for some DSI RX devices (for example, anx7625),
> there is a limitation that packet number should be the same
> on all DSI lanes. In other words, they need to end a HS at
> the same time.
> 
> Because this limitation is for some specific DSI RX devices,
> it is more reasonable to put the enable control in these
> DSI RX drivers. If DSI TX driver knows the information,
> they can adjust the setting for this situation.
> 
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   include/drm/drm_mipi_dsi.h | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
> index 147e51b6d241..342dfe5a0874 100644
> --- a/include/drm/drm_mipi_dsi.h
> +++ b/include/drm/drm_mipi_dsi.h
> @@ -137,6 +137,8 @@ struct mipi_dsi_host *of_find_mipi_dsi_host_by_node(struct device_node *node);
>   #define MIPI_DSI_CLOCK_NON_CONTINUOUS	BIT(10)
>   /* transmit data in low power */
>   #define MIPI_DSI_MODE_LPM		BIT(11)
> +/* transmit data ending in the same hsync for all lanes */
> +#define MIPI_DSI_HS_PKT_END_ALIGNED	BIT(12)
>   
>   enum mipi_dsi_pixel_format {
>   	MIPI_DSI_FMT_RGB888,
> 


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Re: [v9, 1/3] drm/dsi: transfer DSI HS packets ending at the same time

[AngeloGioacchino Del Regno]

Il 14/01/22 10:21, Rex-BC Chen ha scritto:
> Since a HS transmission is composed of an arbitrary number
> of bytes that may not be an integer multiple of lanes, some
> lanes may run out of data before others.
> (Defined in 6.1.3 of mipi_DSI_specification_v.01-02-00)
> 
> However, for some DSI RX devices (for example, anx7625),
> there is a limitation that packet number should be the same
> on all DSI lanes. In other words, they need to end a HS at
> the same time.
> 
> Because this limitation is for some specific DSI RX devices,
> it is more reasonable to put the enable control in these
> DSI RX drivers. If DSI TX driver knows the information,
> they can adjust the setting for this situation.
> 
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   include/drm/drm_mipi_dsi.h | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
> index 147e51b6d241..342dfe5a0874 100644
> --- a/include/drm/drm_mipi_dsi.h
> +++ b/include/drm/drm_mipi_dsi.h
> @@ -137,6 +137,8 @@ struct mipi_dsi_host *of_find_mipi_dsi_host_by_node(struct device_node *node);
>   #define MIPI_DSI_CLOCK_NON_CONTINUOUS	BIT(10)
>   /* transmit data in low power */
>   #define MIPI_DSI_MODE_LPM		BIT(11)
> +/* transmit data ending in the same hsync for all lanes */
> +#define MIPI_DSI_HS_PKT_END_ALIGNED	BIT(12)
>   
>   enum mipi_dsi_pixel_format {
>   	MIPI_DSI_FMT_RGB888,
> 


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Re: [v9,2/3] drm/mediatek: implement the DSI hs packets aligned

[Rex-BC Chen]

Hello AngeloGioacchino,

Thanks for your review.
I will modify this in next version.

BRs,
Rex-BC Chen

On Fri, 2022-01-14 at 10:36 +0100, AngeloGioacchino Del Regno wrote:
> Il 14/01/22 10:21, Rex-BC Chen ha scritto:
> > Some DSI RX devices require the packets on all lanes aligned at the
> > end.
> > Otherwise, there will be some issues of shift or scroll for screen.
> > 
> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> 
> Hello,
> thanks for the patch! However, there's something to improve...
> 
> > ---
> >   drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
> >   1 file changed, 12 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 5d90d2eb0019..ccdda15f5a66 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -195,6 +195,8 @@ struct mtk_dsi {
> >   	struct clk *hs_clk;
> >   
> >   	u32 data_rate;
> > +	/* force dsi line end without dsi_null data */
> > +	bool hs_packet_end_aligned;
> 
> There's no need to introduce a new variable here...
> >   
> >   	unsigned long mode_flags;
> >   	enum mipi_dsi_pixel_format format;
> > @@ -500,6 +502,13 @@ static void mtk_dsi_config_vdo_timing(struct
> > mtk_dsi *dsi)
> >   		DRM_WARN("HFP + HBP less than d-phy, FPS will under
> > 60Hz\n");
> >   	}
> >   
> > +	if (dsi->hs_packet_end_aligned) {
> 
> You can simply check mode_flags here:
> 	if (dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) {
> 
> > +		horizontal_sync_active_byte =
> > roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
> > +		horizontal_frontporch_byte =
> > roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
> > +		horizontal_backporch_byte =
> > roundup(horizontal_backporch_byte, dsi->lanes) - 2;
> > +		horizontal_backporch_byte -= (vm->hactive *
> > dsi_tmp_buf_bpp + 2) % dsi->lanes;
> > +	}
> > +
> >   	writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
> >   	writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
> >   	writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
> > @@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct
> > mipi_dsi_host *host,
> >   	dsi->lanes = device->lanes;
> >   	dsi->format = device->format;
> >   	dsi->mode_flags = device->mode_flags;
> > +	dsi->hs_packet_end_aligned = (dsi->mode_flags &
> > +				      MIPI_DSI_HS_PKT_END_ALIGNED)
> > +				     ? true : false;
> 
> ...so there's no need for this one, either.
> 
> >   
> >   	return 0;
> >   }
> > 
> 
> Regards,
> - Angelo
> 

Re: [v9,2/3] drm/mediatek: implement the DSI hs packets aligned

[Rex-BC Chen]

Hello AngeloGioacchino,

Thanks for your review.
I will modify this in next version.

BRs,
Rex-BC Chen

On Fri, 2022-01-14 at 10:36 +0100, AngeloGioacchino Del Regno wrote:
> Il 14/01/22 10:21, Rex-BC Chen ha scritto:
> > Some DSI RX devices require the packets on all lanes aligned at the
> > end.
> > Otherwise, there will be some issues of shift or scroll for screen.
> > 
> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> 
> Hello,
> thanks for the patch! However, there's something to improve...
> 
> > ---
> >   drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
> >   1 file changed, 12 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 5d90d2eb0019..ccdda15f5a66 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -195,6 +195,8 @@ struct mtk_dsi {
> >   	struct clk *hs_clk;
> >   
> >   	u32 data_rate;
> > +	/* force dsi line end without dsi_null data */
> > +	bool hs_packet_end_aligned;
> 
> There's no need to introduce a new variable here...
> >   
> >   	unsigned long mode_flags;
> >   	enum mipi_dsi_pixel_format format;
> > @@ -500,6 +502,13 @@ static void mtk_dsi_config_vdo_timing(struct
> > mtk_dsi *dsi)
> >   		DRM_WARN("HFP + HBP less than d-phy, FPS will under
> > 60Hz\n");
> >   	}
> >   
> > +	if (dsi->hs_packet_end_aligned) {
> 
> You can simply check mode_flags here:
> 	if (dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) {
> 
> > +		horizontal_sync_active_byte =
> > roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
> > +		horizontal_frontporch_byte =
> > roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
> > +		horizontal_backporch_byte =
> > roundup(horizontal_backporch_byte, dsi->lanes) - 2;
> > +		horizontal_backporch_byte -= (vm->hactive *
> > dsi_tmp_buf_bpp + 2) % dsi->lanes;
> > +	}
> > +
> >   	writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
> >   	writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
> >   	writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
> > @@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct
> > mipi_dsi_host *host,
> >   	dsi->lanes = device->lanes;
> >   	dsi->format = device->format;
> >   	dsi->mode_flags = device->mode_flags;
> > +	dsi->hs_packet_end_aligned = (dsi->mode_flags &
> > +				      MIPI_DSI_HS_PKT_END_ALIGNED)
> > +				     ? true : false;
> 
> ...so there's no need for this one, either.
> 
> >   
> >   	return 0;
> >   }
> > 
> 
> Regards,
> - Angelo
> 


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Re: [v9,2/3] drm/mediatek: implement the DSI hs packets aligned

[Rex-BC Chen]

Hello AngeloGioacchino,

Thanks for your review.
I will modify this in next version.

BRs,
Rex-BC Chen

On Fri, 2022-01-14 at 10:36 +0100, AngeloGioacchino Del Regno wrote:
> Il 14/01/22 10:21, Rex-BC Chen ha scritto:
> > Some DSI RX devices require the packets on all lanes aligned at the
> > end.
> > Otherwise, there will be some issues of shift or scroll for screen.
> > 
> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> 
> Hello,
> thanks for the patch! However, there's something to improve...
> 
> > ---
> >   drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
> >   1 file changed, 12 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 5d90d2eb0019..ccdda15f5a66 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -195,6 +195,8 @@ struct mtk_dsi {
> >   	struct clk *hs_clk;
> >   
> >   	u32 data_rate;
> > +	/* force dsi line end without dsi_null data */
> > +	bool hs_packet_end_aligned;
> 
> There's no need to introduce a new variable here...
> >   
> >   	unsigned long mode_flags;
> >   	enum mipi_dsi_pixel_format format;
> > @@ -500,6 +502,13 @@ static void mtk_dsi_config_vdo_timing(struct
> > mtk_dsi *dsi)
> >   		DRM_WARN("HFP + HBP less than d-phy, FPS will under
> > 60Hz\n");
> >   	}
> >   
> > +	if (dsi->hs_packet_end_aligned) {
> 
> You can simply check mode_flags here:
> 	if (dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) {
> 
> > +		horizontal_sync_active_byte =
> > roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
> > +		horizontal_frontporch_byte =
> > roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
> > +		horizontal_backporch_byte =
> > roundup(horizontal_backporch_byte, dsi->lanes) - 2;
> > +		horizontal_backporch_byte -= (vm->hactive *
> > dsi_tmp_buf_bpp + 2) % dsi->lanes;
> > +	}
> > +
> >   	writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
> >   	writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
> >   	writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
> > @@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct
> > mipi_dsi_host *host,
> >   	dsi->lanes = device->lanes;
> >   	dsi->format = device->format;
> >   	dsi->mode_flags = device->mode_flags;
> > +	dsi->hs_packet_end_aligned = (dsi->mode_flags &
> > +				      MIPI_DSI_HS_PKT_END_ALIGNED)
> > +				     ? true : false;
> 
> ...so there's no need for this one, either.
> 
> >   
> >   	return 0;
> >   }
> > 
> 
> Regards,
> - Angelo
> 


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Re: [v9,3/3] drm/bridge: anx7625: config hs packets end aligned to avoid screen shift

[Xin Ji]

Hi Rex-BC Chen, thanks for your patch, it is OK for me.

Reviewed-by: Xin Ji <xji@analogixsemi.com>

Thanks,
Xin

On Fri, Jan 14, 2022 at 05:21:10PM +0800, Rex-BC Chen wrote:
> This device requires the packets on lanes aligned at the end to fix
> screen shift or scroll.
> 
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>  drivers/gpu/drm/bridge/analogix/anx7625.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
> index 2346dbcc505f..fe32ab0878ae 100644
> --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> @@ -1673,7 +1673,8 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
>  	dsi->format = MIPI_DSI_FMT_RGB888;
>  	dsi->mode_flags = MIPI_DSI_MODE_VIDEO	|
>  		MIPI_DSI_MODE_VIDEO_SYNC_PULSE	|
> -		MIPI_DSI_MODE_VIDEO_HSE;
> +		MIPI_DSI_MODE_VIDEO_HSE	|
> +		MIPI_DSI_HS_PKT_END_ALIGNED;
>  
>  	ret = devm_mipi_dsi_attach(dev, dsi);
>  	if (ret) {
> -- 
> 2.18.0

Re: [v9,3/3] drm/bridge: anx7625: config hs packets end aligned to avoid screen shift

[Xin Ji]

Hi Rex-BC Chen, thanks for your patch, it is OK for me.

Reviewed-by: Xin Ji <xji@analogixsemi.com>

Thanks,
Xin

On Fri, Jan 14, 2022 at 05:21:10PM +0800, Rex-BC Chen wrote:
> This device requires the packets on lanes aligned at the end to fix
> screen shift or scroll.
> 
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>  drivers/gpu/drm/bridge/analogix/anx7625.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
> index 2346dbcc505f..fe32ab0878ae 100644
> --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> @@ -1673,7 +1673,8 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
>  	dsi->format = MIPI_DSI_FMT_RGB888;
>  	dsi->mode_flags = MIPI_DSI_MODE_VIDEO	|
>  		MIPI_DSI_MODE_VIDEO_SYNC_PULSE	|
> -		MIPI_DSI_MODE_VIDEO_HSE;
> +		MIPI_DSI_MODE_VIDEO_HSE	|
> +		MIPI_DSI_HS_PKT_END_ALIGNED;
>  
>  	ret = devm_mipi_dsi_attach(dev, dsi);
>  	if (ret) {
> -- 
> 2.18.0

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Re: [v9,3/3] drm/bridge: anx7625: config hs packets end aligned to avoid screen shift

[Xin Ji]

Hi Rex-BC Chen, thanks for your patch, it is OK for me.

Reviewed-by: Xin Ji <xji@analogixsemi.com>

Thanks,
Xin

On Fri, Jan 14, 2022 at 05:21:10PM +0800, Rex-BC Chen wrote:
> This device requires the packets on lanes aligned at the end to fix
> screen shift or scroll.
> 
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>  drivers/gpu/drm/bridge/analogix/anx7625.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
> index 2346dbcc505f..fe32ab0878ae 100644
> --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> @@ -1673,7 +1673,8 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
>  	dsi->format = MIPI_DSI_FMT_RGB888;
>  	dsi->mode_flags = MIPI_DSI_MODE_VIDEO	|
>  		MIPI_DSI_MODE_VIDEO_SYNC_PULSE	|
> -		MIPI_DSI_MODE_VIDEO_HSE;
> +		MIPI_DSI_MODE_VIDEO_HSE	|
> +		MIPI_DSI_HS_PKT_END_ALIGNED;
>  
>  	ret = devm_mipi_dsi_attach(dev, dsi);
>  	if (ret) {
> -- 
> 2.18.0

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Re: [v9,2/3] drm/mediatek: implement the DSI hs packets aligned

[Andrzej Hajda]

On 14.01.2022 11:20, Rex-BC Chen wrote:
> Hello AngeloGioacchino,
>
> Thanks for your review.
> I will modify this in next version.
>
> BRs,
> Rex-BC Chen
>
> On Fri, 2022-01-14 at 10:36 +0100, AngeloGioacchino Del Regno wrote:
>> Il 14/01/22 10:21, Rex-BC Chen ha scritto:
>>> Some DSI RX devices require the packets on all lanes aligned at the
>>> end.
>>> Otherwise, there will be some issues of shift or scroll for screen.
>>>
>>> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
>>> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>> Hello,
>> thanks for the patch! However, there's something to improve...
>>
>>> ---
>>>    drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
>>>    1 file changed, 12 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> b/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> index 5d90d2eb0019..ccdda15f5a66 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> @@ -195,6 +195,8 @@ struct mtk_dsi {
>>>    	struct clk *hs_clk;
>>>    
>>>    	u32 data_rate;
>>> +	/* force dsi line end without dsi_null data */
>>> +	bool hs_packet_end_aligned;
>> There's no need to introduce a new variable here...
>>>    
>>>    	unsigned long mode_flags;
>>>    	enum mipi_dsi_pixel_format format;
>>> @@ -500,6 +502,13 @@ static void mtk_dsi_config_vdo_timing(struct
>>> mtk_dsi *dsi)
>>>    		DRM_WARN("HFP + HBP less than d-phy, FPS will under
>>> 60Hz\n");
>>>    	}
>>>    
>>> +	if (dsi->hs_packet_end_aligned) {
>> You can simply check mode_flags here:
>> 	if (dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) {
>>
>>> +		horizontal_sync_active_byte =
>>> roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
>>> +		horizontal_frontporch_byte =
>>> roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
>>> +		horizontal_backporch_byte =
>>> roundup(horizontal_backporch_byte, dsi->lanes) - 2;
>>> +		horizontal_backporch_byte -= (vm->hactive *
>>> dsi_tmp_buf_bpp + 2) % dsi->lanes;
>>> +	}
>>> +


And if you could add comment explaining the magic here it would be nice.


Regards

Andrzej


>>>    	writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
>>>    	writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
>>>    	writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
>>> @@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct
>>> mipi_dsi_host *host,
>>>    	dsi->lanes = device->lanes;
>>>    	dsi->format = device->format;
>>>    	dsi->mode_flags = device->mode_flags;
>>> +	dsi->hs_packet_end_aligned = (dsi->mode_flags &
>>> +				      MIPI_DSI_HS_PKT_END_ALIGNED)
>>> +				     ? true : false;
>> ...so there's no need for this one, either.
>>
>>>    
>>>    	return 0;
>>>    }
>>>
>> Regards,
>> - Angelo
>>

Re: [v9,2/3] drm/mediatek: implement the DSI hs packets aligned

[Andrzej Hajda]

On 14.01.2022 11:20, Rex-BC Chen wrote:
> Hello AngeloGioacchino,
>
> Thanks for your review.
> I will modify this in next version.
>
> BRs,
> Rex-BC Chen
>
> On Fri, 2022-01-14 at 10:36 +0100, AngeloGioacchino Del Regno wrote:
>> Il 14/01/22 10:21, Rex-BC Chen ha scritto:
>>> Some DSI RX devices require the packets on all lanes aligned at the
>>> end.
>>> Otherwise, there will be some issues of shift or scroll for screen.
>>>
>>> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
>>> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>> Hello,
>> thanks for the patch! However, there's something to improve...
>>
>>> ---
>>>    drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
>>>    1 file changed, 12 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> b/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> index 5d90d2eb0019..ccdda15f5a66 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> @@ -195,6 +195,8 @@ struct mtk_dsi {
>>>    	struct clk *hs_clk;
>>>    
>>>    	u32 data_rate;
>>> +	/* force dsi line end without dsi_null data */
>>> +	bool hs_packet_end_aligned;
>> There's no need to introduce a new variable here...
>>>    
>>>    	unsigned long mode_flags;
>>>    	enum mipi_dsi_pixel_format format;
>>> @@ -500,6 +502,13 @@ static void mtk_dsi_config_vdo_timing(struct
>>> mtk_dsi *dsi)
>>>    		DRM_WARN("HFP + HBP less than d-phy, FPS will under
>>> 60Hz\n");
>>>    	}
>>>    
>>> +	if (dsi->hs_packet_end_aligned) {
>> You can simply check mode_flags here:
>> 	if (dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) {
>>
>>> +		horizontal_sync_active_byte =
>>> roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
>>> +		horizontal_frontporch_byte =
>>> roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
>>> +		horizontal_backporch_byte =
>>> roundup(horizontal_backporch_byte, dsi->lanes) - 2;
>>> +		horizontal_backporch_byte -= (vm->hactive *
>>> dsi_tmp_buf_bpp + 2) % dsi->lanes;
>>> +	}
>>> +


And if you could add comment explaining the magic here it would be nice.


Regards

Andrzej


>>>    	writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
>>>    	writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
>>>    	writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
>>> @@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct
>>> mipi_dsi_host *host,
>>>    	dsi->lanes = device->lanes;
>>>    	dsi->format = device->format;
>>>    	dsi->mode_flags = device->mode_flags;
>>> +	dsi->hs_packet_end_aligned = (dsi->mode_flags &
>>> +				      MIPI_DSI_HS_PKT_END_ALIGNED)
>>> +				     ? true : false;
>> ...so there's no need for this one, either.
>>
>>>    
>>>    	return 0;
>>>    }
>>>
>> Regards,
>> - Angelo
>>

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Re: [v9,2/3] drm/mediatek: implement the DSI hs packets aligned

[Andrzej Hajda]

On 14.01.2022 11:20, Rex-BC Chen wrote:
> Hello AngeloGioacchino,
>
> Thanks for your review.
> I will modify this in next version.
>
> BRs,
> Rex-BC Chen
>
> On Fri, 2022-01-14 at 10:36 +0100, AngeloGioacchino Del Regno wrote:
>> Il 14/01/22 10:21, Rex-BC Chen ha scritto:
>>> Some DSI RX devices require the packets on all lanes aligned at the
>>> end.
>>> Otherwise, there will be some issues of shift or scroll for screen.
>>>
>>> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
>>> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>> Hello,
>> thanks for the patch! However, there's something to improve...
>>
>>> ---
>>>    drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
>>>    1 file changed, 12 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> b/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> index 5d90d2eb0019..ccdda15f5a66 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> @@ -195,6 +195,8 @@ struct mtk_dsi {
>>>    	struct clk *hs_clk;
>>>    
>>>    	u32 data_rate;
>>> +	/* force dsi line end without dsi_null data */
>>> +	bool hs_packet_end_aligned;
>> There's no need to introduce a new variable here...
>>>    
>>>    	unsigned long mode_flags;
>>>    	enum mipi_dsi_pixel_format format;
>>> @@ -500,6 +502,13 @@ static void mtk_dsi_config_vdo_timing(struct
>>> mtk_dsi *dsi)
>>>    		DRM_WARN("HFP + HBP less than d-phy, FPS will under
>>> 60Hz\n");
>>>    	}
>>>    
>>> +	if (dsi->hs_packet_end_aligned) {
>> You can simply check mode_flags here:
>> 	if (dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) {
>>
>>> +		horizontal_sync_active_byte =
>>> roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
>>> +		horizontal_frontporch_byte =
>>> roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
>>> +		horizontal_backporch_byte =
>>> roundup(horizontal_backporch_byte, dsi->lanes) - 2;
>>> +		horizontal_backporch_byte -= (vm->hactive *
>>> dsi_tmp_buf_bpp + 2) % dsi->lanes;
>>> +	}
>>> +


And if you could add comment explaining the magic here it would be nice.


Regards

Andrzej


>>>    	writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
>>>    	writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
>>>    	writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
>>> @@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct
>>> mipi_dsi_host *host,
>>>    	dsi->lanes = device->lanes;
>>>    	dsi->format = device->format;
>>>    	dsi->mode_flags = device->mode_flags;
>>> +	dsi->hs_packet_end_aligned = (dsi->mode_flags &
>>> +				      MIPI_DSI_HS_PKT_END_ALIGNED)
>>> +				     ? true : false;
>> ...so there's no need for this one, either.
>>
>>>    
>>>    	return 0;
>>>    }
>>>
>> Regards,
>> - Angelo
>>

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Re: [v9,2/3] drm/mediatek: implement the DSI hs packets aligned

[Rex-BC Chen]

Hello Andrzej,

Thanks for your review.
I will give the explanation for this in next version.

BRs,
Rex-BC hen

On Fri, 2022-01-14 at 12:11 +0100, Andrzej Hajda wrote:
> On 14.01.2022 11:20, Rex-BC Chen wrote:
> > Hello AngeloGioacchino,
> > 
> > Thanks for your review.
> > I will modify this in next version.
> > 
> > BRs,
> > Rex-BC Chen
> > 
> > On Fri, 2022-01-14 at 10:36 +0100, AngeloGioacchino Del Regno
> > wrote:
> > > Il 14/01/22 10:21, Rex-BC Chen ha scritto:
> > > > Some DSI RX devices require the packets on all lanes aligned at
> > > > the
> > > > end.
> > > > Otherwise, there will be some issues of shift or scroll for
> > > > screen.
> > > > 
> > > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > > 
> > > Hello,
> > > thanks for the patch! However, there's something to improve...
> > > 
> > > > ---
> > > >    drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
> > > >    1 file changed, 12 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > index 5d90d2eb0019..ccdda15f5a66 100644
> > > > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > @@ -195,6 +195,8 @@ struct mtk_dsi {
> > > >    	struct clk *hs_clk;
> > > >    
> > > >    	u32 data_rate;
> > > > +	/* force dsi line end without dsi_null data */
> > > > +	bool hs_packet_end_aligned;
> > > 
> > > There's no need to introduce a new variable here...
> > > >    
> > > >    	unsigned long mode_flags;
> > > >    	enum mipi_dsi_pixel_format format;
> > > > @@ -500,6 +502,13 @@ static void
> > > > mtk_dsi_config_vdo_timing(struct
> > > > mtk_dsi *dsi)
> > > >    		DRM_WARN("HFP + HBP less than d-phy, FPS will
> > > > under
> > > > 60Hz\n");
> > > >    	}
> > > >    
> > > > +	if (dsi->hs_packet_end_aligned) {
> > > 
> > > You can simply check mode_flags here:
> > > 	if (dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) {
> > > 
> > > > +		horizontal_sync_active_byte =
> > > > roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
> > > > +		horizontal_frontporch_byte =
> > > > roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
> > > > +		horizontal_backporch_byte =
> > > > roundup(horizontal_backporch_byte, dsi->lanes) - 2;
> > > > +		horizontal_backporch_byte -= (vm->hactive *
> > > > dsi_tmp_buf_bpp + 2) % dsi->lanes;
> > > > +	}
> > > > +
> 
> 
> And if you could add comment explaining the magic here it would be
> nice.
> 
> 
> Regards
> 
> Andrzej
> 
> 
> > > >    	writel(horizontal_sync_active_byte, dsi->regs +
> > > > DSI_HSA_WC);
> > > >    	writel(horizontal_backporch_byte, dsi->regs +
> > > > DSI_HBP_WC);
> > > >    	writel(horizontal_frontporch_byte, dsi->regs +
> > > > DSI_HFP_WC);
> > > > @@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct
> > > > mipi_dsi_host *host,
> > > >    	dsi->lanes = device->lanes;
> > > >    	dsi->format = device->format;
> > > >    	dsi->mode_flags = device->mode_flags;
> > > > +	dsi->hs_packet_end_aligned = (dsi->mode_flags &
> > > > +				      MIPI_DSI_HS_PKT_END_ALIGN
> > > > ED)
> > > > +				     ? true : false;
> > > 
> > > ...so there's no need for this one, either.
> > > 
> > > >    
> > > >    	return 0;
> > > >    }
> > > > 
> > > 
> > > Regards,
> > > - Angelo
> > > 

Re: [v9,2/3] drm/mediatek: implement the DSI hs packets aligned

[Rex-BC Chen]

Hello Andrzej,

Thanks for your review.
I will give the explanation for this in next version.

BRs,
Rex-BC hen

On Fri, 2022-01-14 at 12:11 +0100, Andrzej Hajda wrote:
> On 14.01.2022 11:20, Rex-BC Chen wrote:
> > Hello AngeloGioacchino,
> > 
> > Thanks for your review.
> > I will modify this in next version.
> > 
> > BRs,
> > Rex-BC Chen
> > 
> > On Fri, 2022-01-14 at 10:36 +0100, AngeloGioacchino Del Regno
> > wrote:
> > > Il 14/01/22 10:21, Rex-BC Chen ha scritto:
> > > > Some DSI RX devices require the packets on all lanes aligned at
> > > > the
> > > > end.
> > > > Otherwise, there will be some issues of shift or scroll for
> > > > screen.
> > > > 
> > > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > > 
> > > Hello,
> > > thanks for the patch! However, there's something to improve...
> > > 
> > > > ---
> > > >    drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
> > > >    1 file changed, 12 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > index 5d90d2eb0019..ccdda15f5a66 100644
> > > > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > @@ -195,6 +195,8 @@ struct mtk_dsi {
> > > >    	struct clk *hs_clk;
> > > >    
> > > >    	u32 data_rate;
> > > > +	/* force dsi line end without dsi_null data */
> > > > +	bool hs_packet_end_aligned;
> > > 
> > > There's no need to introduce a new variable here...
> > > >    
> > > >    	unsigned long mode_flags;
> > > >    	enum mipi_dsi_pixel_format format;
> > > > @@ -500,6 +502,13 @@ static void
> > > > mtk_dsi_config_vdo_timing(struct
> > > > mtk_dsi *dsi)
> > > >    		DRM_WARN("HFP + HBP less than d-phy, FPS will
> > > > under
> > > > 60Hz\n");
> > > >    	}
> > > >    
> > > > +	if (dsi->hs_packet_end_aligned) {
> > > 
> > > You can simply check mode_flags here:
> > > 	if (dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) {
> > > 
> > > > +		horizontal_sync_active_byte =
> > > > roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
> > > > +		horizontal_frontporch_byte =
> > > > roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
> > > > +		horizontal_backporch_byte =
> > > > roundup(horizontal_backporch_byte, dsi->lanes) - 2;
> > > > +		horizontal_backporch_byte -= (vm->hactive *
> > > > dsi_tmp_buf_bpp + 2) % dsi->lanes;
> > > > +	}
> > > > +
> 
> 
> And if you could add comment explaining the magic here it would be
> nice.
> 
> 
> Regards
> 
> Andrzej
> 
> 
> > > >    	writel(horizontal_sync_active_byte, dsi->regs +
> > > > DSI_HSA_WC);
> > > >    	writel(horizontal_backporch_byte, dsi->regs +
> > > > DSI_HBP_WC);
> > > >    	writel(horizontal_frontporch_byte, dsi->regs +
> > > > DSI_HFP_WC);
> > > > @@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct
> > > > mipi_dsi_host *host,
> > > >    	dsi->lanes = device->lanes;
> > > >    	dsi->format = device->format;
> > > >    	dsi->mode_flags = device->mode_flags;
> > > > +	dsi->hs_packet_end_aligned = (dsi->mode_flags &
> > > > +				      MIPI_DSI_HS_PKT_END_ALIGN
> > > > ED)
> > > > +				     ? true : false;
> > > 
> > > ...so there's no need for this one, either.
> > > 
> > > >    
> > > >    	return 0;
> > > >    }
> > > > 
> > > 
> > > Regards,
> > > - Angelo
> > > 


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Re: [v9,2/3] drm/mediatek: implement the DSI hs packets aligned

[Rex-BC Chen]

Hello Andrzej,

Thanks for your review.
I will give the explanation for this in next version.

BRs,
Rex-BC hen

On Fri, 2022-01-14 at 12:11 +0100, Andrzej Hajda wrote:
> On 14.01.2022 11:20, Rex-BC Chen wrote:
> > Hello AngeloGioacchino,
> > 
> > Thanks for your review.
> > I will modify this in next version.
> > 
> > BRs,
> > Rex-BC Chen
> > 
> > On Fri, 2022-01-14 at 10:36 +0100, AngeloGioacchino Del Regno
> > wrote:
> > > Il 14/01/22 10:21, Rex-BC Chen ha scritto:
> > > > Some DSI RX devices require the packets on all lanes aligned at
> > > > the
> > > > end.
> > > > Otherwise, there will be some issues of shift or scroll for
> > > > screen.
> > > > 
> > > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > > 
> > > Hello,
> > > thanks for the patch! However, there's something to improve...
> > > 
> > > > ---
> > > >    drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
> > > >    1 file changed, 12 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > index 5d90d2eb0019..ccdda15f5a66 100644
> > > > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > > @@ -195,6 +195,8 @@ struct mtk_dsi {
> > > >    	struct clk *hs_clk;
> > > >    
> > > >    	u32 data_rate;
> > > > +	/* force dsi line end without dsi_null data */
> > > > +	bool hs_packet_end_aligned;
> > > 
> > > There's no need to introduce a new variable here...
> > > >    
> > > >    	unsigned long mode_flags;
> > > >    	enum mipi_dsi_pixel_format format;
> > > > @@ -500,6 +502,13 @@ static void
> > > > mtk_dsi_config_vdo_timing(struct
> > > > mtk_dsi *dsi)
> > > >    		DRM_WARN("HFP + HBP less than d-phy, FPS will
> > > > under
> > > > 60Hz\n");
> > > >    	}
> > > >    
> > > > +	if (dsi->hs_packet_end_aligned) {
> > > 
> > > You can simply check mode_flags here:
> > > 	if (dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) {
> > > 
> > > > +		horizontal_sync_active_byte =
> > > > roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
> > > > +		horizontal_frontporch_byte =
> > > > roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
> > > > +		horizontal_backporch_byte =
> > > > roundup(horizontal_backporch_byte, dsi->lanes) - 2;
> > > > +		horizontal_backporch_byte -= (vm->hactive *
> > > > dsi_tmp_buf_bpp + 2) % dsi->lanes;
> > > > +	}
> > > > +
> 
> 
> And if you could add comment explaining the magic here it would be
> nice.
> 
> 
> Regards
> 
> Andrzej
> 
> 
> > > >    	writel(horizontal_sync_active_byte, dsi->regs +
> > > > DSI_HSA_WC);
> > > >    	writel(horizontal_backporch_byte, dsi->regs +
> > > > DSI_HBP_WC);
> > > >    	writel(horizontal_frontporch_byte, dsi->regs +
> > > > DSI_HFP_WC);
> > > > @@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct
> > > > mipi_dsi_host *host,
> > > >    	dsi->lanes = device->lanes;
> > > >    	dsi->format = device->format;
> > > >    	dsi->mode_flags = device->mode_flags;
> > > > +	dsi->hs_packet_end_aligned = (dsi->mode_flags &
> > > > +				      MIPI_DSI_HS_PKT_END_ALIGN
> > > > ED)
> > > > +				     ? true : false;
> > > 
> > > ...so there's no need for this one, either.
> > > 
> > > >    
> > > >    	return 0;
> > > >    }
> > > > 
> > > 
> > > Regards,
> > > - Angelo
> > > 


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