* [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings
@ 2022-01-28 11:48 Imre Deak
2022-01-28 11:48 ` [Intel-gfx] [PATCH 01/19] drm/i915: Fix the VDSC_PW2 power domain enum value Imre Deak
` (21 more replies)
0 siblings, 22 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:48 UTC (permalink / raw)
To: intel-gfx
This patchset moves the per-platform display power domain->power well
mapping descriptors to a separate file and simplifies them by sharing
descriptor data among port power well instances and platforms where
possible.
The power well and domain names are also sanitized to match the actual
specification terminology. For this the patchset removes the aliasing
among the display power domain enum values, which in turn required
extending the u64 domain mask to a bitmap.
I also pushed the changes to:
https://github.com/ideak/linux/commits/power-domain-refactor
Imre Deak (19):
drm/i915: Fix the VDSC_PW2 power domain enum value
drm/i915: Unexport the for_each_power_well() macros
drm/i915: Move the i915_power_well_regs struct into
i915_power_well_ops
drm/i915: Move the power domain->well mappings to
intel_display_power_map.c
drm/i915: Move the dg2 fixed_enable_delay power well param to a common
bitfield
drm/i915: Move the HSW power well flags to a common bitfield
drm/i915: Rename the power domain names to end with pipes/ports
drm/i915: Sanitize the power well names
drm/i915: Convert the power well descriptor domain mask to a list
drm/i915: Convert the u64 power well domains mask to a bitmap
drm/i915: Simplify power well definitions by adding power well
instances
drm/i915: Allow platforms to share power well descriptors
drm/i915: Simplify the DG1 power well descriptors
drm/i915: Sanitize the ADL-S power well definition
drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each
platform
drm/i915: Remove the aliasing of power domain enum values
drm/i915: Remove the ICL specific TBT power domains
drm/i915: Remove duplicate DDI/AUX power domain mappings
drm/i915: Remove the XELPD specific AUX and DDI power domains
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/g4x_dp.c | 3 +-
drivers/gpu/drm/i915/display/g4x_hdmi.c | 3 +-
drivers/gpu/drm/i915/display/icl_dsi.c | 8 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +-
drivers/gpu/drm/i915/display/intel_display.c | 149 +-
drivers/gpu/drm/i915/display/intel_display.h | 4 +-
.../drm/i915/display/intel_display_power.c | 2904 ++---------------
.../drm/i915/display/intel_display_power.h | 133 +-
.../display/intel_display_power_internal.h | 106 +
.../i915/display/intel_display_power_map.c | 1848 +++++++++++
drivers/gpu/drm/i915/display/intel_tc.c | 4 +-
12 files changed, 2263 insertions(+), 2905 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_power_internal.h
create mode 100644 drivers/gpu/drm/i915/display/intel_display_power_map.c
--
2.27.0
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 01/19] drm/i915: Fix the VDSC_PW2 power domain enum value
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
@ 2022-01-28 11:48 ` Imre Deak
2022-01-28 11:48 ` [Intel-gfx] [PATCH 02/19] drm/i915: Unexport the for_each_power_well() macros Imre Deak
` (20 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:48 UTC (permalink / raw)
To: intel-gfx
The POWER_DOMAIN_TRANSCODER() macro depends on the
POWER_DOMAIN_TRANSCODER_A/B .. DSI_A/C enum values to be consecutive,
move POWER_DOMAIN_TRANSCODER_VDSC_PW2 after these to ensure this. The
wrong order didn't cause a problem, since the DSI_A/C domains are in
always-on power wells on all relevant platforms. The same power well
ends up being enabled/disabled when the VDSC_PW2 domain is selected
incorrectly.
While at it add a code comment about enum values that need to stay
consecutive.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display_power.h | 11 +++++++++--
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 369317805d245..e64d407e7b8db 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -152,12 +152,12 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "TRANSCODER_D";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
- case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
- return "TRANSCODER_VDSC_PW2";
case POWER_DOMAIN_TRANSCODER_DSI_A:
return "TRANSCODER_DSI_A";
case POWER_DOMAIN_TRANSCODER_DSI_C:
return "TRANSCODER_DSI_C";
+ case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
+ return "TRANSCODER_VDSC_PW2";
case POWER_DOMAIN_PORT_DDI_A_LANES:
return "PORT_DDI_A_LANES";
case POWER_DOMAIN_PORT_DDI_B_LANES:
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 686d18eaa24c8..a3997f05cd89b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -15,6 +15,11 @@ struct drm_i915_private;
struct i915_power_well;
struct intel_encoder;
+/*
+ * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances
+ * consecutive, so that the pipe,transcoder,port -> power domain macros
+ * work correctly.
+ */
enum intel_display_power_domain {
POWER_DOMAIN_DISPLAY_CORE,
POWER_DOMAIN_PIPE_A,
@@ -30,10 +35,12 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_D,
POWER_DOMAIN_TRANSCODER_EDP,
- /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
- POWER_DOMAIN_TRANSCODER_VDSC_PW2,
POWER_DOMAIN_TRANSCODER_DSI_A,
POWER_DOMAIN_TRANSCODER_DSI_C,
+
+ /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
+ POWER_DOMAIN_TRANSCODER_VDSC_PW2,
+
POWER_DOMAIN_PORT_DDI_A_LANES,
POWER_DOMAIN_PORT_DDI_B_LANES,
POWER_DOMAIN_PORT_DDI_C_LANES,
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 02/19] drm/i915: Unexport the for_each_power_well() macros
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
2022-01-28 11:48 ` [Intel-gfx] [PATCH 01/19] drm/i915: Fix the VDSC_PW2 power domain enum value Imre Deak
@ 2022-01-28 11:48 ` Imre Deak
2022-01-28 11:48 ` [Intel-gfx] [PATCH 03/19] drm/i915: Move the i915_power_well_regs struct into i915_power_well_ops Imre Deak
` (19 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:48 UTC (permalink / raw)
To: intel-gfx
The for_each_power_well() macros are only used in intel_display_power.c,
so unexport them.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_power.c | 20 +++++++++++++++++++
.../drm/i915/display/intel_display_power.h | 20 -------------------
2 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index e64d407e7b8db..b500cc94ded75 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -25,6 +25,26 @@
#include "intel_vga.h"
#include "vlv_sideband.h"
+#define for_each_power_well(__dev_priv, __power_well) \
+ for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
+ (__power_well) - (__dev_priv)->power_domains.power_wells < \
+ (__dev_priv)->power_domains.power_well_count; \
+ (__power_well)++)
+
+#define for_each_power_well_reverse(__dev_priv, __power_well) \
+ for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
+ (__dev_priv)->power_domains.power_well_count - 1; \
+ (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
+ (__power_well)--)
+
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
+ for_each_power_well(__dev_priv, __power_well) \
+ for_each_if((__power_well)->desc->domains & (__domain_mask))
+
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
+ for_each_power_well_reverse(__dev_priv, __power_well) \
+ for_each_if((__power_well)->desc->domains & (__domain_mask))
+
struct i915_power_well_ops {
/*
* Synchronize the well's hw state to match the current sw state, for
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index a3997f05cd89b..b30e6133c66d0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -197,26 +197,6 @@ struct intel_display_power_domain_set {
for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
for_each_if(BIT_ULL(domain) & (mask))
-#define for_each_power_well(__dev_priv, __power_well) \
- for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
- (__power_well) - (__dev_priv)->power_domains.power_wells < \
- (__dev_priv)->power_domains.power_well_count; \
- (__power_well)++)
-
-#define for_each_power_well_reverse(__dev_priv, __power_well) \
- for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
- (__dev_priv)->power_domains.power_well_count - 1; \
- (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
- (__power_well)--)
-
-#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
- for_each_power_well(__dev_priv, __power_well) \
- for_each_if((__power_well)->desc->domains & (__domain_mask))
-
-#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
- for_each_power_well_reverse(__dev_priv, __power_well) \
- for_each_if((__power_well)->desc->domains & (__domain_mask))
-
int intel_power_domains_init(struct drm_i915_private *dev_priv);
void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 03/19] drm/i915: Move the i915_power_well_regs struct into i915_power_well_ops
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
2022-01-28 11:48 ` [Intel-gfx] [PATCH 01/19] drm/i915: Fix the VDSC_PW2 power domain enum value Imre Deak
2022-01-28 11:48 ` [Intel-gfx] [PATCH 02/19] drm/i915: Unexport the for_each_power_well() macros Imre Deak
@ 2022-01-28 11:48 ` Imre Deak
2022-01-28 11:48 ` [Intel-gfx] [PATCH 04/19] drm/i915: Move the power domain->well mappings to intel_display_power_map.c Imre Deak
` (18 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:48 UTC (permalink / raw)
To: intel-gfx
Move the i915_power_well_regs struct into i915_power_well_ops. Most of
the power wells use the same ops/regs combination, so this saves some
space and also simplifies the platform power domain->power well
definitions.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_power.c | 256 +++++-------------
1 file changed, 73 insertions(+), 183 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index b500cc94ded75..72e8eb82f3c74 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -45,7 +45,15 @@
for_each_power_well_reverse(__dev_priv, __power_well) \
for_each_if((__power_well)->desc->domains & (__domain_mask))
+struct i915_power_well_regs {
+ i915_reg_t bios;
+ i915_reg_t driver;
+ i915_reg_t kvmr;
+ i915_reg_t debug;
+};
+
struct i915_power_well_ops {
+ const struct i915_power_well_regs *regs;
/*
* Synchronize the well's hw state to match the current sw state, for
* example enable/disable it based on the current refcount. Called
@@ -72,13 +80,6 @@ struct i915_power_well_ops {
struct i915_power_well *power_well);
};
-struct i915_power_well_regs {
- i915_reg_t bios;
- i915_reg_t driver;
- i915_reg_t kvmr;
- i915_reg_t debug;
-};
-
/* Power well structure for haswell */
struct i915_power_well_desc {
const char *name;
@@ -102,7 +103,6 @@ struct i915_power_well_desc {
enum dpio_phy phy;
} bxt;
struct {
- const struct i915_power_well_regs *regs;
/*
* request/status flag index in the power well
* constrol/status registers.
@@ -457,7 +457,7 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well,
bool timeout_expected)
{
- const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
int pw_idx = power_well->desc->hsw.idx;
int enable_delay = power_well->desc->hsw.fixed_enable_delay;
@@ -501,7 +501,7 @@ static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
int pw_idx = power_well->desc->hsw.idx;
bool disabled;
u32 reqs;
@@ -539,7 +539,7 @@ static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
int pw_idx = power_well->desc->hsw.idx;
u32 val;
@@ -586,7 +586,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
int pw_idx = power_well->desc->hsw.idx;
u32 val;
@@ -603,7 +603,7 @@ static void
icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
int pw_idx = power_well->desc->hsw.idx;
enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
u32 val;
@@ -635,7 +635,7 @@ static void
icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
int pw_idx = power_well->desc->hsw.idx;
enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
u32 val;
@@ -725,7 +725,7 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
{
enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
- const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
bool is_tbt = power_well->desc->hsw.is_tc_tbt;
bool timeout_expected;
u32 val;
@@ -817,7 +817,7 @@ icl_aux_power_well_disable(struct drm_i915_private *dev_priv,
static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
enum i915_power_well_id id = power_well->desc->id;
int pw_idx = power_well->desc->hsw.idx;
u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
@@ -1227,7 +1227,7 @@ static void skl_enable_dc6(struct drm_i915_private *dev_priv)
static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
int pw_idx = power_well->desc->hsw.idx;
u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
u32 bios_req = intel_de_read(dev_priv, regs->bios);
@@ -3299,7 +3299,15 @@ static const struct i915_power_well_desc i830_power_wells[] = {
},
};
+static const struct i915_power_well_regs hsw_power_well_regs = {
+ .bios = HSW_PWR_WELL_CTL1,
+ .driver = HSW_PWR_WELL_CTL2,
+ .kvmr = HSW_PWR_WELL_CTL3,
+ .debug = HSW_PWR_WELL_CTL4,
+};
+
static const struct i915_power_well_ops hsw_power_well_ops = {
+ .regs = &hsw_power_well_regs,
.sync_hw = hsw_power_well_sync_hw,
.enable = hsw_power_well_enable,
.disable = hsw_power_well_disable,
@@ -3320,13 +3328,6 @@ static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
.is_enabled = bxt_dpio_cmn_power_well_enabled,
};
-static const struct i915_power_well_regs hsw_power_well_regs = {
- .bios = HSW_PWR_WELL_CTL1,
- .driver = HSW_PWR_WELL_CTL2,
- .kvmr = HSW_PWR_WELL_CTL3,
- .debug = HSW_PWR_WELL_CTL4,
-};
-
static const struct i915_power_well_desc hsw_power_wells[] = {
{
.name = "always-on",
@@ -3341,7 +3342,6 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
.hsw.has_vga = true,
},
@@ -3362,7 +3362,6 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
@@ -3534,7 +3533,6 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
.hsw.has_fuses = true,
},
@@ -3547,7 +3545,6 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_MISC_IO,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
},
},
@@ -3563,7 +3560,6 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_PW_2,
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
@@ -3576,7 +3572,6 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
},
},
@@ -3586,7 +3581,6 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
},
},
@@ -3596,7 +3590,6 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_C,
},
},
@@ -3606,7 +3599,6 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_D,
},
},
@@ -3628,7 +3620,6 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
.hsw.has_fuses = true,
},
@@ -3645,7 +3636,6 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_PW_2,
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
@@ -3688,7 +3678,6 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
.hsw.has_fuses = true,
},
@@ -3705,7 +3694,6 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_PW_2,
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
@@ -3745,7 +3733,6 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_AUX_A,
},
},
@@ -3755,7 +3742,6 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_AUX_B,
},
},
@@ -3765,7 +3751,6 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_AUX_C,
},
},
@@ -3775,7 +3760,6 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_DDI_A,
},
},
@@ -3785,7 +3769,6 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
},
},
@@ -3795,31 +3778,39 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_C,
},
},
};
-static const struct i915_power_well_ops icl_aux_power_well_ops = {
- .sync_hw = hsw_power_well_sync_hw,
- .enable = icl_aux_power_well_enable,
- .disable = icl_aux_power_well_disable,
- .is_enabled = hsw_power_well_enabled,
-};
-
static const struct i915_power_well_regs icl_aux_power_well_regs = {
.bios = ICL_PWR_WELL_CTL_AUX1,
.driver = ICL_PWR_WELL_CTL_AUX2,
.debug = ICL_PWR_WELL_CTL_AUX4,
};
+static const struct i915_power_well_ops icl_aux_power_well_ops = {
+ .regs = &icl_aux_power_well_regs,
+ .sync_hw = hsw_power_well_sync_hw,
+ .enable = icl_aux_power_well_enable,
+ .disable = icl_aux_power_well_disable,
+ .is_enabled = hsw_power_well_enabled,
+};
+
static const struct i915_power_well_regs icl_ddi_power_well_regs = {
.bios = ICL_PWR_WELL_CTL_DDI1,
.driver = ICL_PWR_WELL_CTL_DDI2,
.debug = ICL_PWR_WELL_CTL_DDI4,
};
+static const struct i915_power_well_ops icl_ddi_power_well_ops = {
+ .regs = &icl_ddi_power_well_regs,
+ .sync_hw = hsw_power_well_sync_hw,
+ .enable = hsw_power_well_enable,
+ .disable = hsw_power_well_disable,
+ .is_enabled = hsw_power_well_enabled,
+};
+
static const struct i915_power_well_desc icl_power_wells[] = {
{
.name = "always-on",
@@ -3836,7 +3827,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
.hsw.has_fuses = true,
},
@@ -3853,7 +3843,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
.hsw.has_fuses = true,
},
@@ -3864,7 +3853,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_3,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
.hsw.irq_pipe_mask = BIT(PIPE_B),
.hsw.has_vga = true,
@@ -3874,60 +3862,54 @@ static const struct i915_power_well_desc icl_power_wells[] = {
{
.name = "DDI A IO",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
},
},
{
.name = "DDI B IO",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
},
},
{
.name = "DDI C IO",
.domains = ICL_DDI_IO_C_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
},
},
{
.name = "DDI D IO",
.domains = ICL_DDI_IO_D_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_D,
},
},
{
.name = "DDI E IO",
.domains = ICL_DDI_IO_E_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_E,
},
},
{
.name = "DDI F IO",
.domains = ICL_DDI_IO_F_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_F,
},
},
@@ -3937,7 +3919,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
},
},
@@ -3947,7 +3928,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
},
},
@@ -3957,7 +3937,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
.hsw.is_tc_tbt = false,
},
@@ -3968,7 +3947,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_D,
.hsw.is_tc_tbt = false,
},
@@ -3979,7 +3957,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_E,
.hsw.is_tc_tbt = false,
},
@@ -3990,7 +3967,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_F,
.hsw.is_tc_tbt = false,
},
@@ -4001,7 +3977,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
.hsw.is_tc_tbt = true,
},
@@ -4012,7 +3987,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
.hsw.is_tc_tbt = true,
},
@@ -4023,7 +3997,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
.hsw.is_tc_tbt = true,
},
@@ -4034,7 +4007,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
.hsw.is_tc_tbt = true,
},
@@ -4045,7 +4017,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
.hsw.has_fuses = true,
.hsw.irq_pipe_mask = BIT(PIPE_C),
@@ -4153,7 +4124,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
.hsw.has_fuses = true,
},
@@ -4170,7 +4140,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
.hsw.has_fuses = true,
},
@@ -4181,7 +4150,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_3,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
.hsw.irq_pipe_mask = BIT(PIPE_B),
.hsw.has_vga = true,
@@ -4191,90 +4159,81 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
{
.name = "DDI A IO",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
}
},
{
.name = "DDI B IO",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
}
},
{
.name = "DDI C IO",
.domains = ICL_DDI_IO_C_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
}
},
{
.name = "DDI IO TC1",
.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
},
},
{
.name = "DDI IO TC2",
.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
},
},
{
.name = "DDI IO TC3",
.domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
},
},
{
.name = "DDI IO TC4",
.domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
},
},
{
.name = "DDI IO TC5",
.domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
},
},
{
.name = "DDI IO TC6",
.domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
},
},
@@ -4290,7 +4249,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
},
},
@@ -4300,7 +4258,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
},
},
@@ -4310,7 +4267,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
},
},
@@ -4320,7 +4276,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
.hsw.is_tc_tbt = false,
},
@@ -4331,7 +4286,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
.hsw.is_tc_tbt = false,
},
@@ -4342,7 +4296,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
.hsw.is_tc_tbt = false,
},
@@ -4353,7 +4306,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
.hsw.is_tc_tbt = false,
},
@@ -4364,7 +4316,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
.hsw.is_tc_tbt = false,
},
@@ -4375,7 +4326,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
.hsw.is_tc_tbt = false,
},
@@ -4386,7 +4336,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
.hsw.is_tc_tbt = true,
},
@@ -4397,7 +4346,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
.hsw.is_tc_tbt = true,
},
@@ -4408,7 +4356,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
.hsw.is_tc_tbt = true,
},
@@ -4419,7 +4366,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
.hsw.is_tc_tbt = true,
},
@@ -4430,7 +4376,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
.hsw.is_tc_tbt = true,
},
@@ -4441,7 +4386,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
.hsw.is_tc_tbt = true,
},
@@ -4452,7 +4396,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
.hsw.has_fuses = true,
.hsw.irq_pipe_mask = BIT(PIPE_C),
@@ -4464,7 +4407,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_PW_5,
.hsw.has_fuses = true,
.hsw.irq_pipe_mask = BIT(PIPE_D),
@@ -4488,7 +4430,6 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
.hsw.has_fuses = true,
},
@@ -4505,7 +4446,6 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_3,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
.hsw.irq_pipe_mask = BIT(PIPE_B),
.hsw.has_vga = true,
@@ -4518,7 +4458,6 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
.hsw.has_fuses = true,
.hsw.irq_pipe_mask = BIT(PIPE_C),
@@ -4527,40 +4466,36 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
{
.name = "DDI A IO",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
}
},
{
.name = "DDI B IO",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
}
},
{
.name = "DDI IO TC1",
.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
},
},
{
.name = "DDI IO TC2",
.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
},
},
@@ -4570,7 +4505,6 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
},
},
@@ -4580,7 +4514,6 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
},
},
@@ -4590,7 +4523,6 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
},
},
@@ -4600,7 +4532,6 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
},
},
@@ -4622,7 +4553,6 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
.hsw.has_fuses = true,
},
@@ -4639,7 +4569,6 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
.hsw.has_fuses = true,
},
@@ -4650,7 +4579,6 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_3,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
.hsw.irq_pipe_mask = BIT(PIPE_B),
.hsw.has_vga = true,
@@ -4660,40 +4588,36 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
{
.name = "DDI A IO",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
}
},
{
.name = "DDI B IO",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
}
},
{
.name = "DDI IO TC1",
.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
},
},
{
.name = "DDI IO TC2",
.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
},
},
@@ -4703,7 +4627,6 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
},
},
@@ -4713,7 +4636,6 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
},
},
@@ -4723,7 +4645,6 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
.hsw.is_tc_tbt = false,
},
@@ -4734,7 +4655,6 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
.hsw.is_tc_tbt = false,
},
@@ -4745,7 +4665,6 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
.hsw.has_fuses = true,
.hsw.irq_pipe_mask = BIT(PIPE_C),
@@ -4757,7 +4676,6 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_PW_5,
.hsw.has_fuses = true,
.hsw.irq_pipe_mask = BIT(PIPE_D),
@@ -4781,7 +4699,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
.hsw.has_fuses = true,
},
@@ -4798,7 +4715,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
.hsw.has_vga = true,
.hsw.has_fuses = true,
@@ -4810,7 +4726,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = XELPD_PW_CTL_IDX_PW_A,
.hsw.irq_pipe_mask = BIT(PIPE_A),
.hsw.has_fuses = true,
@@ -4822,7 +4737,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = XELPD_PW_CTL_IDX_PW_B,
.hsw.irq_pipe_mask = BIT(PIPE_B),
.hsw.has_fuses = true,
@@ -4834,7 +4748,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = XELPD_PW_CTL_IDX_PW_C,
.hsw.irq_pipe_mask = BIT(PIPE_C),
.hsw.has_fuses = true,
@@ -4846,7 +4759,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &hsw_power_well_regs,
.hsw.idx = XELPD_PW_CTL_IDX_PW_D,
.hsw.irq_pipe_mask = BIT(PIPE_D),
.hsw.has_fuses = true,
@@ -4855,90 +4767,81 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
{
.name = "DDI A IO",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
}
},
{
.name = "DDI B IO",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
}
},
{
.name = "DDI C IO",
.domains = ICL_DDI_IO_C_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
}
},
{
.name = "DDI IO D_XELPD",
.domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = XELPD_PW_CTL_IDX_DDI_D,
}
},
{
.name = "DDI IO E_XELPD",
.domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = XELPD_PW_CTL_IDX_DDI_E,
}
},
{
.name = "DDI IO TC1",
.domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
}
},
{
.name = "DDI IO TC2",
.domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
}
},
{
.name = "DDI IO TC3",
.domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
}
},
{
.name = "DDI IO TC4",
.domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
}
},
@@ -4948,7 +4851,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
.hsw.fixed_enable_delay = 600,
},
@@ -4959,7 +4861,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
.hsw.fixed_enable_delay = 600,
},
@@ -4970,7 +4871,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
.hsw.fixed_enable_delay = 600,
},
@@ -4981,7 +4881,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
.hsw.fixed_enable_delay = 600,
},
@@ -4992,7 +4891,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = XELPD_PW_CTL_IDX_AUX_E,
},
},
@@ -5002,7 +4900,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
.hsw.fixed_enable_delay = 600,
},
@@ -5013,7 +4910,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
},
},
@@ -5023,7 +4919,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
},
},
@@ -5033,7 +4928,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
},
},
@@ -5043,7 +4937,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
.hsw.is_tc_tbt = true,
},
@@ -5054,7 +4947,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
.hsw.is_tc_tbt = true,
},
@@ -5065,7 +4957,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
.hsw.is_tc_tbt = true,
},
@@ -5076,7 +4967,6 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
- .hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
.hsw.is_tc_tbt = true,
},
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 04/19] drm/i915: Move the power domain->well mappings to intel_display_power_map.c
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (2 preceding siblings ...)
2022-01-28 11:48 ` [Intel-gfx] [PATCH 03/19] drm/i915: Move the i915_power_well_regs struct into i915_power_well_ops Imre Deak
@ 2022-01-28 11:48 ` Imre Deak
2022-01-31 12:15 ` Jani Nikula
2022-01-28 11:49 ` [Intel-gfx] [PATCH 05/19] drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield Imre Deak
` (17 subsequent siblings)
21 siblings, 1 reply; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:48 UTC (permalink / raw)
To: intel-gfx
Move the list of platform specific power domain -> power well
definitions to intel_display_power_map.c. While at it group the
platforms' power domain macros with the corresponding power well lists
and keep all the power domain lists in the same order (matching the enum
order).
No functional changes.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_power.c | 2483 +----------------
.../drm/i915/display/intel_display_power.h | 5 +
.../display/intel_display_power_internal.h | 93 +
.../i915/display/intel_display_power_map.c | 2277 +++++++++++++++
5 files changed, 2392 insertions(+), 2467 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_power_internal.h
create mode 100644 drivers/gpu/drm/i915/display/intel_display_power_map.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a26e6736bebbc..c6444d6f944b8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -210,6 +210,7 @@ i915-y += \
display/intel_cursor.o \
display/intel_display.o \
display/intel_display_power.o \
+ display/intel_display_power_map.o \
display/intel_dmc.o \
display/intel_dpio_phy.o \
display/intel_dpll.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 72e8eb82f3c74..2ec9c7bd65640 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -11,6 +11,7 @@
#include "intel_crt.h"
#include "intel_de.h"
#include "intel_display_power.h"
+#include "intel_display_power_internal.h"
#include "intel_display_types.h"
#include "intel_dmc.h"
#include "intel_dpio_phy.h"
@@ -80,204 +81,9 @@ struct i915_power_well_ops {
struct i915_power_well *power_well);
};
-/* Power well structure for haswell */
-struct i915_power_well_desc {
- const char *name;
- bool always_on;
- u64 domains;
- /* unique identifier for this power well */
- enum i915_power_well_id id;
- /*
- * Arbitraty data associated with this power well. Platform and power
- * well specific.
- */
- union {
- struct {
- /*
- * request/status flag index in the PUNIT power well
- * control/status registers.
- */
- u8 idx;
- } vlv;
- struct {
- enum dpio_phy phy;
- } bxt;
- struct {
- /*
- * request/status flag index in the power well
- * constrol/status registers.
- */
- u8 idx;
- /* Mask of pipes whose IRQ logic is backed by the pw */
- u8 irq_pipe_mask;
- /*
- * Instead of waiting for the status bit to ack enables,
- * just wait a specific amount of time and then consider
- * the well enabled.
- */
- u16 fixed_enable_delay;
- /* The pw is backing the VGA functionality */
- bool has_vga:1;
- bool has_fuses:1;
- /*
- * The pw is for an ICL+ TypeC PHY port in
- * Thunderbolt mode.
- */
- bool is_tc_tbt:1;
- } hsw;
- };
- const struct i915_power_well_ops *ops;
-};
-
-struct i915_power_well {
- const struct i915_power_well_desc *desc;
- /* power well enable/disable usage count */
- int count;
- /* cached hw enabled state */
- bool hw_enabled;
-};
-
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
-const char *
-intel_display_power_domain_str(enum intel_display_power_domain domain)
-{
- switch (domain) {
- case POWER_DOMAIN_DISPLAY_CORE:
- return "DISPLAY_CORE";
- case POWER_DOMAIN_PIPE_A:
- return "PIPE_A";
- case POWER_DOMAIN_PIPE_B:
- return "PIPE_B";
- case POWER_DOMAIN_PIPE_C:
- return "PIPE_C";
- case POWER_DOMAIN_PIPE_D:
- return "PIPE_D";
- case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
- return "PIPE_A_PANEL_FITTER";
- case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
- return "PIPE_B_PANEL_FITTER";
- case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
- return "PIPE_C_PANEL_FITTER";
- case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
- return "PIPE_D_PANEL_FITTER";
- case POWER_DOMAIN_TRANSCODER_A:
- return "TRANSCODER_A";
- case POWER_DOMAIN_TRANSCODER_B:
- return "TRANSCODER_B";
- case POWER_DOMAIN_TRANSCODER_C:
- return "TRANSCODER_C";
- case POWER_DOMAIN_TRANSCODER_D:
- return "TRANSCODER_D";
- case POWER_DOMAIN_TRANSCODER_EDP:
- return "TRANSCODER_EDP";
- case POWER_DOMAIN_TRANSCODER_DSI_A:
- return "TRANSCODER_DSI_A";
- case POWER_DOMAIN_TRANSCODER_DSI_C:
- return "TRANSCODER_DSI_C";
- case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
- return "TRANSCODER_VDSC_PW2";
- case POWER_DOMAIN_PORT_DDI_A_LANES:
- return "PORT_DDI_A_LANES";
- case POWER_DOMAIN_PORT_DDI_B_LANES:
- return "PORT_DDI_B_LANES";
- case POWER_DOMAIN_PORT_DDI_C_LANES:
- return "PORT_DDI_C_LANES";
- case POWER_DOMAIN_PORT_DDI_D_LANES:
- return "PORT_DDI_D_LANES";
- case POWER_DOMAIN_PORT_DDI_E_LANES:
- return "PORT_DDI_E_LANES";
- case POWER_DOMAIN_PORT_DDI_F_LANES:
- return "PORT_DDI_F_LANES";
- case POWER_DOMAIN_PORT_DDI_G_LANES:
- return "PORT_DDI_G_LANES";
- case POWER_DOMAIN_PORT_DDI_H_LANES:
- return "PORT_DDI_H_LANES";
- case POWER_DOMAIN_PORT_DDI_I_LANES:
- return "PORT_DDI_I_LANES";
- case POWER_DOMAIN_PORT_DDI_A_IO:
- return "PORT_DDI_A_IO";
- case POWER_DOMAIN_PORT_DDI_B_IO:
- return "PORT_DDI_B_IO";
- case POWER_DOMAIN_PORT_DDI_C_IO:
- return "PORT_DDI_C_IO";
- case POWER_DOMAIN_PORT_DDI_D_IO:
- return "PORT_DDI_D_IO";
- case POWER_DOMAIN_PORT_DDI_E_IO:
- return "PORT_DDI_E_IO";
- case POWER_DOMAIN_PORT_DDI_F_IO:
- return "PORT_DDI_F_IO";
- case POWER_DOMAIN_PORT_DDI_G_IO:
- return "PORT_DDI_G_IO";
- case POWER_DOMAIN_PORT_DDI_H_IO:
- return "PORT_DDI_H_IO";
- case POWER_DOMAIN_PORT_DDI_I_IO:
- return "PORT_DDI_I_IO";
- case POWER_DOMAIN_PORT_DSI:
- return "PORT_DSI";
- case POWER_DOMAIN_PORT_CRT:
- return "PORT_CRT";
- case POWER_DOMAIN_PORT_OTHER:
- return "PORT_OTHER";
- case POWER_DOMAIN_VGA:
- return "VGA";
- case POWER_DOMAIN_AUDIO_MMIO:
- return "AUDIO_MMIO";
- case POWER_DOMAIN_AUDIO_PLAYBACK:
- return "AUDIO_PLAYBACK";
- case POWER_DOMAIN_AUX_A:
- return "AUX_A";
- case POWER_DOMAIN_AUX_B:
- return "AUX_B";
- case POWER_DOMAIN_AUX_C:
- return "AUX_C";
- case POWER_DOMAIN_AUX_D:
- return "AUX_D";
- case POWER_DOMAIN_AUX_E:
- return "AUX_E";
- case POWER_DOMAIN_AUX_F:
- return "AUX_F";
- case POWER_DOMAIN_AUX_G:
- return "AUX_G";
- case POWER_DOMAIN_AUX_H:
- return "AUX_H";
- case POWER_DOMAIN_AUX_I:
- return "AUX_I";
- case POWER_DOMAIN_AUX_IO_A:
- return "AUX_IO_A";
- case POWER_DOMAIN_AUX_C_TBT:
- return "AUX_C_TBT";
- case POWER_DOMAIN_AUX_D_TBT:
- return "AUX_D_TBT";
- case POWER_DOMAIN_AUX_E_TBT:
- return "AUX_E_TBT";
- case POWER_DOMAIN_AUX_F_TBT:
- return "AUX_F_TBT";
- case POWER_DOMAIN_AUX_G_TBT:
- return "AUX_G_TBT";
- case POWER_DOMAIN_AUX_H_TBT:
- return "AUX_H_TBT";
- case POWER_DOMAIN_AUX_I_TBT:
- return "AUX_I_TBT";
- case POWER_DOMAIN_GMBUS:
- return "GMBUS";
- case POWER_DOMAIN_INIT:
- return "INIT";
- case POWER_DOMAIN_MODESET:
- return "MODESET";
- case POWER_DOMAIN_GT_IRQ:
- return "GT_IRQ";
- case POWER_DOMAIN_DC_OFF:
- return "DC_OFF";
- case POWER_DOMAIN_TC_COLD_OFF:
- return "TC_COLD_OFF";
- default:
- MISSING_CASE(domain);
- return "?";
- }
-}
-
static void intel_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -1640,8 +1446,6 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
vlv_set_power_well(dev_priv, power_well, false);
}
-#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
-
#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
@@ -2608,697 +2412,34 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
}
}
-#define I830_PIPES_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define CHV_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define HSW_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define BDW_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
-#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
-#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
-#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-/*
- * ICL PW_0/PG_0 domains (HW/DMC control):
- * - PCI
- * - clocks except port PLL
- * - central power except FBC
- * - shared functions except pipe interrupts, pipe MBUS, DBUF registers
- * ICL PW_1/PG_1 domains (HW/DMC control):
- * - DBUF function
- * - PIPE_A and its planes, except VGA
- * - transcoder EDP + PSR
- * - transcoder DSI
- * - DDI_A
- * - FBC
- */
-#define ICL_PW_4_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_INIT))
- /* VDSC/joining */
-#define ICL_PW_3_POWER_DOMAINS ( \
- ICL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_AUX_E) | \
- BIT_ULL(POWER_DOMAIN_AUX_F) | \
- BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
- BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
- BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
- BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
- /*
- * - transcoder WD
- * - KVMR (HW control)
- */
-#define ICL_PW_2_POWER_DOMAINS ( \
- ICL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
- /*
- * - KVMR (HW control)
- */
-#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- ICL_PW_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_DC_OFF) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define ICL_DDI_IO_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
-#define ICL_DDI_IO_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
-#define ICL_DDI_IO_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
-#define ICL_DDI_IO_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
-#define ICL_DDI_IO_E_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
-#define ICL_DDI_IO_F_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
-
-#define ICL_AUX_A_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_A))
-#define ICL_AUX_B_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_B))
-#define ICL_AUX_C_TC1_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_C))
-#define ICL_AUX_D_TC2_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_D))
-#define ICL_AUX_E_TC3_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_E))
-#define ICL_AUX_F_TC4_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_F))
-#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_C_TBT))
-#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
-#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
-#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
-
-#define TGL_PW_5_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define TGL_PW_4_POWER_DOMAINS ( \
- TGL_PW_5_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define TGL_PW_3_POWER_DOMAINS ( \
- TGL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define TGL_PW_2_POWER_DOMAINS ( \
- TGL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- TGL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define TGL_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
-#define TGL_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
-#define TGL_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
-#define TGL_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
-#define TGL_DDI_IO_TC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC5)
-#define TGL_DDI_IO_TC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC6)
-
-#define TGL_AUX_A_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_A))
-#define TGL_AUX_B_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_B))
-#define TGL_AUX_C_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_C))
-
-#define TGL_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
-#define TGL_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
-#define TGL_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
-#define TGL_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
-#define TGL_AUX_IO_USBC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC5)
-#define TGL_AUX_IO_USBC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC6)
-
-#define TGL_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
-#define TGL_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
-#define TGL_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
-#define TGL_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
-#define TGL_AUX_IO_TBT5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT5)
-#define TGL_AUX_IO_TBT6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT6)
-
-#define TGL_TC_COLD_OFF_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
- BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
-
-#define RKL_PW_4_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define RKL_PW_3_POWER_DOMAINS ( \
- RKL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-/*
- * There is no PW_2/PG_2 on RKL.
- *
- * RKL PW_1/PG_1 domains (under HW/DMC control):
- * - DBUF function (note: registers are in PW0)
- * - PIPE_A and its planes and VDSC/joining, except VGA
- * - transcoder A
- * - DDI_A and DDI_B
- * - FBC
- *
- * RKL PW_0/PG_0 domains (under HW/DMC control):
- * - PCI
- * - clocks except port PLL
- * - shared functions:
- * * interrupts except pipe interrupts
- * * MBus except PIPE_MBUS_DBOX_CTL
- * * DBUF registers
- * - central power except FBC
- * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
- */
-
-#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- RKL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-/*
- * DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
- */
-#define DG1_PW_3_POWER_DOMAINS ( \
- TGL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define DG1_PW_2_POWER_DOMAINS ( \
- DG1_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- DG1_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-/*
- * XE_LPD Power Domains
- *
- * Previous platforms required that PG(n-1) be enabled before PG(n). That
- * dependency chain turns into a dependency tree on XE_LPD:
- *
- * PG0
- * |
- * --PG1--
- * / \
- * PGA --PG2--
- * / | \
- * PGB PGC PGD
- *
- * Power wells must be enabled from top to bottom and disabled from bottom
- * to top. This allows pipes to be power gated independently.
- */
-
-#define XELPD_PW_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_2_POWER_DOMAINS ( \
- XELPD_PW_B_POWER_DOMAINS | \
- XELPD_PW_C_POWER_DOMAINS | \
- XELPD_PW_D_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) | \
- BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-/*
- * XELPD PW_1/PG_1 domains (under HW/DMC control):
- * - DBUF function (registers are in PW0)
- * - Transcoder A
- * - DDI_A and DDI_B
- *
- * XELPD PW_0/PW_1 domains (under HW/DMC control):
- * - PCI
- * - Clocks except port PLL
- * - Shared functions:
- * * interrupts except pipe interrupts
- * * MBus except PIPE_MBUS_DBOX_CTL
- * * DBUF registers
- * - Central power except FBC
- * - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
- */
-
-#define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- XELPD_PW_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
-#define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
-#define XELPD_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
-#define XELPD_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
-#define XELPD_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
-#define XELPD_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
-
-#define XELPD_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
-#define XELPD_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
-#define XELPD_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
-#define XELPD_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
-
-#define XELPD_DDI_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D_XELPD)
-#define XELPD_DDI_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E_XELPD)
-#define XELPD_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
-#define XELPD_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
-#define XELPD_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
-#define XELPD_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
-
-static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
+const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = i9xx_always_on_power_well_noop,
.disable = i9xx_always_on_power_well_noop,
.is_enabled = i9xx_always_on_power_well_enabled,
};
-static const struct i915_power_well_ops chv_pipe_power_well_ops = {
+const struct i915_power_well_ops chv_pipe_power_well_ops = {
.sync_hw = chv_pipe_power_well_sync_hw,
.enable = chv_pipe_power_well_enable,
.disable = chv_pipe_power_well_disable,
.is_enabled = chv_pipe_power_well_enabled,
};
-static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
+const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = chv_dpio_cmn_power_well_enable,
.disable = chv_dpio_cmn_power_well_disable,
.is_enabled = vlv_power_well_enabled,
};
-static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
-};
-
-static const struct i915_power_well_ops i830_pipes_power_well_ops = {
+const struct i915_power_well_ops i830_pipes_power_well_ops = {
.sync_hw = i830_pipes_power_well_sync_hw,
.enable = i830_pipes_power_well_enable,
.disable = i830_pipes_power_well_disable,
.is_enabled = i830_pipes_power_well_enabled,
};
-static const struct i915_power_well_desc i830_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "pipes",
- .domains = I830_PIPES_POWER_DOMAINS,
- .ops = &i830_pipes_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
-};
-
static const struct i915_power_well_regs hsw_power_well_regs = {
.bios = HSW_PWR_WELL_CTL1,
.driver = HSW_PWR_WELL_CTL2,
@@ -3306,7 +2447,7 @@ static const struct i915_power_well_regs hsw_power_well_regs = {
.debug = HSW_PWR_WELL_CTL4,
};
-static const struct i915_power_well_ops hsw_power_well_ops = {
+const struct i915_power_well_ops hsw_power_well_ops = {
.regs = &hsw_power_well_regs,
.sync_hw = hsw_power_well_sync_hw,
.enable = hsw_power_well_enable,
@@ -3314,197 +2455,41 @@ static const struct i915_power_well_ops hsw_power_well_ops = {
.is_enabled = hsw_power_well_enabled,
};
-static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
+const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = gen9_dc_off_power_well_enable,
.disable = gen9_dc_off_power_well_disable,
.is_enabled = gen9_dc_off_power_well_enabled,
};
-static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
+const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = bxt_dpio_cmn_power_well_enable,
.disable = bxt_dpio_cmn_power_well_disable,
.is_enabled = bxt_dpio_cmn_power_well_enabled,
};
-static const struct i915_power_well_desc hsw_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "display",
- .domains = HSW_DISPLAY_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = HSW_DISP_PW_GLOBAL,
- {
- .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
- .hsw.has_vga = true,
- },
- },
-};
-
-static const struct i915_power_well_desc bdw_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "display",
- .domains = BDW_DISPLAY_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = HSW_DISP_PW_GLOBAL,
- {
- .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- },
- },
-};
-
-static const struct i915_power_well_ops vlv_display_power_well_ops = {
+const struct i915_power_well_ops vlv_display_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = vlv_display_power_well_enable,
.disable = vlv_display_power_well_disable,
.is_enabled = vlv_power_well_enabled,
};
-static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
+const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = vlv_dpio_cmn_power_well_enable,
.disable = vlv_dpio_cmn_power_well_disable,
.is_enabled = vlv_power_well_enabled,
};
-static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
+const struct i915_power_well_ops vlv_dpio_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = vlv_power_well_enable,
.disable = vlv_power_well_disable,
.is_enabled = vlv_power_well_enabled,
};
-static const struct i915_power_well_desc vlv_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "display",
- .domains = VLV_DISPLAY_POWER_DOMAINS,
- .ops = &vlv_display_power_well_ops,
- .id = VLV_DISP_PW_DISP2D,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
- },
- },
- {
- .name = "dpio-tx-b-01",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
- .ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
- },
- },
- {
- .name = "dpio-tx-b-23",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
- .ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
- },
- },
- {
- .name = "dpio-tx-c-01",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
- .ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
- },
- },
- {
- .name = "dpio-tx-c-23",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
- .ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
- },
- },
- {
- .name = "dpio-common",
- .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
- .ops = &vlv_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
- },
- },
-};
-
-static const struct i915_power_well_desc chv_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "display",
- /*
- * Pipe A power well is the new disp2d well. Pipe B and C
- * power wells don't actually exist. Pipe A power well is
- * required for any pipe to work.
- */
- .domains = CHV_DISPLAY_POWER_DOMAINS,
- .ops = &chv_pipe_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "dpio-common-bc",
- .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
- .ops = &chv_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
- },
- },
- {
- .name = "dpio-common-d",
- .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
- .ops = &chv_dpio_cmn_power_well_ops,
- .id = CHV_DISP_PW_DPIO_CMN_D,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
- },
- },
-};
-
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id)
{
@@ -3517,279 +2502,13 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
return ret;
}
-static const struct i915_power_well_desc skl_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "MISC IO power well",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_MISC_IO,
- {
- .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
- },
- },
- {
- .name = "DC off",
- .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_2,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DDI A/E IO power well",
- .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
- },
- },
- {
- .name = "DDI B IO power well",
- .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
- },
- },
- {
- .name = "DDI C IO power well",
- .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
- },
- },
- {
- .name = "DDI D IO power well",
- .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
- },
- },
-};
-
-static const struct i915_power_well_desc bxt_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DC off",
- .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_2,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "dpio-common-a",
- .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = BXT_DISP_PW_DPIO_CMN_A,
- {
- .bxt.phy = DPIO_PHY1,
- },
- },
- {
- .name = "dpio-common-bc",
- .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .bxt.phy = DPIO_PHY0,
- },
- },
-};
-
-static const struct i915_power_well_desc glk_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DC off",
- .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_2,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "dpio-common-a",
- .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = BXT_DISP_PW_DPIO_CMN_A,
- {
- .bxt.phy = DPIO_PHY1,
- },
- },
- {
- .name = "dpio-common-b",
- .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .bxt.phy = DPIO_PHY0,
- },
- },
- {
- .name = "dpio-common-c",
- .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = GLK_DISP_PW_DPIO_CMN_C,
- {
- .bxt.phy = DPIO_PHY2,
- },
- },
- {
- .name = "AUX A",
- .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
- },
- },
- {
- .name = "AUX B",
- .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
- },
- },
- {
- .name = "AUX C",
- .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
- },
- },
- {
- .name = "DDI A IO power well",
- .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
- },
- },
- {
- .name = "DDI B IO power well",
- .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
- },
- },
- {
- .name = "DDI C IO power well",
- .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
- },
- },
-};
-
static const struct i915_power_well_regs icl_aux_power_well_regs = {
.bios = ICL_PWR_WELL_CTL_AUX1,
.driver = ICL_PWR_WELL_CTL_AUX2,
.debug = ICL_PWR_WELL_CTL_AUX4,
};
-static const struct i915_power_well_ops icl_aux_power_well_ops = {
+const struct i915_power_well_ops icl_aux_power_well_ops = {
.regs = &icl_aux_power_well_regs,
.sync_hw = hsw_power_well_sync_hw,
.enable = icl_aux_power_well_enable,
@@ -3803,7 +2522,7 @@ static const struct i915_power_well_regs icl_ddi_power_well_regs = {
.debug = ICL_PWR_WELL_CTL_DDI4,
};
-static const struct i915_power_well_ops icl_ddi_power_well_ops = {
+const struct i915_power_well_ops icl_ddi_power_well_ops = {
.regs = &icl_ddi_power_well_regs,
.sync_hw = hsw_power_well_sync_hw,
.enable = hsw_power_well_enable,
@@ -3811,219 +2530,6 @@ static const struct i915_power_well_ops icl_ddi_power_well_ops = {
.is_enabled = hsw_power_well_enabled,
};
-static const struct i915_power_well_desc icl_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DC off",
- .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = ICL_PW_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well 3",
- .domains = ICL_PW_3_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DDI A IO",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- },
- },
- {
- .name = "DDI B IO",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- },
- },
- {
- .name = "DDI C IO",
- .domains = ICL_DDI_IO_C_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
- },
- },
- {
- .name = "DDI D IO",
- .domains = ICL_DDI_IO_D_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
- },
- },
- {
- .name = "DDI E IO",
- .domains = ICL_DDI_IO_E_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
- },
- },
- {
- .name = "DDI F IO",
- .domains = ICL_DDI_IO_F_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
- },
- },
- {
- .name = "AUX A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- },
- {
- .name = "AUX B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- },
- {
- .name = "AUX C TC1",
- .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX D TC2",
- .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX E TC3",
- .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX F TC4",
- .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX C TBT1",
- .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX D TBT2",
- .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX E TBT3",
- .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX F TBT4",
- .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "power well 4",
- .domains = ICL_PW_4_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
- },
- },
-};
-
static void
tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
{
@@ -4101,878 +2607,13 @@ tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
return power_well->count;
}
-static const struct i915_power_well_ops tgl_tc_cold_off_ops = {
+const struct i915_power_well_ops tgl_tc_cold_off_ops = {
.sync_hw = tgl_tc_cold_off_power_well_sync_hw,
.enable = tgl_tc_cold_off_power_well_enable,
.disable = tgl_tc_cold_off_power_well_disable,
.is_enabled = tgl_tc_cold_off_power_well_is_enabled,
};
-static const struct i915_power_well_desc tgl_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DC off",
- .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = TGL_PW_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well 3",
- .domains = TGL_PW_3_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DDI A IO",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
- },
- {
- .name = "DDI B IO",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- },
- {
- .name = "DDI C IO",
- .domains = ICL_DDI_IO_C_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
- }
- },
- {
- .name = "DDI IO TC1",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- },
- },
- {
- .name = "DDI IO TC2",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- },
- },
- {
- .name = "DDI IO TC3",
- .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
- },
- },
- {
- .name = "DDI IO TC4",
- .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
- },
- },
- {
- .name = "DDI IO TC5",
- .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
- },
- },
- {
- .name = "DDI IO TC6",
- .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
- },
- },
- {
- .name = "TC cold off",
- .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
- .ops = &tgl_tc_cold_off_ops,
- .id = TGL_DISP_PW_TC_COLD_OFF,
- },
- {
- .name = "AUX A",
- .domains = TGL_AUX_A_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- },
- {
- .name = "AUX B",
- .domains = TGL_AUX_B_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- },
- {
- .name = "AUX C",
- .domains = TGL_AUX_C_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- },
- },
- {
- .name = "AUX USBC1",
- .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX USBC2",
- .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX USBC3",
- .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX USBC4",
- .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX USBC5",
- .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX USBC6",
- .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX TBT1",
- .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT2",
- .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT3",
- .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT4",
- .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT5",
- .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT6",
- .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "power well 4",
- .domains = TGL_PW_4_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
- }
- },
- {
- .name = "power well 5",
- .domains = TGL_PW_5_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_PW_5,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_D),
- },
- },
-};
-
-static const struct i915_power_well_desc rkl_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DC off",
- .domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 3",
- .domains = RKL_PW_3_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well 4",
- .domains = RKL_PW_4_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
- }
- },
- {
- .name = "DDI A IO",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
- },
- {
- .name = "DDI B IO",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- },
- {
- .name = "DDI IO TC1",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- },
- },
- {
- .name = "DDI IO TC2",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- },
- },
- {
- .name = "AUX A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- },
- {
- .name = "AUX B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- },
- {
- .name = "AUX USBC1",
- .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- },
- },
- {
- .name = "AUX USBC2",
- .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- },
- },
-};
-
-static const struct i915_power_well_desc dg1_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DC off",
- .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = DG1_PW_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well 3",
- .domains = DG1_PW_3_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DDI A IO",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
- },
- {
- .name = "DDI B IO",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- },
- {
- .name = "DDI IO TC1",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- },
- },
- {
- .name = "DDI IO TC2",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- },
- },
- {
- .name = "AUX A",
- .domains = TGL_AUX_A_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- },
- {
- .name = "AUX B",
- .domains = TGL_AUX_B_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- },
- {
- .name = "AUX USBC1",
- .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX USBC2",
- .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "power well 4",
- .domains = TGL_PW_4_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
- }
- },
- {
- .name = "power well 5",
- .domains = TGL_PW_5_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_PW_5,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_D),
- },
- },
-};
-
-static const struct i915_power_well_desc xelpd_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DC off",
- .domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = XELPD_PW_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well A",
- .domains = XELPD_PW_A_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_A,
- .hsw.irq_pipe_mask = BIT(PIPE_A),
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well B",
- .domains = XELPD_PW_B_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_B,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well C",
- .domains = XELPD_PW_C_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_C,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well D",
- .domains = XELPD_PW_D_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_D,
- .hsw.irq_pipe_mask = BIT(PIPE_D),
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DDI A IO",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
- },
- {
- .name = "DDI B IO",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- },
- {
- .name = "DDI C IO",
- .domains = ICL_DDI_IO_C_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
- }
- },
- {
- .name = "DDI IO D_XELPD",
- .domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_DDI_D,
- }
- },
- {
- .name = "DDI IO E_XELPD",
- .domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_DDI_E,
- }
- },
- {
- .name = "DDI IO TC1",
- .domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- }
- },
- {
- .name = "DDI IO TC2",
- .domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- }
- },
- {
- .name = "DDI IO TC3",
- .domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
- }
- },
- {
- .name = "DDI IO TC4",
- .domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
- }
- },
- {
- .name = "AUX A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- .hsw.fixed_enable_delay = 600,
- },
- },
- {
- .name = "AUX B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- .hsw.fixed_enable_delay = 600,
- },
- },
- {
- .name = "AUX C",
- .domains = TGL_AUX_C_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- .hsw.fixed_enable_delay = 600,
- },
- },
- {
- .name = "AUX D_XELPD",
- .domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
- .hsw.fixed_enable_delay = 600,
- },
- },
- {
- .name = "AUX E_XELPD",
- .domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_AUX_E,
- },
- },
- {
- .name = "AUX USBC1",
- .domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- .hsw.fixed_enable_delay = 600,
- },
- },
- {
- .name = "AUX USBC2",
- .domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- },
- },
- {
- .name = "AUX USBC3",
- .domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
- },
- },
- {
- .name = "AUX USBC4",
- .domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
- },
- },
- {
- .name = "AUX TBT1",
- .domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT2",
- .domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT3",
- .domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT4",
- .domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
- .hsw.is_tc_tbt = true,
- },
- },
-};
-
static int
sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
int disable_power_well)
@@ -5051,57 +2692,6 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
return mask;
}
-static int
-__set_power_wells(struct i915_power_domains *power_domains,
- const struct i915_power_well_desc *power_well_descs,
- int power_well_descs_sz, u64 skip_mask)
-{
- struct drm_i915_private *i915 = container_of(power_domains,
- struct drm_i915_private,
- power_domains);
- u64 power_well_ids = 0;
- int power_well_count = 0;
- int i, plt_idx = 0;
-
- for (i = 0; i < power_well_descs_sz; i++)
- if (!(BIT_ULL(power_well_descs[i].id) & skip_mask))
- power_well_count++;
-
- power_domains->power_well_count = power_well_count;
- power_domains->power_wells =
- kcalloc(power_well_count,
- sizeof(*power_domains->power_wells),
- GFP_KERNEL);
- if (!power_domains->power_wells)
- return -ENOMEM;
-
- for (i = 0; i < power_well_descs_sz; i++) {
- enum i915_power_well_id id = power_well_descs[i].id;
-
- if (BIT_ULL(id) & skip_mask)
- continue;
-
- power_domains->power_wells[plt_idx++].desc =
- &power_well_descs[i];
-
- if (id == DISP_PW_ID_NONE)
- continue;
-
- drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) * 8);
- drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id));
- power_well_ids |= BIT_ULL(id);
- }
-
- return 0;
-}
-
-#define set_power_wells_mask(power_domains, __power_well_descs, skip_mask) \
- __set_power_wells(power_domains, __power_well_descs, \
- ARRAY_SIZE(__power_well_descs), skip_mask)
-
-#define set_power_wells(power_domains, __power_well_descs) \
- set_power_wells_mask(power_domains, __power_well_descs, 0)
-
/**
* intel_power_domains_init - initializes the power domain structures
* @dev_priv: i915 device instance
@@ -5112,7 +2702,6 @@ __set_power_wells(struct i915_power_domains *power_domains,
int intel_power_domains_init(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
- int err;
dev_priv->params.disable_power_well =
sanitize_disable_power_well_option(dev_priv,
@@ -5130,47 +2719,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
INIT_DELAYED_WORK(&power_domains->async_put_work,
intel_display_power_put_async_work);
- /*
- * The enabling order will be from lower to higher indexed wells,
- * the disabling order is reversed.
- */
- if (!HAS_DISPLAY(dev_priv)) {
- power_domains->power_well_count = 0;
- err = 0;
- } else if (DISPLAY_VER(dev_priv) >= 13) {
- err = set_power_wells(power_domains, xelpd_power_wells);
- } else if (IS_DG1(dev_priv)) {
- err = set_power_wells(power_domains, dg1_power_wells);
- } else if (IS_ALDERLAKE_S(dev_priv)) {
- err = set_power_wells_mask(power_domains, tgl_power_wells,
- BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
- } else if (IS_ROCKETLAKE(dev_priv)) {
- err = set_power_wells(power_domains, rkl_power_wells);
- } else if (DISPLAY_VER(dev_priv) == 12) {
- err = set_power_wells(power_domains, tgl_power_wells);
- } else if (DISPLAY_VER(dev_priv) == 11) {
- err = set_power_wells(power_domains, icl_power_wells);
- } else if (IS_GEMINILAKE(dev_priv)) {
- err = set_power_wells(power_domains, glk_power_wells);
- } else if (IS_BROXTON(dev_priv)) {
- err = set_power_wells(power_domains, bxt_power_wells);
- } else if (DISPLAY_VER(dev_priv) == 9) {
- err = set_power_wells(power_domains, skl_power_wells);
- } else if (IS_CHERRYVIEW(dev_priv)) {
- err = set_power_wells(power_domains, chv_power_wells);
- } else if (IS_BROADWELL(dev_priv)) {
- err = set_power_wells(power_domains, bdw_power_wells);
- } else if (IS_HASWELL(dev_priv)) {
- err = set_power_wells(power_domains, hsw_power_wells);
- } else if (IS_VALLEYVIEW(dev_priv)) {
- err = set_power_wells(power_domains, vlv_power_wells);
- } else if (IS_I830(dev_priv)) {
- err = set_power_wells(power_domains, i830_power_wells);
- } else {
- err = set_power_wells(power_domains, i9xx_always_on_power_well);
- }
-
- return err;
+ return intel_init_power_wells(power_domains);
}
/**
@@ -5181,7 +2730,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
*/
void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
{
- kfree(dev_priv->power_domains.power_wells);
+ intel_cleanup_power_wells(&dev_priv->power_domains);
}
static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index b30e6133c66d0..a0e68ae691021 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -197,6 +197,7 @@ struct intel_display_power_domain_set {
for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
for_each_if(BIT_ULL(domain) & (mask))
+/* intel_display_power.c */
int intel_power_domains_init(struct drm_i915_private *dev_priv);
void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
@@ -316,4 +317,8 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
enum dpio_channel ch, bool override);
+/* intel_display_power_map.c */
+const char *
+intel_display_power_domain_str(enum intel_display_power_domain domain);
+
#endif /* __INTEL_DISPLAY_POWER_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
new file mode 100644
index 0000000000000..3fc7c7d0bc9e9
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_DISPLAY_POWER_INTERNAL_H__
+#define __INTEL_DISPLAY_POWER_INTERNAL_H__
+
+#include "i915_reg_defs.h"
+
+#include "intel_display.h"
+#include "intel_display_power.h"
+
+struct i915_power_well_regs;
+
+/* Power well structure for haswell */
+struct i915_power_well_desc {
+ const char *name;
+ bool always_on;
+ u64 domains;
+ /* unique identifier for this power well */
+ enum i915_power_well_id id;
+ /*
+ * Arbitraty data associated with this power well. Platform and power
+ * well specific.
+ */
+ union {
+ struct {
+ /*
+ * request/status flag index in the PUNIT power well
+ * control/status registers.
+ */
+ u8 idx;
+ } vlv;
+ struct {
+ enum dpio_phy phy;
+ } bxt;
+ struct {
+ /*
+ * request/status flag index in the power well
+ * constrol/status registers.
+ */
+ u8 idx;
+ /* Mask of pipes whose IRQ logic is backed by the pw */
+ u8 irq_pipe_mask;
+ /*
+ * Instead of waiting for the status bit to ack enables,
+ * just wait a specific amount of time and then consider
+ * the well enabled.
+ */
+ u16 fixed_enable_delay;
+ /* The pw is backing the VGA functionality */
+ bool has_vga:1;
+ bool has_fuses:1;
+ /*
+ * The pw is for an ICL+ TypeC PHY port in
+ * Thunderbolt mode.
+ */
+ bool is_tc_tbt:1;
+ } hsw;
+ };
+ const struct i915_power_well_ops *ops;
+};
+
+struct i915_power_well {
+ const struct i915_power_well_desc *desc;
+ /* power well enable/disable usage count */
+ int count;
+ /* cached hw enabled state */
+ bool hw_enabled;
+};
+
+/* intel_display_power.c */
+extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
+extern const struct i915_power_well_ops chv_pipe_power_well_ops;
+extern const struct i915_power_well_ops chv_dpio_cmn_power_well_ops;
+extern const struct i915_power_well_ops i830_pipes_power_well_ops;
+extern const struct i915_power_well_ops hsw_power_well_ops;
+extern const struct i915_power_well_ops hsw_power_well_ops;
+extern const struct i915_power_well_ops gen9_dc_off_power_well_ops;
+extern const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops;
+extern const struct i915_power_well_ops vlv_display_power_well_ops;
+extern const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops;
+extern const struct i915_power_well_ops vlv_dpio_power_well_ops;
+extern const struct i915_power_well_ops icl_ddi_power_well_ops;
+extern const struct i915_power_well_ops icl_aux_power_well_ops;
+extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
+
+/* intel_display_power_map.c */
+int intel_init_power_wells(struct i915_power_domains *power_domains);
+void intel_cleanup_power_wells(struct i915_power_domains *power_domains);
+
+#endif
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
new file mode 100644
index 0000000000000..e8732f6e85098
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -0,0 +1,2277 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "i915_drv.h"
+
+#include "vlv_sideband_reg.h"
+
+#include "intel_display_power.h"
+#include "intel_display_power_internal.h"
+
+#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
+
+const char *
+intel_display_power_domain_str(enum intel_display_power_domain domain)
+{
+ switch (domain) {
+ case POWER_DOMAIN_DISPLAY_CORE:
+ return "DISPLAY_CORE";
+ case POWER_DOMAIN_PIPE_A:
+ return "PIPE_A";
+ case POWER_DOMAIN_PIPE_B:
+ return "PIPE_B";
+ case POWER_DOMAIN_PIPE_C:
+ return "PIPE_C";
+ case POWER_DOMAIN_PIPE_D:
+ return "PIPE_D";
+ case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
+ return "PIPE_A_PANEL_FITTER";
+ case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
+ return "PIPE_B_PANEL_FITTER";
+ case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
+ return "PIPE_C_PANEL_FITTER";
+ case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
+ return "PIPE_D_PANEL_FITTER";
+ case POWER_DOMAIN_TRANSCODER_A:
+ return "TRANSCODER_A";
+ case POWER_DOMAIN_TRANSCODER_B:
+ return "TRANSCODER_B";
+ case POWER_DOMAIN_TRANSCODER_C:
+ return "TRANSCODER_C";
+ case POWER_DOMAIN_TRANSCODER_D:
+ return "TRANSCODER_D";
+ case POWER_DOMAIN_TRANSCODER_EDP:
+ return "TRANSCODER_EDP";
+ case POWER_DOMAIN_TRANSCODER_DSI_A:
+ return "TRANSCODER_DSI_A";
+ case POWER_DOMAIN_TRANSCODER_DSI_C:
+ return "TRANSCODER_DSI_C";
+ case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
+ return "TRANSCODER_VDSC_PW2";
+ case POWER_DOMAIN_PORT_DDI_A_LANES:
+ return "PORT_DDI_A_LANES";
+ case POWER_DOMAIN_PORT_DDI_B_LANES:
+ return "PORT_DDI_B_LANES";
+ case POWER_DOMAIN_PORT_DDI_C_LANES:
+ return "PORT_DDI_C_LANES";
+ case POWER_DOMAIN_PORT_DDI_D_LANES:
+ return "PORT_DDI_D_LANES";
+ case POWER_DOMAIN_PORT_DDI_E_LANES:
+ return "PORT_DDI_E_LANES";
+ case POWER_DOMAIN_PORT_DDI_F_LANES:
+ return "PORT_DDI_F_LANES";
+ case POWER_DOMAIN_PORT_DDI_G_LANES:
+ return "PORT_DDI_G_LANES";
+ case POWER_DOMAIN_PORT_DDI_H_LANES:
+ return "PORT_DDI_H_LANES";
+ case POWER_DOMAIN_PORT_DDI_I_LANES:
+ return "PORT_DDI_I_LANES";
+ case POWER_DOMAIN_PORT_DDI_A_IO:
+ return "PORT_DDI_A_IO";
+ case POWER_DOMAIN_PORT_DDI_B_IO:
+ return "PORT_DDI_B_IO";
+ case POWER_DOMAIN_PORT_DDI_C_IO:
+ return "PORT_DDI_C_IO";
+ case POWER_DOMAIN_PORT_DDI_D_IO:
+ return "PORT_DDI_D_IO";
+ case POWER_DOMAIN_PORT_DDI_E_IO:
+ return "PORT_DDI_E_IO";
+ case POWER_DOMAIN_PORT_DDI_F_IO:
+ return "PORT_DDI_F_IO";
+ case POWER_DOMAIN_PORT_DDI_G_IO:
+ return "PORT_DDI_G_IO";
+ case POWER_DOMAIN_PORT_DDI_H_IO:
+ return "PORT_DDI_H_IO";
+ case POWER_DOMAIN_PORT_DDI_I_IO:
+ return "PORT_DDI_I_IO";
+ case POWER_DOMAIN_PORT_DSI:
+ return "PORT_DSI";
+ case POWER_DOMAIN_PORT_CRT:
+ return "PORT_CRT";
+ case POWER_DOMAIN_PORT_OTHER:
+ return "PORT_OTHER";
+ case POWER_DOMAIN_VGA:
+ return "VGA";
+ case POWER_DOMAIN_AUDIO_MMIO:
+ return "AUDIO_MMIO";
+ case POWER_DOMAIN_AUDIO_PLAYBACK:
+ return "AUDIO_PLAYBACK";
+ case POWER_DOMAIN_AUX_A:
+ return "AUX_A";
+ case POWER_DOMAIN_AUX_B:
+ return "AUX_B";
+ case POWER_DOMAIN_AUX_C:
+ return "AUX_C";
+ case POWER_DOMAIN_AUX_D:
+ return "AUX_D";
+ case POWER_DOMAIN_AUX_E:
+ return "AUX_E";
+ case POWER_DOMAIN_AUX_F:
+ return "AUX_F";
+ case POWER_DOMAIN_AUX_G:
+ return "AUX_G";
+ case POWER_DOMAIN_AUX_H:
+ return "AUX_H";
+ case POWER_DOMAIN_AUX_I:
+ return "AUX_I";
+ case POWER_DOMAIN_AUX_IO_A:
+ return "AUX_IO_A";
+ case POWER_DOMAIN_AUX_C_TBT:
+ return "AUX_C_TBT";
+ case POWER_DOMAIN_AUX_D_TBT:
+ return "AUX_D_TBT";
+ case POWER_DOMAIN_AUX_E_TBT:
+ return "AUX_E_TBT";
+ case POWER_DOMAIN_AUX_F_TBT:
+ return "AUX_F_TBT";
+ case POWER_DOMAIN_AUX_G_TBT:
+ return "AUX_G_TBT";
+ case POWER_DOMAIN_AUX_H_TBT:
+ return "AUX_H_TBT";
+ case POWER_DOMAIN_AUX_I_TBT:
+ return "AUX_I_TBT";
+ case POWER_DOMAIN_GMBUS:
+ return "GMBUS";
+ case POWER_DOMAIN_INIT:
+ return "INIT";
+ case POWER_DOMAIN_MODESET:
+ return "MODESET";
+ case POWER_DOMAIN_GT_IRQ:
+ return "GT_IRQ";
+ case POWER_DOMAIN_DC_OFF:
+ return "DC_OFF";
+ case POWER_DOMAIN_TC_COLD_OFF:
+ return "TC_COLD_OFF";
+ default:
+ MISSING_CASE(domain);
+ return "?";
+ }
+}
+
+static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ },
+};
+
+#define I830_PIPES_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc i830_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "pipes",
+ .domains = I830_PIPES_POWER_DOMAINS,
+ .ops = &i830_pipes_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ },
+};
+
+#define HSW_DISPLAY_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc hsw_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "display",
+ .domains = HSW_DISPLAY_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = HSW_DISP_PW_GLOBAL,
+ {
+ .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
+ .hsw.has_vga = true,
+ },
+ },
+};
+
+#define BDW_DISPLAY_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc bdw_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "display",
+ .domains = BDW_DISPLAY_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = HSW_DISP_PW_GLOBAL,
+ {
+ .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ },
+ },
+};
+
+#define VLV_DISPLAY_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
+ BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_GMBUS) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc vlv_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "display",
+ .domains = VLV_DISPLAY_POWER_DOMAINS,
+ .ops = &vlv_display_power_well_ops,
+ .id = VLV_DISP_PW_DISP2D,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
+ },
+ }, {
+ .name = "dpio-tx-b-01",
+ .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .ops = &vlv_dpio_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
+ },
+ }, {
+ .name = "dpio-tx-b-23",
+ .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .ops = &vlv_dpio_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
+ },
+ }, {
+ .name = "dpio-tx-c-01",
+ .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .ops = &vlv_dpio_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
+ },
+ }, {
+ .name = "dpio-tx-c-23",
+ .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .ops = &vlv_dpio_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
+ },
+ }, {
+ .name = "dpio-common",
+ .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
+ .ops = &vlv_dpio_cmn_power_well_ops,
+ .id = VLV_DISP_PW_DPIO_CMN_BC,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
+ },
+ },
+};
+
+#define CHV_DISPLAY_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_GMBUS) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc chv_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "display",
+ /*
+ * Pipe A power well is the new disp2d well. Pipe B and C
+ * power wells don't actually exist. Pipe A power well is
+ * required for any pipe to work.
+ */
+ .domains = CHV_DISPLAY_POWER_DOMAINS,
+ .ops = &chv_pipe_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "dpio-common-bc",
+ .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
+ .ops = &chv_dpio_cmn_power_well_ops,
+ .id = VLV_DISP_PW_DPIO_CMN_BC,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
+ },
+ }, {
+ .name = "dpio-common-d",
+ .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
+ .ops = &chv_dpio_cmn_power_well_ops,
+ .id = CHV_DISP_PW_DPIO_CMN_D,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
+ },
+ },
+};
+
+#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc skl_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "MISC IO power well",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_MISC_IO,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
+ },
+ }, {
+ .name = "DC off",
+ .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 2",
+ .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DDI A/E IO power well",
+ .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
+ },
+ }, {
+ .name = "DDI B IO power well",
+ .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
+ },
+ }, {
+ .name = "DDI C IO power well",
+ .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
+ },
+ }, {
+ .name = "DDI D IO power well",
+ .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
+ },
+ },
+};
+
+#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_GMBUS) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc bxt_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DC off",
+ .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 2",
+ .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "dpio-common-a",
+ .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
+ .ops = &bxt_dpio_cmn_power_well_ops,
+ .id = BXT_DISP_PW_DPIO_CMN_A,
+ {
+ .bxt.phy = DPIO_PHY1,
+ },
+ }, {
+ .name = "dpio-common-bc",
+ .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
+ .ops = &bxt_dpio_cmn_power_well_ops,
+ .id = VLV_DISP_PW_DPIO_CMN_BC,
+ {
+ .bxt.phy = DPIO_PHY0,
+ },
+ },
+};
+
+#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_GMBUS) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)
+#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)
+#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)
+
+#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc glk_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DC off",
+ .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 2",
+ .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "dpio-common-a",
+ .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
+ .ops = &bxt_dpio_cmn_power_well_ops,
+ .id = BXT_DISP_PW_DPIO_CMN_A,
+ {
+ .bxt.phy = DPIO_PHY1,
+ },
+ }, {
+ .name = "dpio-common-b",
+ .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
+ .ops = &bxt_dpio_cmn_power_well_ops,
+ .id = VLV_DISP_PW_DPIO_CMN_BC,
+ {
+ .bxt.phy = DPIO_PHY0,
+ },
+ }, {
+ .name = "dpio-common-c",
+ .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
+ .ops = &bxt_dpio_cmn_power_well_ops,
+ .id = GLK_DISP_PW_DPIO_CMN_C,
+ {
+ .bxt.phy = DPIO_PHY2,
+ },
+ }, {
+ .name = "AUX A",
+ .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
+ },
+ }, {
+ .name = "AUX B",
+ .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
+ },
+ }, {
+ .name = "AUX C",
+ .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
+ },
+ }, {
+ .name = "DDI A IO power well",
+ .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
+ },
+ }, {
+ .name = "DDI B IO power well",
+ .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
+ },
+ }, {
+ .name = "DDI C IO power well",
+ .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
+ },
+ },
+};
+
+/*
+ * ICL PW_0/PG_0 domains (HW/DMC control):
+ * - PCI
+ * - clocks except port PLL
+ * - central power except FBC
+ * - shared functions except pipe interrupts, pipe MBUS, DBUF registers
+ * ICL PW_1/PG_1 domains (HW/DMC control):
+ * - DBUF function
+ * - PIPE_A and its planes, except VGA
+ * - transcoder EDP + PSR
+ * - transcoder DSI
+ * - DDI_A
+ * - FBC
+ */
+#define ICL_PW_4_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+ /* VDSC/joining */
+
+#define ICL_PW_3_POWER_DOMAINS ( \
+ ICL_PW_4_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E) | \
+ BIT_ULL(POWER_DOMAIN_AUX_F) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+ /*
+ * - transcoder WD
+ * - KVMR (HW control)
+ */
+
+#define ICL_PW_2_POWER_DOMAINS ( \
+ ICL_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+ /*
+ * - KVMR (HW control)
+ */
+
+#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ ICL_PW_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_DC_OFF) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define ICL_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)
+#define ICL_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)
+#define ICL_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)
+#define ICL_DDI_IO_D_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO)
+#define ICL_DDI_IO_E_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO)
+#define ICL_DDI_IO_F_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO)
+
+#define ICL_AUX_A_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_IO_A))
+
+#define ICL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_B)
+#define ICL_AUX_C_TC1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C)
+#define ICL_AUX_D_TC2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D)
+#define ICL_AUX_E_TC3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E)
+#define ICL_AUX_F_TC4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F)
+#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C_TBT)
+#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_TBT)
+#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_TBT)
+#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F_TBT)
+
+static const struct i915_power_well_desc icl_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DC off",
+ .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 2",
+ .domains = ICL_PW_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well 3",
+ .domains = ICL_PW_3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = ICL_DISP_PW_3,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ },
+ }, {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ },
+ }, {
+ .name = "DDI C IO",
+ .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
+ },
+ }, {
+ .name = "DDI D IO",
+ .domains = ICL_DDI_IO_D_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
+ },
+ }, {
+ .name = "DDI E IO",
+ .domains = ICL_DDI_IO_E_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
+ },
+ }, {
+ .name = "DDI F IO",
+ .domains = ICL_DDI_IO_F_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
+ },
+ }, {
+ .name = "AUX A",
+ .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
+ }, {
+ .name = "AUX B",
+ .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ },
+ }, {
+ .name = "AUX C TC1",
+ .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX D TC2",
+ .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX E TC3",
+ .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX F TC4",
+ .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX C TBT1",
+ .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX D TBT2",
+ .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX E TBT3",
+ .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX F TBT4",
+ .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "power well 4",
+ .domains = ICL_PW_4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ },
+ },
+};
+
+#define TGL_PW_5_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_PW_4_POWER_DOMAINS ( \
+ TGL_PW_5_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_PW_3_POWER_DOMAINS ( \
+ TGL_PW_4_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_PW_2_POWER_DOMAINS ( \
+ TGL_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ TGL_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
+#define TGL_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
+#define TGL_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
+#define TGL_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
+#define TGL_DDI_IO_TC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC5)
+#define TGL_DDI_IO_TC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC6)
+
+#define TGL_AUX_A_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_IO_A))
+#define TGL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_B)
+#define TGL_AUX_C_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C)
+
+#define TGL_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
+#define TGL_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
+#define TGL_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
+#define TGL_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
+#define TGL_AUX_IO_USBC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC5)
+#define TGL_AUX_IO_USBC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC6)
+
+#define TGL_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
+#define TGL_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
+#define TGL_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
+#define TGL_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
+#define TGL_AUX_IO_TBT5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT5)
+#define TGL_AUX_IO_TBT6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT6)
+
+#define TGL_TC_COLD_OFF_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
+ BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
+
+static const struct i915_power_well_desc tgl_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DC off",
+ .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 2",
+ .domains = TGL_PW_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well 3",
+ .domains = TGL_PW_3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = ICL_DISP_PW_3,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ }
+ }, {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ }
+ }, {
+ .name = "DDI C IO",
+ .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
+ }
+ }, {
+ .name = "DDI IO TC1",
+ .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+ },
+ }, {
+ .name = "DDI IO TC2",
+ .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+ },
+ }, {
+ .name = "DDI IO TC3",
+ .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
+ },
+ }, {
+ .name = "DDI IO TC4",
+ .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
+ },
+ }, {
+ .name = "DDI IO TC5",
+ .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
+ },
+ }, {
+ .name = "DDI IO TC6",
+ .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
+ },
+ }, {
+ .name = "TC cold off",
+ .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
+ .ops = &tgl_tc_cold_off_ops,
+ .id = TGL_DISP_PW_TC_COLD_OFF,
+ }, {
+ .name = "AUX A",
+ .domains = TGL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
+ }, {
+ .name = "AUX B",
+ .domains = TGL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ },
+ }, {
+ .name = "AUX C",
+ .domains = TGL_AUX_C_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
+ },
+ }, {
+ .name = "AUX USBC1",
+ .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX USBC2",
+ .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX USBC3",
+ .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX USBC4",
+ .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX USBC5",
+ .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX USBC6",
+ .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX TBT1",
+ .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT2",
+ .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT3",
+ .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT4",
+ .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT5",
+ .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT6",
+ .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "power well 4",
+ .domains = TGL_PW_4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ }
+ }, {
+ .name = "power well 5",
+ .domains = TGL_PW_5_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ },
+ },
+};
+
+#define RKL_PW_4_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define RKL_PW_3_POWER_DOMAINS ( \
+ RKL_PW_4_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+/*
+ * There is no PW_2/PG_2 on RKL.
+ *
+ * RKL PW_1/PG_1 domains (under HW/DMC control):
+ * - DBUF function (note: registers are in PW0)
+ * - PIPE_A and its planes and VDSC/joining, except VGA
+ * - transcoder A
+ * - DDI_A and DDI_B
+ * - FBC
+ *
+ * RKL PW_0/PG_0 domains (under HW/DMC control):
+ * - PCI
+ * - clocks except port PLL
+ * - shared functions:
+ * * interrupts except pipe interrupts
+ * * MBus except PIPE_MBUS_DBOX_CTL
+ * * DBUF registers
+ * - central power except FBC
+ * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
+ */
+
+#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ RKL_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc rkl_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DC off",
+ .domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 3",
+ .domains = RKL_PW_3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = ICL_DISP_PW_3,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well 4",
+ .domains = RKL_PW_4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ }
+ }, {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ }
+ }, {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ }
+ }, {
+ .name = "DDI IO TC1",
+ .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+ },
+ }, {
+ .name = "DDI IO TC2",
+ .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+ },
+ }, {
+ .name = "AUX A",
+ .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
+ }, {
+ .name = "AUX B",
+ .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ },
+ }, {
+ .name = "AUX USBC1",
+ .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+ },
+ }, {
+ .name = "AUX USBC2",
+ .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+ },
+ },
+};
+
+/*
+ * DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
+ */
+#define DG1_PW_3_POWER_DOMAINS ( \
+ TGL_PW_4_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ DG1_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_2_POWER_DOMAINS ( \
+ DG1_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc dg1_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DC off",
+ .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 2",
+ .domains = DG1_PW_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well 3",
+ .domains = DG1_PW_3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = ICL_DISP_PW_3,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ }
+ }, {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ }
+ }, {
+ .name = "DDI IO TC1",
+ .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+ },
+ }, {
+ .name = "DDI IO TC2",
+ .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+ },
+ }, {
+ .name = "AUX A",
+ .domains = TGL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
+ }, {
+ .name = "AUX B",
+ .domains = TGL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ },
+ }, {
+ .name = "AUX USBC1",
+ .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX USBC2",
+ .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "power well 4",
+ .domains = TGL_PW_4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ }
+ }, {
+ .name = "power well 5",
+ .domains = TGL_PW_5_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ },
+ },
+};
+
+/*
+ * XE_LPD Power Domains
+ *
+ * Previous platforms required that PG(n-1) be enabled before PG(n). That
+ * dependency chain turns into a dependency tree on XE_LPD:
+ *
+ * PG0
+ * |
+ * --PG1--
+ * / \
+ * PGA --PG2--
+ * / | \
+ * PGB PGC PGD
+ *
+ * Power wells must be enabled from top to bottom and disabled from bottom
+ * to top. This allows pipes to be power gated independently.
+ */
+
+#define XELPD_PW_D_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_2_POWER_DOMAINS ( \
+ XELPD_PW_B_POWER_DOMAINS | \
+ XELPD_PW_C_POWER_DOMAINS | \
+ XELPD_PW_D_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+/*
+ * XELPD PW_1/PG_1 domains (under HW/DMC control):
+ * - DBUF function (registers are in PW0)
+ * - Transcoder A
+ * - DDI_A and DDI_B
+ *
+ * XELPD PW_0/PW_1 domains (under HW/DMC control):
+ * - PCI
+ * - Clocks except port PLL
+ * - Shared functions:
+ * * interrupts except pipe interrupts
+ * * MBus except PIPE_MBUS_DBOX_CTL
+ * * DBUF registers
+ * - Central power except FBC
+ * - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
+ */
+
+#define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ XELPD_PW_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
+#define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
+#define XELPD_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
+#define XELPD_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
+#define XELPD_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
+#define XELPD_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
+
+#define XELPD_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
+#define XELPD_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
+#define XELPD_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
+#define XELPD_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
+
+#define XELPD_DDI_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D_XELPD)
+#define XELPD_DDI_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E_XELPD)
+#define XELPD_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
+#define XELPD_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
+#define XELPD_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
+#define XELPD_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
+
+static const struct i915_power_well_desc xelpd_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DC off",
+ .domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 2",
+ .domains = XELPD_PW_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well A",
+ .domains = XELPD_PW_A_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_A,
+ .hsw.irq_pipe_mask = BIT(PIPE_A),
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well B",
+ .domains = XELPD_PW_B_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_B,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well C",
+ .domains = XELPD_PW_C_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_C,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well D",
+ .domains = XELPD_PW_D_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_D,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ }
+ }, {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ }
+ }, {
+ .name = "DDI C IO",
+ .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
+ }
+ }, {
+ .name = "DDI IO D_XELPD",
+ .domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_DDI_D,
+ }
+ }, {
+ .name = "DDI IO E_XELPD",
+ .domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_DDI_E,
+ }
+ }, {
+ .name = "DDI IO TC1",
+ .domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+ }
+ }, {
+ .name = "DDI IO TC2",
+ .domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+ }
+ }, {
+ .name = "DDI IO TC3",
+ .domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
+ }
+ }, {
+ .name = "DDI IO TC4",
+ .domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
+ }
+ }, {
+ .name = "AUX A",
+ .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ .hsw.fixed_enable_delay = 600,
+ },
+ }, {
+ .name = "AUX B",
+ .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ .hsw.fixed_enable_delay = 600,
+ },
+ }, {
+ .name = "AUX C",
+ .domains = TGL_AUX_C_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
+ .hsw.fixed_enable_delay = 600,
+ },
+ }, {
+ .name = "AUX D_XELPD",
+ .domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
+ .hsw.fixed_enable_delay = 600,
+ },
+ }, {
+ .name = "AUX E_XELPD",
+ .domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_AUX_E,
+ },
+ }, {
+ .name = "AUX USBC1",
+ .domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+ .hsw.fixed_enable_delay = 600,
+ },
+ }, {
+ .name = "AUX USBC2",
+ .domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+ },
+ }, {
+ .name = "AUX USBC3",
+ .domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
+ },
+ }, {
+ .name = "AUX USBC4",
+ .domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
+ },
+ }, {
+ .name = "AUX TBT1",
+ .domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT2",
+ .domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT3",
+ .domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT4",
+ .domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+};
+
+static int
+__set_power_wells(struct i915_power_domains *power_domains,
+ const struct i915_power_well_desc *power_well_descs,
+ int power_well_descs_sz, u64 skip_mask)
+{
+ struct drm_i915_private *i915 = container_of(power_domains,
+ struct drm_i915_private,
+ power_domains);
+ u64 power_well_ids = 0;
+ int power_well_count = 0;
+ int i, plt_idx = 0;
+
+ for (i = 0; i < power_well_descs_sz; i++)
+ if (!(BIT_ULL(power_well_descs[i].id) & skip_mask))
+ power_well_count++;
+
+ power_domains->power_well_count = power_well_count;
+ power_domains->power_wells =
+ kcalloc(power_well_count,
+ sizeof(*power_domains->power_wells),
+ GFP_KERNEL);
+ if (!power_domains->power_wells)
+ return -ENOMEM;
+
+ for (i = 0; i < power_well_descs_sz; i++) {
+ enum i915_power_well_id id = power_well_descs[i].id;
+
+ if (BIT_ULL(id) & skip_mask)
+ continue;
+
+ power_domains->power_wells[plt_idx++].desc =
+ &power_well_descs[i];
+
+ if (id == DISP_PW_ID_NONE)
+ continue;
+
+ drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) * 8);
+ drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id));
+ power_well_ids |= BIT_ULL(id);
+ }
+
+ return 0;
+}
+
+#define set_power_wells_mask(power_domains, __power_well_descs, skip_mask) \
+ __set_power_wells(power_domains, __power_well_descs, \
+ ARRAY_SIZE(__power_well_descs), skip_mask)
+
+#define set_power_wells(power_domains, __power_well_descs) \
+ set_power_wells_mask(power_domains, __power_well_descs, 0)
+
+int intel_init_power_wells(struct i915_power_domains *power_domains)
+{
+ struct drm_i915_private *i915 = container_of(power_domains,
+ struct drm_i915_private,
+ power_domains);
+ /*
+ * The enabling order will be from lower to higher indexed wells,
+ * the disabling order is reversed.
+ */
+ if (!HAS_DISPLAY(i915)) {
+ power_domains->power_well_count = 0;
+ return 0;
+ }
+
+ if (DISPLAY_VER(i915) >= 13)
+ return set_power_wells(power_domains, xelpd_power_wells);
+ else if (IS_DG1(i915))
+ return set_power_wells(power_domains, dg1_power_wells);
+ else if (IS_ALDERLAKE_S(i915))
+ return set_power_wells_mask(power_domains, tgl_power_wells,
+ BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
+ else if (IS_ROCKETLAKE(i915))
+ return set_power_wells(power_domains, rkl_power_wells);
+ else if (DISPLAY_VER(i915) == 12)
+ return set_power_wells(power_domains, tgl_power_wells);
+ else if (DISPLAY_VER(i915) == 11)
+ return set_power_wells(power_domains, icl_power_wells);
+ else if (IS_GEMINILAKE(i915))
+ return set_power_wells(power_domains, glk_power_wells);
+ else if (IS_BROXTON(i915))
+ return set_power_wells(power_domains, bxt_power_wells);
+ else if (DISPLAY_VER(i915) == 9)
+ return set_power_wells(power_domains, skl_power_wells);
+ else if (IS_CHERRYVIEW(i915))
+ return set_power_wells(power_domains, chv_power_wells);
+ else if (IS_BROADWELL(i915))
+ return set_power_wells(power_domains, bdw_power_wells);
+ else if (IS_HASWELL(i915))
+ return set_power_wells(power_domains, hsw_power_wells);
+ else if (IS_VALLEYVIEW(i915))
+ return set_power_wells(power_domains, vlv_power_wells);
+ else if (IS_I830(i915))
+ return set_power_wells(power_domains, i830_power_wells);
+ else
+ return set_power_wells(power_domains, i9xx_always_on_power_well);
+}
+
+void intel_cleanup_power_wells(struct i915_power_domains *power_domains)
+{
+ struct drm_i915_private *i915 = container_of(power_domains,
+ struct drm_i915_private,
+ power_domains);
+
+ kfree(i915->power_domains.power_wells);
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 05/19] drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (3 preceding siblings ...)
2022-01-28 11:48 ` [Intel-gfx] [PATCH 04/19] drm/i915: Move the power domain->well mappings to intel_display_power_map.c Imre Deak
@ 2022-01-28 11:49 ` Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 06/19] drm/i915: Move the HSW power well flags " Imre Deak
` (16 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:49 UTC (permalink / raw)
To: intel-gfx
The DG2 fixed delay duration is always 600usec, so save some space in
the power well descriptors by converting the parameter to a flag. While
at it also use a bitfield for both the always_on and fixed_enable_delay
flag.
This change also lets simplifying the definiton of power wells sharing
the same flags in an upcoming patch.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++---
.../i915/display/intel_display_power_internal.h | 14 +++++++-------
.../gpu/drm/i915/display/intel_display_power_map.c | 10 +++++-----
3 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2ec9c7bd65640..ceac9c1a7693c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -265,15 +265,14 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
int pw_idx = power_well->desc->hsw.idx;
- int enable_delay = power_well->desc->hsw.fixed_enable_delay;
/*
* For some power wells we're not supposed to watch the status bit for
* an ack, but rather just wait a fixed amount of time and then
* proceed. This is only used on DG2.
*/
- if (IS_DG2(dev_priv) && enable_delay) {
- usleep_range(enable_delay, 2 * enable_delay);
+ if (IS_DG2(dev_priv) && power_well->desc->fixed_enable_delay) {
+ usleep_range(600, 1200);
return;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
index 3fc7c7d0bc9e9..540668a1708b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_internal.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
@@ -16,8 +16,14 @@ struct i915_power_well_regs;
/* Power well structure for haswell */
struct i915_power_well_desc {
const char *name;
- bool always_on;
u64 domains;
+ u8 always_on:1;
+ /*
+ * Instead of waiting for the status bit to ack enables,
+ * just wait a specific amount of time and then consider
+ * the well enabled.
+ */
+ u8 fixed_enable_delay:1;
/* unique identifier for this power well */
enum i915_power_well_id id;
/*
@@ -43,12 +49,6 @@ struct i915_power_well_desc {
u8 idx;
/* Mask of pipes whose IRQ logic is backed by the pw */
u8 irq_pipe_mask;
- /*
- * Instead of waiting for the status bit to ack enables,
- * just wait a specific amount of time and then consider
- * the well enabled.
- */
- u16 fixed_enable_delay;
/* The pw is backing the VGA functionality */
bool has_vga:1;
bool has_fuses:1;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index e8732f6e85098..5daa20168b1e5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -2057,37 +2057,37 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.name = "AUX A",
.domains = ICL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX B",
.domains = ICL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX C",
.domains = TGL_AUX_C_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX D_XELPD",
.domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
- .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX E_XELPD",
@@ -2101,10 +2101,10 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.name = "AUX USBC1",
.domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX USBC2",
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 06/19] drm/i915: Move the HSW power well flags to a common bitfield
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (4 preceding siblings ...)
2022-01-28 11:49 ` [Intel-gfx] [PATCH 05/19] drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield Imre Deak
@ 2022-01-28 11:49 ` Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 07/19] drm/i915: Rename the power domain names to end with pipes/ports Imre Deak
` (15 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:49 UTC (permalink / raw)
To: intel-gfx
Save some space by grouping the HSW power well descriptor flags along
with other flags in one bitfield.
This change also lets simplifying the definition of power well
descriptors sharing the same flags in an upcoming patch.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_power.c | 16 +-
.../display/intel_display_power_internal.h | 25 +--
.../i915/display/intel_display_power_map.c | 166 +++++++++---------
3 files changed, 104 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index ceac9c1a7693c..69b75752258d9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -219,8 +219,8 @@ static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well)
{
int pw_idx = power_well->desc->hsw.idx;
- return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
- ICL_AUX_PW_TO_CH(pw_idx);
+ return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
+ ICL_AUX_PW_TO_CH(pw_idx);
}
static struct intel_digital_port *
@@ -348,7 +348,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
int pw_idx = power_well->desc->hsw.idx;
u32 val;
- if (power_well->desc->hsw.has_fuses) {
+ if (power_well->desc->has_fuses) {
enum skl_power_gate pg;
pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
@@ -375,7 +375,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
hsw_wait_for_power_well_enable(dev_priv, power_well, false);
- if (power_well->desc->hsw.has_fuses) {
+ if (power_well->desc->has_fuses) {
enum skl_power_gate pg;
pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
@@ -384,8 +384,8 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
}
hsw_power_well_post_enable(dev_priv,
- power_well->desc->hsw.irq_pipe_mask,
- power_well->desc->hsw.has_vga);
+ power_well->desc->irq_pipe_mask,
+ power_well->desc->has_vga);
}
static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
@@ -396,7 +396,7 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
u32 val;
hsw_power_well_pre_disable(dev_priv,
- power_well->desc->hsw.irq_pipe_mask);
+ power_well->desc->irq_pipe_mask);
val = intel_de_read(dev_priv, regs->driver);
intel_de_write(dev_priv, regs->driver,
@@ -531,7 +531,7 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- bool is_tbt = power_well->desc->hsw.is_tc_tbt;
+ bool is_tbt = power_well->desc->is_tc_tbt;
bool timeout_expected;
u32 val;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
index 540668a1708b7..fd1abb64a8a47 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_internal.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
@@ -17,13 +17,24 @@ struct i915_power_well_regs;
struct i915_power_well_desc {
const char *name;
u64 domains;
- u8 always_on:1;
+ /* Mask of pipes whose IRQ logic is backed by the pw */
+ u16 irq_pipe_mask:4;
+ u16 always_on:1;
/*
* Instead of waiting for the status bit to ack enables,
* just wait a specific amount of time and then consider
* the well enabled.
*/
- u8 fixed_enable_delay:1;
+ u16 fixed_enable_delay:1;
+ /* The pw is backing the VGA functionality */
+ u16 has_vga:1;
+ u16 has_fuses:1;
+ /*
+ * The pw is for an ICL+ TypeC PHY port in
+ * Thunderbolt mode.
+ */
+ u16 is_tc_tbt:1;
+
/* unique identifier for this power well */
enum i915_power_well_id id;
/*
@@ -47,16 +58,6 @@ struct i915_power_well_desc {
* constrol/status registers.
*/
u8 idx;
- /* Mask of pipes whose IRQ logic is backed by the pw */
- u8 irq_pipe_mask;
- /* The pw is backing the VGA functionality */
- bool has_vga:1;
- bool has_fuses:1;
- /*
- * The pw is for an ICL+ TypeC PHY port in
- * Thunderbolt mode.
- */
- bool is_tc_tbt:1;
} hsw;
};
const struct i915_power_well_ops *ops;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 5daa20168b1e5..92bf6337274eb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -213,10 +213,10 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
.name = "display",
.domains = HSW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
.id = HSW_DISP_PW_GLOBAL,
{
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
- .hsw.has_vga = true,
},
},
};
@@ -249,11 +249,11 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
.name = "display",
.domains = BDW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
+ .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.id = HSW_DISP_PW_GLOBAL,
{
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
},
},
};
@@ -505,10 +505,10 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "MISC IO power well",
@@ -529,12 +529,12 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.name = "power well 2",
.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
+ .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_2,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "DDI A/E IO power well",
@@ -621,10 +621,10 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -635,12 +635,12 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.name = "power well 2",
.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
+ .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_2,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "dpio-common-a",
@@ -731,10 +731,10 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -745,12 +745,12 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "power well 2",
.domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
+ .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_2,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "dpio-common-a",
@@ -926,10 +926,10 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -940,21 +940,21 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "power well 2",
.domains = ICL_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_fuses = true,
},
}, {
.name = "power well 3",
.domains = ICL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
+ .irq_pipe_mask = BIT(PIPE_B),
+ .has_fuses = true,
.id = ICL_DISP_PW_3,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "DDI A IO",
@@ -1024,83 +1024,83 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "AUX C TC1",
.domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX D TC2",
.domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_D,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX E TC3",
.domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_E,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX F TC4",
.domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_F,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX C TBT1",
.domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX D TBT2",
.domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX E TBT3",
.domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX F TBT4",
.domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "power well 4",
.domains = ICL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_C),
+ .has_fuses = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
},
},
};
@@ -1214,10 +1214,10 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -1228,21 +1228,21 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.name = "power well 2",
.domains = TGL_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_fuses = true,
},
}, {
.name = "power well 3",
.domains = TGL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
+ .irq_pipe_mask = BIT(PIPE_B),
+ .has_fuses = true,
.id = ICL_DISP_PW_3,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "DDI A IO",
@@ -1349,129 +1349,129 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.name = "AUX USBC1",
.domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX USBC2",
.domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX USBC3",
.domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX USBC4",
.domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX USBC5",
.domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX USBC6",
.domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX TBT1",
.domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT2",
.domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT3",
.domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT4",
.domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT5",
.domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT6",
.domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "power well 4",
.domains = TGL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
+ .irq_pipe_mask = BIT(PIPE_C),
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
}
}, {
.name = "power well 5",
.domains = TGL_PW_5_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
+ .irq_pipe_mask = BIT(PIPE_D),
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_PW_5,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_D),
},
},
};
@@ -1537,10 +1537,10 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -1551,22 +1551,22 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.name = "power well 3",
.domains = RKL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_B),
+ .has_vga = true,
+ .has_fuses = true,
.id = ICL_DISP_PW_3,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "power well 4",
.domains = RKL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
+ .irq_pipe_mask = BIT(PIPE_C),
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
}
}, {
.name = "DDI A IO",
@@ -1677,10 +1677,10 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -1691,21 +1691,21 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.name = "power well 2",
.domains = DG1_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_fuses = true,
},
}, {
.name = "power well 3",
.domains = DG1_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_B),
+ .has_vga = true,
+ .has_fuses = true,
.id = ICL_DISP_PW_3,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "DDI A IO",
@@ -1759,39 +1759,39 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.name = "AUX USBC1",
.domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX USBC2",
.domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "power well 4",
.domains = TGL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
+ .irq_pipe_mask = BIT(PIPE_C),
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
}
}, {
.name = "power well 5",
.domains = TGL_PW_5_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
+ .irq_pipe_mask = BIT(PIPE_D),
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_PW_5,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_D),
},
},
};
@@ -1921,10 +1921,10 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -1935,51 +1935,51 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.name = "power well 2",
.domains = XELPD_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "power well A",
.domains = XELPD_PW_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_A),
+ .has_fuses = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = XELPD_PW_CTL_IDX_PW_A,
- .hsw.irq_pipe_mask = BIT(PIPE_A),
- .hsw.has_fuses = true,
},
}, {
.name = "power well B",
.domains = XELPD_PW_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_B),
+ .has_fuses = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = XELPD_PW_CTL_IDX_PW_B,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_fuses = true,
},
}, {
.name = "power well C",
.domains = XELPD_PW_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_C),
+ .has_fuses = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = XELPD_PW_CTL_IDX_PW_C,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
- .hsw.has_fuses = true,
},
}, {
.name = "power well D",
.domains = XELPD_PW_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_D),
+ .has_fuses = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = XELPD_PW_CTL_IDX_PW_D,
- .hsw.irq_pipe_mask = BIT(PIPE_D),
- .hsw.has_fuses = true,
},
}, {
.name = "DDI A IO",
@@ -2134,37 +2134,37 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.name = "AUX TBT1",
.domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT2",
.domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT3",
.domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT4",
.domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
- .hsw.is_tc_tbt = true,
},
},
};
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 07/19] drm/i915: Rename the power domain names to end with pipes/ports
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (5 preceding siblings ...)
2022-01-28 11:49 ` [Intel-gfx] [PATCH 06/19] drm/i915: Move the HSW power well flags " Imre Deak
@ 2022-01-28 11:49 ` Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 08/19] drm/i915: Sanitize the power well names Imre Deak
` (14 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:49 UTC (permalink / raw)
To: intel-gfx
Make all power domain names end with the pipe/port instance for
consistency.
No functional changes.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 8 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 34 +-
.../drm/i915/display/intel_display_power.h | 66 ++--
.../i915/display/intel_display_power_map.c | 300 +++++++++---------
5 files changed, 205 insertions(+), 205 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 2d5bb9195b20f..990671e7aba21 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -398,8 +398,8 @@ static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
intel_dsi->io_wakeref[port] =
intel_display_power_get(dev_priv,
port == PORT_A ?
- POWER_DOMAIN_PORT_DDI_A_IO :
- POWER_DOMAIN_PORT_DDI_B_IO);
+ POWER_DOMAIN_PORT_DDI_IO_A :
+ POWER_DOMAIN_PORT_DDI_IO_B);
}
}
@@ -1425,8 +1425,8 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
intel_display_power_put(dev_priv,
port == PORT_A ?
- POWER_DOMAIN_PORT_DDI_A_IO :
- POWER_DOMAIN_PORT_DDI_B_IO,
+ POWER_DOMAIN_PORT_DDI_IO_A :
+ POWER_DOMAIN_PORT_DDI_IO_B,
wakeref);
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5d1f7d6218c51..530032f3bb2c2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4475,7 +4475,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
}
drm_WARN_ON(&dev_priv->drm, port > PORT_I);
- dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
+ dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_IO_A +
port - PORT_A;
if (init_dp) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 91add3d85151c..3094cfc668c81 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2289,23 +2289,23 @@ enum intel_display_power_domain intel_port_to_power_domain(enum port port)
{
switch (port) {
case PORT_A:
- return POWER_DOMAIN_PORT_DDI_A_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_A;
case PORT_B:
- return POWER_DOMAIN_PORT_DDI_B_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_B;
case PORT_C:
- return POWER_DOMAIN_PORT_DDI_C_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_C;
case PORT_D:
- return POWER_DOMAIN_PORT_DDI_D_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_D;
case PORT_E:
- return POWER_DOMAIN_PORT_DDI_E_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_E;
case PORT_F:
- return POWER_DOMAIN_PORT_DDI_F_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_F;
case PORT_G:
- return POWER_DOMAIN_PORT_DDI_G_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_G;
case PORT_H:
- return POWER_DOMAIN_PORT_DDI_H_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_H;
case PORT_I:
- return POWER_DOMAIN_PORT_DDI_I_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_I;
default:
MISSING_CASE(port);
return POWER_DOMAIN_PORT_OTHER;
@@ -2318,22 +2318,22 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
switch (dig_port->aux_ch) {
case AUX_CH_C:
- return POWER_DOMAIN_AUX_C_TBT;
+ return POWER_DOMAIN_AUX_TBT_C;
case AUX_CH_D:
- return POWER_DOMAIN_AUX_D_TBT;
+ return POWER_DOMAIN_AUX_TBT_D;
case AUX_CH_E:
- return POWER_DOMAIN_AUX_E_TBT;
+ return POWER_DOMAIN_AUX_TBT_E;
case AUX_CH_F:
- return POWER_DOMAIN_AUX_F_TBT;
+ return POWER_DOMAIN_AUX_TBT_F;
case AUX_CH_G:
- return POWER_DOMAIN_AUX_G_TBT;
+ return POWER_DOMAIN_AUX_TBT_G;
case AUX_CH_H:
- return POWER_DOMAIN_AUX_H_TBT;
+ return POWER_DOMAIN_AUX_TBT_H;
case AUX_CH_I:
- return POWER_DOMAIN_AUX_I_TBT;
+ return POWER_DOMAIN_AUX_TBT_I;
default:
MISSING_CASE(dig_port->aux_ch);
- return POWER_DOMAIN_AUX_C_TBT;
+ return POWER_DOMAIN_AUX_TBT_C;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index a0e68ae691021..c3232809b95f9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -26,10 +26,10 @@ enum intel_display_power_domain {
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
POWER_DOMAIN_PIPE_D,
- POWER_DOMAIN_PIPE_A_PANEL_FITTER,
- POWER_DOMAIN_PIPE_B_PANEL_FITTER,
- POWER_DOMAIN_PIPE_C_PANEL_FITTER,
- POWER_DOMAIN_PIPE_D_PANEL_FITTER,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_D,
POWER_DOMAIN_TRANSCODER_A,
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
@@ -41,17 +41,17 @@ enum intel_display_power_domain {
/* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
POWER_DOMAIN_TRANSCODER_VDSC_PW2,
- POWER_DOMAIN_PORT_DDI_A_LANES,
- POWER_DOMAIN_PORT_DDI_B_LANES,
- POWER_DOMAIN_PORT_DDI_C_LANES,
- POWER_DOMAIN_PORT_DDI_D_LANES,
- POWER_DOMAIN_PORT_DDI_E_LANES,
- POWER_DOMAIN_PORT_DDI_F_LANES,
- POWER_DOMAIN_PORT_DDI_G_LANES,
- POWER_DOMAIN_PORT_DDI_H_LANES,
- POWER_DOMAIN_PORT_DDI_I_LANES,
+ POWER_DOMAIN_PORT_DDI_LANES_A,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
+ POWER_DOMAIN_PORT_DDI_LANES_E,
+ POWER_DOMAIN_PORT_DDI_LANES_F,
+ POWER_DOMAIN_PORT_DDI_LANES_G,
+ POWER_DOMAIN_PORT_DDI_LANES_H,
+ POWER_DOMAIN_PORT_DDI_LANES_I,
- POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_D_LANES, /* tgl+ */
+ POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_LANES_D, /* tgl+ */
POWER_DOMAIN_PORT_DDI_LANES_TC2,
POWER_DOMAIN_PORT_DDI_LANES_TC3,
POWER_DOMAIN_PORT_DDI_LANES_TC4,
@@ -61,17 +61,17 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_LANES_D_XELPD = POWER_DOMAIN_PORT_DDI_LANES_TC5, /* XELPD */
POWER_DOMAIN_PORT_DDI_LANES_E_XELPD,
- POWER_DOMAIN_PORT_DDI_A_IO,
- POWER_DOMAIN_PORT_DDI_B_IO,
- POWER_DOMAIN_PORT_DDI_C_IO,
- POWER_DOMAIN_PORT_DDI_D_IO,
- POWER_DOMAIN_PORT_DDI_E_IO,
- POWER_DOMAIN_PORT_DDI_F_IO,
- POWER_DOMAIN_PORT_DDI_G_IO,
- POWER_DOMAIN_PORT_DDI_H_IO,
- POWER_DOMAIN_PORT_DDI_I_IO,
+ POWER_DOMAIN_PORT_DDI_IO_A,
+ POWER_DOMAIN_PORT_DDI_IO_B,
+ POWER_DOMAIN_PORT_DDI_IO_C,
+ POWER_DOMAIN_PORT_DDI_IO_D,
+ POWER_DOMAIN_PORT_DDI_IO_E,
+ POWER_DOMAIN_PORT_DDI_IO_F,
+ POWER_DOMAIN_PORT_DDI_IO_G,
+ POWER_DOMAIN_PORT_DDI_IO_H,
+ POWER_DOMAIN_PORT_DDI_IO_I,
- POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_D_IO, /* tgl+ */
+ POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_IO_D, /* tgl+ */
POWER_DOMAIN_PORT_DDI_IO_TC2,
POWER_DOMAIN_PORT_DDI_IO_TC3,
POWER_DOMAIN_PORT_DDI_IO_TC4,
@@ -108,15 +108,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_E_XELPD,
POWER_DOMAIN_AUX_IO_A,
- POWER_DOMAIN_AUX_C_TBT,
- POWER_DOMAIN_AUX_D_TBT,
- POWER_DOMAIN_AUX_E_TBT,
- POWER_DOMAIN_AUX_F_TBT,
- POWER_DOMAIN_AUX_G_TBT,
- POWER_DOMAIN_AUX_H_TBT,
- POWER_DOMAIN_AUX_I_TBT,
+ POWER_DOMAIN_AUX_TBT_C,
+ POWER_DOMAIN_AUX_TBT_D,
+ POWER_DOMAIN_AUX_TBT_E,
+ POWER_DOMAIN_AUX_TBT_F,
+ POWER_DOMAIN_AUX_TBT_G,
+ POWER_DOMAIN_AUX_TBT_H,
+ POWER_DOMAIN_AUX_TBT_I,
- POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_D_TBT, /* tgl+ */
+ POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_TBT_D, /* tgl+ */
POWER_DOMAIN_AUX_TBT2,
POWER_DOMAIN_AUX_TBT3,
POWER_DOMAIN_AUX_TBT4,
@@ -159,7 +159,7 @@ enum i915_power_well_id {
#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
- ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
+ ((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A)
#define POWER_DOMAIN_TRANSCODER(tran) \
((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
(tran) + POWER_DOMAIN_TRANSCODER_A)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 92bf6337274eb..30c9d94b55929 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -26,14 +26,14 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PIPE_C";
case POWER_DOMAIN_PIPE_D:
return "PIPE_D";
- case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
- return "PIPE_A_PANEL_FITTER";
- case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
- return "PIPE_B_PANEL_FITTER";
- case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
- return "PIPE_C_PANEL_FITTER";
- case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
- return "PIPE_D_PANEL_FITTER";
+ case POWER_DOMAIN_PIPE_PANEL_FITTER_A:
+ return "PIPE_PANEL_FITTER_A";
+ case POWER_DOMAIN_PIPE_PANEL_FITTER_B:
+ return "PIPE_PANEL_FITTER_B";
+ case POWER_DOMAIN_PIPE_PANEL_FITTER_C:
+ return "PIPE_PANEL_FITTER_C";
+ case POWER_DOMAIN_PIPE_PANEL_FITTER_D:
+ return "PIPE_PANEL_FITTER_D";
case POWER_DOMAIN_TRANSCODER_A:
return "TRANSCODER_A";
case POWER_DOMAIN_TRANSCODER_B:
@@ -50,42 +50,42 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "TRANSCODER_DSI_C";
case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
return "TRANSCODER_VDSC_PW2";
- case POWER_DOMAIN_PORT_DDI_A_LANES:
- return "PORT_DDI_A_LANES";
- case POWER_DOMAIN_PORT_DDI_B_LANES:
- return "PORT_DDI_B_LANES";
- case POWER_DOMAIN_PORT_DDI_C_LANES:
- return "PORT_DDI_C_LANES";
- case POWER_DOMAIN_PORT_DDI_D_LANES:
- return "PORT_DDI_D_LANES";
- case POWER_DOMAIN_PORT_DDI_E_LANES:
- return "PORT_DDI_E_LANES";
- case POWER_DOMAIN_PORT_DDI_F_LANES:
- return "PORT_DDI_F_LANES";
- case POWER_DOMAIN_PORT_DDI_G_LANES:
- return "PORT_DDI_G_LANES";
- case POWER_DOMAIN_PORT_DDI_H_LANES:
- return "PORT_DDI_H_LANES";
- case POWER_DOMAIN_PORT_DDI_I_LANES:
- return "PORT_DDI_I_LANES";
- case POWER_DOMAIN_PORT_DDI_A_IO:
- return "PORT_DDI_A_IO";
- case POWER_DOMAIN_PORT_DDI_B_IO:
- return "PORT_DDI_B_IO";
- case POWER_DOMAIN_PORT_DDI_C_IO:
- return "PORT_DDI_C_IO";
- case POWER_DOMAIN_PORT_DDI_D_IO:
- return "PORT_DDI_D_IO";
- case POWER_DOMAIN_PORT_DDI_E_IO:
- return "PORT_DDI_E_IO";
- case POWER_DOMAIN_PORT_DDI_F_IO:
- return "PORT_DDI_F_IO";
- case POWER_DOMAIN_PORT_DDI_G_IO:
- return "PORT_DDI_G_IO";
- case POWER_DOMAIN_PORT_DDI_H_IO:
- return "PORT_DDI_H_IO";
- case POWER_DOMAIN_PORT_DDI_I_IO:
- return "PORT_DDI_I_IO";
+ case POWER_DOMAIN_PORT_DDI_LANES_A:
+ return "PORT_DDI_LANES_A";
+ case POWER_DOMAIN_PORT_DDI_LANES_B:
+ return "PORT_DDI_LANES_B";
+ case POWER_DOMAIN_PORT_DDI_LANES_C:
+ return "PORT_DDI_LANES_C";
+ case POWER_DOMAIN_PORT_DDI_LANES_D:
+ return "PORT_DDI_LANES_D";
+ case POWER_DOMAIN_PORT_DDI_LANES_E:
+ return "PORT_DDI_LANES_E";
+ case POWER_DOMAIN_PORT_DDI_LANES_F:
+ return "PORT_DDI_LANES_F";
+ case POWER_DOMAIN_PORT_DDI_LANES_G:
+ return "PORT_DDI_LANES_G";
+ case POWER_DOMAIN_PORT_DDI_LANES_H:
+ return "PORT_DDI_LANES_H";
+ case POWER_DOMAIN_PORT_DDI_LANES_I:
+ return "PORT_DDI_LANES_I";
+ case POWER_DOMAIN_PORT_DDI_IO_A:
+ return "PORT_DDI_IO_A";
+ case POWER_DOMAIN_PORT_DDI_IO_B:
+ return "PORT_DDI_IO_B";
+ case POWER_DOMAIN_PORT_DDI_IO_C:
+ return "PORT_DDI_IO_C";
+ case POWER_DOMAIN_PORT_DDI_IO_D:
+ return "PORT_DDI_IO_D";
+ case POWER_DOMAIN_PORT_DDI_IO_E:
+ return "PORT_DDI_IO_E";
+ case POWER_DOMAIN_PORT_DDI_IO_F:
+ return "PORT_DDI_IO_F";
+ case POWER_DOMAIN_PORT_DDI_IO_G:
+ return "PORT_DDI_IO_G";
+ case POWER_DOMAIN_PORT_DDI_IO_H:
+ return "PORT_DDI_IO_H";
+ case POWER_DOMAIN_PORT_DDI_IO_I:
+ return "PORT_DDI_IO_I";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
@@ -118,20 +118,20 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_I";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
- case POWER_DOMAIN_AUX_C_TBT:
- return "AUX_C_TBT";
- case POWER_DOMAIN_AUX_D_TBT:
- return "AUX_D_TBT";
- case POWER_DOMAIN_AUX_E_TBT:
- return "AUX_E_TBT";
- case POWER_DOMAIN_AUX_F_TBT:
- return "AUX_F_TBT";
- case POWER_DOMAIN_AUX_G_TBT:
- return "AUX_G_TBT";
- case POWER_DOMAIN_AUX_H_TBT:
- return "AUX_H_TBT";
- case POWER_DOMAIN_AUX_I_TBT:
- return "AUX_I_TBT";
+ case POWER_DOMAIN_AUX_TBT_C:
+ return "AUX_TBT_C";
+ case POWER_DOMAIN_AUX_TBT_D:
+ return "AUX_TBT_D";
+ case POWER_DOMAIN_AUX_TBT_E:
+ return "AUX_TBT_E";
+ case POWER_DOMAIN_AUX_TBT_F:
+ return "AUX_TBT_F";
+ case POWER_DOMAIN_AUX_TBT_G:
+ return "AUX_TBT_G";
+ case POWER_DOMAIN_AUX_TBT_H:
+ return "AUX_TBT_H";
+ case POWER_DOMAIN_AUX_TBT_I:
+ return "AUX_TBT_I";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
case POWER_DOMAIN_INIT:
@@ -163,8 +163,8 @@ static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
#define I830_PIPES_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_A) | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -187,15 +187,15 @@ static const struct i915_power_well_desc i830_power_wells[] = {
#define HSW_DISPLAY_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
@@ -224,14 +224,14 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
#define BDW_DISPLAY_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
@@ -262,12 +262,12 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
BIT_ULL(POWER_DOMAIN_PIPE_A) | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
@@ -279,30 +279,30 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -381,15 +381,15 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
BIT_ULL(POWER_DOMAIN_PIPE_A) | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
@@ -401,14 +401,14 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
BIT_ULL(POWER_DOMAIN_INIT))
#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
BIT_ULL(POWER_DOMAIN_AUX_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -451,15 +451,15 @@ static const struct i915_power_well_desc chv_power_wells[] = {
#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
@@ -476,20 +476,20 @@ static const struct i915_power_well_desc chv_power_wells[] = {
BIT_ULL(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
static const struct i915_power_well_desc skl_power_wells[] = {
@@ -574,13 +574,13 @@ static const struct i915_power_well_desc skl_power_wells[] = {
#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
@@ -597,13 +597,13 @@ static const struct i915_power_well_desc skl_power_wells[] = {
BIT_ULL(POWER_DOMAIN_INIT))
#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -664,13 +664,13 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
@@ -686,22 +686,22 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)
-#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)
-#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)
+#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
+#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
+#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -843,22 +843,22 @@ static const struct i915_power_well_desc glk_power_wells[] = {
*/
#define ICL_PW_4_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
/* VDSC/joining */
#define ICL_PW_3_POWER_DOMAINS ( \
ICL_PW_4_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_F) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
@@ -867,10 +867,10 @@ static const struct i915_power_well_desc glk_power_wells[] = {
BIT_ULL(POWER_DOMAIN_AUX_D) | \
BIT_ULL(POWER_DOMAIN_AUX_E) | \
BIT_ULL(POWER_DOMAIN_AUX_F) | \
- BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
- BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
- BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
- BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT_D) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT_E) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT_F) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
* - transcoder WD
@@ -892,12 +892,12 @@ static const struct i915_power_well_desc glk_power_wells[] = {
BIT_ULL(POWER_DOMAIN_DC_OFF) | \
BIT_ULL(POWER_DOMAIN_INIT))
-#define ICL_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)
-#define ICL_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)
-#define ICL_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)
-#define ICL_DDI_IO_D_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO)
-#define ICL_DDI_IO_E_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO)
-#define ICL_DDI_IO_F_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO)
+#define ICL_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
+#define ICL_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
+#define ICL_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
+#define ICL_DDI_IO_D_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D)
+#define ICL_DDI_IO_E_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E)
+#define ICL_DDI_IO_F_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_F)
#define ICL_AUX_A_IO_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
@@ -908,10 +908,10 @@ static const struct i915_power_well_desc glk_power_wells[] = {
#define ICL_AUX_D_TC2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D)
#define ICL_AUX_E_TC3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E)
#define ICL_AUX_F_TC4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F)
-#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C_TBT)
-#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_TBT)
-#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_TBT)
-#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F_TBT)
+#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_C)
+#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_D)
+#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_E)
+#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_F)
static const struct i915_power_well_desc icl_power_wells[] = {
{
@@ -1107,21 +1107,21 @@ static const struct i915_power_well_desc icl_power_wells[] = {
#define TGL_PW_5_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define TGL_PW_4_POWER_DOMAINS ( \
TGL_PW_5_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define TGL_PW_3_POWER_DOMAINS ( \
TGL_PW_4_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
@@ -1478,14 +1478,14 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
#define RKL_PW_4_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define RKL_PW_3_POWER_DOMAINS ( \
RKL_PW_4_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
@@ -1641,7 +1641,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
#define DG1_PW_3_POWER_DOMAINS ( \
TGL_PW_4_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
@@ -1816,32 +1816,32 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
#define XELPD_PW_D_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define XELPD_PW_C_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define XELPD_PW_B_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define XELPD_PW_A_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define XELPD_PW_2_POWER_DOMAINS ( \
XELPD_PW_B_POWER_DOMAINS | \
XELPD_PW_C_POWER_DOMAINS | \
XELPD_PW_D_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 08/19] drm/i915: Sanitize the power well names
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (6 preceding siblings ...)
2022-01-28 11:49 ` [Intel-gfx] [PATCH 07/19] drm/i915: Rename the power domain names to end with pipes/ports Imre Deak
@ 2022-01-28 11:49 ` Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 09/19] drm/i915: Convert the power well descriptor domain mask to a list Imre Deak
` (13 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:49 UTC (permalink / raw)
To: intel-gfx
Use the shortest descriptive name for all power wells for simplicity and
to use the same name for the same type of power wells on multiple
platforms.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../i915/display/intel_display_power_map.c | 254 +++++++++---------
1 file changed, 127 insertions(+), 127 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 30c9d94b55929..773b133902e3d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -500,7 +500,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -511,7 +511,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "MISC IO power well",
+ .name = "MISC_IO",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -521,12 +521,12 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 2",
+ .name = "PW_2",
.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_vga = true,
@@ -537,7 +537,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_PW_2,
},
}, {
- .name = "DDI A/E IO power well",
+ .name = "DDI_IO_A_E",
.domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -545,7 +545,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
},
}, {
- .name = "DDI B IO power well",
+ .name = "DDI_IO_B",
.domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -553,7 +553,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
},
}, {
- .name = "DDI C IO power well",
+ .name = "DDI_IO_C",
.domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -561,7 +561,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_DDI_C,
},
}, {
- .name = "DDI D IO power well",
+ .name = "DDI_IO_D",
.domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -616,7 +616,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -627,12 +627,12 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 2",
+ .name = "PW_2",
.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_vga = true,
@@ -726,7 +726,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -737,12 +737,12 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 2",
+ .name = "PW_2",
.domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_vga = true,
@@ -777,7 +777,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.bxt.phy = DPIO_PHY2,
},
}, {
- .name = "AUX A",
+ .name = "AUX_A",
.domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -785,7 +785,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.hsw.idx = GLK_PW_CTL_IDX_AUX_A,
},
}, {
- .name = "AUX B",
+ .name = "AUX_B",
.domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -793,7 +793,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.hsw.idx = GLK_PW_CTL_IDX_AUX_B,
},
}, {
- .name = "AUX C",
+ .name = "AUX_C",
.domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -801,7 +801,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.hsw.idx = GLK_PW_CTL_IDX_AUX_C,
},
}, {
- .name = "DDI A IO power well",
+ .name = "DDI_IO_A",
.domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -809,7 +809,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.hsw.idx = GLK_PW_CTL_IDX_DDI_A,
},
}, {
- .name = "DDI B IO power well",
+ .name = "DDI_IO_B",
.domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -817,7 +817,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
},
}, {
- .name = "DDI C IO power well",
+ .name = "DDI_IO_C",
.domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -921,7 +921,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -932,12 +932,12 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 2",
+ .name = "PW_2",
.domains = ICL_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -946,7 +946,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
},
}, {
- .name = "power well 3",
+ .name = "PW_3",
.domains = ICL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_vga = true,
@@ -957,7 +957,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
},
}, {
- .name = "DDI A IO",
+ .name = "DDI_IO_A",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -965,7 +965,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
},
}, {
- .name = "DDI B IO",
+ .name = "DDI_IO_B",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -973,7 +973,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
},
}, {
- .name = "DDI C IO",
+ .name = "DDI_IO_C",
.domains = ICL_DDI_IO_C_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -981,7 +981,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
},
}, {
- .name = "DDI D IO",
+ .name = "DDI_IO_D",
.domains = ICL_DDI_IO_D_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -989,7 +989,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_D,
},
}, {
- .name = "DDI E IO",
+ .name = "DDI_IO_E",
.domains = ICL_DDI_IO_E_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -997,7 +997,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_E,
},
}, {
- .name = "DDI F IO",
+ .name = "DDI_IO_F",
.domains = ICL_DDI_IO_F_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1005,7 +1005,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_F,
},
}, {
- .name = "AUX A",
+ .name = "AUX_A",
.domains = ICL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1013,7 +1013,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
},
}, {
- .name = "AUX B",
+ .name = "AUX_B",
.domains = ICL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1021,7 +1021,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
},
}, {
- .name = "AUX C TC1",
+ .name = "AUX_C",
.domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1030,7 +1030,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
},
}, {
- .name = "AUX D TC2",
+ .name = "AUX_D",
.domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1039,7 +1039,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_D,
},
}, {
- .name = "AUX E TC3",
+ .name = "AUX_E",
.domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1048,7 +1048,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_E,
},
}, {
- .name = "AUX F TC4",
+ .name = "AUX_F",
.domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1057,7 +1057,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_F,
},
}, {
- .name = "AUX C TBT1",
+ .name = "AUX_TBT1",
.domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1066,7 +1066,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
},
}, {
- .name = "AUX D TBT2",
+ .name = "AUX_TBT2",
.domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1075,7 +1075,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
},
}, {
- .name = "AUX E TBT3",
+ .name = "AUX_TBT3",
.domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1084,7 +1084,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
},
}, {
- .name = "AUX F TBT4",
+ .name = "AUX_TBT4",
.domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1093,7 +1093,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
},
}, {
- .name = "power well 4",
+ .name = "PW_4",
.domains = ICL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_C),
@@ -1209,7 +1209,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -1220,12 +1220,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 2",
+ .name = "PW_2",
.domains = TGL_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -1234,7 +1234,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
},
}, {
- .name = "power well 3",
+ .name = "PW_3",
.domains = TGL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_vga = true,
@@ -1245,7 +1245,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
},
}, {
- .name = "DDI A IO",
+ .name = "DDI_IO_A",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1253,7 +1253,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
}
}, {
- .name = "DDI B IO",
+ .name = "DDI_IO_B",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1261,7 +1261,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
}
}, {
- .name = "DDI C IO",
+ .name = "DDI_IO_C",
.domains = ICL_DDI_IO_C_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1269,7 +1269,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
}
}, {
- .name = "DDI IO TC1",
+ .name = "DDI_IO_TC1",
.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1277,7 +1277,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
},
}, {
- .name = "DDI IO TC2",
+ .name = "DDI_IO_TC2",
.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1285,7 +1285,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
},
}, {
- .name = "DDI IO TC3",
+ .name = "DDI_IO_TC3",
.domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1293,7 +1293,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
},
}, {
- .name = "DDI IO TC4",
+ .name = "DDI_IO_TC4",
.domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1301,7 +1301,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
},
}, {
- .name = "DDI IO TC5",
+ .name = "DDI_IO_TC5",
.domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1309,7 +1309,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
},
}, {
- .name = "DDI IO TC6",
+ .name = "DDI_IO_TC6",
.domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1317,12 +1317,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
},
}, {
- .name = "TC cold off",
+ .name = "TC_cold_off",
.domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
.ops = &tgl_tc_cold_off_ops,
.id = TGL_DISP_PW_TC_COLD_OFF,
}, {
- .name = "AUX A",
+ .name = "AUX_A",
.domains = TGL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1330,7 +1330,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
},
}, {
- .name = "AUX B",
+ .name = "AUX_B",
.domains = TGL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1338,7 +1338,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
},
}, {
- .name = "AUX C",
+ .name = "AUX_C",
.domains = TGL_AUX_C_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1346,7 +1346,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
},
}, {
- .name = "AUX USBC1",
+ .name = "AUX_USBC1",
.domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1355,7 +1355,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
},
}, {
- .name = "AUX USBC2",
+ .name = "AUX_USBC2",
.domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1364,7 +1364,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
},
}, {
- .name = "AUX USBC3",
+ .name = "AUX_USBC3",
.domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1373,7 +1373,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
},
}, {
- .name = "AUX USBC4",
+ .name = "AUX_USBC4",
.domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1382,7 +1382,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
},
}, {
- .name = "AUX USBC5",
+ .name = "AUX_USBC5",
.domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1391,7 +1391,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
},
}, {
- .name = "AUX USBC6",
+ .name = "AUX_USBC6",
.domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1400,7 +1400,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
},
}, {
- .name = "AUX TBT1",
+ .name = "AUX_TBT1",
.domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1409,7 +1409,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
},
}, {
- .name = "AUX TBT2",
+ .name = "AUX_TBT2",
.domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1418,7 +1418,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
},
}, {
- .name = "AUX TBT3",
+ .name = "AUX_TBT3",
.domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1427,7 +1427,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
},
}, {
- .name = "AUX TBT4",
+ .name = "AUX_TBT4",
.domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1436,7 +1436,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
},
}, {
- .name = "AUX TBT5",
+ .name = "AUX_TBT5",
.domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1445,7 +1445,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
},
}, {
- .name = "AUX TBT6",
+ .name = "AUX_TBT6",
.domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1454,7 +1454,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
},
}, {
- .name = "power well 4",
+ .name = "PW_4",
.domains = TGL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -1464,7 +1464,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
}
}, {
- .name = "power well 5",
+ .name = "PW_5",
.domains = TGL_PW_5_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -1532,7 +1532,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -1543,12 +1543,12 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 3",
+ .name = "PW_3",
.domains = RKL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
@@ -1559,7 +1559,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
},
}, {
- .name = "power well 4",
+ .name = "PW_4",
.domains = RKL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -1569,7 +1569,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
}
}, {
- .name = "DDI A IO",
+ .name = "DDI_IO_A",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1577,7 +1577,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
}
}, {
- .name = "DDI B IO",
+ .name = "DDI_IO_B",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1585,7 +1585,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
}
}, {
- .name = "DDI IO TC1",
+ .name = "DDI_IO_TC1",
.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1593,7 +1593,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
},
}, {
- .name = "DDI IO TC2",
+ .name = "DDI_IO_TC2",
.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1601,7 +1601,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
},
}, {
- .name = "AUX A",
+ .name = "AUX_A",
.domains = ICL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1609,7 +1609,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
},
}, {
- .name = "AUX B",
+ .name = "AUX_B",
.domains = ICL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1617,7 +1617,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
},
}, {
- .name = "AUX USBC1",
+ .name = "AUX_USBC1",
.domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1625,7 +1625,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
},
}, {
- .name = "AUX USBC2",
+ .name = "AUX_USBC2",
.domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1672,7 +1672,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -1683,12 +1683,12 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 2",
+ .name = "PW_2",
.domains = DG1_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -1697,7 +1697,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
},
}, {
- .name = "power well 3",
+ .name = "PW_3",
.domains = DG1_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
@@ -1708,7 +1708,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
},
}, {
- .name = "DDI A IO",
+ .name = "DDI_IO_A",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1716,7 +1716,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
}
}, {
- .name = "DDI B IO",
+ .name = "DDI_IO_B",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1724,7 +1724,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
}
}, {
- .name = "DDI IO TC1",
+ .name = "DDI_IO_TC1",
.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1732,7 +1732,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
},
}, {
- .name = "DDI IO TC2",
+ .name = "DDI_IO_TC2",
.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1740,7 +1740,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
},
}, {
- .name = "AUX A",
+ .name = "AUX_A",
.domains = TGL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1748,7 +1748,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
},
}, {
- .name = "AUX B",
+ .name = "AUX_B",
.domains = TGL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1756,7 +1756,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
},
}, {
- .name = "AUX USBC1",
+ .name = "AUX_USBC1",
.domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1765,7 +1765,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
},
}, {
- .name = "AUX USBC2",
+ .name = "AUX_USBC2",
.domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1774,7 +1774,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
},
}, {
- .name = "power well 4",
+ .name = "PW_4",
.domains = TGL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -1784,7 +1784,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
}
}, {
- .name = "power well 5",
+ .name = "PW_5",
.domains = TGL_PW_5_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -1916,7 +1916,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -1927,12 +1927,12 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 2",
+ .name = "PW_2",
.domains = XELPD_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_vga = true,
@@ -1942,7 +1942,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
},
}, {
- .name = "power well A",
+ .name = "PW_A",
.domains = XELPD_PW_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_A),
@@ -1952,7 +1952,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_PW_A,
},
}, {
- .name = "power well B",
+ .name = "PW_B",
.domains = XELPD_PW_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
@@ -1962,7 +1962,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_PW_B,
},
}, {
- .name = "power well C",
+ .name = "PW_C",
.domains = XELPD_PW_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_C),
@@ -1972,7 +1972,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_PW_C,
},
}, {
- .name = "power well D",
+ .name = "PW_D",
.domains = XELPD_PW_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_D),
@@ -1982,7 +1982,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_PW_D,
},
}, {
- .name = "DDI A IO",
+ .name = "DDI_IO_A",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1990,7 +1990,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
}
}, {
- .name = "DDI B IO",
+ .name = "DDI_IO_B",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1998,7 +1998,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
}
}, {
- .name = "DDI C IO",
+ .name = "DDI_IO_C",
.domains = ICL_DDI_IO_C_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2006,7 +2006,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
}
}, {
- .name = "DDI IO D_XELPD",
+ .name = "DDI_IO_D_XELPD",
.domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2014,7 +2014,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_DDI_D,
}
}, {
- .name = "DDI IO E_XELPD",
+ .name = "DDI_IO_E_XELPD",
.domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2022,7 +2022,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_DDI_E,
}
}, {
- .name = "DDI IO TC1",
+ .name = "DDI_IO_TC1",
.domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2030,7 +2030,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
}
}, {
- .name = "DDI IO TC2",
+ .name = "DDI_IO_TC2",
.domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2038,7 +2038,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
}
}, {
- .name = "DDI IO TC3",
+ .name = "DDI_IO_TC3",
.domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2046,7 +2046,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
}
}, {
- .name = "DDI IO TC4",
+ .name = "DDI_IO_TC4",
.domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2054,7 +2054,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
}
}, {
- .name = "AUX A",
+ .name = "AUX_A",
.domains = ICL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
@@ -2063,7 +2063,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
},
}, {
- .name = "AUX B",
+ .name = "AUX_B",
.domains = ICL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
@@ -2072,7 +2072,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
},
}, {
- .name = "AUX C",
+ .name = "AUX_C",
.domains = TGL_AUX_C_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
@@ -2081,7 +2081,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
},
}, {
- .name = "AUX D_XELPD",
+ .name = "AUX_D_XELPD",
.domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
@@ -2090,7 +2090,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
},
}, {
- .name = "AUX E_XELPD",
+ .name = "AUX_E_XELPD",
.domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2098,7 +2098,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_AUX_E,
},
}, {
- .name = "AUX USBC1",
+ .name = "AUX_USBC1",
.domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
@@ -2107,7 +2107,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
},
}, {
- .name = "AUX USBC2",
+ .name = "AUX_USBC2",
.domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2115,7 +2115,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
},
}, {
- .name = "AUX USBC3",
+ .name = "AUX_USBC3",
.domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2123,7 +2123,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
},
}, {
- .name = "AUX USBC4",
+ .name = "AUX_USBC4",
.domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2131,7 +2131,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
},
}, {
- .name = "AUX TBT1",
+ .name = "AUX_TBT1",
.domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -2140,7 +2140,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
},
}, {
- .name = "AUX TBT2",
+ .name = "AUX_TBT2",
.domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -2149,7 +2149,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
},
}, {
- .name = "AUX TBT3",
+ .name = "AUX_TBT3",
.domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -2158,7 +2158,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
},
}, {
- .name = "AUX TBT4",
+ .name = "AUX_TBT4",
.domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 09/19] drm/i915: Convert the power well descriptor domain mask to a list
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (7 preceding siblings ...)
2022-01-28 11:49 ` [Intel-gfx] [PATCH 08/19] drm/i915: Sanitize the power well names Imre Deak
@ 2022-01-28 11:49 ` Imre Deak
2022-02-01 11:10 ` Jani Nikula
2022-01-28 11:49 ` [Intel-gfx] [PATCH 10/19] drm/i915: Convert the u64 power well domains mask to a bitmap Imre Deak
` (12 subsequent siblings)
21 siblings, 1 reply; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:49 UTC (permalink / raw)
To: intel-gfx
The next patch converts the i915_power_well_desc::domain mask from a u64
mask to a bitmap. I didn't find a reasonably simple way to initialize
bitmaps statically, so prepare for the next patch here by converting the
masks to a list and initing the masks from these lists during module
loading.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_power.c | 12 +-
.../display/intel_display_power_internal.h | 6 +-
.../i915/display/intel_display_power_map.c | 1426 +++++++++--------
3 files changed, 756 insertions(+), 688 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 69b75752258d9..a370ef8376410 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -40,11 +40,11 @@
#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
for_each_power_well(__dev_priv, __power_well) \
- for_each_if((__power_well)->desc->domains & (__domain_mask))
+ for_each_if((__power_well)->domains & (__domain_mask))
#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
for_each_power_well_reverse(__dev_priv, __power_well) \
- for_each_if((__power_well)->desc->domains & (__domain_mask))
+ for_each_if((__power_well)->domains & (__domain_mask))
struct i915_power_well_regs {
i915_reg_t bios;
@@ -465,7 +465,7 @@ static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
static int power_well_async_ref_count(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- int refs = hweight64(power_well->desc->domains &
+ int refs = hweight64(power_well->domains &
async_put_domains_mask(&dev_priv->power_domains));
drm_WARN_ON(&dev_priv->drm, refs > power_well->count);
@@ -3805,7 +3805,7 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
drm_dbg(&i915->drm, "%-25s %d\n",
power_well->desc->name, power_well->count);
- for_each_power_domain(domain, power_well->desc->domains)
+ for_each_power_domain(domain, power_well->domains)
drm_dbg(&i915->drm, " %-23s %d\n",
intel_display_power_domain_str(domain),
power_domains->domain_use_count[domain]);
@@ -3847,7 +3847,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
power_well->count, enabled);
domains_count = 0;
- for_each_power_domain(domain, power_well->desc->domains)
+ for_each_power_domain(domain, power_well->domains)
domains_count += power_domains->domain_use_count[domain];
if (power_well->count != domains_count) {
@@ -3962,7 +3962,7 @@ void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m
seq_printf(m, "%-25s %d\n", power_well->desc->name,
power_well->count);
- for_each_power_domain(power_domain, power_well->desc->domains)
+ for_each_power_domain(power_domain, power_well->domains)
seq_printf(m, " %-23s %d\n",
intel_display_power_domain_str(power_domain),
power_domains->domain_use_count[power_domain]);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
index fd1abb64a8a47..49f6155e62c47 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_internal.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
@@ -16,7 +16,10 @@ struct i915_power_well_regs;
/* Power well structure for haswell */
struct i915_power_well_desc {
const char *name;
- u64 domains;
+ const struct i915_power_domain_list {
+ const enum intel_display_power_domain *list;
+ u8 count;
+ } *domain_list;
/* Mask of pipes whose IRQ logic is backed by the pw */
u16 irq_pipe_mask:4;
u16 always_on:1;
@@ -65,6 +68,7 @@ struct i915_power_well_desc {
struct i915_power_well {
const struct i915_power_well_desc *desc;
+ u64 domains;
/* power well enable/disable usage count */
int count;
/* cached hw enabled state */
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 773b133902e3d..42f5541c5ecc8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -10,7 +10,24 @@
#include "intel_display_power.h"
#include "intel_display_power_internal.h"
-#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
+#define __LIST_INLINE_ELEMS(__elem_type, ...) \
+ ((__elem_type []){ __VA_ARGS__ })
+
+#define __LIST(__elems) { \
+ .list = __elems, \
+ .count = ARRAY_SIZE(__elems), \
+}
+
+#define I915_PW_DOMAINS(...) \
+ (const struct i915_power_domain_list) \
+ __LIST(__LIST_INLINE_ELEMS(enum intel_display_power_domain, __VA_ARGS__))
+
+#define I915_DECL_PW_DOMAINS(__name, ...) \
+ static const struct i915_power_domain_list __name = I915_PW_DOMAINS(__VA_ARGS__)
+
+/* Zero-length list assigns all power domains, a NULL list assigns none. */
+#define I915_PW_DOMAINS_NONE NULL
+#define I915_PW_DOMAINS_ALL /* zero-length list */
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain)
@@ -150,68 +167,70 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
}
}
+I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
+
static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
},
};
-#define I830_PIPES_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
+ POWER_DOMAIN_PIPE_A,
+ POWER_DOMAIN_PIPE_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_TRANSCODER_A,
+ POWER_DOMAIN_TRANSCODER_B,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc i830_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "pipes",
- .domains = I830_PIPES_POWER_DOMAINS,
+ .domain_list = &i830_pwdoms_pipes,
.ops = &i830_pipes_power_well_ops,
.id = DISP_PW_ID_NONE,
},
};
-#define HSW_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
+ POWER_DOMAIN_PIPE_B,
+ POWER_DOMAIN_PIPE_C,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C,
+ POWER_DOMAIN_TRANSCODER_A,
+ POWER_DOMAIN_TRANSCODER_B,
+ POWER_DOMAIN_TRANSCODER_C,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
+ POWER_DOMAIN_PORT_CRT, /* DDI E */
+ POWER_DOMAIN_VGA,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUDIO_PLAYBACK,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc hsw_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "display",
- .domains = HSW_DISPLAY_POWER_DOMAINS,
+ .domain_list = &hsw_pwdoms_display,
.ops = &hsw_power_well_ops,
.has_vga = true,
.id = HSW_DISP_PW_GLOBAL,
@@ -221,33 +240,33 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
},
};
-#define BDW_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
+ POWER_DOMAIN_PIPE_B,
+ POWER_DOMAIN_PIPE_C,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C,
+ POWER_DOMAIN_TRANSCODER_A,
+ POWER_DOMAIN_TRANSCODER_B,
+ POWER_DOMAIN_TRANSCODER_C,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
+ POWER_DOMAIN_PORT_CRT, /* DDI E */
+ POWER_DOMAIN_VGA,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUDIO_PLAYBACK,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc bdw_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "display",
- .domains = BDW_DISPLAY_POWER_DOMAINS,
+ .domain_list = &bdw_pwdoms_display,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
@@ -258,64 +277,51 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
},
};
-#define VLV_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
+ POWER_DOMAIN_DISPLAY_CORE,
+ POWER_DOMAIN_PIPE_A,
+ POWER_DOMAIN_PIPE_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_TRANSCODER_A,
+ POWER_DOMAIN_TRANSCODER_B,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_DSI,
+ POWER_DOMAIN_PORT_CRT,
+ POWER_DOMAIN_VGA,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUDIO_PLAYBACK,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_GMBUS,
+ POWER_DOMAIN_INIT);
-#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_CRT,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
-#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc vlv_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "display",
- .domains = VLV_DISPLAY_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_display,
.ops = &vlv_display_power_well_ops,
.id = VLV_DISP_PW_DISP2D,
{
@@ -323,10 +329,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
},
}, {
.name = "dpio-tx-b-01",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
.ops = &vlv_dpio_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -334,10 +337,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
},
}, {
.name = "dpio-tx-b-23",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
.ops = &vlv_dpio_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -345,10 +345,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
},
}, {
.name = "dpio-tx-c-01",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
.ops = &vlv_dpio_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -356,10 +353,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
},
}, {
.name = "dpio-tx-c-23",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
.ops = &vlv_dpio_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -367,7 +361,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
},
}, {
.name = "dpio-common",
- .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_dpio_cmn_bc,
.ops = &vlv_dpio_cmn_power_well_ops,
.id = VLV_DISP_PW_DPIO_CMN_BC,
{
@@ -376,46 +370,46 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
},
};
-#define CHV_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(chv_pwdoms_display,
+ POWER_DOMAIN_DISPLAY_CORE,
+ POWER_DOMAIN_PIPE_A,
+ POWER_DOMAIN_PIPE_B,
+ POWER_DOMAIN_PIPE_C,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C,
+ POWER_DOMAIN_TRANSCODER_A,
+ POWER_DOMAIN_TRANSCODER_B,
+ POWER_DOMAIN_TRANSCODER_C,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
+ POWER_DOMAIN_PORT_DSI,
+ POWER_DOMAIN_VGA,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUDIO_PLAYBACK,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_AUX_D,
+ POWER_DOMAIN_GMBUS,
+ POWER_DOMAIN_INIT);
-#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
-#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
+ POWER_DOMAIN_AUX_D,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc chv_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
@@ -426,12 +420,12 @@ static const struct i915_power_well_desc chv_power_wells[] = {
* power wells don't actually exist. Pipe A power well is
* required for any pipe to work.
*/
- .domains = CHV_DISPLAY_POWER_DOMAINS,
+ .domain_list = &chv_pwdoms_display,
.ops = &chv_pipe_power_well_ops,
.id = DISP_PW_ID_NONE,
}, {
.name = "dpio-common-bc",
- .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
+ .domain_list = &chv_pwdoms_dpio_cmn_bc,
.ops = &chv_dpio_cmn_power_well_ops,
.id = VLV_DISP_PW_DPIO_CMN_BC,
{
@@ -439,7 +433,7 @@ static const struct i915_power_well_desc chv_power_wells[] = {
},
}, {
.name = "dpio-common-d",
- .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
+ .domain_list = &chv_pwdoms_dpio_cmn_d,
.ops = &chv_dpio_cmn_power_well_ops,
.id = CHV_DISP_PW_DPIO_CMN_D,
{
@@ -448,61 +442,64 @@ static const struct i915_power_well_desc chv_power_wells[] = {
},
};
-#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define SKL_PW_2_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_D, \
+ POWER_DOMAIN_PORT_DDI_LANES_E, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C, \
+ POWER_DOMAIN_AUX_D
-#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2,
+ SKL_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
-#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off,
+ SKL_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_GT_IRQ,
+ POWER_DOMAIN_INIT);
-#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e,
+ POWER_DOMAIN_PORT_DDI_IO_A,
+ POWER_DOMAIN_PORT_DDI_IO_E,
+ POWER_DOMAIN_INIT);
-#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_b,
+ POWER_DOMAIN_PORT_DDI_IO_B,
+ POWER_DOMAIN_INIT);
-#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_c,
+ POWER_DOMAIN_PORT_DDI_IO_C,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d,
+ POWER_DOMAIN_PORT_DDI_IO_D,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc skl_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -513,7 +510,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
}, {
.name = "MISC_IO",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.id = SKL_DISP_PW_MISC_IO,
@@ -522,12 +519,12 @@ static const struct i915_power_well_desc skl_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
@@ -538,7 +535,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
},
}, {
.name = "DDI_IO_A_E",
- .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_ddi_io_a_e,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -546,7 +543,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
},
}, {
.name = "DDI_IO_B",
- .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_ddi_io_b,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -554,7 +551,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
},
}, {
.name = "DDI_IO_C",
- .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_ddi_io_c,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -562,7 +559,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
},
}, {
.name = "DDI_IO_D",
- .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_ddi_io_d,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -571,54 +568,57 @@ static const struct i915_power_well_desc skl_power_wells[] = {
},
};
-#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define BXT_PW_2_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C
-#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(bxt_pwdoms_pw_2,
+ BXT_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
-#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off,
+ BXT_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_GMBUS,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_GT_IRQ,
+ POWER_DOMAIN_INIT);
-#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
+ POWER_DOMAIN_PORT_DDI_LANES_A,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc bxt_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -628,12 +628,12 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &bxt_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .domain_list = &bxt_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
@@ -644,7 +644,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
},
}, {
.name = "dpio-common-a",
- .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
+ .domain_list = &bxt_pwdoms_dpio_cmn_a,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = BXT_DISP_PW_DPIO_CMN_A,
{
@@ -652,7 +652,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
},
}, {
.name = "dpio-common-bc",
- .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
+ .domain_list = &bxt_pwdoms_dpio_cmn_bc,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = VLV_DISP_PW_DPIO_CMN_BC,
{
@@ -661,74 +661,77 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
},
};
-#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
-#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
-#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
-
-#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_PW_2_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_pw_2,
+ GLK_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off,
+ GLK_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_GMBUS,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_GT_IRQ,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A);
+I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B);
+I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
+ POWER_DOMAIN_PORT_DDI_LANES_A,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_IO_A,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc glk_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -738,12 +741,12 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
@@ -754,7 +757,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "dpio-common-a",
- .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_dpio_cmn_a,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = BXT_DISP_PW_DPIO_CMN_A,
{
@@ -762,7 +765,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "dpio-common-b",
- .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_dpio_cmn_b,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = VLV_DISP_PW_DPIO_CMN_BC,
{
@@ -770,7 +773,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "dpio-common-c",
- .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_dpio_cmn_c,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = GLK_DISP_PW_DPIO_CMN_C,
{
@@ -778,7 +781,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "AUX_A",
- .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_aux_a,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -786,7 +789,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "AUX_B",
- .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_aux_b,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -794,7 +797,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "AUX_C",
- .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_aux_c,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -802,7 +805,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "DDI_IO_A",
- .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_ddi_io_a,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -810,7 +813,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "DDI_IO_B",
- .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_ddi_io_b,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -818,7 +821,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "DDI_IO_C",
- .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_ddi_io_c,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -841,89 +844,97 @@ static const struct i915_power_well_desc glk_power_wells[] = {
* - DDI_A
* - FBC
*/
-#define ICL_PW_4_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define ICL_PW_4_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C
+
+I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
+ ICL_PW_4_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
/* VDSC/joining */
-#define ICL_PW_3_POWER_DOMAINS ( \
- ICL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_F) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_AUX_E) | \
- BIT_ULL(POWER_DOMAIN_AUX_F) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT_D) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT_E) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT_F) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define ICL_PW_3_POWER_DOMAINS \
+ ICL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_D, \
+ POWER_DOMAIN_PORT_DDI_LANES_E, \
+ POWER_DOMAIN_PORT_DDI_LANES_F, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C, \
+ POWER_DOMAIN_AUX_D, \
+ POWER_DOMAIN_AUX_E, \
+ POWER_DOMAIN_AUX_F, \
+ POWER_DOMAIN_AUX_TBT_C, \
+ POWER_DOMAIN_AUX_TBT_D, \
+ POWER_DOMAIN_AUX_TBT_E, \
+ POWER_DOMAIN_AUX_TBT_F
+
+I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3,
+ ICL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
/*
* - transcoder WD
* - KVMR (HW control)
*/
-#define ICL_PW_2_POWER_DOMAINS ( \
- ICL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define ICL_PW_2_POWER_DOMAINS \
+ ICL_PW_3_POWER_DOMAINS, \
+ POWER_DOMAIN_TRANSCODER_VDSC_PW2
+
+I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2,
+ ICL_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
/*
* - KVMR (HW control)
*/
-#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- ICL_PW_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_DC_OFF) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off,
+ ICL_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_DC_OFF,
+ POWER_DOMAIN_INIT);
-#define ICL_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
-#define ICL_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
-#define ICL_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
-#define ICL_DDI_IO_D_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D)
-#define ICL_DDI_IO_E_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E)
-#define ICL_DDI_IO_F_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_F)
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A);
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B);
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C);
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d, POWER_DOMAIN_PORT_DDI_IO_D);
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e, POWER_DOMAIN_PORT_DDI_IO_E);
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f, POWER_DOMAIN_PORT_DDI_IO_F);
-#define ICL_AUX_A_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_IO_A))
-
-#define ICL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_B)
-#define ICL_AUX_C_TC1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C)
-#define ICL_AUX_D_TC2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D)
-#define ICL_AUX_E_TC3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E)
-#define ICL_AUX_F_TC4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F)
-#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_C)
-#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_D)
-#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_E)
-#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_F)
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_IO_A);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b, POWER_DOMAIN_AUX_B);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d, POWER_DOMAIN_AUX_D);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e, POWER_DOMAIN_AUX_E);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f, POWER_DOMAIN_AUX_F);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT_C);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT_D);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT_E);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT_F);
static const struct i915_power_well_desc icl_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -933,12 +944,12 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = ICL_PW_2_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.id = SKL_DISP_PW_2,
@@ -947,7 +958,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "PW_3",
- .domains = ICL_PW_3_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_pw_3,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B),
@@ -958,7 +969,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "DDI_IO_A",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_a,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -966,7 +977,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "DDI_IO_B",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_b,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -974,7 +985,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "DDI_IO_C",
- .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_c,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -982,7 +993,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "DDI_IO_D",
- .domains = ICL_DDI_IO_D_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_d,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -990,7 +1001,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "DDI_IO_E",
- .domains = ICL_DDI_IO_E_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_e,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -998,7 +1009,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "DDI_IO_F",
- .domains = ICL_DDI_IO_F_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_f,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1006,7 +1017,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_a,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1014,7 +1025,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_b,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1022,7 +1033,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_C",
- .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_c,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1031,7 +1042,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_D",
- .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_d,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1040,7 +1051,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_E",
- .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_e,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1049,7 +1060,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_F",
- .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_f,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1058,7 +1069,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_TBT1",
- .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_tbt1,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1067,7 +1078,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_TBT2",
- .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_tbt2,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1076,7 +1087,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_TBT3",
- .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_tbt3,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1085,7 +1096,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_TBT4",
- .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_tbt4,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1094,7 +1105,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "PW_4",
- .domains = ICL_PW_4_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_pw_4,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_C),
.has_fuses = true,
@@ -1105,113 +1116,122 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
};
-#define TGL_PW_5_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define TGL_PW_5_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_D, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
+ POWER_DOMAIN_TRANSCODER_D
-#define TGL_PW_4_POWER_DOMAINS ( \
- TGL_PW_5_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_5,
+ TGL_PW_5_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
-#define TGL_PW_3_POWER_DOMAINS ( \
- TGL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define TGL_PW_4_POWER_DOMAINS \
+ TGL_PW_5_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_C
-#define TGL_PW_2_POWER_DOMAINS ( \
- TGL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_4,
+ TGL_PW_4_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
-#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- TGL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define TGL_PW_3_POWER_DOMAINS \
+ TGL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC3, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC4, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC5, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC6, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2, \
+ POWER_DOMAIN_AUX_USBC3, \
+ POWER_DOMAIN_AUX_USBC4, \
+ POWER_DOMAIN_AUX_USBC5, \
+ POWER_DOMAIN_AUX_USBC6, \
+ POWER_DOMAIN_AUX_TBT1, \
+ POWER_DOMAIN_AUX_TBT2, \
+ POWER_DOMAIN_AUX_TBT3, \
+ POWER_DOMAIN_AUX_TBT4, \
+ POWER_DOMAIN_AUX_TBT5, \
+ POWER_DOMAIN_AUX_TBT6
-#define TGL_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
-#define TGL_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
-#define TGL_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
-#define TGL_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
-#define TGL_DDI_IO_TC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC5)
-#define TGL_DDI_IO_TC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC6)
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_3,
+ TGL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
-#define TGL_AUX_A_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_IO_A))
-#define TGL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_B)
-#define TGL_AUX_C_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C)
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_2,
+ TGL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_TRANSCODER_VDSC_PW2,
+ POWER_DOMAIN_INIT);
-#define TGL_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
-#define TGL_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
-#define TGL_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
-#define TGL_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
-#define TGL_AUX_IO_USBC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC5)
-#define TGL_AUX_IO_USBC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC6)
+I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off,
+ TGL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_INIT);
-#define TGL_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
-#define TGL_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
-#define TGL_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
-#define TGL_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
-#define TGL_AUX_IO_TBT5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT5)
-#define TGL_AUX_IO_TBT6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT6)
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5, POWER_DOMAIN_PORT_DDI_IO_TC5);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6, POWER_DOMAIN_PORT_DDI_IO_TC6);
-#define TGL_TC_COLD_OFF_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
- BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_a,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_IO_A);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_b, POWER_DOMAIN_AUX_B);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5, POWER_DOMAIN_AUX_USBC5);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6, POWER_DOMAIN_AUX_USBC6);
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5, POWER_DOMAIN_AUX_TBT5);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6, POWER_DOMAIN_AUX_TBT6);
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off,
+ POWER_DOMAIN_AUX_USBC1,
+ POWER_DOMAIN_AUX_USBC2,
+ POWER_DOMAIN_AUX_USBC3,
+ POWER_DOMAIN_AUX_USBC4,
+ POWER_DOMAIN_AUX_USBC5,
+ POWER_DOMAIN_AUX_USBC6,
+ POWER_DOMAIN_AUX_TBT1,
+ POWER_DOMAIN_AUX_TBT2,
+ POWER_DOMAIN_AUX_TBT3,
+ POWER_DOMAIN_AUX_TBT4,
+ POWER_DOMAIN_AUX_TBT5,
+ POWER_DOMAIN_AUX_TBT6,
+ POWER_DOMAIN_TC_COLD_OFF);
static const struct i915_power_well_desc tgl_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -1221,12 +1241,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = TGL_PW_2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.id = SKL_DISP_PW_2,
@@ -1235,7 +1255,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "PW_3",
- .domains = TGL_PW_3_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_3,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B),
@@ -1246,7 +1266,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "DDI_IO_A",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_a,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1254,7 +1274,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
}
}, {
.name = "DDI_IO_B",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_b,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1262,7 +1282,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
}
}, {
.name = "DDI_IO_C",
- .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_c,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1270,7 +1290,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
}
}, {
.name = "DDI_IO_TC1",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc1,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1278,7 +1298,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "DDI_IO_TC2",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc2,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1286,7 +1306,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "DDI_IO_TC3",
- .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc3,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1294,7 +1314,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "DDI_IO_TC4",
- .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc4,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1302,7 +1322,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "DDI_IO_TC5",
- .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc5,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1310,7 +1330,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "DDI_IO_TC6",
- .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc6,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1318,12 +1338,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "TC_cold_off",
- .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_tc_cold_off,
.ops = &tgl_tc_cold_off_ops,
.id = TGL_DISP_PW_TC_COLD_OFF,
}, {
.name = "AUX_A",
- .domains = TGL_AUX_A_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_a,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1331,7 +1351,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_B",
- .domains = TGL_AUX_B_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_b,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1339,7 +1359,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_C",
- .domains = TGL_AUX_C_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_c,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1347,7 +1367,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_USBC1",
- .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc1,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1356,7 +1376,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_USBC2",
- .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc2,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1365,7 +1385,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_USBC3",
- .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc3,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1374,7 +1394,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_USBC4",
- .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc4,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1383,7 +1403,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_USBC5",
- .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc5,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1392,7 +1412,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_USBC6",
- .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc6,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1401,7 +1421,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_TBT1",
- .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt1,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1410,7 +1430,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_TBT2",
- .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt2,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1419,7 +1439,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_TBT3",
- .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt3,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1428,7 +1448,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_TBT4",
- .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt4,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1437,7 +1457,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_TBT5",
- .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt5,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1446,7 +1466,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_TBT6",
- .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt6,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1455,7 +1475,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "PW_4",
- .domains = TGL_PW_4_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_4,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
@@ -1465,7 +1485,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
}
}, {
.name = "PW_5",
- .domains = TGL_PW_5_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_5,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_D),
@@ -1476,25 +1496,31 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
};
-#define RKL_PW_4_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define RKL_PW_4_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_C
-#define RKL_PW_3_POWER_DOMAINS ( \
- RKL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_4,
+ RKL_PW_4_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+#define RKL_PW_3_POWER_DOMAINS \
+ RKL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2
+
+I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_3,
+ RKL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
/*
* There is no PW_2/PG_2 on RKL.
@@ -1517,24 +1543,24 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
* - top-level GTC (DDI-level GTC is in the well associated with the DDI)
*/
-#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- RKL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
+ RKL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc rkl_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -1544,12 +1570,12 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &rkl_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_3",
- .domains = RKL_PW_3_POWER_DOMAINS,
+ .domain_list = &rkl_pwdoms_pw_3,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
.has_vga = true,
@@ -1560,7 +1586,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
}, {
.name = "PW_4",
- .domains = RKL_PW_4_POWER_DOMAINS,
+ .domain_list = &rkl_pwdoms_pw_4,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
@@ -1570,7 +1596,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
}
}, {
.name = "DDI_IO_A",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_a,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1578,7 +1604,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
}
}, {
.name = "DDI_IO_B",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_b,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1586,7 +1612,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
}
}, {
.name = "DDI_IO_TC1",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc1,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1594,7 +1620,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
}, {
.name = "DDI_IO_TC2",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc2,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1602,7 +1628,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
}, {
.name = "AUX_A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_a,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1610,7 +1636,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
}, {
.name = "AUX_B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_b,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1618,7 +1644,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
}, {
.name = "AUX_USBC1",
- .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc1,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1626,7 +1652,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
}, {
.name = "AUX_USBC2",
- .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc2,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1638,43 +1664,46 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
/*
* DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
*/
-#define DG1_PW_3_POWER_DOMAINS ( \
- TGL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define DG1_PW_3_POWER_DOMAINS \
+ TGL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2
-#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- DG1_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_3,
+ DG1_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
-#define DG1_PW_2_POWER_DOMAINS ( \
- DG1_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off,
+ DG1_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
+ DG1_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_TRANSCODER_VDSC_PW2,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc dg1_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -1684,12 +1713,12 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &dg1_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = DG1_PW_2_POWER_DOMAINS,
+ .domain_list = &dg1_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.id = SKL_DISP_PW_2,
@@ -1698,7 +1727,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "PW_3",
- .domains = DG1_PW_3_POWER_DOMAINS,
+ .domain_list = &dg1_pwdoms_pw_3,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
.has_vga = true,
@@ -1709,7 +1738,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "DDI_IO_A",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_a,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1717,7 +1746,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
}
}, {
.name = "DDI_IO_B",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_b,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1725,7 +1754,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
}
}, {
.name = "DDI_IO_TC1",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc1,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1733,7 +1762,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "DDI_IO_TC2",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc2,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1741,7 +1770,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "AUX_A",
- .domains = TGL_AUX_A_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_a,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1749,7 +1778,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "AUX_B",
- .domains = TGL_AUX_B_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_b,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1757,7 +1786,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "AUX_USBC1",
- .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc1,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1766,7 +1795,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "AUX_USBC2",
- .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc2,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1775,7 +1804,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "PW_4",
- .domains = TGL_PW_4_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_4,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
@@ -1785,7 +1814,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
}
}, {
.name = "PW_5",
- .domains = TGL_PW_5_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_5,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_D),
@@ -1814,54 +1843,66 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
* to top. This allows pipes to be power gated independently.
*/
-#define XELPD_PW_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_2_POWER_DOMAINS ( \
- XELPD_PW_B_POWER_DOMAINS | \
- XELPD_PW_C_POWER_DOMAINS | \
- XELPD_PW_D_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) | \
- BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define XELPD_PW_D_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_D, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
+ POWER_DOMAIN_TRANSCODER_D
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_d,
+ XELPD_PW_D_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+#define XELPD_PW_C_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_C
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_c,
+ XELPD_PW_C_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+#define XELPD_PW_B_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_b,
+ XELPD_PW_B_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
+ POWER_DOMAIN_PIPE_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_INIT);
+
+#define XELPD_PW_2_POWER_DOMAINS \
+ XELPD_PW_B_POWER_DOMAINS, \
+ XELPD_PW_C_POWER_DOMAINS, \
+ XELPD_PW_D_POWER_DOMAINS, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_D_XELPD, \
+ POWER_DOMAIN_PORT_DDI_LANES_E_XELPD, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC3, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC4, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_C, \
+ POWER_DOMAIN_AUX_D_XELPD, \
+ POWER_DOMAIN_AUX_E_XELPD, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2, \
+ POWER_DOMAIN_AUX_USBC3, \
+ POWER_DOMAIN_AUX_USBC4, \
+ POWER_DOMAIN_AUX_TBT1, \
+ POWER_DOMAIN_AUX_TBT2, \
+ POWER_DOMAIN_AUX_TBT3, \
+ POWER_DOMAIN_AUX_TBT4
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
+ XELPD_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
/*
* XELPD PW_1/PG_1 domains (under HW/DMC control):
@@ -1880,45 +1921,46 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
* - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
*/
-#define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- XELPD_PW_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
+ XELPD_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_PORT_DSI,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_INIT);
-#define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
-#define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
-#define XELPD_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
-#define XELPD_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
-#define XELPD_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
-#define XELPD_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_d_xelpd, POWER_DOMAIN_AUX_D_XELPD);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_e_xelpd, POWER_DOMAIN_AUX_E_XELPD);
-#define XELPD_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
-#define XELPD_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
-#define XELPD_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
-#define XELPD_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4);
-#define XELPD_DDI_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D_XELPD)
-#define XELPD_DDI_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E_XELPD)
-#define XELPD_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
-#define XELPD_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
-#define XELPD_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
-#define XELPD_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_d_xelpd, POWER_DOMAIN_PORT_DDI_IO_D_XELPD);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_e_xelpd, POWER_DOMAIN_PORT_DDI_IO_E_XELPD);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
static const struct i915_power_well_desc xelpd_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -1928,12 +1970,12 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = XELPD_PW_2_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_vga = true,
.has_fuses = true,
@@ -1943,7 +1985,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "PW_A",
- .domains = XELPD_PW_A_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_pw_a,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_A),
.has_fuses = true,
@@ -1953,7 +1995,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "PW_B",
- .domains = XELPD_PW_B_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_pw_b,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
.has_fuses = true,
@@ -1963,7 +2005,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "PW_C",
- .domains = XELPD_PW_C_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_pw_c,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_C),
.has_fuses = true,
@@ -1973,7 +2015,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "PW_D",
- .domains = XELPD_PW_D_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_pw_d,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_D),
.has_fuses = true,
@@ -1983,7 +2025,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "DDI_IO_A",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_a,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1991,7 +2033,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_B",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_b,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1999,7 +2041,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_C",
- .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_c,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -2007,7 +2049,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_D_XELPD",
- .domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_d_xelpd,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -2015,7 +2057,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_E_XELPD",
- .domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_e_xelpd,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -2023,7 +2065,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_TC1",
- .domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_tc1,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -2031,7 +2073,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_TC2",
- .domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_tc2,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -2039,7 +2081,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_TC3",
- .domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_tc3,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -2047,7 +2089,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_TC4",
- .domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_tc4,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -2055,7 +2097,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "AUX_A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_a,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
@@ -2064,7 +2106,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_b,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
@@ -2073,7 +2115,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_C",
- .domains = TGL_AUX_C_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_c,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
@@ -2082,7 +2124,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_D_XELPD",
- .domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_d_xelpd,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
@@ -2091,7 +2133,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_E_XELPD",
- .domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_e_xelpd,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -2099,7 +2141,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_USBC1",
- .domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_usbc1,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
@@ -2108,7 +2150,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_USBC2",
- .domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_usbc2,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -2116,7 +2158,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_USBC3",
- .domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_usbc3,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -2124,7 +2166,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_USBC4",
- .domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_usbc4,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -2132,7 +2174,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_TBT1",
- .domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_tbt1,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -2141,7 +2183,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_TBT2",
- .domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_tbt2,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -2150,7 +2192,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_TBT3",
- .domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_tbt3,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -2159,7 +2201,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_TBT4",
- .domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_tbt4,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -2169,6 +2211,24 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
};
+static void init_power_well_domains(const struct i915_power_well_desc *desc,
+ struct i915_power_well *power_well)
+{
+ int j;
+
+ if (!desc->domain_list)
+ return;
+
+ if (desc->domain_list->count == 0) {
+ power_well->domains = GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0);
+
+ return;
+ }
+
+ for (j = 0; j < desc->domain_list->count; j++)
+ power_well->domains |= BIT_ULL(desc->domain_list->list[j]);
+}
+
static int
__set_power_wells(struct i915_power_domains *power_domains,
const struct i915_power_well_desc *power_well_descs,
@@ -2199,9 +2259,13 @@ __set_power_wells(struct i915_power_domains *power_domains,
if (BIT_ULL(id) & skip_mask)
continue;
- power_domains->power_wells[plt_idx++].desc =
+ power_domains->power_wells[plt_idx].desc =
&power_well_descs[i];
+ init_power_well_domains(&power_well_descs[i], &power_domains->power_wells[plt_idx]);
+
+ plt_idx++;
+
if (id == DISP_PW_ID_NONE)
continue;
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 10/19] drm/i915: Convert the u64 power well domains mask to a bitmap
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (8 preceding siblings ...)
2022-01-28 11:49 ` [Intel-gfx] [PATCH 09/19] drm/i915: Convert the power well descriptor domain mask to a list Imre Deak
@ 2022-01-28 11:49 ` Imre Deak
2022-02-01 11:20 ` Jani Nikula
2022-01-28 11:49 ` [Intel-gfx] [PATCH 11/19] drm/i915: Simplify power well definitions by adding power well instances Imre Deak
` (11 subsequent siblings)
21 siblings, 1 reply; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:49 UTC (permalink / raw)
To: intel-gfx
To remove the aliasing of the power domain enum values in a follow-up
patch in this patchset (requiring a bigger mask) and allow for defining
additional power domains in the future (at least some upcoming TypeC
changes requires this) convert the u64 i915_power_well_desc::domains
mask to a bitmap.
For simplicity I changed the for_each_power_domain_well() macros to
accept one domain only instead of a mask, as there isn't any current
user passing multiple domains.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 65 ++++-----
.../drm/i915/display/intel_display_power.c | 123 +++++++++++-------
.../drm/i915/display/intel_display_power.h | 16 ++-
.../display/intel_display_power_internal.h | 2 +-
.../i915/display/intel_display_power_map.c | 4 +-
5 files changed, 119 insertions(+), 91 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3094cfc668c81..d0b9618383ce3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2372,66 +2372,71 @@ intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
}
}
-static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
+static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
+ intel_power_domain_mask_t *mask)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
struct drm_encoder *encoder;
enum pipe pipe = crtc->pipe;
- u64 mask;
+
+ bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
if (!crtc_state->hw.active)
- return 0;
+ return;
- mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
- mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(cpu_transcoder));
+ set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
+ set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
if (crtc_state->pch_pfit.enabled ||
crtc_state->pch_pfit.force_thru)
- mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
+ set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
drm_for_each_encoder_mask(encoder, &dev_priv->drm,
crtc_state->uapi.encoder_mask) {
struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
- mask |= BIT_ULL(intel_encoder->power_domain);
+ set_bit(intel_encoder->power_domain, mask->bits);
}
if (HAS_DDI(dev_priv) && crtc_state->has_audio)
- mask |= BIT_ULL(POWER_DOMAIN_AUDIO_MMIO);
+ set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
if (crtc_state->shared_dpll)
- mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
+ set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
if (crtc_state->dsc.compression_enable)
- mask |= BIT_ULL(intel_dsc_power_domain(crtc, cpu_transcoder));
-
- return mask;
+ set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
}
-static u64
-modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
+static void
+modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
+ intel_power_domain_mask_t *old_domains)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum intel_display_power_domain domain;
- u64 domains, new_domains, old_domains;
+ intel_power_domain_mask_t domains, new_domains;
- domains = get_crtc_power_domains(crtc_state);
+ get_crtc_power_domains(crtc_state, &domains);
- new_domains = domains & ~crtc->enabled_power_domains.mask;
- old_domains = crtc->enabled_power_domains.mask & ~domains;
+ bitmap_andnot(new_domains.bits,
+ domains.bits,
+ crtc->enabled_power_domains.mask.bits,
+ POWER_DOMAIN_NUM);
+ bitmap_andnot(old_domains->bits,
+ crtc->enabled_power_domains.mask.bits,
+ domains.bits,
+ POWER_DOMAIN_NUM);
- for_each_power_domain(domain, new_domains)
+ for_each_power_domain(domain, &new_domains)
intel_display_power_get_in_set(dev_priv,
&crtc->enabled_power_domains,
domain);
-
- return old_domains;
}
static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
- u64 domains)
+ intel_power_domain_mask_t *domains)
{
intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
&crtc->enabled_power_domains,
@@ -8628,7 +8633,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
struct intel_crtc *crtc;
- u64 put_domains[I915_MAX_PIPES] = {};
+ intel_power_domain_mask_t put_domains[I915_MAX_PIPES] = {};
intel_wakeref_t wakeref = 0;
int i;
@@ -8645,9 +8650,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
new_crtc_state, i) {
if (intel_crtc_needs_modeset(new_crtc_state) ||
new_crtc_state->update_pipe) {
-
- put_domains[crtc->pipe] =
- modeset_get_crtc_power_domains(new_crtc_state);
+ modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
}
}
@@ -8746,7 +8749,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
intel_post_plane_update(state, crtc);
- modeset_put_crtc_power_domains(crtc, put_domains[crtc->pipe]);
+ modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
@@ -10702,11 +10705,11 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
for_each_intel_crtc(dev, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
- u64 put_domains;
+ intel_power_domain_mask_t put_domains;
- put_domains = modeset_get_crtc_power_domains(crtc_state);
- if (drm_WARN_ON(dev, put_domains))
- modeset_put_crtc_power_domains(crtc, put_domains);
+ modeset_get_crtc_power_domains(crtc_state, &put_domains);
+ if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
+ modeset_put_crtc_power_domains(crtc, &put_domains);
}
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index a370ef8376410..cf014d79682ca 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -38,13 +38,13 @@
(__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
(__power_well)--)
-#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain) \
for_each_power_well(__dev_priv, __power_well) \
- for_each_if((__power_well)->domains & (__domain_mask))
+ for_each_if(test_bit((__domain), (__power_well)->domains.bits))
-#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \
for_each_power_well_reverse(__dev_priv, __power_well) \
- for_each_if((__power_well)->domains & (__domain_mask))
+ for_each_if(test_bit((__domain), (__power_well)->domains.bits))
struct i915_power_well_regs {
i915_reg_t bios;
@@ -141,7 +141,7 @@ bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
is_enabled = true;
- for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) {
+ for_each_power_domain_well_reverse(dev_priv, power_well, domain) {
if (power_well->desc->always_on)
continue;
@@ -460,13 +460,18 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
-static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
+static void async_put_domains_mask(struct i915_power_domains *power_domains,
+ intel_power_domain_mask_t *mask);
static int power_well_async_ref_count(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- int refs = hweight64(power_well->domains &
- async_put_domains_mask(&dev_priv->power_domains));
+ intel_power_domain_mask_t domain_mask;
+ int refs;
+
+ async_put_domains_mask(&dev_priv->power_domains, &domain_mask);
+ bitmap_and(domain_mask.bits, domain_mask.bits, power_well->domains.bits, POWER_DOMAIN_NUM);
+ refs = bitmap_weight(domain_mask.bits, POWER_DOMAIN_NUM);
drm_WARN_ON(&dev_priv->drm, refs > power_well->count);
@@ -1869,10 +1874,13 @@ static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
chv_set_pipe_power_well(dev_priv, power_well, false);
}
-static u64 __async_put_domains_mask(struct i915_power_domains *power_domains)
+static void __async_put_domains_mask(struct i915_power_domains *power_domains,
+ intel_power_domain_mask_t *mask)
{
- return power_domains->async_put_domains[0] |
- power_domains->async_put_domains[1];
+ bitmap_or(mask->bits,
+ power_domains->async_put_domains[0].bits,
+ power_domains->async_put_domains[1].bits,
+ POWER_DOMAIN_NUM);
}
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
@@ -1883,8 +1891,11 @@ assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
power_domains);
- return !drm_WARN_ON(&i915->drm, power_domains->async_put_domains[0] &
- power_domains->async_put_domains[1]);
+
+ return !drm_WARN_ON(&i915->drm,
+ bitmap_intersects(power_domains->async_put_domains[0].bits,
+ power_domains->async_put_domains[1].bits,
+ POWER_DOMAIN_NUM));
}
static bool
@@ -1893,14 +1904,17 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
power_domains);
+ intel_power_domain_mask_t async_put_mask;
enum intel_display_power_domain domain;
bool err = false;
err |= !assert_async_put_domain_masks_disjoint(power_domains);
- err |= drm_WARN_ON(&i915->drm, !!power_domains->async_put_wakeref !=
- !!__async_put_domains_mask(power_domains));
+ __async_put_domains_mask(power_domains, &async_put_mask);
+ err |= drm_WARN_ON(&i915->drm,
+ !!power_domains->async_put_wakeref !=
+ !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM));
- for_each_power_domain(domain, __async_put_domains_mask(power_domains))
+ for_each_power_domain(domain, &async_put_mask)
err |= drm_WARN_ON(&i915->drm,
power_domains->domain_use_count[domain] != 1);
@@ -1908,14 +1922,14 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
}
static void print_power_domains(struct i915_power_domains *power_domains,
- const char *prefix, u64 mask)
+ const char *prefix, intel_power_domain_mask_t *mask)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
power_domains);
enum intel_display_power_domain domain;
- drm_dbg(&i915->drm, "%s (%lu):\n", prefix, hweight64(mask));
+ drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
for_each_power_domain(domain, mask)
drm_dbg(&i915->drm, "%s use_count %d\n",
intel_display_power_domain_str(domain),
@@ -1933,9 +1947,9 @@ print_async_put_domains_state(struct i915_power_domains *power_domains)
power_domains->async_put_wakeref);
print_power_domains(power_domains, "async_put_domains[0]",
- power_domains->async_put_domains[0]);
+ &power_domains->async_put_domains[0]);
print_power_domains(power_domains, "async_put_domains[1]",
- power_domains->async_put_domains[1]);
+ &power_domains->async_put_domains[1]);
}
static void
@@ -1959,11 +1973,13 @@ verify_async_put_domains_state(struct i915_power_domains *power_domains)
#endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */
-static u64 async_put_domains_mask(struct i915_power_domains *power_domains)
+static void async_put_domains_mask(struct i915_power_domains *power_domains,
+ intel_power_domain_mask_t *mask)
+
{
assert_async_put_domain_masks_disjoint(power_domains);
- return __async_put_domains_mask(power_domains);
+ __async_put_domains_mask(power_domains, mask);
}
static void
@@ -1972,8 +1988,8 @@ async_put_domains_clear_domain(struct i915_power_domains *power_domains,
{
assert_async_put_domain_masks_disjoint(power_domains);
- power_domains->async_put_domains[0] &= ~BIT_ULL(domain);
- power_domains->async_put_domains[1] &= ~BIT_ULL(domain);
+ clear_bit(domain, power_domains->async_put_domains[0].bits);
+ clear_bit(domain, power_domains->async_put_domains[1].bits);
}
static bool
@@ -1981,16 +1997,19 @@ intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ intel_power_domain_mask_t async_put_mask;
bool ret = false;
- if (!(async_put_domains_mask(power_domains) & BIT_ULL(domain)))
+ async_put_domains_mask(power_domains, &async_put_mask);
+ if (!test_bit(domain, async_put_mask.bits))
goto out_verify;
async_put_domains_clear_domain(power_domains, domain);
ret = true;
- if (async_put_domains_mask(power_domains))
+ async_put_domains_mask(power_domains, &async_put_mask);
+ if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM))
goto out_verify;
cancel_delayed_work(&power_domains->async_put_work);
@@ -2012,7 +2031,7 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
if (intel_display_power_grab_async_put_ref(dev_priv, domain))
return;
- for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
+ for_each_power_domain_well(dev_priv, power_well, domain)
intel_power_well_get(dev_priv, power_well);
power_domains->domain_use_count[domain]++;
@@ -2093,20 +2112,22 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
struct i915_power_domains *power_domains;
struct i915_power_well *power_well;
const char *name = intel_display_power_domain_str(domain);
+ intel_power_domain_mask_t async_put_mask;
power_domains = &dev_priv->power_domains;
drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain],
"Use count on domain %s is already zero\n",
name);
+ async_put_domains_mask(power_domains, &async_put_mask);
drm_WARN(&dev_priv->drm,
- async_put_domains_mask(power_domains) & BIT_ULL(domain),
+ test_bit(domain, async_put_mask.bits),
"Async disabling of domain %s is pending\n",
name);
power_domains->domain_use_count[domain]--;
- for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain))
+ for_each_power_domain_well_reverse(dev_priv, power_well, domain)
intel_power_well_put(dev_priv, power_well);
}
@@ -2135,7 +2156,7 @@ queue_async_put_domains_work(struct i915_power_domains *power_domains,
}
static void
-release_async_put_domains(struct i915_power_domains *power_domains, u64 mask)
+release_async_put_domains(struct i915_power_domains *power_domains, intel_power_domain_mask_t *mask)
{
struct drm_i915_private *dev_priv =
container_of(power_domains, struct drm_i915_private,
@@ -2183,12 +2204,15 @@ intel_display_power_put_async_work(struct work_struct *work)
goto out_verify;
release_async_put_domains(power_domains,
- power_domains->async_put_domains[0]);
+ &power_domains->async_put_domains[0]);
/* Requeue the work if more domains were async put meanwhile. */
- if (power_domains->async_put_domains[1]) {
- power_domains->async_put_domains[0] =
- fetch_and_zero(&power_domains->async_put_domains[1]);
+ if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) {
+ bitmap_copy(power_domains->async_put_domains[0].bits,
+ power_domains->async_put_domains[1].bits,
+ POWER_DOMAIN_NUM);
+ bitmap_zero(power_domains->async_put_domains[1].bits,
+ POWER_DOMAIN_NUM);
queue_async_put_domains_work(power_domains,
fetch_and_zero(&new_work_wakeref));
} else {
@@ -2240,9 +2264,9 @@ void __intel_display_power_put_async(struct drm_i915_private *i915,
/* Let a pending work requeue itself or queue a new one. */
if (power_domains->async_put_wakeref) {
- power_domains->async_put_domains[1] |= BIT_ULL(domain);
+ set_bit(domain, power_domains->async_put_domains[1].bits);
} else {
- power_domains->async_put_domains[0] |= BIT_ULL(domain);
+ set_bit(domain, power_domains->async_put_domains[0].bits);
queue_async_put_domains_work(power_domains,
fetch_and_zero(&work_wakeref));
}
@@ -2273,6 +2297,7 @@ void __intel_display_power_put_async(struct drm_i915_private *i915,
void intel_display_power_flush_work(struct drm_i915_private *i915)
{
struct i915_power_domains *power_domains = &i915->power_domains;
+ intel_power_domain_mask_t async_put_mask;
intel_wakeref_t work_wakeref;
mutex_lock(&power_domains->lock);
@@ -2281,8 +2306,8 @@ void intel_display_power_flush_work(struct drm_i915_private *i915)
if (!work_wakeref)
goto out_verify;
- release_async_put_domains(power_domains,
- async_put_domains_mask(power_domains));
+ async_put_domains_mask(power_domains, &async_put_mask);
+ release_async_put_domains(power_domains, &async_put_mask);
cancel_delayed_work(&power_domains->async_put_work);
out_verify:
@@ -2361,13 +2386,13 @@ intel_display_power_get_in_set(struct drm_i915_private *i915,
{
intel_wakeref_t __maybe_unused wf;
- drm_WARN_ON(&i915->drm, power_domain_set->mask & BIT_ULL(domain));
+ drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
wf = intel_display_power_get(i915, domain);
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
power_domain_set->wakerefs[domain] = wf;
#endif
- power_domain_set->mask |= BIT_ULL(domain);
+ set_bit(domain, power_domain_set->mask.bits);
}
bool
@@ -2377,7 +2402,7 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
{
intel_wakeref_t wf;
- drm_WARN_ON(&i915->drm, power_domain_set->mask & BIT_ULL(domain));
+ drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
wf = intel_display_power_get_if_enabled(i915, domain);
if (!wf)
@@ -2386,7 +2411,7 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
power_domain_set->wakerefs[domain] = wf;
#endif
- power_domain_set->mask |= BIT_ULL(domain);
+ set_bit(domain, power_domain_set->mask.bits);
return true;
}
@@ -2394,11 +2419,11 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
void
intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
struct intel_display_power_domain_set *power_domain_set,
- u64 mask)
+ intel_power_domain_mask_t *mask)
{
enum intel_display_power_domain domain;
- drm_WARN_ON(&i915->drm, mask & ~power_domain_set->mask);
+ drm_WARN_ON(&i915->drm, !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
for_each_power_domain(domain, mask) {
intel_wakeref_t __maybe_unused wf = -1;
@@ -2407,7 +2432,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
#endif
intel_display_power_put(i915, domain, wf);
- power_domain_set->mask &= ~BIT_ULL(domain);
+ clear_bit(domain, power_domain_set->mask.bits);
}
}
@@ -2711,8 +2736,6 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
dev_priv->dmc.target_dc_state =
sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
- BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
-
mutex_init(&power_domains->lock);
INIT_DELAYED_WORK(&power_domains->async_put_work,
@@ -3805,7 +3828,7 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
drm_dbg(&i915->drm, "%-25s %d\n",
power_well->desc->name, power_well->count);
- for_each_power_domain(domain, power_well->domains)
+ for_each_power_domain(domain, &power_well->domains)
drm_dbg(&i915->drm, " %-23s %d\n",
intel_display_power_domain_str(domain),
power_domains->domain_use_count[domain]);
@@ -3847,7 +3870,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
power_well->count, enabled);
domains_count = 0;
- for_each_power_domain(domain, power_well->domains)
+ for_each_power_domain(domain, &power_well->domains)
domains_count += power_domains->domain_use_count[domain];
if (power_well->count != domains_count) {
@@ -3962,7 +3985,7 @@ void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m
seq_printf(m, "%-25s %d\n", power_well->desc->name,
power_well->count);
- for_each_power_domain(power_domain, power_well->domains)
+ for_each_power_domain(power_domain, &power_well->domains)
seq_printf(m, " %-23s %d\n",
intel_display_power_domain_str(power_domain),
power_domains->domain_use_count[power_domain]);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index c3232809b95f9..c7155801f9bc6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -164,6 +164,8 @@ enum i915_power_well_id {
((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
(tran) + POWER_DOMAIN_TRANSCODER_A)
+typedef struct { DECLARE_BITMAP(bits, POWER_DOMAIN_NUM); } intel_power_domain_mask_t;
+
struct i915_power_domains {
/*
* Power wells needed for initialization at driver init and suspend
@@ -181,21 +183,21 @@ struct i915_power_domains {
struct delayed_work async_put_work;
intel_wakeref_t async_put_wakeref;
- u64 async_put_domains[2];
+ intel_power_domain_mask_t async_put_domains[2];
struct i915_power_well *power_wells;
};
struct intel_display_power_domain_set {
- u64 mask;
+ intel_power_domain_mask_t mask;
#ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
#endif
};
-#define for_each_power_domain(domain, mask) \
- for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
- for_each_if(BIT_ULL(domain) & (mask))
+#define for_each_power_domain(__domain, __mask) \
+ for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \
+ for_each_if(test_bit((__domain), (__mask)->bits))
/* intel_display_power.c */
int intel_power_domains_init(struct drm_i915_private *dev_priv);
@@ -278,13 +280,13 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
void
intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
struct intel_display_power_domain_set *power_domain_set,
- u64 mask);
+ intel_power_domain_mask_t *mask);
static inline void
intel_display_power_put_all_in_set(struct drm_i915_private *i915,
struct intel_display_power_domain_set *power_domain_set)
{
- intel_display_power_put_mask_in_set(i915, power_domain_set, power_domain_set->mask);
+ intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
}
void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
index 49f6155e62c47..c4167ac2f21f8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_internal.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
@@ -68,7 +68,7 @@ struct i915_power_well_desc {
struct i915_power_well {
const struct i915_power_well_desc *desc;
- u64 domains;
+ intel_power_domain_mask_t domains;
/* power well enable/disable usage count */
int count;
/* cached hw enabled state */
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 42f5541c5ecc8..7ec4cafec6ba5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -2220,13 +2220,13 @@ static void init_power_well_domains(const struct i915_power_well_desc *desc,
return;
if (desc->domain_list->count == 0) {
- power_well->domains = GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0);
+ bitmap_fill(power_well->domains.bits, POWER_DOMAIN_NUM);
return;
}
for (j = 0; j < desc->domain_list->count; j++)
- power_well->domains |= BIT_ULL(desc->domain_list->list[j]);
+ set_bit(desc->domain_list->list[j], power_well->domains.bits);
}
static int
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 11/19] drm/i915: Simplify power well definitions by adding power well instances
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (9 preceding siblings ...)
2022-01-28 11:49 ` [Intel-gfx] [PATCH 10/19] drm/i915: Convert the u64 power well domains mask to a bitmap Imre Deak
@ 2022-01-28 11:49 ` Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 12/19] drm/i915: Allow platforms to share power well descriptors Imre Deak
` (10 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:49 UTC (permalink / raw)
To: intel-gfx
All the port specific AUX/DDI_IO power wells share the same power well
ops struct and flags, so we can save some space and simplify the
definition of these by listing for all such power wells only the params
specific to them (name, domains, power well register index, id). Move
these params to a new i915_power_well_instance struct and convert the
per-platform power well definitions accordingly.
For all power well instance the name and power domain list params must
be specified, while the register index and id are optional, add the
I915_PW() macro that both simplifies the definitions and ensures that
the required params are set.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_power.c | 87 +-
.../drm/i915/display/intel_display_power.h | 2 +-
.../display/intel_display_power_internal.h | 48 +-
.../i915/display/intel_display_power_map.c | 1515 +++++------------
4 files changed, 515 insertions(+), 1137 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cf014d79682ca..321ff776ef283 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -81,13 +81,20 @@ struct i915_power_well_ops {
struct i915_power_well *power_well);
};
+static const struct i915_power_well_instance *
+i915_power_well_instance(const struct i915_power_well *power_well)
+{
+ return &power_well->desc->instances->list[power_well->instance_idx];
+}
+
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
static void intel_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- drm_dbg_kms(&dev_priv->drm, "enabling %s\n", power_well->desc->name);
+ drm_dbg_kms(&dev_priv->drm, "enabling %s\n",
+ i915_power_well_instance(power_well)->name);
power_well->desc->ops->enable(dev_priv, power_well);
power_well->hw_enabled = true;
}
@@ -95,7 +102,8 @@ static void intel_power_well_enable(struct drm_i915_private *dev_priv,
static void intel_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- drm_dbg_kms(&dev_priv->drm, "disabling %s\n", power_well->desc->name);
+ drm_dbg_kms(&dev_priv->drm, "disabling %s\n",
+ i915_power_well_instance(power_well)->name);
power_well->hw_enabled = false;
power_well->desc->ops->disable(dev_priv, power_well);
}
@@ -112,7 +120,7 @@ static void intel_power_well_put(struct drm_i915_private *dev_priv,
{
drm_WARN(&dev_priv->drm, !power_well->count,
"Use count on power well %s is already zero",
- power_well->desc->name);
+ i915_power_well_instance(power_well)->name);
if (!--power_well->count)
intel_power_well_disable(dev_priv, power_well);
@@ -217,7 +225,7 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well)
{
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
ICL_AUX_PW_TO_CH(pw_idx);
@@ -264,7 +272,7 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
bool timeout_expected)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
/*
* For some power wells we're not supposed to watch the status bit for
@@ -280,7 +288,7 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
if (intel_de_wait_for_set(dev_priv, regs->driver,
HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) {
drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n",
- power_well->desc->name);
+ i915_power_well_instance(power_well)->name);
drm_WARN_ON(&dev_priv->drm, !timeout_expected);
@@ -307,7 +315,7 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
bool disabled;
u32 reqs;
@@ -328,7 +336,7 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
drm_dbg_kms(&dev_priv->drm,
"%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
- power_well->desc->name,
+ i915_power_well_instance(power_well)->name,
!!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
}
@@ -345,7 +353,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
u32 val;
if (power_well->desc->has_fuses) {
@@ -392,7 +400,7 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
u32 val;
hsw_power_well_pre_disable(dev_priv,
@@ -409,7 +417,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
u32 val;
@@ -441,7 +449,7 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
u32 val;
@@ -550,7 +558,7 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
val = intel_de_read(dev_priv, regs->driver);
intel_de_write(dev_priv, regs->driver,
- val | HSW_PWR_WELL_CTL_REQ(power_well->desc->hsw.idx));
+ val | HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx));
/*
* An AUX timeout is expected if the TBT DP tunnel is down,
@@ -566,7 +574,7 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) {
enum tc_port tc_port;
- tc_port = TGL_AUX_PW_TO_TC_PORT(power_well->desc->hsw.idx);
+ tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx);
intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
HIP_INDEX_VAL(tc_port, 0x2));
@@ -628,8 +636,8 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- enum i915_power_well_id id = power_well->desc->id;
- int pw_idx = power_well->desc->hsw.idx;
+ enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
HSW_PWR_WELL_CTL_STATE(pw_idx);
u32 val;
@@ -909,7 +917,7 @@ lookup_power_well(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well;
for_each_power_well(dev_priv, power_well)
- if (power_well->desc->id == power_well_id)
+ if (i915_power_well_instance(power_well)->id == power_well_id)
return power_well;
/*
@@ -1038,7 +1046,7 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
u32 bios_req = intel_de_read(dev_priv, regs->bios);
@@ -1055,19 +1063,19 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy);
+ bxt_ddi_phy_init(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
}
static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy);
+ bxt_ddi_phy_uninit(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
}
static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc->bxt.phy);
+ return bxt_ddi_phy_is_enabled(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
}
static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
@@ -1076,18 +1084,18 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
if (power_well->count > 0)
- bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
+ bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
if (power_well->count > 0)
- bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
+ bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
if (IS_GEMINILAKE(dev_priv)) {
power_well = lookup_power_well(dev_priv,
GLK_DISP_PW_DPIO_CMN_C);
if (power_well->count > 0)
bxt_ddi_phy_verify_state(dev_priv,
- power_well->desc->bxt.phy);
+ i915_power_well_instance(power_well)->bxt.phy);
}
}
@@ -1220,7 +1228,7 @@ static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
static void vlv_set_power_well(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well, bool enable)
{
- int pw_idx = power_well->desc->vlv.idx;
+ int pw_idx = i915_power_well_instance(power_well)->vlv.idx;
u32 mask;
u32 state;
u32 ctrl;
@@ -1269,7 +1277,7 @@ static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- int pw_idx = power_well->desc->vlv.idx;
+ int pw_idx = i915_power_well_instance(power_well)->vlv.idx;
bool enabled = false;
u32 mask;
u32 state;
@@ -1561,15 +1569,16 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
+ enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
enum dpio_phy phy;
enum pipe pipe;
u32 tmp;
drm_WARN_ON_ONCE(&dev_priv->drm,
- power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
- power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
+ id != VLV_DISP_PW_DPIO_CMN_BC &&
+ id != CHV_DISP_PW_DPIO_CMN_D);
- if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
+ if (id == VLV_DISP_PW_DPIO_CMN_BC) {
pipe = PIPE_A;
phy = DPIO_PHY0;
} else {
@@ -1595,7 +1604,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
- if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
+ if (id == VLV_DISP_PW_DPIO_CMN_BC) {
tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
tmp |= DPIO_DYNPWRDOWNEN_CH1;
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
@@ -1626,13 +1635,14 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
+ enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
enum dpio_phy phy;
drm_WARN_ON_ONCE(&dev_priv->drm,
- power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
- power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
+ id != VLV_DISP_PW_DPIO_CMN_BC &&
+ id != CHV_DISP_PW_DPIO_CMN_D);
- if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
+ if (id == VLV_DISP_PW_DPIO_CMN_BC) {
phy = DPIO_PHY0;
assert_pll_disabled(dev_priv, PIPE_A);
assert_pll_disabled(dev_priv, PIPE_B);
@@ -3826,7 +3836,8 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
enum intel_display_power_domain domain;
drm_dbg(&i915->drm, "%-25s %d\n",
- power_well->desc->name, power_well->count);
+ i915_power_well_instance(power_well)->name,
+ power_well->count);
for_each_power_domain(domain, &power_well->domains)
drm_dbg(&i915->drm, " %-23s %d\n",
@@ -3866,7 +3877,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
enabled)
drm_err(&i915->drm,
"power well %s state mismatch (refcount %d/enabled %d)",
- power_well->desc->name,
+ i915_power_well_instance(power_well)->name,
power_well->count, enabled);
domains_count = 0;
@@ -3877,7 +3888,8 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
drm_err(&i915->drm,
"power well %s refcount/domain refcount mismatch "
"(refcount %d/domains refcount %d)\n",
- power_well->desc->name, power_well->count,
+ i915_power_well_instance(power_well)->name,
+ power_well->count,
domains_count);
dump_domain_info = true;
}
@@ -3982,7 +3994,8 @@ void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m
enum intel_display_power_domain power_domain;
power_well = &power_domains->power_wells[i];
- seq_printf(m, "%-25s %d\n", power_well->desc->name,
+ seq_printf(m, "%-25s %d\n",
+ i915_power_well_instance(power_well)->name,
power_well->count);
for_each_power_domain(power_domain, &power_well->domains)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index c7155801f9bc6..04486b922878c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -141,7 +141,7 @@ enum intel_display_power_domain {
* wells must be assigned DISP_PW_ID_NONE.
*/
enum i915_power_well_id {
- DISP_PW_ID_NONE,
+ DISP_PW_ID_NONE = 0, /* must be kept zero */
VLV_DISP_PW_DISP2D,
BXT_DISP_PW_DPIO_CMN_A,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
index c4167ac2f21f8..251fd0b47412f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_internal.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
@@ -13,31 +13,12 @@
struct i915_power_well_regs;
-/* Power well structure for haswell */
-struct i915_power_well_desc {
+struct i915_power_well_instance {
const char *name;
const struct i915_power_domain_list {
const enum intel_display_power_domain *list;
u8 count;
} *domain_list;
- /* Mask of pipes whose IRQ logic is backed by the pw */
- u16 irq_pipe_mask:4;
- u16 always_on:1;
- /*
- * Instead of waiting for the status bit to ack enables,
- * just wait a specific amount of time and then consider
- * the well enabled.
- */
- u16 fixed_enable_delay:1;
- /* The pw is backing the VGA functionality */
- u16 has_vga:1;
- u16 has_fuses:1;
- /*
- * The pw is for an ICL+ TypeC PHY port in
- * Thunderbolt mode.
- */
- u16 is_tc_tbt:1;
-
/* unique identifier for this power well */
enum i915_power_well_id id;
/*
@@ -63,7 +44,32 @@ struct i915_power_well_desc {
u8 idx;
} hsw;
};
+};
+
+struct i915_power_well_desc {
const struct i915_power_well_ops *ops;
+ const struct i915_power_well_instance_list {
+ const struct i915_power_well_instance *list;
+ u8 count;
+ } *instances;
+
+ /* Mask of pipes whose IRQ logic is backed by the pw */
+ u16 irq_pipe_mask:4;
+ u16 always_on:1;
+ /*
+ * Instead of waiting for the status bit to ack enables,
+ * just wait a specific amount of time and then consider
+ * the well enabled.
+ */
+ u16 fixed_enable_delay:1;
+ /* The pw is backing the VGA functionality */
+ u16 has_vga:1;
+ u16 has_fuses:1;
+ /*
+ * The pw is for an ICL+ TypeC PHY port in
+ * Thunderbolt mode.
+ */
+ u16 is_tc_tbt:1;
};
struct i915_power_well {
@@ -73,6 +79,8 @@ struct i915_power_well {
int count;
/* cached hw enabled state */
bool hw_enabled;
+ /* index into desc->instances->list */
+ u8 instance_idx;
};
/* intel_display_power.c */
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 7ec4cafec6ba5..0061646763089 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -29,6 +29,14 @@
#define I915_PW_DOMAINS_NONE NULL
#define I915_PW_DOMAINS_ALL /* zero-length list */
+#define I915_PW_INSTANCES(...) \
+ (const struct i915_power_well_instance_list) \
+ __LIST(__LIST_INLINE_ELEMS(struct i915_power_well_instance, __VA_ARGS__))
+
+#define I915_PW(_name, _domain_list, ...) \
+ { .name = _name, .domain_list = _domain_list, ## __VA_ARGS__ }
+
+
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain)
{
@@ -171,11 +179,11 @@ I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
},
};
@@ -190,16 +198,16 @@ I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
static const struct i915_power_well_desc i830_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "pipes",
- .domain_list = &i830_pwdoms_pipes,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("pipes", &i830_pwdoms_pipes),
+ ),
.ops = &i830_pipes_power_well_ops,
- .id = DISP_PW_ID_NONE,
},
};
@@ -223,20 +231,19 @@ I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
static const struct i915_power_well_desc hsw_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "display",
- .domain_list = &hsw_pwdoms_display,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("display", &hsw_pwdoms_display,
+ .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
+ .id = HSW_DISP_PW_GLOBAL),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
- .id = HSW_DISP_PW_GLOBAL,
- {
- .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
- },
},
};
@@ -259,21 +266,20 @@ I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
static const struct i915_power_well_desc bdw_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "display",
- .domain_list = &bdw_pwdoms_display,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("display", &bdw_pwdoms_display,
+ .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
+ .id = HSW_DISP_PW_GLOBAL),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .id = HSW_DISP_PW_GLOBAL,
- {
- .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
- },
},
};
@@ -314,59 +320,37 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
static const struct i915_power_well_desc vlv_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "display",
- .domain_list = &vlv_pwdoms_display,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("display", &vlv_pwdoms_display,
+ .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
+ .id = VLV_DISP_PW_DISP2D),
+ ),
.ops = &vlv_display_power_well_ops,
- .id = VLV_DISP_PW_DISP2D,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
- },
}, {
- .name = "dpio-tx-b-01",
- .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("dpio-tx-b-01", &vlv_pwdoms_dpio_tx_bc_lanes,
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01),
+ I915_PW("dpio-tx-b-23", &vlv_pwdoms_dpio_tx_bc_lanes,
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23),
+ I915_PW("dpio-tx-c-01", &vlv_pwdoms_dpio_tx_bc_lanes,
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01),
+ I915_PW("dpio-tx-c-23", &vlv_pwdoms_dpio_tx_bc_lanes,
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23),
+ ),
.ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
- },
}, {
- .name = "dpio-tx-b-23",
- .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
- .ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
- },
- }, {
- .name = "dpio-tx-c-01",
- .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
- .ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
- },
- }, {
- .name = "dpio-tx-c-23",
- .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
- .ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
- },
- }, {
- .name = "dpio-common",
- .domain_list = &vlv_pwdoms_dpio_cmn_bc,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("dpio-common", &vlv_pwdoms_dpio_cmn_bc,
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
+ .id = VLV_DISP_PW_DPIO_CMN_BC),
+ ),
.ops = &vlv_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
- },
},
};
@@ -408,37 +392,31 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
static const struct i915_power_well_desc chv_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "display",
/*
* Pipe A power well is the new disp2d well. Pipe B and C
* power wells don't actually exist. Pipe A power well is
* required for any pipe to work.
*/
- .domain_list = &chv_pwdoms_display,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("display", &chv_pwdoms_display),
+ ),
.ops = &chv_pipe_power_well_ops,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "dpio-common-bc",
- .domain_list = &chv_pwdoms_dpio_cmn_bc,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("dpio-common-bc", &chv_pwdoms_dpio_cmn_bc,
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
+ .id = VLV_DISP_PW_DPIO_CMN_BC),
+ I915_PW("dpio-common-d", &chv_pwdoms_dpio_cmn_d,
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
+ .id = CHV_DISP_PW_DPIO_CMN_D),
+ ),
.ops = &chv_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
- },
- }, {
- .name = "dpio-common-d",
- .domain_list = &chv_pwdoms_dpio_cmn_d,
- .ops = &chv_dpio_cmn_power_well_ops,
- .id = CHV_DISP_PW_DPIO_CMN_D,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
- },
},
};
@@ -491,80 +469,54 @@ I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d,
static const struct i915_power_well_desc skl_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "MISC_IO",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("MISC_IO", I915_PW_DOMAINS_NONE,
+ .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
+ .id = SKL_DISP_PW_MISC_IO),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
- .id = SKL_DISP_PW_MISC_IO,
- {
- .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
- },
}, {
- .name = "DC_off",
- .domain_list = &skl_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &skl_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_2",
- .domain_list = &skl_pwdoms_pw_2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_2", &skl_pwdoms_pw_2,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.has_fuses = true,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_2,
- },
}, {
- .name = "DDI_IO_A_E",
- .domain_list = &skl_pwdoms_ddi_io_a_e,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DDI_IO_A_E", &skl_pwdoms_ddi_io_a_e, .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E),
+ I915_PW("DDI_IO_B", &skl_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &skl_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C),
+ I915_PW("DDI_IO_D", &skl_pwdoms_ddi_io_d, .hsw.idx = SKL_PW_CTL_IDX_DDI_D),
+ ),
.ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
- },
- }, {
- .name = "DDI_IO_B",
- .domain_list = &skl_pwdoms_ddi_io_b,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
- },
- }, {
- .name = "DDI_IO_C",
- .domain_list = &skl_pwdoms_ddi_io_c,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
- },
- }, {
- .name = "DDI_IO_D",
- .domain_list = &skl_pwdoms_ddi_io_d,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
- },
},
};
@@ -610,54 +562,47 @@ I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
static const struct i915_power_well_desc bxt_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "DC_off",
- .domain_list = &bxt_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &bxt_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_2",
- .domain_list = &bxt_pwdoms_pw_2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_2", &bxt_pwdoms_pw_2,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.has_fuses = true,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_2,
- },
}, {
- .name = "dpio-common-a",
- .domain_list = &bxt_pwdoms_dpio_cmn_a,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("dpio-common-a", &bxt_pwdoms_dpio_cmn_a,
+ .bxt.phy = DPIO_PHY1,
+ .id = BXT_DISP_PW_DPIO_CMN_A),
+ I915_PW("dpio-common-bc", &bxt_pwdoms_dpio_cmn_bc,
+ .bxt.phy = DPIO_PHY0,
+ .id = VLV_DISP_PW_DPIO_CMN_BC),
+ ),
.ops = &bxt_dpio_cmn_power_well_ops,
- .id = BXT_DISP_PW_DPIO_CMN_A,
- {
- .bxt.phy = DPIO_PHY1,
- },
- }, {
- .name = "dpio-common-bc",
- .domain_list = &bxt_pwdoms_dpio_cmn_bc,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .bxt.phy = DPIO_PHY0,
- },
},
};
@@ -723,110 +668,60 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
static const struct i915_power_well_desc glk_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "DC_off",
- .domain_list = &glk_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &glk_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_2",
- .domain_list = &glk_pwdoms_pw_2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_2", &glk_pwdoms_pw_2,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.has_fuses = true,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_2,
- },
}, {
- .name = "dpio-common-a",
- .domain_list = &glk_pwdoms_dpio_cmn_a,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("dpio-common-a", &glk_pwdoms_dpio_cmn_a,
+ .bxt.phy = DPIO_PHY1,
+ .id = BXT_DISP_PW_DPIO_CMN_A),
+ I915_PW("dpio-common-b", &glk_pwdoms_dpio_cmn_b,
+ .bxt.phy = DPIO_PHY0,
+ .id = VLV_DISP_PW_DPIO_CMN_BC),
+ I915_PW("dpio-common-c", &glk_pwdoms_dpio_cmn_c,
+ .bxt.phy = DPIO_PHY2,
+ .id = GLK_DISP_PW_DPIO_CMN_C),
+ ),
.ops = &bxt_dpio_cmn_power_well_ops,
- .id = BXT_DISP_PW_DPIO_CMN_A,
- {
- .bxt.phy = DPIO_PHY1,
- },
}, {
- .name = "dpio-common-b",
- .domain_list = &glk_pwdoms_dpio_cmn_b,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .bxt.phy = DPIO_PHY0,
- },
- }, {
- .name = "dpio-common-c",
- .domain_list = &glk_pwdoms_dpio_cmn_c,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = GLK_DISP_PW_DPIO_CMN_C,
- {
- .bxt.phy = DPIO_PHY2,
- },
- }, {
- .name = "AUX_A",
- .domain_list = &glk_pwdoms_aux_a,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
- },
- }, {
- .name = "AUX_B",
- .domain_list = &glk_pwdoms_aux_b,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
- },
- }, {
- .name = "AUX_C",
- .domain_list = &glk_pwdoms_aux_c,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
- },
- }, {
- .name = "DDI_IO_A",
- .domain_list = &glk_pwdoms_ddi_io_a,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
- },
- }, {
- .name = "DDI_IO_B",
- .domain_list = &glk_pwdoms_ddi_io_b,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
- },
- }, {
- .name = "DDI_IO_C",
- .domain_list = &glk_pwdoms_ddi_io_c,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_A", &glk_pwdoms_aux_a, .hsw.idx = GLK_PW_CTL_IDX_AUX_A),
+ I915_PW("AUX_B", &glk_pwdoms_aux_b, .hsw.idx = GLK_PW_CTL_IDX_AUX_B),
+ I915_PW("AUX_C", &glk_pwdoms_aux_c, .hsw.idx = GLK_PW_CTL_IDX_AUX_C),
+ I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = GLK_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C),
+ ),
.ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
- },
},
};
@@ -926,193 +821,82 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT_F);
static const struct i915_power_well_desc icl_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "DC_off",
- .domain_list = &icl_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &icl_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_2",
- .domain_list = &icl_pwdoms_pw_2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_2", &icl_pwdoms_pw_2,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- },
}, {
- .name = "PW_3",
- .domain_list = &icl_pwdoms_pw_3,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_3", &icl_pwdoms_pw_3,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .id = ICL_DISP_PW_3),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B),
.has_fuses = true,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- },
}, {
- .name = "DDI_IO_A",
- .domain_list = &icl_pwdoms_ddi_io_a,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &icl_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
+ I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = ICL_PW_CTL_IDX_DDI_D),
+ I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = ICL_PW_CTL_IDX_DDI_E),
+ I915_PW("DDI_IO_F", &icl_pwdoms_ddi_io_f, .hsw.idx = ICL_PW_CTL_IDX_DDI_F),
+ ),
.ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- },
}, {
- .name = "DDI_IO_B",
- .domain_list = &icl_pwdoms_ddi_io_b,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- },
- }, {
- .name = "DDI_IO_C",
- .domain_list = &icl_pwdoms_ddi_io_c,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
- },
- }, {
- .name = "DDI_IO_D",
- .domain_list = &icl_pwdoms_ddi_io_d,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
- },
- }, {
- .name = "DDI_IO_E",
- .domain_list = &icl_pwdoms_ddi_io_e,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
- },
- }, {
- .name = "DDI_IO_F",
- .domain_list = &icl_pwdoms_ddi_io_f,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
- },
- }, {
- .name = "AUX_A",
- .domain_list = &icl_pwdoms_aux_a,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- }, {
- .name = "AUX_B",
- .domain_list = &icl_pwdoms_aux_b,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
+ I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
+ I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
+ I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = ICL_PW_CTL_IDX_AUX_D),
+ I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = ICL_PW_CTL_IDX_AUX_E),
+ I915_PW("AUX_F", &icl_pwdoms_aux_f, .hsw.idx = ICL_PW_CTL_IDX_AUX_F),
+ ),
.ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- }, {
- .name = "AUX_C",
- .domain_list = &icl_pwdoms_aux_c,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- },
- }, {
- .name = "AUX_D",
- .domain_list = &icl_pwdoms_aux_d,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
- },
- }, {
- .name = "AUX_E",
- .domain_list = &icl_pwdoms_aux_e,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
- },
- }, {
- .name = "AUX_F",
- .domain_list = &icl_pwdoms_aux_f,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
- },
- }, {
- .name = "AUX_TBT1",
- .domain_list = &icl_pwdoms_aux_tbt1,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
- },
- }, {
- .name = "AUX_TBT2",
- .domain_list = &icl_pwdoms_aux_tbt2,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
- },
- }, {
- .name = "AUX_TBT3",
- .domain_list = &icl_pwdoms_aux_tbt3,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
- },
}, {
- .name = "AUX_TBT4",
- .domain_list = &icl_pwdoms_aux_tbt4,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1),
+ I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2),
+ I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3),
+ I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4),
+ ),
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
- },
}, {
- .name = "PW_4",
- .domain_list = &icl_pwdoms_pw_4,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_4", &icl_pwdoms_pw_4,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4),
+ ),
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_C),
.has_fuses = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- },
},
};
@@ -1223,276 +1007,104 @@ I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off,
static const struct i915_power_well_desc tgl_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "DC_off",
- .domain_list = &tgl_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &tgl_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_2",
- .domain_list = &tgl_pwdoms_pw_2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_2", &tgl_pwdoms_pw_2,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- },
}, {
- .name = "PW_3",
- .domain_list = &tgl_pwdoms_pw_3,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_3", &tgl_pwdoms_pw_3,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .id = ICL_DISP_PW_3),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B),
.has_fuses = true,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- },
}, {
- .name = "DDI_IO_A",
- .domain_list = &icl_pwdoms_ddi_io_a,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
- }, {
- .name = "DDI_IO_B",
- .domain_list = &icl_pwdoms_ddi_io_b,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- }, {
- .name = "DDI_IO_C",
- .domain_list = &icl_pwdoms_ddi_io_c,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
- }
- }, {
- .name = "DDI_IO_TC1",
- .domain_list = &tgl_pwdoms_ddi_io_tc1,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- },
- }, {
- .name = "DDI_IO_TC2",
- .domain_list = &tgl_pwdoms_ddi_io_tc2,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- },
- }, {
- .name = "DDI_IO_TC3",
- .domain_list = &tgl_pwdoms_ddi_io_tc3,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
- },
- }, {
- .name = "DDI_IO_TC4",
- .domain_list = &tgl_pwdoms_ddi_io_tc4,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
- },
- }, {
- .name = "DDI_IO_TC5",
- .domain_list = &tgl_pwdoms_ddi_io_tc5,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
- },
- }, {
- .name = "DDI_IO_TC6",
- .domain_list = &tgl_pwdoms_ddi_io_tc6,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
- },
- }, {
- .name = "TC_cold_off",
- .domain_list = &tgl_pwdoms_tc_cold_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &icl_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
+ I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
+ I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
+ I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
+ I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4),
+ I915_PW("DDI_IO_TC5", &tgl_pwdoms_ddi_io_tc5, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5),
+ I915_PW("DDI_IO_TC6", &tgl_pwdoms_ddi_io_tc6, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6),
+ ),
+ .ops = &icl_ddi_power_well_ops,
+ }, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("TC_cold_off", &tgl_pwdoms_tc_cold_off,
+ .id = TGL_DISP_PW_TC_COLD_OFF),
+ ),
.ops = &tgl_tc_cold_off_ops,
- .id = TGL_DISP_PW_TC_COLD_OFF,
}, {
- .name = "AUX_A",
- .domain_list = &tgl_pwdoms_aux_a,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- }, {
- .name = "AUX_B",
- .domain_list = &tgl_pwdoms_aux_b,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- }, {
- .name = "AUX_C",
- .domain_list = &tgl_pwdoms_aux_c,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- },
- }, {
- .name = "AUX_USBC1",
- .domain_list = &tgl_pwdoms_aux_usbc1,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- },
- }, {
- .name = "AUX_USBC2",
- .domain_list = &tgl_pwdoms_aux_usbc2,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- },
- }, {
- .name = "AUX_USBC3",
- .domain_list = &tgl_pwdoms_aux_usbc3,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
- },
- }, {
- .name = "AUX_USBC4",
- .domain_list = &tgl_pwdoms_aux_usbc4,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
- },
- }, {
- .name = "AUX_USBC5",
- .domain_list = &tgl_pwdoms_aux_usbc5,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
- },
- }, {
- .name = "AUX_USBC6",
- .domain_list = &tgl_pwdoms_aux_usbc6,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
- },
- }, {
- .name = "AUX_TBT1",
- .domain_list = &tgl_pwdoms_aux_tbt1,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
- },
- }, {
- .name = "AUX_TBT2",
- .domain_list = &tgl_pwdoms_aux_tbt2,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
- },
- }, {
- .name = "AUX_TBT3",
- .domain_list = &tgl_pwdoms_aux_tbt3,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
- },
- }, {
- .name = "AUX_TBT4",
- .domain_list = &tgl_pwdoms_aux_tbt4,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
- },
- }, {
- .name = "AUX_TBT5",
- .domain_list = &tgl_pwdoms_aux_tbt5,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
- },
- }, {
- .name = "AUX_TBT6",
- .domain_list = &tgl_pwdoms_aux_tbt6,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_A", &tgl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
+ I915_PW("AUX_B", &tgl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
+ I915_PW("AUX_C", &tgl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
+ I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
+ I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
+ I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
+ I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4),
+ I915_PW("AUX_USBC5", &tgl_pwdoms_aux_usbc5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5),
+ I915_PW("AUX_USBC6", &tgl_pwdoms_aux_usbc6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6),
+ ),
+ .ops = &icl_aux_power_well_ops,
+ }, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_TBT1", &tgl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
+ I915_PW("AUX_TBT2", &tgl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
+ I915_PW("AUX_TBT3", &tgl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
+ I915_PW("AUX_TBT4", &tgl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
+ I915_PW("AUX_TBT5", &tgl_pwdoms_aux_tbt5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5),
+ I915_PW("AUX_TBT6", &tgl_pwdoms_aux_tbt6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6),
+ ),
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
- },
}, {
- .name = "PW_4",
- .domain_list = &tgl_pwdoms_pw_4,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_4", &tgl_pwdoms_pw_4,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- }
}, {
- .name = "PW_5",
- .domain_list = &tgl_pwdoms_pw_5,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_5", &tgl_pwdoms_pw_5,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_D),
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_PW_5,
- },
},
};
@@ -1552,112 +1164,61 @@ I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
static const struct i915_power_well_desc rkl_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "DC_off",
- .domain_list = &rkl_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &rkl_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_3",
- .domain_list = &rkl_pwdoms_pw_3,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_3", &rkl_pwdoms_pw_3,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .id = ICL_DISP_PW_3),
+ ),
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
.has_vga = true,
.has_fuses = true,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- },
}, {
- .name = "PW_4",
- .domain_list = &rkl_pwdoms_pw_4,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_4", &rkl_pwdoms_pw_4,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- }
}, {
- .name = "DDI_IO_A",
- .domain_list = &icl_pwdoms_ddi_io_a,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
+ I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
+ ),
.ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
}, {
- .name = "DDI_IO_B",
- .domain_list = &icl_pwdoms_ddi_io_b,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- }, {
- .name = "DDI_IO_TC1",
- .domain_list = &tgl_pwdoms_ddi_io_tc1,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- },
- }, {
- .name = "DDI_IO_TC2",
- .domain_list = &tgl_pwdoms_ddi_io_tc2,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- },
- }, {
- .name = "AUX_A",
- .domain_list = &icl_pwdoms_aux_a,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- }, {
- .name = "AUX_B",
- .domain_list = &icl_pwdoms_aux_b,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- }, {
- .name = "AUX_USBC1",
- .domain_list = &tgl_pwdoms_aux_usbc1,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- },
- }, {
- .name = "AUX_USBC2",
- .domain_list = &tgl_pwdoms_aux_usbc2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
+ I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
+ I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
+ I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
+ ),
.ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- },
},
};
@@ -1695,133 +1256,77 @@ I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
static const struct i915_power_well_desc dg1_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "DC_off",
- .domain_list = &dg1_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &dg1_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_2",
- .domain_list = &dg1_pwdoms_pw_2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_2", &dg1_pwdoms_pw_2,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- },
}, {
- .name = "PW_3",
- .domain_list = &dg1_pwdoms_pw_3,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_3", &dg1_pwdoms_pw_3,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .id = ICL_DISP_PW_3),
+ ),
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
.has_vga = true,
.has_fuses = true,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- },
}, {
- .name = "DDI_IO_A",
- .domain_list = &icl_pwdoms_ddi_io_a,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
+ I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
+ ),
.ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
}, {
- .name = "DDI_IO_B",
- .domain_list = &icl_pwdoms_ddi_io_b,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- }, {
- .name = "DDI_IO_TC1",
- .domain_list = &tgl_pwdoms_ddi_io_tc1,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- },
- }, {
- .name = "DDI_IO_TC2",
- .domain_list = &tgl_pwdoms_ddi_io_tc2,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- },
- }, {
- .name = "AUX_A",
- .domain_list = &tgl_pwdoms_aux_a,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- }, {
- .name = "AUX_B",
- .domain_list = &tgl_pwdoms_aux_b,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- }, {
- .name = "AUX_USBC1",
- .domain_list = &tgl_pwdoms_aux_usbc1,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- },
- }, {
- .name = "AUX_USBC2",
- .domain_list = &tgl_pwdoms_aux_usbc2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_A", &tgl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
+ I915_PW("AUX_B", &tgl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
+ I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
+ I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
+ ),
.ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- },
}, {
- .name = "PW_4",
- .domain_list = &tgl_pwdoms_pw_4,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_4", &tgl_pwdoms_pw_4,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- }
}, {
- .name = "PW_5",
- .domain_list = &tgl_pwdoms_pw_5,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_5", &tgl_pwdoms_pw_5,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_D),
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_PW_5,
- },
},
};
@@ -1952,283 +1457,131 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
static const struct i915_power_well_desc xelpd_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "DC_off",
- .domain_list = &xelpd_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &xelpd_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_2",
- .domain_list = &xelpd_pwdoms_pw_2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_2", &xelpd_pwdoms_pw_2,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
.has_fuses = true,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- },
}, {
- .name = "PW_A",
- .domain_list = &xelpd_pwdoms_pw_a,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_A", &xelpd_pwdoms_pw_a,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_A),
+ ),
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_A),
.has_fuses = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_A,
- },
}, {
- .name = "PW_B",
- .domain_list = &xelpd_pwdoms_pw_b,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_B", &xelpd_pwdoms_pw_b,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_B),
+ ),
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
.has_fuses = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_B,
- },
}, {
- .name = "PW_C",
- .domain_list = &xelpd_pwdoms_pw_c,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_C", &xelpd_pwdoms_pw_c,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_C),
+ ),
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_C),
.has_fuses = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_C,
- },
}, {
- .name = "PW_D",
- .domain_list = &xelpd_pwdoms_pw_d,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_D", &xelpd_pwdoms_pw_d,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_D),
+ ),
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_D),
.has_fuses = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_D,
- },
}, {
- .name = "DDI_IO_A",
- .domain_list = &icl_pwdoms_ddi_io_a,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
- }, {
- .name = "DDI_IO_B",
- .domain_list = &icl_pwdoms_ddi_io_b,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- }, {
- .name = "DDI_IO_C",
- .domain_list = &icl_pwdoms_ddi_io_c,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
- }
- }, {
- .name = "DDI_IO_D_XELPD",
- .domain_list = &xelpd_pwdoms_ddi_io_d_xelpd,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_DDI_D,
- }
- }, {
- .name = "DDI_IO_E_XELPD",
- .domain_list = &xelpd_pwdoms_ddi_io_e_xelpd,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_DDI_E,
- }
- }, {
- .name = "DDI_IO_TC1",
- .domain_list = &xelpd_pwdoms_ddi_io_tc1,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- }
- }, {
- .name = "DDI_IO_TC2",
- .domain_list = &xelpd_pwdoms_ddi_io_tc2,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- }
- }, {
- .name = "DDI_IO_TC3",
- .domain_list = &xelpd_pwdoms_ddi_io_tc3,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
- }
- }, {
- .name = "DDI_IO_TC4",
- .domain_list = &xelpd_pwdoms_ddi_io_tc4,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
- }
- }, {
- .name = "AUX_A",
- .domain_list = &icl_pwdoms_aux_a,
- .ops = &icl_aux_power_well_ops,
- .fixed_enable_delay = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- }, {
- .name = "AUX_B",
- .domain_list = &icl_pwdoms_aux_b,
- .ops = &icl_aux_power_well_ops,
- .fixed_enable_delay = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- }, {
- .name = "AUX_C",
- .domain_list = &tgl_pwdoms_aux_c,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &icl_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
+ I915_PW("DDI_IO_D_XELPD", &xelpd_pwdoms_ddi_io_d_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_DDI_D),
+ I915_PW("DDI_IO_E_XELPD", &xelpd_pwdoms_ddi_io_e_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_DDI_E),
+ I915_PW("DDI_IO_TC1", &xelpd_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
+ I915_PW("DDI_IO_TC2", &xelpd_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
+ I915_PW("DDI_IO_TC3", &xelpd_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
+ I915_PW("DDI_IO_TC4", &xelpd_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4),
+ ),
+ .ops = &icl_ddi_power_well_ops,
+ }, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
+ I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
+ I915_PW("AUX_C", &tgl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
+ I915_PW("AUX_D_XELPD", &xelpd_pwdoms_aux_d_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D),
+ I915_PW("AUX_E_XELPD", &xelpd_pwdoms_aux_e_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E),
+ I915_PW("AUX_USBC1", &xelpd_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
+ I915_PW("AUX_USBC2", &xelpd_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
+ I915_PW("AUX_USBC3", &xelpd_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
+ I915_PW("AUX_USBC4", &xelpd_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4),
+ ),
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- },
- }, {
- .name = "AUX_D_XELPD",
- .domain_list = &xelpd_pwdoms_aux_d_xelpd,
- .ops = &icl_aux_power_well_ops,
- .fixed_enable_delay = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
- },
- }, {
- .name = "AUX_E_XELPD",
- .domain_list = &xelpd_pwdoms_aux_e_xelpd,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_AUX_E,
- },
- }, {
- .name = "AUX_USBC1",
- .domain_list = &xelpd_pwdoms_aux_usbc1,
- .ops = &icl_aux_power_well_ops,
- .fixed_enable_delay = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- },
- }, {
- .name = "AUX_USBC2",
- .domain_list = &xelpd_pwdoms_aux_usbc2,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- },
- }, {
- .name = "AUX_USBC3",
- .domain_list = &xelpd_pwdoms_aux_usbc3,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
- },
- }, {
- .name = "AUX_USBC4",
- .domain_list = &xelpd_pwdoms_aux_usbc4,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
- },
- }, {
- .name = "AUX_TBT1",
- .domain_list = &xelpd_pwdoms_aux_tbt1,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
- },
- }, {
- .name = "AUX_TBT2",
- .domain_list = &xelpd_pwdoms_aux_tbt2,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
- },
- }, {
- .name = "AUX_TBT3",
- .domain_list = &xelpd_pwdoms_aux_tbt3,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
- },
}, {
- .name = "AUX_TBT4",
- .domain_list = &xelpd_pwdoms_aux_tbt4,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_TBT1", &xelpd_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
+ I915_PW("AUX_TBT2", &xelpd_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
+ I915_PW("AUX_TBT3", &xelpd_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
+ I915_PW("AUX_TBT4", &xelpd_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
+ ),
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
- },
},
};
-static void init_power_well_domains(const struct i915_power_well_desc *desc,
+static void init_power_well_domains(const struct i915_power_well_instance *inst,
struct i915_power_well *power_well)
{
int j;
- if (!desc->domain_list)
+ if (!inst->domain_list)
return;
- if (desc->domain_list->count == 0) {
+ if (inst->domain_list->count == 0) {
bitmap_fill(power_well->domains.bits, POWER_DOMAIN_NUM);
return;
}
- for (j = 0; j < desc->domain_list->count; j++)
- set_bit(desc->domain_list->list[j], power_well->domains.bits);
+ for (j = 0; j < inst->domain_list->count; j++)
+ set_bit(inst->domain_list->list[j], power_well->domains.bits);
}
+#define for_each_power_well_instance(_desc_list, _desc_count, _desc, _inst) \
+ for ((_desc) = (_desc_list); (_desc) - (_desc_list) < (_desc_count); (_desc)++) \
+ for ((_inst) = (_desc)->instances->list; \
+ (_inst) - (_desc)->instances->list < (_desc)->instances->count; \
+ (_inst)++)
+
static int
__set_power_wells(struct i915_power_domains *power_domains,
const struct i915_power_well_desc *power_well_descs,
@@ -2238,11 +1591,13 @@ __set_power_wells(struct i915_power_domains *power_domains,
struct drm_i915_private,
power_domains);
u64 power_well_ids = 0;
+ const struct i915_power_well_desc *desc;
+ const struct i915_power_well_instance *inst;
int power_well_count = 0;
- int i, plt_idx = 0;
+ int plt_idx = 0;
- for (i = 0; i < power_well_descs_sz; i++)
- if (!(BIT_ULL(power_well_descs[i].id) & skip_mask))
+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc, inst)
+ if (!(BIT_ULL(inst->id) & skip_mask))
power_well_count++;
power_domains->power_well_count = power_well_count;
@@ -2253,16 +1608,18 @@ __set_power_wells(struct i915_power_domains *power_domains,
if (!power_domains->power_wells)
return -ENOMEM;
- for (i = 0; i < power_well_descs_sz; i++) {
- enum i915_power_well_id id = power_well_descs[i].id;
+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc, inst) {
+ struct i915_power_well *pw = &power_domains->power_wells[plt_idx];
+ enum i915_power_well_id id = inst->id;
if (BIT_ULL(id) & skip_mask)
continue;
- power_domains->power_wells[plt_idx].desc =
- &power_well_descs[i];
+ pw->desc = desc;
+ drm_WARN_ON(&i915->drm, overflows_type(inst - desc->instances->list, pw->instance_idx));
+ pw->instance_idx = inst - desc->instances->list;
- init_power_well_domains(&power_well_descs[i], &power_domains->power_wells[plt_idx]);
+ init_power_well_domains(inst, pw);
plt_idx++;
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 12/19] drm/i915: Allow platforms to share power well descriptors
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (10 preceding siblings ...)
2022-01-28 11:49 ` [Intel-gfx] [PATCH 11/19] drm/i915: Simplify power well definitions by adding power well instances Imre Deak
@ 2022-01-28 11:49 ` Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 13/19] drm/i915: Simplify the DG1 " Imre Deak
` (9 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:49 UTC (permalink / raw)
To: intel-gfx
Some power wells - like always-on and skl+/icl+ PW_1 - with the same
name, domain list, flags, ops are used by multiple platforms, so allow
platforms to reuse the descriptors of such power wells.
This change also lets the follow up patches to simplify the DG1/RKL
power well definitions, and remove the ADL-S skip_mask special casing.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../i915/display/intel_display_power_map.c | 280 ++++++++----------
1 file changed, 121 insertions(+), 159 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 0061646763089..1ddac0e15605e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -37,6 +37,14 @@
{ .name = _name, .domain_list = _domain_list, ## __VA_ARGS__ }
+struct i915_power_well_desc_list {
+ const struct i915_power_well_desc *list;
+ u8 count;
+};
+
+#define I915_PW_DESCRIPTORS(x) __LIST(x)
+
+
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain)
{
@@ -177,7 +185,7 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
-static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
+static const struct i915_power_well_desc i9xx_power_wells_always_on[] = {
{
.instances = &I915_PW_INSTANCES(
I915_PW("always-on", &i9xx_pwdoms_always_on),
@@ -187,6 +195,10 @@ static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
},
};
+static const struct i915_power_well_desc_list i9xx_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+};
+
I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
POWER_DOMAIN_PIPE_A,
POWER_DOMAIN_PIPE_B,
@@ -196,14 +208,8 @@ I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc i830_power_wells[] = {
+static const struct i915_power_well_desc i830_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("pipes", &i830_pwdoms_pipes),
),
@@ -211,6 +217,11 @@ static const struct i915_power_well_desc i830_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list i830_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(i830_power_wells_main),
+};
+
I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
@@ -229,14 +240,8 @@ I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
POWER_DOMAIN_AUDIO_PLAYBACK,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc hsw_power_wells[] = {
+static const struct i915_power_well_desc hsw_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("display", &hsw_pwdoms_display,
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
@@ -247,6 +252,11 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list hsw_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(hsw_power_wells_main),
+};
+
I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
@@ -264,14 +274,8 @@ I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
POWER_DOMAIN_AUDIO_PLAYBACK,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc bdw_power_wells[] = {
+static const struct i915_power_well_desc bdw_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("display", &bdw_pwdoms_display,
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
@@ -283,6 +287,11 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list bdw_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(bdw_power_wells_main),
+};
+
I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
POWER_DOMAIN_DISPLAY_CORE,
POWER_DOMAIN_PIPE_A,
@@ -318,14 +327,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc vlv_power_wells[] = {
+static const struct i915_power_well_desc vlv_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("display", &vlv_pwdoms_display,
.vlv.idx = PUNIT_PWGT_IDX_DISP2D,
@@ -354,6 +357,11 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list vlv_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(vlv_power_wells_main),
+};
+
I915_DECL_PW_DOMAINS(chv_pwdoms_display,
POWER_DOMAIN_DISPLAY_CORE,
POWER_DOMAIN_PIPE_A,
@@ -390,14 +398,8 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
POWER_DOMAIN_AUX_D,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc chv_power_wells[] = {
+static const struct i915_power_well_desc chv_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
/*
* Pipe A power well is the new disp2d well. Pipe B and C
* power wells don't actually exist. Pipe A power well is
@@ -420,6 +422,11 @@ static const struct i915_power_well_desc chv_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list chv_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(chv_power_wells_main),
+};
+
#define SKL_PW_2_POWER_DOMAINS \
POWER_DOMAIN_PIPE_B, \
POWER_DOMAIN_PIPE_C, \
@@ -467,14 +474,8 @@ I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d,
POWER_DOMAIN_PORT_DDI_IO_D,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc skl_power_wells[] = {
+static const struct i915_power_well_desc skl_power_wells_pw_1[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
/* Handled by the DMC firmware */
.instances = &I915_PW_INSTANCES(
I915_PW("PW_1", I915_PW_DOMAINS_NONE,
@@ -484,7 +485,11 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- }, {
+ },
+};
+
+static const struct i915_power_well_desc skl_power_wells_main[] = {
+ {
/* Handled by the DMC firmware */
.instances = &I915_PW_INSTANCES(
I915_PW("MISC_IO", I915_PW_DOMAINS_NONE,
@@ -520,6 +525,12 @@ static const struct i915_power_well_desc skl_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list skl_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(skl_power_wells_main),
+};
+
#define BXT_PW_2_POWER_DOMAINS \
POWER_DOMAIN_PIPE_B, \
POWER_DOMAIN_PIPE_C, \
@@ -560,24 +571,8 @@ I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc bxt_power_wells[] = {
+static const struct i915_power_well_desc bxt_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &bxt_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -606,6 +601,12 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list bxt_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(bxt_power_wells_main),
+};
+
#define GLK_PW_2_POWER_DOMAINS \
POWER_DOMAIN_PIPE_B, \
POWER_DOMAIN_PIPE_C, \
@@ -666,24 +667,8 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc glk_power_wells[] = {
+static const struct i915_power_well_desc glk_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &glk_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -725,6 +710,12 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list glk_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(glk_power_wells_main),
+};
+
/*
* ICL PW_0/PG_0 domains (HW/DMC control):
* - PCI
@@ -819,14 +810,8 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT_D);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT_E);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT_F);
-static const struct i915_power_well_desc icl_power_wells[] = {
+static const struct i915_power_well_desc icl_power_wells_pw_1[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
/* Handled by the DMC firmware */
.instances = &I915_PW_INSTANCES(
I915_PW("PW_1", I915_PW_DOMAINS_NONE,
@@ -836,7 +821,11 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- }, {
+ },
+};
+
+static const struct i915_power_well_desc icl_power_wells_main[] = {
+ {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &icl_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -900,6 +889,12 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list icl_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(icl_power_wells_main),
+};
+
#define TGL_PW_5_POWER_DOMAINS \
POWER_DOMAIN_PIPE_D, \
POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
@@ -1005,24 +1000,8 @@ I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off,
POWER_DOMAIN_AUX_TBT6,
POWER_DOMAIN_TC_COLD_OFF);
-static const struct i915_power_well_desc tgl_power_wells[] = {
+static const struct i915_power_well_desc tgl_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &tgl_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -1108,6 +1087,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list tgl_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(tgl_power_wells_main),
+};
+
#define RKL_PW_4_POWER_DOMAINS \
POWER_DOMAIN_PIPE_C, \
POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
@@ -1162,24 +1147,8 @@ I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc rkl_power_wells[] = {
+static const struct i915_power_well_desc rkl_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &rkl_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -1222,6 +1191,12 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list rkl_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(rkl_power_wells_main),
+};
+
/*
* DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
*/
@@ -1254,24 +1229,8 @@ I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
POWER_DOMAIN_TRANSCODER_VDSC_PW2,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc dg1_power_wells[] = {
+static const struct i915_power_well_desc dg1_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &dg1_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -1330,6 +1289,12 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list dg1_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(dg1_power_wells_main),
+};
+
/*
* XE_LPD Power Domains
*
@@ -1455,24 +1420,8 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
-static const struct i915_power_well_desc xelpd_power_wells[] = {
+static const struct i915_power_well_desc xelpd_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &xelpd_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -1558,6 +1507,12 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list xelpd_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(xelpd_power_wells_main),
+};
+
static void init_power_well_domains(const struct i915_power_well_instance *inst,
struct i915_power_well *power_well)
{
@@ -1576,27 +1531,34 @@ static void init_power_well_domains(const struct i915_power_well_instance *inst,
set_bit(inst->domain_list->list[j], power_well->domains.bits);
}
-#define for_each_power_well_instance(_desc_list, _desc_count, _desc, _inst) \
+#define for_each_power_well_instance_in_desc_list(_desc_list, _desc_count, _desc, _inst) \
for ((_desc) = (_desc_list); (_desc) - (_desc_list) < (_desc_count); (_desc)++) \
for ((_inst) = (_desc)->instances->list; \
(_inst) - (_desc)->instances->list < (_desc)->instances->count; \
(_inst)++)
+#define for_each_power_well_instance(_desc_list, _desc_count, _descs, _desc, _inst) \
+ for ((_descs) = (_desc_list); \
+ (_descs) - (_desc_list) < (_desc_count); \
+ (_descs)++) \
+ for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, (_desc), (_inst))
+
static int
__set_power_wells(struct i915_power_domains *power_domains,
- const struct i915_power_well_desc *power_well_descs,
+ const struct i915_power_well_desc_list *power_well_descs,
int power_well_descs_sz, u64 skip_mask)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
power_domains);
u64 power_well_ids = 0;
+ const struct i915_power_well_desc_list *desc_list;
const struct i915_power_well_desc *desc;
const struct i915_power_well_instance *inst;
int power_well_count = 0;
int plt_idx = 0;
- for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc, inst)
+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst)
if (!(BIT_ULL(inst->id) & skip_mask))
power_well_count++;
@@ -1608,7 +1570,7 @@ __set_power_wells(struct i915_power_domains *power_domains,
if (!power_domains->power_wells)
return -ENOMEM;
- for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc, inst) {
+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) {
struct i915_power_well *pw = &power_domains->power_wells[plt_idx];
enum i915_power_well_id id = inst->id;
@@ -1685,7 +1647,7 @@ int intel_init_power_wells(struct i915_power_domains *power_domains)
else if (IS_I830(i915))
return set_power_wells(power_domains, i830_power_wells);
else
- return set_power_wells(power_domains, i9xx_always_on_power_well);
+ return set_power_wells(power_domains, i9xx_power_wells);
}
void intel_cleanup_power_wells(struct i915_power_domains *power_domains)
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 13/19] drm/i915: Simplify the DG1 power well descriptors
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (11 preceding siblings ...)
2022-01-28 11:49 ` [Intel-gfx] [PATCH 12/19] drm/i915: Allow platforms to share power well descriptors Imre Deak
@ 2022-01-28 11:49 ` Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 14/19] drm/i915: Sanitize the ADL-S power well definition Imre Deak
` (8 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:49 UTC (permalink / raw)
To: intel-gfx
Simplify the definition of DG1 power wells by reusing the identical
RKL DDI/AUX descriptors.
This reorders the DG1 DDI/AUX vs. PW4/5 power wells, but this shouldn't
make a difference (it is the order on RKL and the DDI/AUX power wells
don't have a dependency on PW4/5).
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../i915/display/intel_display_power_map.c | 24 ++++++-------------
1 file changed, 7 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 1ddac0e15605e..164eeed3ee75c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1172,7 +1172,11 @@ static const struct i915_power_well_desc rkl_power_wells_main[] = {
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
- }, {
+ },
+};
+
+static const struct i915_power_well_desc rkl_power_wells_ddi_aux[] = {
+ {
.instances = &I915_PW_INSTANCES(
I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
@@ -1195,6 +1199,7 @@ static const struct i915_power_well_desc_list rkl_power_wells[] = {
I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
I915_PW_DESCRIPTORS(rkl_power_wells_main),
+ I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux),
};
/*
@@ -1254,22 +1259,6 @@ static const struct i915_power_well_desc dg1_power_wells_main[] = {
.irq_pipe_mask = BIT(PIPE_B),
.has_vga = true,
.has_fuses = true,
- }, {
- .instances = &I915_PW_INSTANCES(
- I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
- I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
- I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
- I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
- ),
- .ops = &icl_ddi_power_well_ops,
- }, {
- .instances = &I915_PW_INSTANCES(
- I915_PW("AUX_A", &tgl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
- I915_PW("AUX_B", &tgl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
- I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
- I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
- ),
- .ops = &icl_aux_power_well_ops,
}, {
.instances = &I915_PW_INSTANCES(
I915_PW("PW_4", &tgl_pwdoms_pw_4,
@@ -1293,6 +1282,7 @@ static const struct i915_power_well_desc_list dg1_power_wells[] = {
I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
I915_PW_DESCRIPTORS(dg1_power_wells_main),
+ I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux),
};
/*
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 14/19] drm/i915: Sanitize the ADL-S power well definition
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (12 preceding siblings ...)
2022-01-28 11:49 ` [Intel-gfx] [PATCH 13/19] drm/i915: Simplify the DG1 " Imre Deak
@ 2022-01-28 11:49 ` Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 15/19] drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform Imre Deak
` (7 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:49 UTC (permalink / raw)
To: intel-gfx
Instead of the skip_mask special casing of the ADL-S power well
descriptors, add a power well descriptor list for ADL-S as well reusing
the TGL descriptors, w/o the TC-cold power well. ADL-S doesn't have
TypeC PHYs, so a better way would be having ADL-S specific AUX
descriptors, but I left changing this for a follow-up.
This changes the ordering of the the AUX and TC-cold vs. PW_4/5 power
wells on TGL and ADL-S, but this shouldn't make a difference (the
AUX/TC-cold power wells don't depend on PW_4/5).
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../i915/display/intel_display_power_map.c | 69 +++++++++++--------
1 file changed, 39 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 164eeed3ee75c..a72ebde959cde 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1039,12 +1039,36 @@ static const struct i915_power_well_desc tgl_power_wells_main[] = {
),
.ops = &icl_ddi_power_well_ops,
}, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_4", &tgl_pwdoms_pw_4,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4),
+ ),
+ .ops = &hsw_power_well_ops,
+ .has_fuses = true,
+ .irq_pipe_mask = BIT(PIPE_C),
+ }, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_5", &tgl_pwdoms_pw_5,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5),
+ ),
+ .ops = &hsw_power_well_ops,
+ .has_fuses = true,
+ .irq_pipe_mask = BIT(PIPE_D),
+ },
+};
+
+static const struct i915_power_well_desc tgl_power_wells_tc_cold_off[] = {
+ {
.instances = &I915_PW_INSTANCES(
I915_PW("TC_cold_off", &tgl_pwdoms_tc_cold_off,
.id = TGL_DISP_PW_TC_COLD_OFF),
),
.ops = &tgl_tc_cold_off_ops,
- }, {
+ },
+};
+
+static const struct i915_power_well_desc tgl_power_wells_aux[] = {
+ {
.instances = &I915_PW_INSTANCES(
I915_PW("AUX_A", &tgl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
I915_PW("AUX_B", &tgl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
@@ -1068,22 +1092,6 @@ static const struct i915_power_well_desc tgl_power_wells_main[] = {
),
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
- }, {
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_4", &tgl_pwdoms_pw_4,
- .hsw.idx = ICL_PW_CTL_IDX_PW_4),
- ),
- .ops = &hsw_power_well_ops,
- .has_fuses = true,
- .irq_pipe_mask = BIT(PIPE_C),
- }, {
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_5", &tgl_pwdoms_pw_5,
- .hsw.idx = TGL_PW_CTL_IDX_PW_5),
- ),
- .ops = &hsw_power_well_ops,
- .has_fuses = true,
- .irq_pipe_mask = BIT(PIPE_D),
},
};
@@ -1091,6 +1099,15 @@ static const struct i915_power_well_desc_list tgl_power_wells[] = {
I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
I915_PW_DESCRIPTORS(tgl_power_wells_main),
+ I915_PW_DESCRIPTORS(tgl_power_wells_tc_cold_off),
+ I915_PW_DESCRIPTORS(tgl_power_wells_aux),
+};
+
+static const struct i915_power_well_desc_list adls_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(tgl_power_wells_main),
+ I915_PW_DESCRIPTORS(tgl_power_wells_aux),
};
#define RKL_PW_4_POWER_DOMAINS \
@@ -1536,7 +1553,7 @@ static void init_power_well_domains(const struct i915_power_well_instance *inst,
static int
__set_power_wells(struct i915_power_domains *power_domains,
const struct i915_power_well_desc_list *power_well_descs,
- int power_well_descs_sz, u64 skip_mask)
+ int power_well_descs_sz)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
@@ -1549,8 +1566,7 @@ __set_power_wells(struct i915_power_domains *power_domains,
int plt_idx = 0;
for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst)
- if (!(BIT_ULL(inst->id) & skip_mask))
- power_well_count++;
+ power_well_count++;
power_domains->power_well_count = power_well_count;
power_domains->power_wells =
@@ -1564,9 +1580,6 @@ __set_power_wells(struct i915_power_domains *power_domains,
struct i915_power_well *pw = &power_domains->power_wells[plt_idx];
enum i915_power_well_id id = inst->id;
- if (BIT_ULL(id) & skip_mask)
- continue;
-
pw->desc = desc;
drm_WARN_ON(&i915->drm, overflows_type(inst - desc->instances->list, pw->instance_idx));
pw->instance_idx = inst - desc->instances->list;
@@ -1586,12 +1599,9 @@ __set_power_wells(struct i915_power_domains *power_domains,
return 0;
}
-#define set_power_wells_mask(power_domains, __power_well_descs, skip_mask) \
- __set_power_wells(power_domains, __power_well_descs, \
- ARRAY_SIZE(__power_well_descs), skip_mask)
-
#define set_power_wells(power_domains, __power_well_descs) \
- set_power_wells_mask(power_domains, __power_well_descs, 0)
+ __set_power_wells(power_domains, __power_well_descs, \
+ ARRAY_SIZE(__power_well_descs))
int intel_init_power_wells(struct i915_power_domains *power_domains)
{
@@ -1612,8 +1622,7 @@ int intel_init_power_wells(struct i915_power_domains *power_domains)
else if (IS_DG1(i915))
return set_power_wells(power_domains, dg1_power_wells);
else if (IS_ALDERLAKE_S(i915))
- return set_power_wells_mask(power_domains, tgl_power_wells,
- BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
+ return set_power_wells(power_domains, adls_power_wells);
else if (IS_ROCKETLAKE(i915))
return set_power_wells(power_domains, rkl_power_wells);
else if (DISPLAY_VER(i915) == 12)
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 15/19] drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (13 preceding siblings ...)
2022-01-28 11:49 ` [Intel-gfx] [PATCH 14/19] drm/i915: Sanitize the ADL-S power well definition Imre Deak
@ 2022-01-28 11:49 ` Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 16/19] drm/i915: Remove the aliasing of power domain enum values Imre Deak
` (6 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:49 UTC (permalink / raw)
To: intel-gfx
Atm the port -> DDI and AUX power domain mapping is specified by relying
on the aliasing of the platform specific intel_display_power_domain enum
values. For instance D12+ platforms refer to the 'D' port and power
domain instances, which doesn't match the bspec terminology, on these
platforms the corresponding port is TC1. To make it clear what
port/domain the code refers to add a mapping between them which matches
the bspec terms on different display versions.
This also allows for removing the aliasing in enum values in a follow-up
patch.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 3 +-
drivers/gpu/drm/i915/display/g4x_hdmi.c | 3 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +-
drivers/gpu/drm/i915/display/intel_display.c | 84 +------
drivers/gpu/drm/i915/display/intel_display.h | 4 +-
.../drm/i915/display/intel_display_power.h | 12 +
.../i915/display/intel_display_power_map.c | 206 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_tc.c | 4 +-
8 files changed, 232 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index f37677df6ebfc..b87cbecc0d213 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -11,6 +11,7 @@
#include "intel_connector.h"
#include "intel_crtc.h"
#include "intel_de.h"
+#include "intel_display_power.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dp_link_training.h"
@@ -1386,7 +1387,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
dig_port->max_lanes = 4;
intel_encoder->type = INTEL_OUTPUT_DP;
- intel_encoder->power_domain = intel_port_to_power_domain(port);
+ intel_encoder->power_domain = intel_ddi_lanes_power_domain(dev_priv, port);
if (IS_CHERRYVIEW(dev_priv)) {
if (port == PORT_D)
intel_encoder->pipe_mask = BIT(PIPE_C);
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 06e00b1eaa7ce..92474ef7a2e1d 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -10,6 +10,7 @@
#include "intel_connector.h"
#include "intel_crtc.h"
#include "intel_de.h"
+#include "intel_display_power.h"
#include "intel_display_types.h"
#include "intel_dpio_phy.h"
#include "intel_fifo_underrun.h"
@@ -588,7 +589,7 @@ void g4x_hdmi_init(struct drm_i915_private *dev_priv,
intel_encoder->shutdown = intel_hdmi_encoder_shutdown;
intel_encoder->type = INTEL_OUTPUT_HDMI;
- intel_encoder->power_domain = intel_port_to_power_domain(port);
+ intel_encoder->power_domain = intel_ddi_lanes_power_domain(dev_priv, port);
intel_encoder->port = port;
if (IS_CHERRYVIEW(dev_priv)) {
if (port == PORT_D)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 530032f3bb2c2..b848bfc8de432 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4347,7 +4347,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->get_power_domains = intel_ddi_get_power_domains;
encoder->type = INTEL_OUTPUT_DDI;
- encoder->power_domain = intel_port_to_power_domain(port);
+ encoder->power_domain = intel_ddi_lanes_power_domain(dev_priv, port);
encoder->port = port;
encoder->cloneable = 0;
encoder->pipe_mask = ~0;
@@ -4475,8 +4475,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
}
drm_WARN_ON(&dev_priv->drm, port > PORT_I);
- dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_IO_A +
- port - PORT_A;
+ dig_port->ddi_io_power_domain = intel_ddi_io_power_domain(dev_priv, port);
if (init_dp) {
if (!intel_ddi_init_dp_connector(dig_port))
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d0b9618383ce3..f1248b891bd6e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2285,91 +2285,15 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
return TC_PORT_1 + port - PORT_C;
}
-enum intel_display_power_domain intel_port_to_power_domain(enum port port)
-{
- switch (port) {
- case PORT_A:
- return POWER_DOMAIN_PORT_DDI_LANES_A;
- case PORT_B:
- return POWER_DOMAIN_PORT_DDI_LANES_B;
- case PORT_C:
- return POWER_DOMAIN_PORT_DDI_LANES_C;
- case PORT_D:
- return POWER_DOMAIN_PORT_DDI_LANES_D;
- case PORT_E:
- return POWER_DOMAIN_PORT_DDI_LANES_E;
- case PORT_F:
- return POWER_DOMAIN_PORT_DDI_LANES_F;
- case PORT_G:
- return POWER_DOMAIN_PORT_DDI_LANES_G;
- case PORT_H:
- return POWER_DOMAIN_PORT_DDI_LANES_H;
- case PORT_I:
- return POWER_DOMAIN_PORT_DDI_LANES_I;
- default:
- MISSING_CASE(port);
- return POWER_DOMAIN_PORT_OTHER;
- }
-}
-
enum intel_display_power_domain
intel_aux_power_domain(struct intel_digital_port *dig_port)
{
- if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
- switch (dig_port->aux_ch) {
- case AUX_CH_C:
- return POWER_DOMAIN_AUX_TBT_C;
- case AUX_CH_D:
- return POWER_DOMAIN_AUX_TBT_D;
- case AUX_CH_E:
- return POWER_DOMAIN_AUX_TBT_E;
- case AUX_CH_F:
- return POWER_DOMAIN_AUX_TBT_F;
- case AUX_CH_G:
- return POWER_DOMAIN_AUX_TBT_G;
- case AUX_CH_H:
- return POWER_DOMAIN_AUX_TBT_H;
- case AUX_CH_I:
- return POWER_DOMAIN_AUX_TBT_I;
- default:
- MISSING_CASE(dig_port->aux_ch);
- return POWER_DOMAIN_AUX_TBT_C;
- }
- }
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
-}
+ if (intel_tc_port_in_tbt_alt_mode(dig_port))
+ return intel_tbt_aux_power_domain(i915, dig_port->aux_ch);
-/*
- * Converts aux_ch to power_domain without caring about TBT ports for that use
- * intel_aux_power_domain()
- */
-enum intel_display_power_domain
-intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
-{
- switch (aux_ch) {
- case AUX_CH_A:
- return POWER_DOMAIN_AUX_A;
- case AUX_CH_B:
- return POWER_DOMAIN_AUX_B;
- case AUX_CH_C:
- return POWER_DOMAIN_AUX_C;
- case AUX_CH_D:
- return POWER_DOMAIN_AUX_D;
- case AUX_CH_E:
- return POWER_DOMAIN_AUX_E;
- case AUX_CH_F:
- return POWER_DOMAIN_AUX_F;
- case AUX_CH_G:
- return POWER_DOMAIN_AUX_G;
- case AUX_CH_H:
- return POWER_DOMAIN_AUX_H;
- case AUX_CH_I:
- return POWER_DOMAIN_AUX_I;
- default:
- MISSING_CASE(aux_ch);
- return POWER_DOMAIN_AUX_A;
- }
+ return intel_legacy_aux_power_domain(i915, dig_port->aux_ch);
}
static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index b61b75248ded3..12a6521883fc3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -617,11 +617,9 @@ int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
-enum intel_display_power_domain intel_port_to_power_domain(enum port port);
+enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
enum intel_display_power_domain
intel_aux_power_domain(struct intel_digital_port *dig_port);
-enum intel_display_power_domain
-intel_legacy_aux_to_power_domain(enum aux_ch aux_ch);
void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 04486b922878c..f7d5d467fb46f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -9,8 +9,10 @@
#include "intel_runtime_pm.h"
#include "i915_reg.h"
+enum aux_ch;
enum dpio_channel;
enum dpio_phy;
+enum port;
struct drm_i915_private;
struct i915_power_well;
struct intel_encoder;
@@ -131,6 +133,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_INIT,
POWER_DOMAIN_NUM,
+ POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM,
};
/*
@@ -323,4 +326,13 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain);
+enum intel_display_power_domain
+intel_ddi_lanes_power_domain(struct drm_i915_private *i915, enum port port);
+enum intel_display_power_domain
+intel_ddi_io_power_domain(struct drm_i915_private *i915, enum port port);
+enum intel_display_power_domain
+intel_legacy_aux_power_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
+enum intel_display_power_domain
+intel_tbt_aux_power_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
+
#endif /* __INTEL_DISPLAY_POWER_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index a72ebde959cde..c0222d392543c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -183,6 +183,212 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
}
}
+struct intel_ddi_power_domain_map {
+ enum port port_start;
+ enum port port_end;
+ enum aux_ch aux_ch_start;
+ enum aux_ch aux_ch_end;
+
+ enum intel_display_power_domain ddi_lanes;
+ enum intel_display_power_domain ddi_io;
+ enum intel_display_power_domain aux_legacy_usbc;
+ enum intel_display_power_domain aux_tbt;
+};
+
+static const struct intel_ddi_power_domain_map
+i9xx_port_map[] = {
+ {
+ .port_start = PORT_A,
+ .port_end = PORT_F,
+ .aux_ch_start = AUX_CH_A,
+ .aux_ch_end = AUX_CH_F,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
+ .aux_tbt = POWER_DOMAIN_INVALID,
+ },
+};
+
+static const struct intel_ddi_power_domain_map
+d11_port_map[] = {
+ {
+ .port_start = PORT_A,
+ .port_end = PORT_B,
+ .aux_ch_start = AUX_CH_A,
+ .aux_ch_end = AUX_CH_B,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
+ .aux_tbt = POWER_DOMAIN_INVALID,
+ }, {
+ .port_start = PORT_C,
+ .port_end = PORT_F,
+ .aux_ch_start = AUX_CH_C,
+ .aux_ch_end = AUX_CH_F,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_C,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_C,
+ .aux_tbt = POWER_DOMAIN_AUX_TBT_C,
+ },
+};
+
+static const struct intel_ddi_power_domain_map
+d12_port_map[] = {
+ {
+ .port_start = PORT_A,
+ .port_end = PORT_C,
+ .aux_ch_start = AUX_CH_A,
+ .aux_ch_end = AUX_CH_C,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
+ .aux_tbt = POWER_DOMAIN_INVALID,
+ }, {
+ .port_start = PORT_TC1,
+ .port_end = PORT_TC6,
+ .aux_ch_start = AUX_CH_USBC1,
+ .aux_ch_end = AUX_CH_USBC6,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
+ .aux_tbt = POWER_DOMAIN_AUX_TBT1,
+ },
+};
+
+static const struct intel_ddi_power_domain_map
+d13_port_map[] = {
+ {
+ .port_start = PORT_A,
+ .port_end = PORT_C,
+ .aux_ch_start = AUX_CH_A,
+ .aux_ch_end = AUX_CH_C,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
+ .aux_tbt = POWER_DOMAIN_INVALID,
+ }, {
+ .port_start = PORT_TC1,
+ .port_end = PORT_TC4,
+ .aux_ch_start = AUX_CH_USBC1,
+ .aux_ch_end = AUX_CH_USBC4,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
+ .aux_tbt = POWER_DOMAIN_AUX_TBT1,
+ }, {
+ .port_start = PORT_D_XELPD,
+ .port_end = PORT_E_XELPD,
+ .aux_ch_start = AUX_CH_D_XELPD,
+ .aux_ch_end = AUX_CH_E_XELPD,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D_XELPD,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D_XELPD,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_D_XELPD,
+ .aux_tbt = POWER_DOMAIN_INVALID,
+ },
+};
+
+static void
+intel_power_domain_map_for_platform(struct drm_i915_private *i915,
+ const struct intel_ddi_power_domain_map **map,
+ int *map_size)
+{
+ if (DISPLAY_VER(i915) >= 13) {
+ *map = d13_port_map;
+ *map_size = ARRAY_SIZE(d13_port_map);
+ } else if (DISPLAY_VER(i915) >= 12) {
+ *map = d12_port_map;
+ *map_size = ARRAY_SIZE(d12_port_map);
+ } else if (DISPLAY_VER(i915) >= 11) {
+ *map = d11_port_map;
+ *map_size = ARRAY_SIZE(d11_port_map);
+ } else {
+ *map = i9xx_port_map;
+ *map_size = ARRAY_SIZE(i9xx_port_map);
+ }
+}
+
+static const struct intel_ddi_power_domain_map *
+intel_power_domain_map_for_port(struct drm_i915_private *i915, enum port port)
+{
+ const struct intel_ddi_power_domain_map *map;
+ int map_size;
+ int i;
+
+ intel_power_domain_map_for_platform(i915, &map, &map_size);
+ for (i = 0; i < map_size; i++)
+ if (port >= map[i].port_start && port <= map[i].port_end)
+ return &map[i];
+
+ return NULL;
+}
+
+enum intel_display_power_domain
+intel_ddi_io_power_domain(struct drm_i915_private *i915, enum port port)
+{
+ const struct intel_ddi_power_domain_map *map = intel_power_domain_map_for_port(i915, port);
+
+ if (drm_WARN_ON(&i915->drm, !map) || map->ddi_io == POWER_DOMAIN_INVALID)
+ return POWER_DOMAIN_PORT_DDI_IO_A;
+
+ return map->ddi_io + port - map->port_start;
+}
+
+enum intel_display_power_domain
+intel_ddi_lanes_power_domain(struct drm_i915_private *i915, enum port port)
+{
+ const struct intel_ddi_power_domain_map *map = intel_power_domain_map_for_port(i915, port);
+
+ if (drm_WARN_ON(&i915->drm, !map) || map->ddi_lanes == POWER_DOMAIN_INVALID)
+ return POWER_DOMAIN_PORT_DDI_LANES_A;
+
+ return map->ddi_lanes + port - map->port_start;
+}
+
+static const struct intel_ddi_power_domain_map *
+intel_power_domain_map_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch)
+{
+ const struct intel_ddi_power_domain_map *map;
+ int map_size;
+ int i;
+
+ intel_power_domain_map_for_platform(i915, &map, &map_size);
+ for (i = 0; i < map_size; i++)
+ if (aux_ch >= map[i].aux_ch_start && aux_ch <= map[i].aux_ch_end)
+ return &map[i];
+
+ return NULL;
+}
+
+enum intel_display_power_domain
+intel_legacy_aux_power_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
+{
+ const struct intel_ddi_power_domain_map *map = intel_power_domain_map_for_aux_ch(i915, aux_ch);
+
+ if (drm_WARN_ON(&i915->drm, !map) || map->aux_legacy_usbc == POWER_DOMAIN_INVALID)
+ return POWER_DOMAIN_AUX_A;
+
+ return map->aux_legacy_usbc + aux_ch - map->aux_ch_start;
+}
+
+enum intel_display_power_domain
+intel_tbt_aux_power_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
+{
+ const struct intel_ddi_power_domain_map *map = intel_power_domain_map_for_aux_ch(i915, aux_ch);
+
+ if (drm_WARN_ON(&i915->drm, !map) || map->aux_tbt == POWER_DOMAIN_INVALID)
+ return POWER_DOMAIN_AUX_TBT1;
+
+ return map->aux_tbt + aux_ch - map->aux_ch_start;
+}
+
I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
static const struct i915_power_well_desc i9xx_power_wells_always_on[] = {
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 3291124a99e5a..5871b7b418a51 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -60,10 +60,12 @@ bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port)
static enum intel_display_power_domain
tc_cold_get_power_domain(struct intel_digital_port *dig_port, enum tc_port_mode mode)
{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
if (mode == TC_PORT_TBT_ALT || !intel_tc_cold_requires_aux_pw(dig_port))
return POWER_DOMAIN_TC_COLD_OFF;
- return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
+ return intel_legacy_aux_power_domain(i915, dig_port->aux_ch);
}
static intel_wakeref_t
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 16/19] drm/i915: Remove the aliasing of power domain enum values
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (14 preceding siblings ...)
2022-01-28 11:49 ` [Intel-gfx] [PATCH 15/19] drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform Imre Deak
@ 2022-01-28 11:49 ` Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 17/19] drm/i915: Remove the ICL specific TBT power domains Imre Deak
` (5 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:49 UTC (permalink / raw)
To: intel-gfx
Aliasing the intel_display_power_domain enum values was required because
of the u64 power domain mask size limit. This makes the dmesg/debugfs
printouts of the domain names somewhat unclear, for instance domain
names for port D are shown on D12+ platforms where the corresponding
port is called TC1. Make this clearer by removing the aliasing which is
possible after a previous patch converting the mask to a bitmap.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_power.h | 26 ++----
.../i915/display/intel_display_power_map.c | 84 +++++++++++++------
2 files changed, 67 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index f7d5d467fb46f..355819a163b6f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -49,18 +49,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_LANES_D,
POWER_DOMAIN_PORT_DDI_LANES_E,
POWER_DOMAIN_PORT_DDI_LANES_F,
- POWER_DOMAIN_PORT_DDI_LANES_G,
- POWER_DOMAIN_PORT_DDI_LANES_H,
- POWER_DOMAIN_PORT_DDI_LANES_I,
- POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_LANES_D, /* tgl+ */
+ POWER_DOMAIN_PORT_DDI_LANES_TC1,
POWER_DOMAIN_PORT_DDI_LANES_TC2,
POWER_DOMAIN_PORT_DDI_LANES_TC3,
POWER_DOMAIN_PORT_DDI_LANES_TC4,
POWER_DOMAIN_PORT_DDI_LANES_TC5,
POWER_DOMAIN_PORT_DDI_LANES_TC6,
- POWER_DOMAIN_PORT_DDI_LANES_D_XELPD = POWER_DOMAIN_PORT_DDI_LANES_TC5, /* XELPD */
+ POWER_DOMAIN_PORT_DDI_LANES_D_XELPD,
POWER_DOMAIN_PORT_DDI_LANES_E_XELPD,
POWER_DOMAIN_PORT_DDI_IO_A,
@@ -69,18 +66,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_IO_D,
POWER_DOMAIN_PORT_DDI_IO_E,
POWER_DOMAIN_PORT_DDI_IO_F,
- POWER_DOMAIN_PORT_DDI_IO_G,
- POWER_DOMAIN_PORT_DDI_IO_H,
- POWER_DOMAIN_PORT_DDI_IO_I,
- POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_IO_D, /* tgl+ */
+ POWER_DOMAIN_PORT_DDI_IO_TC1,
POWER_DOMAIN_PORT_DDI_IO_TC2,
POWER_DOMAIN_PORT_DDI_IO_TC3,
POWER_DOMAIN_PORT_DDI_IO_TC4,
POWER_DOMAIN_PORT_DDI_IO_TC5,
POWER_DOMAIN_PORT_DDI_IO_TC6,
- POWER_DOMAIN_PORT_DDI_IO_D_XELPD = POWER_DOMAIN_PORT_DDI_IO_TC5, /* XELPD */
+ POWER_DOMAIN_PORT_DDI_IO_D_XELPD,
POWER_DOMAIN_PORT_DDI_IO_E_XELPD,
POWER_DOMAIN_PORT_DSI,
@@ -95,18 +89,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_D,
POWER_DOMAIN_AUX_E,
POWER_DOMAIN_AUX_F,
- POWER_DOMAIN_AUX_G,
- POWER_DOMAIN_AUX_H,
- POWER_DOMAIN_AUX_I,
- POWER_DOMAIN_AUX_USBC1 = POWER_DOMAIN_AUX_D, /* tgl+ */
+ POWER_DOMAIN_AUX_USBC1,
POWER_DOMAIN_AUX_USBC2,
POWER_DOMAIN_AUX_USBC3,
POWER_DOMAIN_AUX_USBC4,
POWER_DOMAIN_AUX_USBC5,
POWER_DOMAIN_AUX_USBC6,
- POWER_DOMAIN_AUX_D_XELPD = POWER_DOMAIN_AUX_USBC5, /* XELPD */
+ POWER_DOMAIN_AUX_D_XELPD,
POWER_DOMAIN_AUX_E_XELPD,
POWER_DOMAIN_AUX_IO_A,
@@ -114,11 +105,8 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_TBT_D,
POWER_DOMAIN_AUX_TBT_E,
POWER_DOMAIN_AUX_TBT_F,
- POWER_DOMAIN_AUX_TBT_G,
- POWER_DOMAIN_AUX_TBT_H,
- POWER_DOMAIN_AUX_TBT_I,
- POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_TBT_D, /* tgl+ */
+ POWER_DOMAIN_AUX_TBT1,
POWER_DOMAIN_AUX_TBT2,
POWER_DOMAIN_AUX_TBT3,
POWER_DOMAIN_AUX_TBT4,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index c0222d392543c..a82887410ba6e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -95,12 +95,22 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_LANES_E";
case POWER_DOMAIN_PORT_DDI_LANES_F:
return "PORT_DDI_LANES_F";
- case POWER_DOMAIN_PORT_DDI_LANES_G:
- return "PORT_DDI_LANES_G";
- case POWER_DOMAIN_PORT_DDI_LANES_H:
- return "PORT_DDI_LANES_H";
- case POWER_DOMAIN_PORT_DDI_LANES_I:
- return "PORT_DDI_LANES_I";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC1:
+ return "PORT_DDI_LANES_TC1";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC2:
+ return "PORT_DDI_LANES_TC2";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC3:
+ return "PORT_DDI_LANES_TC3";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC4:
+ return "PORT_DDI_LANES_TC4";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC5:
+ return "PORT_DDI_LANES_TC5";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC6:
+ return "PORT_DDI_LANES_TC6";
+ case POWER_DOMAIN_PORT_DDI_LANES_D_XELPD:
+ return "PORT_DDI_LANES_D_XELPD";
+ case POWER_DOMAIN_PORT_DDI_LANES_E_XELPD:
+ return "PORT_DDI_LANES_E_XELPD";
case POWER_DOMAIN_PORT_DDI_IO_A:
return "PORT_DDI_IO_A";
case POWER_DOMAIN_PORT_DDI_IO_B:
@@ -113,12 +123,22 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_IO_E";
case POWER_DOMAIN_PORT_DDI_IO_F:
return "PORT_DDI_IO_F";
- case POWER_DOMAIN_PORT_DDI_IO_G:
- return "PORT_DDI_IO_G";
- case POWER_DOMAIN_PORT_DDI_IO_H:
- return "PORT_DDI_IO_H";
- case POWER_DOMAIN_PORT_DDI_IO_I:
- return "PORT_DDI_IO_I";
+ case POWER_DOMAIN_PORT_DDI_IO_TC1:
+ return "PORT_DDI_IO_TC1";
+ case POWER_DOMAIN_PORT_DDI_IO_TC2:
+ return "PORT_DDI_IO_TC2";
+ case POWER_DOMAIN_PORT_DDI_IO_TC3:
+ return "PORT_DDI_IO_TC3";
+ case POWER_DOMAIN_PORT_DDI_IO_TC4:
+ return "PORT_DDI_IO_TC4";
+ case POWER_DOMAIN_PORT_DDI_IO_TC5:
+ return "PORT_DDI_IO_TC5";
+ case POWER_DOMAIN_PORT_DDI_IO_TC6:
+ return "PORT_DDI_IO_TC6";
+ case POWER_DOMAIN_PORT_DDI_IO_D_XELPD:
+ return "PORT_DDI_IO_D_XELPD";
+ case POWER_DOMAIN_PORT_DDI_IO_E_XELPD:
+ return "PORT_DDI_IO_E_XELPD";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
@@ -143,12 +163,22 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_E";
case POWER_DOMAIN_AUX_F:
return "AUX_F";
- case POWER_DOMAIN_AUX_G:
- return "AUX_G";
- case POWER_DOMAIN_AUX_H:
- return "AUX_H";
- case POWER_DOMAIN_AUX_I:
- return "AUX_I";
+ case POWER_DOMAIN_AUX_USBC1:
+ return "AUX_USBC1";
+ case POWER_DOMAIN_AUX_USBC2:
+ return "AUX_USBC2";
+ case POWER_DOMAIN_AUX_USBC3:
+ return "AUX_USBC3";
+ case POWER_DOMAIN_AUX_USBC4:
+ return "AUX_USBC4";
+ case POWER_DOMAIN_AUX_USBC5:
+ return "AUX_USBC5";
+ case POWER_DOMAIN_AUX_USBC6:
+ return "AUX_USBC6";
+ case POWER_DOMAIN_AUX_D_XELPD:
+ return "AUX_D_XELPD";
+ case POWER_DOMAIN_AUX_E_XELPD:
+ return "AUX_E_XELPD";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
case POWER_DOMAIN_AUX_TBT_C:
@@ -159,12 +189,18 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_TBT_E";
case POWER_DOMAIN_AUX_TBT_F:
return "AUX_TBT_F";
- case POWER_DOMAIN_AUX_TBT_G:
- return "AUX_TBT_G";
- case POWER_DOMAIN_AUX_TBT_H:
- return "AUX_TBT_H";
- case POWER_DOMAIN_AUX_TBT_I:
- return "AUX_TBT_I";
+ case POWER_DOMAIN_AUX_TBT1:
+ return "AUX_TBT1";
+ case POWER_DOMAIN_AUX_TBT2:
+ return "AUX_TBT2";
+ case POWER_DOMAIN_AUX_TBT3:
+ return "AUX_TBT3";
+ case POWER_DOMAIN_AUX_TBT4:
+ return "AUX_TBT4";
+ case POWER_DOMAIN_AUX_TBT5:
+ return "AUX_TBT5";
+ case POWER_DOMAIN_AUX_TBT6:
+ return "AUX_TBT6";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
case POWER_DOMAIN_INIT:
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 17/19] drm/i915: Remove the ICL specific TBT power domains
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (15 preceding siblings ...)
2022-01-28 11:49 ` [Intel-gfx] [PATCH 16/19] drm/i915: Remove the aliasing of power domain enum values Imre Deak
@ 2022-01-28 11:49 ` Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 18/19] drm/i915: Remove duplicate DDI/AUX power domain mappings Imre Deak
` (4 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:49 UTC (permalink / raw)
To: intel-gfx
The spec calls the ICL TBT AUX power well instances TBT1-4 (similarly to
all later platforms), align the power domain names with the spec.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_power.h | 4 ---
.../i915/display/intel_display_power_map.c | 26 +++++++------------
2 files changed, 9 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 355819a163b6f..28291decc3789 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -101,10 +101,6 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_E_XELPD,
POWER_DOMAIN_AUX_IO_A,
- POWER_DOMAIN_AUX_TBT_C,
- POWER_DOMAIN_AUX_TBT_D,
- POWER_DOMAIN_AUX_TBT_E,
- POWER_DOMAIN_AUX_TBT_F,
POWER_DOMAIN_AUX_TBT1,
POWER_DOMAIN_AUX_TBT2,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index a82887410ba6e..1b79f04b1dd5d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -181,14 +181,6 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_E_XELPD";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
- case POWER_DOMAIN_AUX_TBT_C:
- return "AUX_TBT_C";
- case POWER_DOMAIN_AUX_TBT_D:
- return "AUX_TBT_D";
- case POWER_DOMAIN_AUX_TBT_E:
- return "AUX_TBT_E";
- case POWER_DOMAIN_AUX_TBT_F:
- return "AUX_TBT_F";
case POWER_DOMAIN_AUX_TBT1:
return "AUX_TBT1";
case POWER_DOMAIN_AUX_TBT2:
@@ -267,7 +259,7 @@ d11_port_map[] = {
.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C,
.ddi_io = POWER_DOMAIN_PORT_DDI_IO_C,
.aux_legacy_usbc = POWER_DOMAIN_AUX_C,
- .aux_tbt = POWER_DOMAIN_AUX_TBT_C,
+ .aux_tbt = POWER_DOMAIN_AUX_TBT1,
},
};
@@ -1001,10 +993,10 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
POWER_DOMAIN_AUX_D, \
POWER_DOMAIN_AUX_E, \
POWER_DOMAIN_AUX_F, \
- POWER_DOMAIN_AUX_TBT_C, \
- POWER_DOMAIN_AUX_TBT_D, \
- POWER_DOMAIN_AUX_TBT_E, \
- POWER_DOMAIN_AUX_TBT_F
+ POWER_DOMAIN_AUX_TBT1, \
+ POWER_DOMAIN_AUX_TBT2, \
+ POWER_DOMAIN_AUX_TBT3, \
+ POWER_DOMAIN_AUX_TBT4
I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3,
ICL_PW_3_POWER_DOMAINS,
@@ -1047,10 +1039,10 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d, POWER_DOMAIN_AUX_D);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e, POWER_DOMAIN_AUX_E);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f, POWER_DOMAIN_AUX_F);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT_C);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT_D);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT_E);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT_F);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
static const struct i915_power_well_desc icl_power_wells_pw_1[] = {
{
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 18/19] drm/i915: Remove duplicate DDI/AUX power domain mappings
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (16 preceding siblings ...)
2022-01-28 11:49 ` [Intel-gfx] [PATCH 17/19] drm/i915: Remove the ICL specific TBT power domains Imre Deak
@ 2022-01-28 11:49 ` Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 19/19] drm/i915: Remove the XELPD specific AUX and DDI power domains Imre Deak
` (3 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:49 UTC (permalink / raw)
To: intel-gfx
The DDI and AUX domain -> power well mappings are identical for a few
platforms/power well instances, reuse the mappings of earlier platforms
for these removing the duplicate mapping of new platforms.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../i915/display/intel_display_power_map.c | 89 +++++++------------
1 file changed, 31 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 1b79f04b1dd5d..2c9e55cb6e47d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1024,9 +1024,6 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off,
POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_INIT);
-I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A);
-I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B);
-I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C);
I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d, POWER_DOMAIN_PORT_DDI_IO_D);
I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e, POWER_DOMAIN_PORT_DDI_IO_E);
I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f, POWER_DOMAIN_PORT_DDI_IO_F);
@@ -1085,9 +1082,9 @@ static const struct i915_power_well_desc icl_power_wells_main[] = {
.has_fuses = true,
}, {
.instances = &I915_PW_INSTANCES(
- I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
- I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
- I915_PW("DDI_IO_C", &icl_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
+ I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = ICL_PW_CTL_IDX_DDI_D),
I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = ICL_PW_CTL_IDX_DDI_E),
I915_PW("DDI_IO_F", &icl_pwdoms_ddi_io_f, .hsw.idx = ICL_PW_CTL_IDX_DDI_F),
@@ -1199,12 +1196,6 @@ I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5, POWER_DOMAIN_PORT_DDI_IO_TC5);
I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6, POWER_DOMAIN_PORT_DDI_IO_TC6);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_a,
- POWER_DOMAIN_AUX_A,
- POWER_DOMAIN_AUX_IO_A);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_b, POWER_DOMAIN_AUX_B);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
-
I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1);
I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2);
I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3);
@@ -1212,10 +1203,6 @@ I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4);
I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5, POWER_DOMAIN_AUX_USBC5);
I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6, POWER_DOMAIN_AUX_USBC6);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5, POWER_DOMAIN_AUX_TBT5);
I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6, POWER_DOMAIN_AUX_TBT6);
@@ -1261,9 +1248,9 @@ static const struct i915_power_well_desc tgl_power_wells_main[] = {
.has_fuses = true,
}, {
.instances = &I915_PW_INSTANCES(
- I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
- I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
- I915_PW("DDI_IO_C", &icl_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
+ I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
@@ -1304,9 +1291,9 @@ static const struct i915_power_well_desc tgl_power_wells_tc_cold_off[] = {
static const struct i915_power_well_desc tgl_power_wells_aux[] = {
{
.instances = &I915_PW_INSTANCES(
- I915_PW("AUX_A", &tgl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
- I915_PW("AUX_B", &tgl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
- I915_PW("AUX_C", &tgl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
+ I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
+ I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
+ I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
@@ -1317,10 +1304,10 @@ static const struct i915_power_well_desc tgl_power_wells_aux[] = {
.ops = &icl_aux_power_well_ops,
}, {
.instances = &I915_PW_INSTANCES(
- I915_PW("AUX_TBT1", &tgl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
- I915_PW("AUX_TBT2", &tgl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
- I915_PW("AUX_TBT3", &tgl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
- I915_PW("AUX_TBT4", &tgl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
+ I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
+ I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
+ I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
+ I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
I915_PW("AUX_TBT5", &tgl_pwdoms_aux_tbt5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5),
I915_PW("AUX_TBT6", &tgl_pwdoms_aux_tbt6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6),
),
@@ -1429,8 +1416,8 @@ static const struct i915_power_well_desc rkl_power_wells_main[] = {
static const struct i915_power_well_desc rkl_power_wells_ddi_aux[] = {
{
.instances = &I915_PW_INSTANCES(
- I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
- I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
),
@@ -1644,22 +1631,8 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_d_xelpd, POWER_DOMAIN_AUX_D_XELPD);
I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_e_xelpd, POWER_DOMAIN_AUX_E_XELPD);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4);
-
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
-
I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_d_xelpd, POWER_DOMAIN_PORT_DDI_IO_D_XELPD);
I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_e_xelpd, POWER_DOMAIN_PORT_DDI_IO_E_XELPD);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
static const struct i915_power_well_desc xelpd_power_wells_main[] = {
{
@@ -1711,37 +1684,37 @@ static const struct i915_power_well_desc xelpd_power_wells_main[] = {
.has_fuses = true,
}, {
.instances = &I915_PW_INSTANCES(
- I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
- I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
- I915_PW("DDI_IO_C", &icl_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
+ I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
I915_PW("DDI_IO_D_XELPD", &xelpd_pwdoms_ddi_io_d_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_DDI_D),
I915_PW("DDI_IO_E_XELPD", &xelpd_pwdoms_ddi_io_e_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_DDI_E),
- I915_PW("DDI_IO_TC1", &xelpd_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
- I915_PW("DDI_IO_TC2", &xelpd_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
- I915_PW("DDI_IO_TC3", &xelpd_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
- I915_PW("DDI_IO_TC4", &xelpd_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4),
+ I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
+ I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
+ I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
+ I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4),
),
.ops = &icl_ddi_power_well_ops,
}, {
.instances = &I915_PW_INSTANCES(
I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
- I915_PW("AUX_C", &tgl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
+ I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
I915_PW("AUX_D_XELPD", &xelpd_pwdoms_aux_d_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D),
I915_PW("AUX_E_XELPD", &xelpd_pwdoms_aux_e_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E),
- I915_PW("AUX_USBC1", &xelpd_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
- I915_PW("AUX_USBC2", &xelpd_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
- I915_PW("AUX_USBC3", &xelpd_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
- I915_PW("AUX_USBC4", &xelpd_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4),
+ I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
+ I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
+ I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
+ I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4),
),
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
}, {
.instances = &I915_PW_INSTANCES(
- I915_PW("AUX_TBT1", &xelpd_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
- I915_PW("AUX_TBT2", &xelpd_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
- I915_PW("AUX_TBT3", &xelpd_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
- I915_PW("AUX_TBT4", &xelpd_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
+ I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
+ I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
+ I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
+ I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
),
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 19/19] drm/i915: Remove the XELPD specific AUX and DDI power domains
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (17 preceding siblings ...)
2022-01-28 11:49 ` [Intel-gfx] [PATCH 18/19] drm/i915: Remove duplicate DDI/AUX power domain mappings Imre Deak
@ 2022-01-28 11:49 ` Imre Deak
2022-01-28 12:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Refactor the display power domain mappings Patchwork
` (2 subsequent siblings)
21 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-01-28 11:49 UTC (permalink / raw)
To: intel-gfx
The spec calls the XELPD_D/E ports just D/E, the platform prefix in the
domain names was only needed by the port->domain mapping relying on
matching enum values for the whole port/domain range (and the
corresponding aliasing between the platform specific domain enums).
Since a previous patch we can define the port->domain mapping explicitly
so do this by reusing the already existing D/E power domain names.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_power.h | 9 -----
.../i915/display/intel_display_power_map.c | 40 +++++--------------
2 files changed, 11 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 28291decc3789..94cf2f03fdef5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -57,9 +57,6 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_LANES_TC5,
POWER_DOMAIN_PORT_DDI_LANES_TC6,
- POWER_DOMAIN_PORT_DDI_LANES_D_XELPD,
- POWER_DOMAIN_PORT_DDI_LANES_E_XELPD,
-
POWER_DOMAIN_PORT_DDI_IO_A,
POWER_DOMAIN_PORT_DDI_IO_B,
POWER_DOMAIN_PORT_DDI_IO_C,
@@ -74,9 +71,6 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_IO_TC5,
POWER_DOMAIN_PORT_DDI_IO_TC6,
- POWER_DOMAIN_PORT_DDI_IO_D_XELPD,
- POWER_DOMAIN_PORT_DDI_IO_E_XELPD,
-
POWER_DOMAIN_PORT_DSI,
POWER_DOMAIN_PORT_CRT,
POWER_DOMAIN_PORT_OTHER,
@@ -97,9 +91,6 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_USBC5,
POWER_DOMAIN_AUX_USBC6,
- POWER_DOMAIN_AUX_D_XELPD,
- POWER_DOMAIN_AUX_E_XELPD,
-
POWER_DOMAIN_AUX_IO_A,
POWER_DOMAIN_AUX_TBT1,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 2c9e55cb6e47d..79baf0ea588bb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -107,10 +107,6 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_LANES_TC5";
case POWER_DOMAIN_PORT_DDI_LANES_TC6:
return "PORT_DDI_LANES_TC6";
- case POWER_DOMAIN_PORT_DDI_LANES_D_XELPD:
- return "PORT_DDI_LANES_D_XELPD";
- case POWER_DOMAIN_PORT_DDI_LANES_E_XELPD:
- return "PORT_DDI_LANES_E_XELPD";
case POWER_DOMAIN_PORT_DDI_IO_A:
return "PORT_DDI_IO_A";
case POWER_DOMAIN_PORT_DDI_IO_B:
@@ -135,10 +131,6 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_IO_TC5";
case POWER_DOMAIN_PORT_DDI_IO_TC6:
return "PORT_DDI_IO_TC6";
- case POWER_DOMAIN_PORT_DDI_IO_D_XELPD:
- return "PORT_DDI_IO_D_XELPD";
- case POWER_DOMAIN_PORT_DDI_IO_E_XELPD:
- return "PORT_DDI_IO_E_XELPD";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
@@ -175,10 +167,6 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_USBC5";
case POWER_DOMAIN_AUX_USBC6:
return "AUX_USBC6";
- case POWER_DOMAIN_AUX_D_XELPD:
- return "AUX_D_XELPD";
- case POWER_DOMAIN_AUX_E_XELPD:
- return "AUX_E_XELPD";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
case POWER_DOMAIN_AUX_TBT1:
@@ -316,9 +304,9 @@ d13_port_map[] = {
.aux_ch_start = AUX_CH_D_XELPD,
.aux_ch_end = AUX_CH_E_XELPD,
- .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D_XELPD,
- .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D_XELPD,
- .aux_legacy_usbc = POWER_DOMAIN_AUX_D_XELPD,
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_D,
.aux_tbt = POWER_DOMAIN_INVALID,
},
};
@@ -1578,8 +1566,8 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
XELPD_PW_C_POWER_DOMAINS, \
XELPD_PW_D_POWER_DOMAINS, \
POWER_DOMAIN_PORT_DDI_LANES_C, \
- POWER_DOMAIN_PORT_DDI_LANES_D_XELPD, \
- POWER_DOMAIN_PORT_DDI_LANES_E_XELPD, \
+ POWER_DOMAIN_PORT_DDI_LANES_D, \
+ POWER_DOMAIN_PORT_DDI_LANES_E, \
POWER_DOMAIN_PORT_DDI_LANES_TC1, \
POWER_DOMAIN_PORT_DDI_LANES_TC2, \
POWER_DOMAIN_PORT_DDI_LANES_TC3, \
@@ -1587,8 +1575,8 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
POWER_DOMAIN_VGA, \
POWER_DOMAIN_AUDIO_PLAYBACK, \
POWER_DOMAIN_AUX_C, \
- POWER_DOMAIN_AUX_D_XELPD, \
- POWER_DOMAIN_AUX_E_XELPD, \
+ POWER_DOMAIN_AUX_D, \
+ POWER_DOMAIN_AUX_E, \
POWER_DOMAIN_AUX_USBC1, \
POWER_DOMAIN_AUX_USBC2, \
POWER_DOMAIN_AUX_USBC3, \
@@ -1628,12 +1616,6 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_INIT);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_d_xelpd, POWER_DOMAIN_AUX_D_XELPD);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_e_xelpd, POWER_DOMAIN_AUX_E_XELPD);
-
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_d_xelpd, POWER_DOMAIN_PORT_DDI_IO_D_XELPD);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_e_xelpd, POWER_DOMAIN_PORT_DDI_IO_E_XELPD);
-
static const struct i915_power_well_desc xelpd_power_wells_main[] = {
{
.instances = &I915_PW_INSTANCES(
@@ -1687,8 +1669,8 @@ static const struct i915_power_well_desc xelpd_power_wells_main[] = {
I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
- I915_PW("DDI_IO_D_XELPD", &xelpd_pwdoms_ddi_io_d_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_DDI_D),
- I915_PW("DDI_IO_E_XELPD", &xelpd_pwdoms_ddi_io_e_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_DDI_E),
+ I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = XELPD_PW_CTL_IDX_DDI_D),
+ I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = XELPD_PW_CTL_IDX_DDI_E),
I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
@@ -1700,8 +1682,8 @@ static const struct i915_power_well_desc xelpd_power_wells_main[] = {
I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
- I915_PW("AUX_D_XELPD", &xelpd_pwdoms_aux_d_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D),
- I915_PW("AUX_E_XELPD", &xelpd_pwdoms_aux_e_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E),
+ I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D),
+ I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E),
I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Refactor the display power domain mappings
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (18 preceding siblings ...)
2022-01-28 11:49 ` [Intel-gfx] [PATCH 19/19] drm/i915: Remove the XELPD specific AUX and DDI power domains Imre Deak
@ 2022-01-28 12:49 ` Patchwork
2022-01-28 12:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-28 13:27 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
21 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2022-01-28 12:49 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Refactor the display power domain mappings
URL : https://patchwork.freedesktop.org/series/99476/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b526cacc94dc drm/i915: Fix the VDSC_PW2 power domain enum value
2f95deec7aed drm/i915: Unexport the for_each_power_well() macros
-:19: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__dev_priv' - possible side-effects?
#19: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:28:
+#define for_each_power_well(__dev_priv, __power_well) \
+ for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
+ (__power_well) - (__dev_priv)->power_domains.power_wells < \
+ (__dev_priv)->power_domains.power_well_count; \
+ (__power_well)++)
-:19: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#19: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:28:
+#define for_each_power_well(__dev_priv, __power_well) \
+ for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
+ (__power_well) - (__dev_priv)->power_domains.power_wells < \
+ (__dev_priv)->power_domains.power_well_count; \
+ (__power_well)++)
-:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__dev_priv' - possible side-effects?
#25: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:34:
+#define for_each_power_well_reverse(__dev_priv, __power_well) \
+ for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
+ (__dev_priv)->power_domains.power_well_count - 1; \
+ (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
+ (__power_well)--)
-:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#25: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:34:
+#define for_each_power_well_reverse(__dev_priv, __power_well) \
+ for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
+ (__dev_priv)->power_domains.power_well_count - 1; \
+ (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
+ (__power_well)--)
-:31: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#31: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:40:
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
+ for_each_power_well(__dev_priv, __power_well) \
+ for_each_if((__power_well)->desc->domains & (__domain_mask))
-:31: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#31: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:40:
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
+ for_each_power_well(__dev_priv, __power_well) \
+ for_each_if((__power_well)->desc->domains & (__domain_mask))
-:35: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#35: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:44:
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
+ for_each_power_well_reverse(__dev_priv, __power_well) \
+ for_each_if((__power_well)->desc->domains & (__domain_mask))
-:35: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#35: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:44:
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
+ for_each_power_well_reverse(__dev_priv, __power_well) \
+ for_each_if((__power_well)->desc->domains & (__domain_mask))
total: 2 errors, 0 warnings, 6 checks, 52 lines checked
0cceed36071a drm/i915: Move the i915_power_well_regs struct into i915_power_well_ops
18079359bdb7 drm/i915: Move the power domain->well mappings to intel_display_power_map.c
-:2705: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#2705:
new file mode 100644
-:2809: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for 'drivers/gpu/drm/i915/display/intel_display_power_map.c', please use '//' instead
#2809: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1:
+/* SPDX-License-Identifier: MIT */
-:2809: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#2809: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1:
+/* SPDX-License-Identifier: MIT */
-:5024: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well_descs' - possible side-effects?
#5024: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:2216:
+#define set_power_wells_mask(power_domains, __power_well_descs, skip_mask) \
+ __set_power_wells(power_domains, __power_well_descs, \
+ ARRAY_SIZE(__power_well_descs), skip_mask)
total: 0 errors, 3 warnings, 1 checks, 5028 lines checked
b7347fe242d7 drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield
7f3b9c90f90e drm/i915: Move the HSW power well flags to a common bitfield
e9c6e51f909b drm/i915: Rename the power domain names to end with pipes/ports
cecd93009957 drm/i915: Sanitize the power well names
f2b0c2050d8f drm/i915: Convert the power well descriptor domain mask to a list
-:103: ERROR:BRACKET_SPACE: space prohibited before open square bracket '['
#103: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:14:
+ ((__elem_type []){ __VA_ARGS__ })
-:103: ERROR:SPACING: space required before the open brace '{'
#103: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:14:
+ ((__elem_type []){ __VA_ARGS__ })
-:105: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__elems' - possible side-effects?
#105: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:16:
+#define __LIST(__elems) { \
+ .list = __elems, \
+ .count = ARRAY_SIZE(__elems), \
+}
-:110: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#110: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:21:
+#define I915_PW_DOMAINS(...) \
+ (const struct i915_power_domain_list) \
+ __LIST(__LIST_INLINE_ELEMS(enum intel_display_power_domain, __VA_ARGS__))
-:149: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#149: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:183:
+I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
+ POWER_DOMAIN_PIPE_A,
-:192: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#192: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:207:
+I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
+ POWER_DOMAIN_PIPE_B,
-:245: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#245: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:244:
+I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
+ POWER_DOMAIN_PIPE_B,
-:328: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#328: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:281:
+I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
+ POWER_DOMAIN_DISPLAY_CORE,
-:348: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#348: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:301:
+I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
-:356: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#356: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:309:
+I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
-:474: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#474: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:374:
+I915_DECL_PW_DOMAINS(chv_pwdoms_display,
+ POWER_DOMAIN_DISPLAY_CORE,
-:498: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#498: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:398:
+I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
-:505: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#505: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:405:
+I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
-:588: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#588: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:445:
+#define SKL_PW_2_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_D, \
+ POWER_DOMAIN_PORT_DDI_LANES_E, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C, \
+ POWER_DOMAIN_AUX_D
-:608: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#608: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:465:
+I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2,
+ SKL_PW_2_POWER_DOMAINS,
-:612: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#612: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:469:
+I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off,
+ SKL_PW_2_POWER_DOMAINS,
-:619: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#619: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:476:
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e,
+ POWER_DOMAIN_PORT_DDI_IO_A,
-:624: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#624: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:481:
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_b,
+ POWER_DOMAIN_PORT_DDI_IO_B,
-:628: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#628: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:485:
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_c,
+ POWER_DOMAIN_PORT_DDI_IO_C,
-:632: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#632: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:489:
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d,
+ POWER_DOMAIN_PORT_DDI_IO_D,
-:751: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#751: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:571:
+#define BXT_PW_2_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C
-:768: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#768: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:588:
+I915_DECL_PW_DOMAINS(bxt_pwdoms_pw_2,
+ BXT_PW_2_POWER_DOMAINS,
-:772: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#772: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:592:
+I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off,
+ BXT_PW_2_POWER_DOMAINS,
-:780: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#780: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:600:
+I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
+ POWER_DOMAIN_PORT_DDI_LANES_A,
-:785: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#785: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:605:
+I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
-:900: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#900: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:664:
+#define GLK_PW_2_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C
-:917: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#917: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:681:
+I915_DECL_PW_DOMAINS(glk_pwdoms_pw_2,
+ GLK_PW_2_POWER_DOMAINS,
-:921: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#921: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:685:
+I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off,
+ GLK_PW_2_POWER_DOMAINS,
-:933: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#933: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:697:
+I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
+ POWER_DOMAIN_PORT_DDI_LANES_A,
-:938: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#938: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:702:
+I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
-:943: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#943: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:707:
+I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
-:948: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#948: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:712:
+I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
+ POWER_DOMAIN_AUX_A,
-:953: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#953: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:717:
+I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
+ POWER_DOMAIN_AUX_B,
-:957: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#957: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:721:
+I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
+ POWER_DOMAIN_AUX_C,
-:1080: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1080: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:847:
+#define ICL_PW_4_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C
-:1085: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1085: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:852:
+I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
+ ICL_PW_4_POWER_DOMAINS,
-:1114: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1114: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:856:
+#define ICL_PW_3_POWER_DOMAINS \
+ ICL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_D, \
+ POWER_DOMAIN_PORT_DDI_LANES_E, \
+ POWER_DOMAIN_PORT_DDI_LANES_F, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C, \
+ POWER_DOMAIN_AUX_D, \
+ POWER_DOMAIN_AUX_E, \
+ POWER_DOMAIN_AUX_F, \
+ POWER_DOMAIN_AUX_TBT_C, \
+ POWER_DOMAIN_AUX_TBT_D, \
+ POWER_DOMAIN_AUX_TBT_E, \
+ POWER_DOMAIN_AUX_TBT_F
-:1140: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1140: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:882:
+I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3,
+ ICL_PW_3_POWER_DOMAINS,
-:1151: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1151: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:889:
+#define ICL_PW_2_POWER_DOMAINS \
+ ICL_PW_3_POWER_DOMAINS, \
+ POWER_DOMAIN_TRANSCODER_VDSC_PW2
-:1156: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1156: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:894:
+I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2,
+ ICL_PW_2_POWER_DOMAINS,
-:1190: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1190: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:901:
+I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off,
+ ICL_PW_2_POWER_DOMAINS,
-:1204: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1204: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:915:
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
+ POWER_DOMAIN_AUX_A,
-:1508: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1508: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1119:
+#define TGL_PW_5_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_D, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
+ POWER_DOMAIN_TRANSCODER_D
-:1514: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1514: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1125:
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_5,
+ TGL_PW_5_POWER_DOMAINS,
-:1517: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1517: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1128:
+#define TGL_PW_4_POWER_DOMAINS \
+ TGL_PW_5_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_C
-:1524: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1524: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1135:
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_4,
+ TGL_PW_4_POWER_DOMAINS,
-:1527: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1527: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1138:
+#define TGL_PW_3_POWER_DOMAINS \
+ TGL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC3, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC4, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC5, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC6, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2, \
+ POWER_DOMAIN_AUX_USBC3, \
+ POWER_DOMAIN_AUX_USBC4, \
+ POWER_DOMAIN_AUX_USBC5, \
+ POWER_DOMAIN_AUX_USBC6, \
+ POWER_DOMAIN_AUX_TBT1, \
+ POWER_DOMAIN_AUX_TBT2, \
+ POWER_DOMAIN_AUX_TBT3, \
+ POWER_DOMAIN_AUX_TBT4, \
+ POWER_DOMAIN_AUX_TBT5, \
+ POWER_DOMAIN_AUX_TBT6
-:1555: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1555: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1166:
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_3,
+ TGL_PW_3_POWER_DOMAINS,
-:1559: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1559: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1170:
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_2,
+ TGL_PW_3_POWER_DOMAINS,
-:1564: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1564: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1175:
+I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off,
+ TGL_PW_3_POWER_DOMAINS,
-:1579: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1579: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1190:
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_a,
+ POWER_DOMAIN_AUX_A,
-:1599: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1599: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1210:
+I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off,
+ POWER_DOMAIN_AUX_USBC1,
-:1916: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1916: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1499:
+#define RKL_PW_4_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_C
-:1922: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1922: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1505:
+I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_4,
+ RKL_PW_4_POWER_DOMAINS,
-:1925: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1925: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1508:
+#define RKL_PW_3_POWER_DOMAINS \
+ RKL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2
-:1939: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1939: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1522:
+I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_3,
+ RKL_PW_3_POWER_DOMAINS,
-:1955: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1955: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1547:
+I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
+ RKL_PW_3_POWER_DOMAINS,
-:2102: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#2102: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1667:
+#define DG1_PW_3_POWER_DOMAINS \
+ TGL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2
-:2115: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2115: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1680:
+I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_3,
+ DG1_PW_3_POWER_DOMAINS,
-:2119: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2119: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1684:
+I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off,
+ DG1_PW_3_POWER_DOMAINS,
-:2127: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2127: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1692:
+I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
+ DG1_PW_3_POWER_DOMAINS,
-:2313: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#2313: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1846:
+#define XELPD_PW_D_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_D, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
+ POWER_DOMAIN_TRANSCODER_D
-:2319: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2319: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1852:
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_d,
+ XELPD_PW_D_POWER_DOMAINS,
-:2322: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#2322: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1855:
+#define XELPD_PW_C_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_C
-:2328: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2328: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1861:
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_c,
+ XELPD_PW_C_POWER_DOMAINS,
-:2331: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#2331: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1864:
+#define XELPD_PW_B_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B
-:2337: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2337: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1870:
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_b,
+ XELPD_PW_B_POWER_DOMAINS,
-:2341: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2341: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1874:
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
+ POWER_DOMAIN_PIPE_A,
-:2345: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#2345: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1878:
+#define XELPD_PW_2_POWER_DOMAINS \
+ XELPD_PW_B_POWER_DOMAINS, \
+ XELPD_PW_C_POWER_DOMAINS, \
+ XELPD_PW_D_POWER_DOMAINS, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_D_XELPD, \
+ POWER_DOMAIN_PORT_DDI_LANES_E_XELPD, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC3, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC4, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_C, \
+ POWER_DOMAIN_AUX_D_XELPD, \
+ POWER_DOMAIN_AUX_E_XELPD, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2, \
+ POWER_DOMAIN_AUX_USBC3, \
+ POWER_DOMAIN_AUX_USBC4, \
+ POWER_DOMAIN_AUX_TBT1, \
+ POWER_DOMAIN_AUX_TBT2, \
+ POWER_DOMAIN_AUX_TBT3, \
+ POWER_DOMAIN_AUX_TBT4
-:2371: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2371: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1904:
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
+ XELPD_PW_2_POWER_DOMAINS,
-:2408: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2408: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1925:
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
+ XELPD_PW_2_POWER_DOMAINS,
total: 19 errors, 0 warnings, 52 checks, 2568 lines checked
97c2753b151f drm/i915: Convert the u64 power well domains mask to a bitmap
-:170: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#170: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:41:
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain) \
for_each_power_well(__dev_priv, __power_well) \
+ for_each_if(test_bit((__domain), (__power_well)->domains.bits))
-:170: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#170: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:41:
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain) \
for_each_power_well(__dev_priv, __power_well) \
+ for_each_if(test_bit((__domain), (__power_well)->domains.bits))
-:176: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#176: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:45:
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \
for_each_power_well_reverse(__dev_priv, __power_well) \
+ for_each_if(test_bit((__domain), (__power_well)->domains.bits))
-:176: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#176: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:45:
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \
for_each_power_well_reverse(__dev_priv, __power_well) \
+ for_each_if(test_bit((__domain), (__power_well)->domains.bits))
-:482: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#482: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:2426:
+ drm_WARN_ON(&i915->drm, !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
-:539: WARNING:NEW_TYPEDEFS: do not add new typedefs
#539: FILE: drivers/gpu/drm/i915/display/intel_display_power.h:167:
+typedef struct { DECLARE_BITMAP(bits, POWER_DOMAIN_NUM); } intel_power_domain_mask_t;
-:565: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__domain' - possible side-effects?
#565: FILE: drivers/gpu/drm/i915/display/intel_display_power.h:198:
+#define for_each_power_domain(__domain, __mask) \
+ for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \
+ for_each_if(test_bit((__domain), (__mask)->bits))
total: 2 errors, 2 warnings, 3 checks, 545 lines checked
3572a30cfdc7 drm/i915: Simplify power well definitions by adding power well instances
-:443: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#443: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:32:
+#define I915_PW_INSTANCES(...) \
+ (const struct i915_power_well_instance_list) \
+ __LIST(__LIST_INLINE_ELEMS(struct i915_power_well_instance, __VA_ARGS__))
-:450: CHECK:LINE_SPACING: Please don't use multiple blank lines
#450: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:39:
+
+
-:460: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#460: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:182:
+ .instances = &I915_PW_INSTANCES(
-:475: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#475: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:201:
+ .instances = &I915_PW_INSTANCES(
-:484: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#484: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:207:
+ .instances = &I915_PW_INSTANCES(
-:498: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#498: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:234:
+ .instances = &I915_PW_INSTANCES(
-:507: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#507: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:240:
+ .instances = &I915_PW_INSTANCES(
-:527: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#527: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:269:
+ .instances = &I915_PW_INSTANCES(
-:536: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#536: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:275:
+ .instances = &I915_PW_INSTANCES(
-:557: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#557: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:323:
+ .instances = &I915_PW_INSTANCES(
-:566: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#566: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:329:
+ .instances = &I915_PW_INSTANCES(
-:579: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#579: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:336:
+ .instances = &I915_PW_INSTANCES(
-:621: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#621: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:348:
+ .instances = &I915_PW_INSTANCES(
-:640: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#640: FILE: driv
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Refactor the display power domain mappings
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (19 preceding siblings ...)
2022-01-28 12:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Refactor the display power domain mappings Patchwork
@ 2022-01-28 12:51 ` Patchwork
2022-01-28 13:27 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
21 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2022-01-28 12:51 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Refactor the display power domain mappings
URL : https://patchwork.freedesktop.org/series/99476/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Refactor the display power domain mappings
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
` (20 preceding siblings ...)
2022-01-28 12:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-01-28 13:27 ` Patchwork
21 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2022-01-28 13:27 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 11782 bytes --]
== Series Details ==
Series: drm/i915: Refactor the display power domain mappings
URL : https://patchwork.freedesktop.org/series/99476/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11158 -> Patchwork_22137
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22137 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22137, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/index.html
Participating hosts (41 -> 42)
------------------------------
Additional (4): fi-kbl-soraka fi-kbl-8809g bat-adlp-4 fi-pnv-d510
Missing (3): fi-bsw-cyan fi-icl-u2 fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22137:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gt_engines:
- fi-rkl-guc: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
Known issues
------------
Here are the changes found in Patchwork_22137 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271]) +8 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_exec_suspend@basic-s0@smem:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][5] ([i915#4962]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-kbl-8809g/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: NOTRUN -> [FAIL][6] ([i915#4547])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
- fi-kbl-8809g: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- bat-adlp-4: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/bat-adlp-4/igt@gem_lmem_swapping@basic.html
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-kbl-8809g/igt@gem_lmem_swapping@random-engines.html
* igt@gem_tiled_pread_basic:
- bat-adlp-4: NOTRUN -> [SKIP][12] ([i915#3282])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/bat-adlp-4/igt@gem_tiled_pread_basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][13] ([i915#1886] / [i915#2291])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][14] -> [DMESG-FAIL][15] ([i915#4494] / [i915#4957])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- bat-adlp-4: NOTRUN -> [SKIP][17] ([fdo#111827]) +8 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/bat-adlp-4/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-8809g: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +8 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-kbl-8809g/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-adlp-4: NOTRUN -> [SKIP][19] ([i915#4103]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/bat-adlp-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-adlp-4: NOTRUN -> [SKIP][20] ([fdo#109285])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/bat-adlp-4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#533])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-8809g: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#533])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-kbl-8809g/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g: NOTRUN -> [SKIP][23] ([fdo#109271]) +54 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html
* igt@prime_vgem@basic-fence-read:
- bat-adlp-4: NOTRUN -> [SKIP][24] ([i915#3291] / [i915#3708]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/bat-adlp-4/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][25] ([fdo#109271]) +57 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-pnv-d510/igt@prime_vgem@basic-userptr.html
- bat-adlp-4: NOTRUN -> [SKIP][26] ([i915#3301] / [i915#3708])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/bat-adlp-4/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-rkl-guc: NOTRUN -> [FAIL][27] ([i915#4312])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-rkl-guc/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: [INCOMPLETE][28] ([i915#4547]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][30] ([i915#3921]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
#### Warnings ####
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][32] ([i915#4494] / [i915#4957]) -> [DMESG-FAIL][33] ([i915#4957])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4962]: https://gitlab.freedesktop.org/drm/intel/issues/4962
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* Linux: CI_DRM_11158 -> Patchwork_22137
CI-20190529: 20190529
CI_DRM_11158: e130c3068948a12aacfd1771c59a5294fcab3c56 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6336: ae2eb9e18bc58a4c45f28cfd80962938198dec3c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22137: f4ad29eb3b639be28c53b655aee8cec6ec0913c9 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f4ad29eb3b63 drm/i915: Remove the XELPD specific AUX and DDI power domains
bb9cda56837f drm/i915: Remove duplicate DDI/AUX power domain mappings
443d91f4c7a4 drm/i915: Remove the ICL specific TBT power domains
3bf7ceb05075 drm/i915: Remove the aliasing of power domain enum values
0c445f08027c drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform
d8a4274e7228 drm/i915: Sanitize the ADL-S power well definition
432ea70fa4f7 drm/i915: Simplify the DG1 power well descriptors
3eca526b6e0f drm/i915: Allow platforms to share power well descriptors
3572a30cfdc7 drm/i915: Simplify power well definitions by adding power well instances
97c2753b151f drm/i915: Convert the u64 power well domains mask to a bitmap
f2b0c2050d8f drm/i915: Convert the power well descriptor domain mask to a list
cecd93009957 drm/i915: Sanitize the power well names
e9c6e51f909b drm/i915: Rename the power domain names to end with pipes/ports
7f3b9c90f90e drm/i915: Move the HSW power well flags to a common bitfield
b7347fe242d7 drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield
18079359bdb7 drm/i915: Move the power domain->well mappings to intel_display_power_map.c
0cceed36071a drm/i915: Move the i915_power_well_regs struct into i915_power_well_ops
2f95deec7aed drm/i915: Unexport the for_each_power_well() macros
b526cacc94dc drm/i915: Fix the VDSC_PW2 power domain enum value
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22137/index.html
[-- Attachment #2: Type: text/html, Size: 14587 bytes --]
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 04/19] drm/i915: Move the power domain->well mappings to intel_display_power_map.c
2022-01-28 11:48 ` [Intel-gfx] [PATCH 04/19] drm/i915: Move the power domain->well mappings to intel_display_power_map.c Imre Deak
@ 2022-01-31 12:15 ` Jani Nikula
2022-01-31 16:00 ` Imre Deak
0 siblings, 1 reply; 32+ messages in thread
From: Jani Nikula @ 2022-01-31 12:15 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On Fri, 28 Jan 2022, Imre Deak <imre.deak@intel.com> wrote:
> Move the list of platform specific power domain -> power well
> definitions to intel_display_power_map.c. While at it group the
> platforms' power domain macros with the corresponding power well lists
> and keep all the power domain lists in the same order (matching the enum
> order).
>
> No functional changes.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
The commit message should explain the why.
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index b30e6133c66d0..a0e68ae691021 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -197,6 +197,7 @@ struct intel_display_power_domain_set {
> for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
> for_each_if(BIT_ULL(domain) & (mask))
>
> +/* intel_display_power.c */
> int intel_power_domains_init(struct drm_i915_private *dev_priv);
> void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
> void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
> @@ -316,4 +317,8 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
> bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> enum dpio_channel ch, bool override);
>
> +/* intel_display_power_map.c */
> +const char *
> +intel_display_power_domain_str(enum intel_display_power_domain domain);
> +
> #endif /* __INTEL_DISPLAY_POWER_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> new file mode 100644
> index 0000000000000..3fc7c7d0bc9e9
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> @@ -0,0 +1,93 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DISPLAY_POWER_INTERNAL_H__
> +#define __INTEL_DISPLAY_POWER_INTERNAL_H__
> +
> +#include "i915_reg_defs.h"
> +
> +#include "intel_display.h"
> +#include "intel_display_power.h"
> +
> +struct i915_power_well_regs;
> +
> +/* Power well structure for haswell */
> +struct i915_power_well_desc {
> + const char *name;
> + bool always_on;
> + u64 domains;
> + /* unique identifier for this power well */
> + enum i915_power_well_id id;
> + /*
> + * Arbitraty data associated with this power well. Platform and power
> + * well specific.
> + */
> + union {
> + struct {
> + /*
> + * request/status flag index in the PUNIT power well
> + * control/status registers.
> + */
> + u8 idx;
> + } vlv;
> + struct {
> + enum dpio_phy phy;
> + } bxt;
> + struct {
> + /*
> + * request/status flag index in the power well
> + * constrol/status registers.
> + */
> + u8 idx;
> + /* Mask of pipes whose IRQ logic is backed by the pw */
> + u8 irq_pipe_mask;
> + /*
> + * Instead of waiting for the status bit to ack enables,
> + * just wait a specific amount of time and then consider
> + * the well enabled.
> + */
> + u16 fixed_enable_delay;
> + /* The pw is backing the VGA functionality */
> + bool has_vga:1;
> + bool has_fuses:1;
> + /*
> + * The pw is for an ICL+ TypeC PHY port in
> + * Thunderbolt mode.
> + */
> + bool is_tc_tbt:1;
> + } hsw;
> + };
> + const struct i915_power_well_ops *ops;
> +};
> +
> +struct i915_power_well {
> + const struct i915_power_well_desc *desc;
> + /* power well enable/disable usage count */
> + int count;
> + /* cached hw enabled state */
> + bool hw_enabled;
> +};
> +
> +/* intel_display_power.c */
I've put a lot of effort into splitting our (display) codebase towards
having a 1-to-1 mapping between .c and .h files. This patch adds an odd
split between two headers and two compilation units, and I don't think
it's pretty.
> +extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
> +extern const struct i915_power_well_ops chv_pipe_power_well_ops;
> +extern const struct i915_power_well_ops chv_dpio_cmn_power_well_ops;
> +extern const struct i915_power_well_ops i830_pipes_power_well_ops;
> +extern const struct i915_power_well_ops hsw_power_well_ops;
> +extern const struct i915_power_well_ops hsw_power_well_ops;
> +extern const struct i915_power_well_ops gen9_dc_off_power_well_ops;
> +extern const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops;
> +extern const struct i915_power_well_ops vlv_display_power_well_ops;
> +extern const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops;
> +extern const struct i915_power_well_ops vlv_dpio_power_well_ops;
> +extern const struct i915_power_well_ops icl_ddi_power_well_ops;
> +extern const struct i915_power_well_ops icl_aux_power_well_ops;
> +extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
Also not happy about this. Data is not an interface.
We currently have 20 symbols with extern, and this adds 14 more with a
clear path to add more for new platforms. I'd rather we were heading in
the other direction.
I'm just wondering if the split introduced here is sound. All of the
above would make this turn up when I look for stuff that I think needs
to be refactored. And the commit message does not even say why...
BR,
Jani.
> +
> +/* intel_display_power_map.c */
> +int intel_init_power_wells(struct i915_power_domains *power_domains);
> +void intel_cleanup_power_wells(struct i915_power_domains *power_domains);
> +
> +#endif
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 04/19] drm/i915: Move the power domain->well mappings to intel_display_power_map.c
2022-01-31 12:15 ` Jani Nikula
@ 2022-01-31 16:00 ` Imre Deak
2022-02-01 10:53 ` Jani Nikula
0 siblings, 1 reply; 32+ messages in thread
From: Imre Deak @ 2022-01-31 16:00 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Mon, Jan 31, 2022 at 02:15:25PM +0200, Jani Nikula wrote:
> On Fri, 28 Jan 2022, Imre Deak <imre.deak@intel.com> wrote:
> > Move the list of platform specific power domain -> power well
> > definitions to intel_display_power_map.c. While at it group the
> > platforms' power domain macros with the corresponding power well lists
> > and keep all the power domain lists in the same order (matching the enum
> > order).
> >
> > No functional changes.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>
> The commit message should explain the why.
>
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> > index b30e6133c66d0..a0e68ae691021 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > @@ -197,6 +197,7 @@ struct intel_display_power_domain_set {
> > for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
> > for_each_if(BIT_ULL(domain) & (mask))
> >
> > +/* intel_display_power.c */
> > int intel_power_domains_init(struct drm_i915_private *dev_priv);
> > void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
> > void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
> > @@ -316,4 +317,8 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
> > bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> > enum dpio_channel ch, bool override);
> >
> > +/* intel_display_power_map.c */
> > +const char *
> > +intel_display_power_domain_str(enum intel_display_power_domain domain);
> > +
> > #endif /* __INTEL_DISPLAY_POWER_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> > new file mode 100644
> > index 0000000000000..3fc7c7d0bc9e9
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> > @@ -0,0 +1,93 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2022 Intel Corporation
> > + */
> > +
> > +#ifndef __INTEL_DISPLAY_POWER_INTERNAL_H__
> > +#define __INTEL_DISPLAY_POWER_INTERNAL_H__
> > +
> > +#include "i915_reg_defs.h"
> > +
> > +#include "intel_display.h"
> > +#include "intel_display_power.h"
> > +
> > +struct i915_power_well_regs;
> > +
> > +/* Power well structure for haswell */
> > +struct i915_power_well_desc {
> > + const char *name;
> > + bool always_on;
> > + u64 domains;
> > + /* unique identifier for this power well */
> > + enum i915_power_well_id id;
> > + /*
> > + * Arbitraty data associated with this power well. Platform and power
> > + * well specific.
> > + */
> > + union {
> > + struct {
> > + /*
> > + * request/status flag index in the PUNIT power well
> > + * control/status registers.
> > + */
> > + u8 idx;
> > + } vlv;
> > + struct {
> > + enum dpio_phy phy;
> > + } bxt;
> > + struct {
> > + /*
> > + * request/status flag index in the power well
> > + * constrol/status registers.
> > + */
> > + u8 idx;
> > + /* Mask of pipes whose IRQ logic is backed by the pw */
> > + u8 irq_pipe_mask;
> > + /*
> > + * Instead of waiting for the status bit to ack enables,
> > + * just wait a specific amount of time and then consider
> > + * the well enabled.
> > + */
> > + u16 fixed_enable_delay;
> > + /* The pw is backing the VGA functionality */
> > + bool has_vga:1;
> > + bool has_fuses:1;
> > + /*
> > + * The pw is for an ICL+ TypeC PHY port in
> > + * Thunderbolt mode.
> > + */
> > + bool is_tc_tbt:1;
> > + } hsw;
> > + };
> > + const struct i915_power_well_ops *ops;
> > +};
> > +
> > +struct i915_power_well {
> > + const struct i915_power_well_desc *desc;
> > + /* power well enable/disable usage count */
> > + int count;
> > + /* cached hw enabled state */
> > + bool hw_enabled;
> > +};
> > +
> > +/* intel_display_power.c */
>
> I've put a lot of effort into splitting our (display) codebase towards
> having a 1-to-1 mapping between .c and .h files. This patch adds an odd
> split between two headers and two compilation units, and I don't think
> it's pretty.
This header includes struct definitions used by intel_display_power.c
and intel_display_power_map.c. I don't see why this would be a problem,
there are many other cases where multiple .c files include a header file
for the same reason.
> > +extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
> > +extern const struct i915_power_well_ops chv_pipe_power_well_ops;
> > +extern const struct i915_power_well_ops chv_dpio_cmn_power_well_ops;
> > +extern const struct i915_power_well_ops i830_pipes_power_well_ops;
> > +extern const struct i915_power_well_ops hsw_power_well_ops;
> > +extern const struct i915_power_well_ops hsw_power_well_ops;
> > +extern const struct i915_power_well_ops gen9_dc_off_power_well_ops;
> > +extern const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops;
> > +extern const struct i915_power_well_ops vlv_display_power_well_ops;
> > +extern const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops;
> > +extern const struct i915_power_well_ops vlv_dpio_power_well_ops;
> > +extern const struct i915_power_well_ops icl_ddi_power_well_ops;
> > +extern const struct i915_power_well_ops icl_aux_power_well_ops;
> > +extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
>
> Also not happy about this. Data is not an interface.
>
> We currently have 20 symbols with extern, and this adds 14 more with a
> clear path to add more for new platforms. I'd rather we were heading in
> the other direction.
>
> I'm just wondering if the split introduced here is sound. All of the
> above would make this turn up when I look for stuff that I think needs
> to be refactored. And the commit message does not even say why...
The reason is to reduce the size of intel_display_power.c, to make it
more readable/manageable. The implementation of the power well
enable/disable etc. functionality and the mapping of these power wells
to power domains are two distinct parts in that file that can be
separated.
The externs above are power wells that are mapped to domains, and
besides the symbol name are opaque to the mapping code.
> BR,
> Jani.
>
>
> > +
> > +/* intel_display_power_map.c */
> > +int intel_init_power_wells(struct i915_power_domains *power_domains);
> > +void intel_cleanup_power_wells(struct i915_power_domains *power_domains);
> > +
> > +#endif
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 04/19] drm/i915: Move the power domain->well mappings to intel_display_power_map.c
2022-01-31 16:00 ` Imre Deak
@ 2022-02-01 10:53 ` Jani Nikula
2022-02-01 11:22 ` Jani Nikula
0 siblings, 1 reply; 32+ messages in thread
From: Jani Nikula @ 2022-02-01 10:53 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, 31 Jan 2022, Imre Deak <imre.deak@intel.com> wrote:
> On Mon, Jan 31, 2022 at 02:15:25PM +0200, Jani Nikula wrote:
>> On Fri, 28 Jan 2022, Imre Deak <imre.deak@intel.com> wrote:
>> > Move the list of platform specific power domain -> power well
>> > definitions to intel_display_power_map.c. While at it group the
>> > platforms' power domain macros with the corresponding power well lists
>> > and keep all the power domain lists in the same order (matching the enum
>> > order).
>> >
>> > No functional changes.
>> >
>> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>>
>> The commit message should explain the why.
>>
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
>> > index b30e6133c66d0..a0e68ae691021 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> > @@ -197,6 +197,7 @@ struct intel_display_power_domain_set {
>> > for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
>> > for_each_if(BIT_ULL(domain) & (mask))
>> >
>> > +/* intel_display_power.c */
>> > int intel_power_domains_init(struct drm_i915_private *dev_priv);
>> > void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
>> > void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
>> > @@ -316,4 +317,8 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
>> > bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
>> > enum dpio_channel ch, bool override);
>> >
>> > +/* intel_display_power_map.c */
>> > +const char *
>> > +intel_display_power_domain_str(enum intel_display_power_domain domain);
>> > +
>> > #endif /* __INTEL_DISPLAY_POWER_H__ */
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
>> > new file mode 100644
>> > index 0000000000000..3fc7c7d0bc9e9
>> > --- /dev/null
>> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
>> > @@ -0,0 +1,93 @@
>> > +/* SPDX-License-Identifier: MIT */
>> > +/*
>> > + * Copyright © 2022 Intel Corporation
>> > + */
>> > +
>> > +#ifndef __INTEL_DISPLAY_POWER_INTERNAL_H__
>> > +#define __INTEL_DISPLAY_POWER_INTERNAL_H__
>> > +
>> > +#include "i915_reg_defs.h"
>> > +
>> > +#include "intel_display.h"
>> > +#include "intel_display_power.h"
>> > +
>> > +struct i915_power_well_regs;
>> > +
>> > +/* Power well structure for haswell */
>> > +struct i915_power_well_desc {
>> > + const char *name;
>> > + bool always_on;
>> > + u64 domains;
>> > + /* unique identifier for this power well */
>> > + enum i915_power_well_id id;
>> > + /*
>> > + * Arbitraty data associated with this power well. Platform and power
>> > + * well specific.
>> > + */
>> > + union {
>> > + struct {
>> > + /*
>> > + * request/status flag index in the PUNIT power well
>> > + * control/status registers.
>> > + */
>> > + u8 idx;
>> > + } vlv;
>> > + struct {
>> > + enum dpio_phy phy;
>> > + } bxt;
>> > + struct {
>> > + /*
>> > + * request/status flag index in the power well
>> > + * constrol/status registers.
>> > + */
>> > + u8 idx;
>> > + /* Mask of pipes whose IRQ logic is backed by the pw */
>> > + u8 irq_pipe_mask;
>> > + /*
>> > + * Instead of waiting for the status bit to ack enables,
>> > + * just wait a specific amount of time and then consider
>> > + * the well enabled.
>> > + */
>> > + u16 fixed_enable_delay;
>> > + /* The pw is backing the VGA functionality */
>> > + bool has_vga:1;
>> > + bool has_fuses:1;
>> > + /*
>> > + * The pw is for an ICL+ TypeC PHY port in
>> > + * Thunderbolt mode.
>> > + */
>> > + bool is_tc_tbt:1;
>> > + } hsw;
>> > + };
>> > + const struct i915_power_well_ops *ops;
>> > +};
>> > +
>> > +struct i915_power_well {
>> > + const struct i915_power_well_desc *desc;
>> > + /* power well enable/disable usage count */
>> > + int count;
>> > + /* cached hw enabled state */
>> > + bool hw_enabled;
>> > +};
>> > +
>> > +/* intel_display_power.c */
>>
>> I've put a lot of effort into splitting our (display) codebase towards
>> having a 1-to-1 mapping between .c and .h files. This patch adds an odd
>> split between two headers and two compilation units, and I don't think
>> it's pretty.
>
> This header includes struct definitions used by intel_display_power.c
> and intel_display_power_map.c. I don't see why this would be a problem,
> there are many other cases where multiple .c files include a header file
> for the same reason.
Declaring types is one thing, but I'd like to have the symbols defined
in intel_foo.c be declared in intel_foo.h, and named intel_foo_*. And by
symbols I mostly mean functions, preferrably nothing else.
IOW, if you have stuff in intel_display_power_map.c, add
intel_display_power_map.h that describes the interface to that file.
>
>> > +extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
>> > +extern const struct i915_power_well_ops chv_pipe_power_well_ops;
>> > +extern const struct i915_power_well_ops chv_dpio_cmn_power_well_ops;
>> > +extern const struct i915_power_well_ops i830_pipes_power_well_ops;
>> > +extern const struct i915_power_well_ops hsw_power_well_ops;
>> > +extern const struct i915_power_well_ops hsw_power_well_ops;
>> > +extern const struct i915_power_well_ops gen9_dc_off_power_well_ops;
>> > +extern const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops;
>> > +extern const struct i915_power_well_ops vlv_display_power_well_ops;
>> > +extern const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops;
>> > +extern const struct i915_power_well_ops vlv_dpio_power_well_ops;
>> > +extern const struct i915_power_well_ops icl_ddi_power_well_ops;
>> > +extern const struct i915_power_well_ops icl_aux_power_well_ops;
>> > +extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
>>
>> Also not happy about this. Data is not an interface.
>>
>> We currently have 20 symbols with extern, and this adds 14 more with a
>> clear path to add more for new platforms. I'd rather we were heading in
>> the other direction.
>>
>> I'm just wondering if the split introduced here is sound. All of the
>> above would make this turn up when I look for stuff that I think needs
>> to be refactored. And the commit message does not even say why...
>
> The reason is to reduce the size of intel_display_power.c, to make it
> more readable/manageable. The implementation of the power well
> enable/disable etc. functionality and the mapping of these power wells
> to power domains are two distinct parts in that file that can be
> separated.
>
> The externs above are power wells that are mapped to domains, and
> besides the symbol name are opaque to the mapping code.
I understand the mapping is a complicated and kind of separate part of
it all. But if I put that aside for a bit, I think I'd consider putting
the abstraction boundary at struct i915_power_well_desc and everything
within.
What would the code look like if struct i915_power_well_desc and
subsequently struct i915_power_well_ops were opaque pointers and split
out of current intel_display_power.c to a separate file? Add functions
to access everything in desc and to call the ops.
Just splitting out the mapping still leaves high and low level code in
the same file, and I think intel_display_power.c would be clarified a
great deal more if the split was between them instead.
Also, intel_display_power_* functions in the file are a kind of separate
set of functionality from the intel_power_domains_* functions. I think
that's a clear candidate for a split too. There's also the dbuf stuff
that probably belongs somewhere else (lots of it in intel_pm.c but
that's another rabbit hole).
Long story short, I think there are other, IMHO cleaner, splits to be
made in intel_display_power.c that should have priority. And they don't
block us from splitting the mapping as follow-up later, but I think that
should not be the first thing.
BR,
Jani.
>
>> BR,
>> Jani.
>>
>>
>> > +
>> > +/* intel_display_power_map.c */
>> > +int intel_init_power_wells(struct i915_power_domains *power_domains);
>> > +void intel_cleanup_power_wells(struct i915_power_domains *power_domains);
>> > +
>> > +#endif
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 09/19] drm/i915: Convert the power well descriptor domain mask to a list
2022-01-28 11:49 ` [Intel-gfx] [PATCH 09/19] drm/i915: Convert the power well descriptor domain mask to a list Imre Deak
@ 2022-02-01 11:10 ` Jani Nikula
2022-02-03 18:11 ` Imre Deak
0 siblings, 1 reply; 32+ messages in thread
From: Jani Nikula @ 2022-02-01 11:10 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On Fri, 28 Jan 2022, Imre Deak <imre.deak@intel.com> wrote:
> The next patch converts the i915_power_well_desc::domain mask from a u64
> mask to a bitmap. I didn't find a reasonably simple way to initialize
> bitmaps statically, so prepare for the next patch here by converting the
> masks to a list and initing the masks from these lists during module
> loading.
I think "list" is a very specific thing in the kernel, and I find the
list naming here confusing.
I'll try to give the initialization thing some thought.
BR,
Jani.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 12 +-
> .../display/intel_display_power_internal.h | 6 +-
> .../i915/display/intel_display_power_map.c | 1426 +++++++++--------
> 3 files changed, 756 insertions(+), 688 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 69b75752258d9..a370ef8376410 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -40,11 +40,11 @@
>
> #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
> for_each_power_well(__dev_priv, __power_well) \
> - for_each_if((__power_well)->desc->domains & (__domain_mask))
> + for_each_if((__power_well)->domains & (__domain_mask))
>
> #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
> for_each_power_well_reverse(__dev_priv, __power_well) \
> - for_each_if((__power_well)->desc->domains & (__domain_mask))
> + for_each_if((__power_well)->domains & (__domain_mask))
>
> struct i915_power_well_regs {
> i915_reg_t bios;
> @@ -465,7 +465,7 @@ static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
> static int power_well_async_ref_count(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - int refs = hweight64(power_well->desc->domains &
> + int refs = hweight64(power_well->domains &
> async_put_domains_mask(&dev_priv->power_domains));
>
> drm_WARN_ON(&dev_priv->drm, refs > power_well->count);
> @@ -3805,7 +3805,7 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
> drm_dbg(&i915->drm, "%-25s %d\n",
> power_well->desc->name, power_well->count);
>
> - for_each_power_domain(domain, power_well->desc->domains)
> + for_each_power_domain(domain, power_well->domains)
> drm_dbg(&i915->drm, " %-23s %d\n",
> intel_display_power_domain_str(domain),
> power_domains->domain_use_count[domain]);
> @@ -3847,7 +3847,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
> power_well->count, enabled);
>
> domains_count = 0;
> - for_each_power_domain(domain, power_well->desc->domains)
> + for_each_power_domain(domain, power_well->domains)
> domains_count += power_domains->domain_use_count[domain];
>
> if (power_well->count != domains_count) {
> @@ -3962,7 +3962,7 @@ void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m
> seq_printf(m, "%-25s %d\n", power_well->desc->name,
> power_well->count);
>
> - for_each_power_domain(power_domain, power_well->desc->domains)
> + for_each_power_domain(power_domain, power_well->domains)
> seq_printf(m, " %-23s %d\n",
> intel_display_power_domain_str(power_domain),
> power_domains->domain_use_count[power_domain]);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> index fd1abb64a8a47..49f6155e62c47 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> @@ -16,7 +16,10 @@ struct i915_power_well_regs;
> /* Power well structure for haswell */
> struct i915_power_well_desc {
> const char *name;
> - u64 domains;
> + const struct i915_power_domain_list {
> + const enum intel_display_power_domain *list;
> + u8 count;
> + } *domain_list;
> /* Mask of pipes whose IRQ logic is backed by the pw */
> u16 irq_pipe_mask:4;
> u16 always_on:1;
> @@ -65,6 +68,7 @@ struct i915_power_well_desc {
>
> struct i915_power_well {
> const struct i915_power_well_desc *desc;
> + u64 domains;
> /* power well enable/disable usage count */
> int count;
> /* cached hw enabled state */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index 773b133902e3d..42f5541c5ecc8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -10,7 +10,24 @@
> #include "intel_display_power.h"
> #include "intel_display_power_internal.h"
>
> -#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
> +#define __LIST_INLINE_ELEMS(__elem_type, ...) \
> + ((__elem_type []){ __VA_ARGS__ })
> +
> +#define __LIST(__elems) { \
> + .list = __elems, \
> + .count = ARRAY_SIZE(__elems), \
> +}
> +
> +#define I915_PW_DOMAINS(...) \
> + (const struct i915_power_domain_list) \
> + __LIST(__LIST_INLINE_ELEMS(enum intel_display_power_domain, __VA_ARGS__))
> +
> +#define I915_DECL_PW_DOMAINS(__name, ...) \
> + static const struct i915_power_domain_list __name = I915_PW_DOMAINS(__VA_ARGS__)
> +
> +/* Zero-length list assigns all power domains, a NULL list assigns none. */
> +#define I915_PW_DOMAINS_NONE NULL
> +#define I915_PW_DOMAINS_ALL /* zero-length list */
>
> const char *
> intel_display_power_domain_str(enum intel_display_power_domain domain)
> @@ -150,68 +167,70 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
> }
> }
>
> +I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
> +
> static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
> {
> .name = "always-on",
> - .domains = POWER_DOMAIN_MASK,
> + .domain_list = &i9xx_pwdoms_always_on,
> .ops = &i9xx_always_on_power_well_ops,
> .always_on = true,
> .id = DISP_PW_ID_NONE,
> },
> };
>
> -#define I830_PIPES_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
> + POWER_DOMAIN_PIPE_A,
> + POWER_DOMAIN_PIPE_B,
> + POWER_DOMAIN_PIPE_PANEL_FITTER_A,
> + POWER_DOMAIN_PIPE_PANEL_FITTER_B,
> + POWER_DOMAIN_TRANSCODER_A,
> + POWER_DOMAIN_TRANSCODER_B,
> + POWER_DOMAIN_INIT);
>
> static const struct i915_power_well_desc i830_power_wells[] = {
> {
> .name = "always-on",
> - .domains = POWER_DOMAIN_MASK,
> + .domain_list = &i9xx_pwdoms_always_on,
> .ops = &i9xx_always_on_power_well_ops,
> .always_on = true,
> .id = DISP_PW_ID_NONE,
> }, {
> .name = "pipes",
> - .domains = I830_PIPES_POWER_DOMAINS,
> + .domain_list = &i830_pwdoms_pipes,
> .ops = &i830_pipes_power_well_ops,
> .id = DISP_PW_ID_NONE,
> },
> };
>
> -#define HSW_DISPLAY_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
> - BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
> + POWER_DOMAIN_PIPE_B,
> + POWER_DOMAIN_PIPE_C,
> + POWER_DOMAIN_PIPE_PANEL_FITTER_A,
> + POWER_DOMAIN_PIPE_PANEL_FITTER_B,
> + POWER_DOMAIN_PIPE_PANEL_FITTER_C,
> + POWER_DOMAIN_TRANSCODER_A,
> + POWER_DOMAIN_TRANSCODER_B,
> + POWER_DOMAIN_TRANSCODER_C,
> + POWER_DOMAIN_PORT_DDI_LANES_B,
> + POWER_DOMAIN_PORT_DDI_LANES_C,
> + POWER_DOMAIN_PORT_DDI_LANES_D,
> + POWER_DOMAIN_PORT_CRT, /* DDI E */
> + POWER_DOMAIN_VGA,
> + POWER_DOMAIN_AUDIO_MMIO,
> + POWER_DOMAIN_AUDIO_PLAYBACK,
> + POWER_DOMAIN_INIT);
>
> static const struct i915_power_well_desc hsw_power_wells[] = {
> {
> .name = "always-on",
> - .domains = POWER_DOMAIN_MASK,
> + .domain_list = &i9xx_pwdoms_always_on,
> .ops = &i9xx_always_on_power_well_ops,
> .always_on = true,
> .id = DISP_PW_ID_NONE,
> }, {
> .name = "display",
> - .domains = HSW_DISPLAY_POWER_DOMAINS,
> + .domain_list = &hsw_pwdoms_display,
> .ops = &hsw_power_well_ops,
> .has_vga = true,
> .id = HSW_DISP_PW_GLOBAL,
> @@ -221,33 +240,33 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
> },
> };
>
> -#define BDW_DISPLAY_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
> - BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
> + POWER_DOMAIN_PIPE_B,
> + POWER_DOMAIN_PIPE_C,
> + POWER_DOMAIN_PIPE_PANEL_FITTER_B,
> + POWER_DOMAIN_PIPE_PANEL_FITTER_C,
> + POWER_DOMAIN_TRANSCODER_A,
> + POWER_DOMAIN_TRANSCODER_B,
> + POWER_DOMAIN_TRANSCODER_C,
> + POWER_DOMAIN_PORT_DDI_LANES_B,
> + POWER_DOMAIN_PORT_DDI_LANES_C,
> + POWER_DOMAIN_PORT_DDI_LANES_D,
> + POWER_DOMAIN_PORT_CRT, /* DDI E */
> + POWER_DOMAIN_VGA,
> + POWER_DOMAIN_AUDIO_MMIO,
> + POWER_DOMAIN_AUDIO_PLAYBACK,
> + POWER_DOMAIN_INIT);
>
> static const struct i915_power_well_desc bdw_power_wells[] = {
> {
> .name = "always-on",
> - .domains = POWER_DOMAIN_MASK,
> + .domain_list = &i9xx_pwdoms_always_on,
> .ops = &i9xx_always_on_power_well_ops,
> .always_on = true,
> .id = DISP_PW_ID_NONE,
> }, {
> .name = "display",
> - .domains = BDW_DISPLAY_POWER_DOMAINS,
> + .domain_list = &bdw_pwdoms_display,
> .ops = &hsw_power_well_ops,
> .has_vga = true,
> .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> @@ -258,64 +277,51 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
> },
> };
>
> -#define VLV_DISPLAY_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> - BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_GMBUS) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
> + POWER_DOMAIN_DISPLAY_CORE,
> + POWER_DOMAIN_PIPE_A,
> + POWER_DOMAIN_PIPE_B,
> + POWER_DOMAIN_PIPE_PANEL_FITTER_A,
> + POWER_DOMAIN_PIPE_PANEL_FITTER_B,
> + POWER_DOMAIN_TRANSCODER_A,
> + POWER_DOMAIN_TRANSCODER_B,
> + POWER_DOMAIN_PORT_DDI_LANES_B,
> + POWER_DOMAIN_PORT_DDI_LANES_C,
> + POWER_DOMAIN_PORT_DSI,
> + POWER_DOMAIN_PORT_CRT,
> + POWER_DOMAIN_VGA,
> + POWER_DOMAIN_AUDIO_MMIO,
> + POWER_DOMAIN_AUDIO_PLAYBACK,
> + POWER_DOMAIN_AUX_B,
> + POWER_DOMAIN_AUX_C,
> + POWER_DOMAIN_GMBUS,
> + POWER_DOMAIN_INIT);
>
> -#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
> + POWER_DOMAIN_PORT_DDI_LANES_B,
> + POWER_DOMAIN_PORT_DDI_LANES_C,
> + POWER_DOMAIN_PORT_CRT,
> + POWER_DOMAIN_AUX_B,
> + POWER_DOMAIN_AUX_C,
> + POWER_DOMAIN_INIT);
>
> -#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
> + POWER_DOMAIN_PORT_DDI_LANES_B,
> + POWER_DOMAIN_PORT_DDI_LANES_C,
> + POWER_DOMAIN_AUX_B,
> + POWER_DOMAIN_AUX_C,
> + POWER_DOMAIN_INIT);
>
> static const struct i915_power_well_desc vlv_power_wells[] = {
> {
> .name = "always-on",
> - .domains = POWER_DOMAIN_MASK,
> + .domain_list = &i9xx_pwdoms_always_on,
> .ops = &i9xx_always_on_power_well_ops,
> .always_on = true,
> .id = DISP_PW_ID_NONE,
> }, {
> .name = "display",
> - .domains = VLV_DISPLAY_POWER_DOMAINS,
> + .domain_list = &vlv_pwdoms_display,
> .ops = &vlv_display_power_well_ops,
> .id = VLV_DISP_PW_DISP2D,
> {
> @@ -323,10 +329,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
> },
> }, {
> .name = "dpio-tx-b-01",
> - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> + .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
> .ops = &vlv_dpio_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -334,10 +337,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
> },
> }, {
> .name = "dpio-tx-b-23",
> - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> + .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
> .ops = &vlv_dpio_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -345,10 +345,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
> },
> }, {
> .name = "dpio-tx-c-01",
> - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> + .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
> .ops = &vlv_dpio_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -356,10 +353,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
> },
> }, {
> .name = "dpio-tx-c-23",
> - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> + .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
> .ops = &vlv_dpio_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -367,7 +361,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
> },
> }, {
> .name = "dpio-common",
> - .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
> + .domain_list = &vlv_pwdoms_dpio_cmn_bc,
> .ops = &vlv_dpio_cmn_power_well_ops,
> .id = VLV_DISP_PW_DPIO_CMN_BC,
> {
> @@ -376,46 +370,46 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
> },
> };
>
> -#define CHV_DISPLAY_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> - BIT_ULL(POWER_DOMAIN_GMBUS) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(chv_pwdoms_display,
> + POWER_DOMAIN_DISPLAY_CORE,
> + POWER_DOMAIN_PIPE_A,
> + POWER_DOMAIN_PIPE_B,
> + POWER_DOMAIN_PIPE_C,
> + POWER_DOMAIN_PIPE_PANEL_FITTER_A,
> + POWER_DOMAIN_PIPE_PANEL_FITTER_B,
> + POWER_DOMAIN_PIPE_PANEL_FITTER_C,
> + POWER_DOMAIN_TRANSCODER_A,
> + POWER_DOMAIN_TRANSCODER_B,
> + POWER_DOMAIN_TRANSCODER_C,
> + POWER_DOMAIN_PORT_DDI_LANES_B,
> + POWER_DOMAIN_PORT_DDI_LANES_C,
> + POWER_DOMAIN_PORT_DDI_LANES_D,
> + POWER_DOMAIN_PORT_DSI,
> + POWER_DOMAIN_VGA,
> + POWER_DOMAIN_AUDIO_MMIO,
> + POWER_DOMAIN_AUDIO_PLAYBACK,
> + POWER_DOMAIN_AUX_B,
> + POWER_DOMAIN_AUX_C,
> + POWER_DOMAIN_AUX_D,
> + POWER_DOMAIN_GMBUS,
> + POWER_DOMAIN_INIT);
>
> -#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
> + POWER_DOMAIN_PORT_DDI_LANES_B,
> + POWER_DOMAIN_PORT_DDI_LANES_C,
> + POWER_DOMAIN_AUX_B,
> + POWER_DOMAIN_AUX_C,
> + POWER_DOMAIN_INIT);
>
> -#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
> - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
> + POWER_DOMAIN_PORT_DDI_LANES_D,
> + POWER_DOMAIN_AUX_D,
> + POWER_DOMAIN_INIT);
>
> static const struct i915_power_well_desc chv_power_wells[] = {
> {
> .name = "always-on",
> - .domains = POWER_DOMAIN_MASK,
> + .domain_list = &i9xx_pwdoms_always_on,
> .ops = &i9xx_always_on_power_well_ops,
> .always_on = true,
> .id = DISP_PW_ID_NONE,
> @@ -426,12 +420,12 @@ static const struct i915_power_well_desc chv_power_wells[] = {
> * power wells don't actually exist. Pipe A power well is
> * required for any pipe to work.
> */
> - .domains = CHV_DISPLAY_POWER_DOMAINS,
> + .domain_list = &chv_pwdoms_display,
> .ops = &chv_pipe_power_well_ops,
> .id = DISP_PW_ID_NONE,
> }, {
> .name = "dpio-common-bc",
> - .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
> + .domain_list = &chv_pwdoms_dpio_cmn_bc,
> .ops = &chv_dpio_cmn_power_well_ops,
> .id = VLV_DISP_PW_DPIO_CMN_BC,
> {
> @@ -439,7 +433,7 @@ static const struct i915_power_well_desc chv_power_wells[] = {
> },
> }, {
> .name = "dpio-common-d",
> - .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
> + .domain_list = &chv_pwdoms_dpio_cmn_d,
> .ops = &chv_dpio_cmn_power_well_ops,
> .id = CHV_DISP_PW_DPIO_CMN_D,
> {
> @@ -448,61 +442,64 @@ static const struct i915_power_well_desc chv_power_wells[] = {
> },
> };
>
> -#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +#define SKL_PW_2_POWER_DOMAINS \
> + POWER_DOMAIN_PIPE_B, \
> + POWER_DOMAIN_PIPE_C, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
> + POWER_DOMAIN_TRANSCODER_A, \
> + POWER_DOMAIN_TRANSCODER_B, \
> + POWER_DOMAIN_TRANSCODER_C, \
> + POWER_DOMAIN_PORT_DDI_LANES_B, \
> + POWER_DOMAIN_PORT_DDI_LANES_C, \
> + POWER_DOMAIN_PORT_DDI_LANES_D, \
> + POWER_DOMAIN_PORT_DDI_LANES_E, \
> + POWER_DOMAIN_VGA, \
> + POWER_DOMAIN_AUDIO_MMIO, \
> + POWER_DOMAIN_AUDIO_PLAYBACK, \
> + POWER_DOMAIN_AUX_B, \
> + POWER_DOMAIN_AUX_C, \
> + POWER_DOMAIN_AUX_D
>
> -#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2,
> + SKL_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
>
> -#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off,
> + SKL_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_MODESET,
> + POWER_DOMAIN_GT_IRQ,
> + POWER_DOMAIN_INIT);
>
> -#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e,
> + POWER_DOMAIN_PORT_DDI_IO_A,
> + POWER_DOMAIN_PORT_DDI_IO_E,
> + POWER_DOMAIN_INIT);
>
> -#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_b,
> + POWER_DOMAIN_PORT_DDI_IO_B,
> + POWER_DOMAIN_INIT);
>
> -#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_c,
> + POWER_DOMAIN_PORT_DDI_IO_C,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d,
> + POWER_DOMAIN_PORT_DDI_IO_D,
> + POWER_DOMAIN_INIT);
>
> static const struct i915_power_well_desc skl_power_wells[] = {
> {
> .name = "always-on",
> - .domains = POWER_DOMAIN_MASK,
> + .domain_list = &i9xx_pwdoms_always_on,
> .ops = &i9xx_always_on_power_well_ops,
> .always_on = true,
> .id = DISP_PW_ID_NONE,
> }, {
> .name = "PW_1",
> /* Handled by the DMC firmware */
> - .domains = 0,
> + .domain_list = I915_PW_DOMAINS_NONE,
> .ops = &hsw_power_well_ops,
> .always_on = true,
> .has_fuses = true,
> @@ -513,7 +510,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> }, {
> .name = "MISC_IO",
> /* Handled by the DMC firmware */
> - .domains = 0,
> + .domain_list = I915_PW_DOMAINS_NONE,
> .ops = &hsw_power_well_ops,
> .always_on = true,
> .id = SKL_DISP_PW_MISC_IO,
> @@ -522,12 +519,12 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> },
> }, {
> .name = "DC_off",
> - .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .domain_list = &skl_pwdoms_dc_off,
> .ops = &gen9_dc_off_power_well_ops,
> .id = SKL_DISP_DC_OFF,
> }, {
> .name = "PW_2",
> - .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> + .domain_list = &skl_pwdoms_pw_2,
> .ops = &hsw_power_well_ops,
> .has_vga = true,
> .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> @@ -538,7 +535,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_A_E",
> - .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
> + .domain_list = &skl_pwdoms_ddi_io_a_e,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -546,7 +543,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_B",
> - .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
> + .domain_list = &skl_pwdoms_ddi_io_b,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -554,7 +551,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_C",
> - .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
> + .domain_list = &skl_pwdoms_ddi_io_c,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -562,7 +559,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_D",
> - .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
> + .domain_list = &skl_pwdoms_ddi_io_d,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -571,54 +568,57 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> },
> };
>
> -#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +#define BXT_PW_2_POWER_DOMAINS \
> + POWER_DOMAIN_PIPE_B, \
> + POWER_DOMAIN_PIPE_C, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
> + POWER_DOMAIN_TRANSCODER_A, \
> + POWER_DOMAIN_TRANSCODER_B, \
> + POWER_DOMAIN_TRANSCODER_C, \
> + POWER_DOMAIN_PORT_DDI_LANES_B, \
> + POWER_DOMAIN_PORT_DDI_LANES_C, \
> + POWER_DOMAIN_VGA, \
> + POWER_DOMAIN_AUDIO_MMIO, \
> + POWER_DOMAIN_AUDIO_PLAYBACK, \
> + POWER_DOMAIN_AUX_B, \
> + POWER_DOMAIN_AUX_C
>
> -#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_GMBUS) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(bxt_pwdoms_pw_2,
> + BXT_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
>
> -#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off,
> + BXT_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_GMBUS,
> + POWER_DOMAIN_MODESET,
> + POWER_DOMAIN_GT_IRQ,
> + POWER_DOMAIN_INIT);
>
> -#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
> + POWER_DOMAIN_PORT_DDI_LANES_A,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
> + POWER_DOMAIN_PORT_DDI_LANES_B,
> + POWER_DOMAIN_PORT_DDI_LANES_C,
> + POWER_DOMAIN_AUX_B,
> + POWER_DOMAIN_AUX_C,
> + POWER_DOMAIN_INIT);
>
> static const struct i915_power_well_desc bxt_power_wells[] = {
> {
> .name = "always-on",
> - .domains = POWER_DOMAIN_MASK,
> + .domain_list = &i9xx_pwdoms_always_on,
> .ops = &i9xx_always_on_power_well_ops,
> .always_on = true,
> .id = DISP_PW_ID_NONE,
> }, {
> .name = "PW_1",
> /* Handled by the DMC firmware */
> - .domains = 0,
> + .domain_list = I915_PW_DOMAINS_NONE,
> .ops = &hsw_power_well_ops,
> .always_on = true,
> .has_fuses = true,
> @@ -628,12 +628,12 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
> },
> }, {
> .name = "DC_off",
> - .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .domain_list = &bxt_pwdoms_dc_off,
> .ops = &gen9_dc_off_power_well_ops,
> .id = SKL_DISP_DC_OFF,
> }, {
> .name = "PW_2",
> - .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> + .domain_list = &bxt_pwdoms_pw_2,
> .ops = &hsw_power_well_ops,
> .has_vga = true,
> .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> @@ -644,7 +644,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
> },
> }, {
> .name = "dpio-common-a",
> - .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
> + .domain_list = &bxt_pwdoms_dpio_cmn_a,
> .ops = &bxt_dpio_cmn_power_well_ops,
> .id = BXT_DISP_PW_DPIO_CMN_A,
> {
> @@ -652,7 +652,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
> },
> }, {
> .name = "dpio-common-bc",
> - .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
> + .domain_list = &bxt_pwdoms_dpio_cmn_bc,
> .ops = &bxt_dpio_cmn_power_well_ops,
> .id = VLV_DISP_PW_DPIO_CMN_BC,
> {
> @@ -661,74 +661,77 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
> },
> };
>
> -#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_GMBUS) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
> -#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
> -#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
> -
> -#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +#define GLK_PW_2_POWER_DOMAINS \
> + POWER_DOMAIN_PIPE_B, \
> + POWER_DOMAIN_PIPE_C, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
> + POWER_DOMAIN_TRANSCODER_A, \
> + POWER_DOMAIN_TRANSCODER_B, \
> + POWER_DOMAIN_TRANSCODER_C, \
> + POWER_DOMAIN_PORT_DDI_LANES_B, \
> + POWER_DOMAIN_PORT_DDI_LANES_C, \
> + POWER_DOMAIN_VGA, \
> + POWER_DOMAIN_AUDIO_MMIO, \
> + POWER_DOMAIN_AUDIO_PLAYBACK, \
> + POWER_DOMAIN_AUX_B, \
> + POWER_DOMAIN_AUX_C
> +
> +I915_DECL_PW_DOMAINS(glk_pwdoms_pw_2,
> + GLK_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off,
> + GLK_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_GMBUS,
> + POWER_DOMAIN_MODESET,
> + POWER_DOMAIN_GT_IRQ,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A);
> +I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B);
> +I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C);
> +
> +I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
> + POWER_DOMAIN_PORT_DDI_LANES_A,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
> + POWER_DOMAIN_PORT_DDI_LANES_B,
> + POWER_DOMAIN_AUX_B,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
> + POWER_DOMAIN_PORT_DDI_LANES_C,
> + POWER_DOMAIN_AUX_C,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_AUX_IO_A,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
> + POWER_DOMAIN_AUX_B,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
> + POWER_DOMAIN_AUX_C,
> + POWER_DOMAIN_INIT);
>
> static const struct i915_power_well_desc glk_power_wells[] = {
> {
> .name = "always-on",
> - .domains = POWER_DOMAIN_MASK,
> + .domain_list = &i9xx_pwdoms_always_on,
> .ops = &i9xx_always_on_power_well_ops,
> .always_on = true,
> .id = DISP_PW_ID_NONE,
> }, {
> .name = "PW_1",
> /* Handled by the DMC firmware */
> - .domains = 0,
> + .domain_list = I915_PW_DOMAINS_NONE,
> .ops = &hsw_power_well_ops,
> .always_on = true,
> .has_fuses = true,
> @@ -738,12 +741,12 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> },
> }, {
> .name = "DC_off",
> - .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .domain_list = &glk_pwdoms_dc_off,
> .ops = &gen9_dc_off_power_well_ops,
> .id = SKL_DISP_DC_OFF,
> }, {
> .name = "PW_2",
> - .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> + .domain_list = &glk_pwdoms_pw_2,
> .ops = &hsw_power_well_ops,
> .has_vga = true,
> .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> @@ -754,7 +757,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> },
> }, {
> .name = "dpio-common-a",
> - .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
> + .domain_list = &glk_pwdoms_dpio_cmn_a,
> .ops = &bxt_dpio_cmn_power_well_ops,
> .id = BXT_DISP_PW_DPIO_CMN_A,
> {
> @@ -762,7 +765,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> },
> }, {
> .name = "dpio-common-b",
> - .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
> + .domain_list = &glk_pwdoms_dpio_cmn_b,
> .ops = &bxt_dpio_cmn_power_well_ops,
> .id = VLV_DISP_PW_DPIO_CMN_BC,
> {
> @@ -770,7 +773,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> },
> }, {
> .name = "dpio-common-c",
> - .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
> + .domain_list = &glk_pwdoms_dpio_cmn_c,
> .ops = &bxt_dpio_cmn_power_well_ops,
> .id = GLK_DISP_PW_DPIO_CMN_C,
> {
> @@ -778,7 +781,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> },
> }, {
> .name = "AUX_A",
> - .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
> + .domain_list = &glk_pwdoms_aux_a,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -786,7 +789,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> },
> }, {
> .name = "AUX_B",
> - .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
> + .domain_list = &glk_pwdoms_aux_b,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -794,7 +797,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> },
> }, {
> .name = "AUX_C",
> - .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
> + .domain_list = &glk_pwdoms_aux_c,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -802,7 +805,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_A",
> - .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
> + .domain_list = &glk_pwdoms_ddi_io_a,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -810,7 +813,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_B",
> - .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
> + .domain_list = &glk_pwdoms_ddi_io_b,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -818,7 +821,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_C",
> - .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
> + .domain_list = &glk_pwdoms_ddi_io_c,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -841,89 +844,97 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> * - DDI_A
> * - FBC
> */
> -#define ICL_PW_4_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +#define ICL_PW_4_POWER_DOMAINS \
> + POWER_DOMAIN_PIPE_C, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_C
> +
> +I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
> + ICL_PW_4_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
> /* VDSC/joining */
>
> -#define ICL_PW_3_POWER_DOMAINS ( \
> - ICL_PW_4_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_F) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> - BIT_ULL(POWER_DOMAIN_AUX_E) | \
> - BIT_ULL(POWER_DOMAIN_AUX_F) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT_D) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT_E) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT_F) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +#define ICL_PW_3_POWER_DOMAINS \
> + ICL_PW_4_POWER_DOMAINS, \
> + POWER_DOMAIN_PIPE_B, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> + POWER_DOMAIN_TRANSCODER_A, \
> + POWER_DOMAIN_TRANSCODER_B, \
> + POWER_DOMAIN_TRANSCODER_C, \
> + POWER_DOMAIN_PORT_DDI_LANES_B, \
> + POWER_DOMAIN_PORT_DDI_LANES_C, \
> + POWER_DOMAIN_PORT_DDI_LANES_D, \
> + POWER_DOMAIN_PORT_DDI_LANES_E, \
> + POWER_DOMAIN_PORT_DDI_LANES_F, \
> + POWER_DOMAIN_VGA, \
> + POWER_DOMAIN_AUDIO_MMIO, \
> + POWER_DOMAIN_AUDIO_PLAYBACK, \
> + POWER_DOMAIN_AUX_B, \
> + POWER_DOMAIN_AUX_C, \
> + POWER_DOMAIN_AUX_D, \
> + POWER_DOMAIN_AUX_E, \
> + POWER_DOMAIN_AUX_F, \
> + POWER_DOMAIN_AUX_TBT_C, \
> + POWER_DOMAIN_AUX_TBT_D, \
> + POWER_DOMAIN_AUX_TBT_E, \
> + POWER_DOMAIN_AUX_TBT_F
> +
> +I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3,
> + ICL_PW_3_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
> /*
> * - transcoder WD
> * - KVMR (HW control)
> */
>
> -#define ICL_PW_2_POWER_DOMAINS ( \
> - ICL_PW_3_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +#define ICL_PW_2_POWER_DOMAINS \
> + ICL_PW_3_POWER_DOMAINS, \
> + POWER_DOMAIN_TRANSCODER_VDSC_PW2
> +
> +I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2,
> + ICL_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
> /*
> * - KVMR (HW control)
> */
>
> -#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - ICL_PW_2_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_DC_OFF) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off,
> + ICL_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_MODESET,
> + POWER_DOMAIN_DC_OFF,
> + POWER_DOMAIN_INIT);
>
> -#define ICL_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
> -#define ICL_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
> -#define ICL_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
> -#define ICL_DDI_IO_D_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D)
> -#define ICL_DDI_IO_E_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E)
> -#define ICL_DDI_IO_F_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_F)
> +I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d, POWER_DOMAIN_PORT_DDI_IO_D);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e, POWER_DOMAIN_PORT_DDI_IO_E);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f, POWER_DOMAIN_PORT_DDI_IO_F);
>
> -#define ICL_AUX_A_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_IO_A))
> -
> -#define ICL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_B)
> -#define ICL_AUX_C_TC1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C)
> -#define ICL_AUX_D_TC2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D)
> -#define ICL_AUX_E_TC3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E)
> -#define ICL_AUX_F_TC4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F)
> -#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_C)
> -#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_D)
> -#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_E)
> -#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_F)
> +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_AUX_IO_A);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b, POWER_DOMAIN_AUX_B);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d, POWER_DOMAIN_AUX_D);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e, POWER_DOMAIN_AUX_E);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f, POWER_DOMAIN_AUX_F);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT_C);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT_D);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT_E);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT_F);
>
> static const struct i915_power_well_desc icl_power_wells[] = {
> {
> .name = "always-on",
> - .domains = POWER_DOMAIN_MASK,
> + .domain_list = &i9xx_pwdoms_always_on,
> .ops = &i9xx_always_on_power_well_ops,
> .always_on = true,
> .id = DISP_PW_ID_NONE,
> }, {
> .name = "PW_1",
> /* Handled by the DMC firmware */
> - .domains = 0,
> + .domain_list = I915_PW_DOMAINS_NONE,
> .ops = &hsw_power_well_ops,
> .always_on = true,
> .has_fuses = true,
> @@ -933,12 +944,12 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "DC_off",
> - .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_dc_off,
> .ops = &gen9_dc_off_power_well_ops,
> .id = SKL_DISP_DC_OFF,
> }, {
> .name = "PW_2",
> - .domains = ICL_PW_2_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_pw_2,
> .ops = &hsw_power_well_ops,
> .has_fuses = true,
> .id = SKL_DISP_PW_2,
> @@ -947,7 +958,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "PW_3",
> - .domains = ICL_PW_3_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_pw_3,
> .ops = &hsw_power_well_ops,
> .has_vga = true,
> .irq_pipe_mask = BIT(PIPE_B),
> @@ -958,7 +969,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_A",
> - .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_a,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -966,7 +977,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_B",
> - .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_b,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -974,7 +985,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_C",
> - .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_c,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -982,7 +993,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_D",
> - .domains = ICL_DDI_IO_D_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_d,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -990,7 +1001,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_E",
> - .domains = ICL_DDI_IO_E_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_e,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -998,7 +1009,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_F",
> - .domains = ICL_DDI_IO_F_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_f,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1006,7 +1017,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "AUX_A",
> - .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_aux_a,
> .ops = &icl_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1014,7 +1025,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "AUX_B",
> - .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_aux_b,
> .ops = &icl_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1022,7 +1033,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "AUX_C",
> - .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_aux_c,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = false,
> .id = DISP_PW_ID_NONE,
> @@ -1031,7 +1042,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "AUX_D",
> - .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_aux_d,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = false,
> .id = DISP_PW_ID_NONE,
> @@ -1040,7 +1051,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "AUX_E",
> - .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_aux_e,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = false,
> .id = DISP_PW_ID_NONE,
> @@ -1049,7 +1060,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "AUX_F",
> - .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_aux_f,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = false,
> .id = DISP_PW_ID_NONE,
> @@ -1058,7 +1069,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "AUX_TBT1",
> - .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_aux_tbt1,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = true,
> .id = DISP_PW_ID_NONE,
> @@ -1067,7 +1078,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "AUX_TBT2",
> - .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_aux_tbt2,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = true,
> .id = DISP_PW_ID_NONE,
> @@ -1076,7 +1087,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "AUX_TBT3",
> - .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_aux_tbt3,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = true,
> .id = DISP_PW_ID_NONE,
> @@ -1085,7 +1096,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "AUX_TBT4",
> - .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_aux_tbt4,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = true,
> .id = DISP_PW_ID_NONE,
> @@ -1094,7 +1105,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> }, {
> .name = "PW_4",
> - .domains = ICL_PW_4_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_pw_4,
> .ops = &hsw_power_well_ops,
> .irq_pipe_mask = BIT(PIPE_C),
> .has_fuses = true,
> @@ -1105,113 +1116,122 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> },
> };
>
> -#define TGL_PW_5_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_D) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +#define TGL_PW_5_POWER_DOMAINS \
> + POWER_DOMAIN_PIPE_D, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
> + POWER_DOMAIN_TRANSCODER_D
>
> -#define TGL_PW_4_POWER_DOMAINS ( \
> - TGL_PW_5_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_5,
> + TGL_PW_5_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
>
> -#define TGL_PW_3_POWER_DOMAINS ( \
> - TGL_PW_4_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +#define TGL_PW_4_POWER_DOMAINS \
> + TGL_PW_5_POWER_DOMAINS, \
> + POWER_DOMAIN_PIPE_C, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
> + POWER_DOMAIN_TRANSCODER_C
>
> -#define TGL_PW_2_POWER_DOMAINS ( \
> - TGL_PW_3_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_4,
> + TGL_PW_4_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
>
> -#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - TGL_PW_3_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +#define TGL_PW_3_POWER_DOMAINS \
> + TGL_PW_4_POWER_DOMAINS, \
> + POWER_DOMAIN_PIPE_B, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> + POWER_DOMAIN_TRANSCODER_B, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC1, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC2, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC3, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC4, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC5, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC6, \
> + POWER_DOMAIN_VGA, \
> + POWER_DOMAIN_AUDIO_MMIO, \
> + POWER_DOMAIN_AUDIO_PLAYBACK, \
> + POWER_DOMAIN_AUX_USBC1, \
> + POWER_DOMAIN_AUX_USBC2, \
> + POWER_DOMAIN_AUX_USBC3, \
> + POWER_DOMAIN_AUX_USBC4, \
> + POWER_DOMAIN_AUX_USBC5, \
> + POWER_DOMAIN_AUX_USBC6, \
> + POWER_DOMAIN_AUX_TBT1, \
> + POWER_DOMAIN_AUX_TBT2, \
> + POWER_DOMAIN_AUX_TBT3, \
> + POWER_DOMAIN_AUX_TBT4, \
> + POWER_DOMAIN_AUX_TBT5, \
> + POWER_DOMAIN_AUX_TBT6
>
> -#define TGL_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
> -#define TGL_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
> -#define TGL_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
> -#define TGL_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
> -#define TGL_DDI_IO_TC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC5)
> -#define TGL_DDI_IO_TC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC6)
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_3,
> + TGL_PW_3_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
>
> -#define TGL_AUX_A_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_IO_A))
> -#define TGL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_B)
> -#define TGL_AUX_C_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C)
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_2,
> + TGL_PW_3_POWER_DOMAINS,
> + POWER_DOMAIN_TRANSCODER_VDSC_PW2,
> + POWER_DOMAIN_INIT);
>
> -#define TGL_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
> -#define TGL_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
> -#define TGL_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
> -#define TGL_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
> -#define TGL_AUX_IO_USBC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC5)
> -#define TGL_AUX_IO_USBC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC6)
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off,
> + TGL_PW_3_POWER_DOMAINS,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_AUX_B,
> + POWER_DOMAIN_AUX_C,
> + POWER_DOMAIN_MODESET,
> + POWER_DOMAIN_INIT);
>
> -#define TGL_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
> -#define TGL_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
> -#define TGL_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
> -#define TGL_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
> -#define TGL_AUX_IO_TBT5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT5)
> -#define TGL_AUX_IO_TBT6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT6)
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5, POWER_DOMAIN_PORT_DDI_IO_TC5);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6, POWER_DOMAIN_PORT_DDI_IO_TC6);
>
> -#define TGL_TC_COLD_OFF_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
> - BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_a,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_AUX_IO_A);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_b, POWER_DOMAIN_AUX_B);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
> +
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5, POWER_DOMAIN_AUX_USBC5);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6, POWER_DOMAIN_AUX_USBC6);
> +
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5, POWER_DOMAIN_AUX_TBT5);
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6, POWER_DOMAIN_AUX_TBT6);
> +
> +I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off,
> + POWER_DOMAIN_AUX_USBC1,
> + POWER_DOMAIN_AUX_USBC2,
> + POWER_DOMAIN_AUX_USBC3,
> + POWER_DOMAIN_AUX_USBC4,
> + POWER_DOMAIN_AUX_USBC5,
> + POWER_DOMAIN_AUX_USBC6,
> + POWER_DOMAIN_AUX_TBT1,
> + POWER_DOMAIN_AUX_TBT2,
> + POWER_DOMAIN_AUX_TBT3,
> + POWER_DOMAIN_AUX_TBT4,
> + POWER_DOMAIN_AUX_TBT5,
> + POWER_DOMAIN_AUX_TBT6,
> + POWER_DOMAIN_TC_COLD_OFF);
>
> static const struct i915_power_well_desc tgl_power_wells[] = {
> {
> .name = "always-on",
> - .domains = POWER_DOMAIN_MASK,
> + .domain_list = &i9xx_pwdoms_always_on,
> .ops = &i9xx_always_on_power_well_ops,
> .always_on = true,
> .id = DISP_PW_ID_NONE,
> }, {
> .name = "PW_1",
> /* Handled by the DMC firmware */
> - .domains = 0,
> + .domain_list = I915_PW_DOMAINS_NONE,
> .ops = &hsw_power_well_ops,
> .always_on = true,
> .has_fuses = true,
> @@ -1221,12 +1241,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "DC_off",
> - .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_dc_off,
> .ops = &gen9_dc_off_power_well_ops,
> .id = SKL_DISP_DC_OFF,
> }, {
> .name = "PW_2",
> - .domains = TGL_PW_2_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_pw_2,
> .ops = &hsw_power_well_ops,
> .has_fuses = true,
> .id = SKL_DISP_PW_2,
> @@ -1235,7 +1255,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "PW_3",
> - .domains = TGL_PW_3_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_pw_3,
> .ops = &hsw_power_well_ops,
> .has_vga = true,
> .irq_pipe_mask = BIT(PIPE_B),
> @@ -1246,7 +1266,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_A",
> - .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_a,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1254,7 +1274,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_B",
> - .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_b,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1262,7 +1282,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_C",
> - .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_c,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1270,7 +1290,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_TC1",
> - .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_ddi_io_tc1,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1278,7 +1298,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_TC2",
> - .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_ddi_io_tc2,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1286,7 +1306,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_TC3",
> - .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_ddi_io_tc3,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1294,7 +1314,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_TC4",
> - .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_ddi_io_tc4,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1302,7 +1322,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_TC5",
> - .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_ddi_io_tc5,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1310,7 +1330,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_TC6",
> - .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_ddi_io_tc6,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1318,12 +1338,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "TC_cold_off",
> - .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_tc_cold_off,
> .ops = &tgl_tc_cold_off_ops,
> .id = TGL_DISP_PW_TC_COLD_OFF,
> }, {
> .name = "AUX_A",
> - .domains = TGL_AUX_A_IO_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_a,
> .ops = &icl_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1331,7 +1351,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "AUX_B",
> - .domains = TGL_AUX_B_IO_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_b,
> .ops = &icl_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1339,7 +1359,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "AUX_C",
> - .domains = TGL_AUX_C_IO_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_c,
> .ops = &icl_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1347,7 +1367,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "AUX_USBC1",
> - .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_usbc1,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = false,
> .id = DISP_PW_ID_NONE,
> @@ -1356,7 +1376,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "AUX_USBC2",
> - .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_usbc2,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = false,
> .id = DISP_PW_ID_NONE,
> @@ -1365,7 +1385,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "AUX_USBC3",
> - .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_usbc3,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = false,
> .id = DISP_PW_ID_NONE,
> @@ -1374,7 +1394,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "AUX_USBC4",
> - .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_usbc4,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = false,
> .id = DISP_PW_ID_NONE,
> @@ -1383,7 +1403,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "AUX_USBC5",
> - .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_usbc5,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = false,
> .id = DISP_PW_ID_NONE,
> @@ -1392,7 +1412,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "AUX_USBC6",
> - .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_usbc6,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = false,
> .id = DISP_PW_ID_NONE,
> @@ -1401,7 +1421,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "AUX_TBT1",
> - .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_tbt1,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = true,
> .id = DISP_PW_ID_NONE,
> @@ -1410,7 +1430,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "AUX_TBT2",
> - .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_tbt2,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = true,
> .id = DISP_PW_ID_NONE,
> @@ -1419,7 +1439,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "AUX_TBT3",
> - .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_tbt3,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = true,
> .id = DISP_PW_ID_NONE,
> @@ -1428,7 +1448,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "AUX_TBT4",
> - .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_tbt4,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = true,
> .id = DISP_PW_ID_NONE,
> @@ -1437,7 +1457,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "AUX_TBT5",
> - .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_tbt5,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = true,
> .id = DISP_PW_ID_NONE,
> @@ -1446,7 +1466,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "AUX_TBT6",
> - .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_tbt6,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = true,
> .id = DISP_PW_ID_NONE,
> @@ -1455,7 +1475,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> }, {
> .name = "PW_4",
> - .domains = TGL_PW_4_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_pw_4,
> .ops = &hsw_power_well_ops,
> .has_fuses = true,
> .irq_pipe_mask = BIT(PIPE_C),
> @@ -1465,7 +1485,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> }
> }, {
> .name = "PW_5",
> - .domains = TGL_PW_5_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_pw_5,
> .ops = &hsw_power_well_ops,
> .has_fuses = true,
> .irq_pipe_mask = BIT(PIPE_D),
> @@ -1476,25 +1496,31 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> };
>
> -#define RKL_PW_4_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +#define RKL_PW_4_POWER_DOMAINS \
> + POWER_DOMAIN_PIPE_C, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
> + POWER_DOMAIN_TRANSCODER_C
>
> -#define RKL_PW_3_POWER_DOMAINS ( \
> - RKL_PW_4_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_4,
> + RKL_PW_4_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
> +
> +#define RKL_PW_3_POWER_DOMAINS \
> + RKL_PW_4_POWER_DOMAINS, \
> + POWER_DOMAIN_PIPE_B, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> + POWER_DOMAIN_TRANSCODER_B, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC1, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC2, \
> + POWER_DOMAIN_VGA, \
> + POWER_DOMAIN_AUDIO_MMIO, \
> + POWER_DOMAIN_AUDIO_PLAYBACK, \
> + POWER_DOMAIN_AUX_USBC1, \
> + POWER_DOMAIN_AUX_USBC2
> +
> +I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_3,
> + RKL_PW_3_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
>
> /*
> * There is no PW_2/PG_2 on RKL.
> @@ -1517,24 +1543,24 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
> */
>
> -#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - RKL_PW_3_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
> + RKL_PW_3_POWER_DOMAINS,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_AUX_B,
> + POWER_DOMAIN_MODESET,
> + POWER_DOMAIN_INIT);
>
> static const struct i915_power_well_desc rkl_power_wells[] = {
> {
> .name = "always-on",
> - .domains = POWER_DOMAIN_MASK,
> + .domain_list = &i9xx_pwdoms_always_on,
> .ops = &i9xx_always_on_power_well_ops,
> .always_on = true,
> .id = DISP_PW_ID_NONE,
> }, {
> .name = "PW_1",
> /* Handled by the DMC firmware */
> - .domains = 0,
> + .domain_list = I915_PW_DOMAINS_NONE,
> .ops = &hsw_power_well_ops,
> .always_on = true,
> .has_fuses = true,
> @@ -1544,12 +1570,12 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> },
> }, {
> .name = "DC_off",
> - .domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .domain_list = &rkl_pwdoms_dc_off,
> .ops = &gen9_dc_off_power_well_ops,
> .id = SKL_DISP_DC_OFF,
> }, {
> .name = "PW_3",
> - .domains = RKL_PW_3_POWER_DOMAINS,
> + .domain_list = &rkl_pwdoms_pw_3,
> .ops = &hsw_power_well_ops,
> .irq_pipe_mask = BIT(PIPE_B),
> .has_vga = true,
> @@ -1560,7 +1586,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> },
> }, {
> .name = "PW_4",
> - .domains = RKL_PW_4_POWER_DOMAINS,
> + .domain_list = &rkl_pwdoms_pw_4,
> .ops = &hsw_power_well_ops,
> .has_fuses = true,
> .irq_pipe_mask = BIT(PIPE_C),
> @@ -1570,7 +1596,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_A",
> - .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_a,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1578,7 +1604,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_B",
> - .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_b,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1586,7 +1612,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_TC1",
> - .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_ddi_io_tc1,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1594,7 +1620,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_TC2",
> - .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_ddi_io_tc2,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1602,7 +1628,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> },
> }, {
> .name = "AUX_A",
> - .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_aux_a,
> .ops = &icl_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1610,7 +1636,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> },
> }, {
> .name = "AUX_B",
> - .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_aux_b,
> .ops = &icl_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1618,7 +1644,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> },
> }, {
> .name = "AUX_USBC1",
> - .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_usbc1,
> .ops = &icl_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1626,7 +1652,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> },
> }, {
> .name = "AUX_USBC2",
> - .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_usbc2,
> .ops = &icl_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1638,43 +1664,46 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> /*
> * DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
> */
> -#define DG1_PW_3_POWER_DOMAINS ( \
> - TGL_PW_4_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +#define DG1_PW_3_POWER_DOMAINS \
> + TGL_PW_4_POWER_DOMAINS, \
> + POWER_DOMAIN_PIPE_B, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> + POWER_DOMAIN_TRANSCODER_B, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC1, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC2, \
> + POWER_DOMAIN_VGA, \
> + POWER_DOMAIN_AUDIO_PLAYBACK, \
> + POWER_DOMAIN_AUX_USBC1, \
> + POWER_DOMAIN_AUX_USBC2
>
> -#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - DG1_PW_3_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_3,
> + DG1_PW_3_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
>
> -#define DG1_PW_2_POWER_DOMAINS ( \
> - DG1_PW_3_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off,
> + DG1_PW_3_POWER_DOMAINS,
> + POWER_DOMAIN_AUDIO_MMIO,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_AUX_B,
> + POWER_DOMAIN_MODESET,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
> + DG1_PW_3_POWER_DOMAINS,
> + POWER_DOMAIN_TRANSCODER_VDSC_PW2,
> + POWER_DOMAIN_INIT);
>
> static const struct i915_power_well_desc dg1_power_wells[] = {
> {
> .name = "always-on",
> - .domains = POWER_DOMAIN_MASK,
> + .domain_list = &i9xx_pwdoms_always_on,
> .ops = &i9xx_always_on_power_well_ops,
> .always_on = true,
> .id = DISP_PW_ID_NONE,
> }, {
> .name = "PW_1",
> /* Handled by the DMC firmware */
> - .domains = 0,
> + .domain_list = I915_PW_DOMAINS_NONE,
> .ops = &hsw_power_well_ops,
> .always_on = true,
> .has_fuses = true,
> @@ -1684,12 +1713,12 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> },
> }, {
> .name = "DC_off",
> - .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .domain_list = &dg1_pwdoms_dc_off,
> .ops = &gen9_dc_off_power_well_ops,
> .id = SKL_DISP_DC_OFF,
> }, {
> .name = "PW_2",
> - .domains = DG1_PW_2_POWER_DOMAINS,
> + .domain_list = &dg1_pwdoms_pw_2,
> .ops = &hsw_power_well_ops,
> .has_fuses = true,
> .id = SKL_DISP_PW_2,
> @@ -1698,7 +1727,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> },
> }, {
> .name = "PW_3",
> - .domains = DG1_PW_3_POWER_DOMAINS,
> + .domain_list = &dg1_pwdoms_pw_3,
> .ops = &hsw_power_well_ops,
> .irq_pipe_mask = BIT(PIPE_B),
> .has_vga = true,
> @@ -1709,7 +1738,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_A",
> - .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_a,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1717,7 +1746,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_B",
> - .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_b,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1725,7 +1754,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_TC1",
> - .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_ddi_io_tc1,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1733,7 +1762,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_TC2",
> - .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_ddi_io_tc2,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1741,7 +1770,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> },
> }, {
> .name = "AUX_A",
> - .domains = TGL_AUX_A_IO_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_a,
> .ops = &icl_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1749,7 +1778,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> },
> }, {
> .name = "AUX_B",
> - .domains = TGL_AUX_B_IO_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_b,
> .ops = &icl_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1757,7 +1786,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> },
> }, {
> .name = "AUX_USBC1",
> - .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_usbc1,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = false,
> .id = DISP_PW_ID_NONE,
> @@ -1766,7 +1795,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> },
> }, {
> .name = "AUX_USBC2",
> - .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_usbc2,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = false,
> .id = DISP_PW_ID_NONE,
> @@ -1775,7 +1804,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> },
> }, {
> .name = "PW_4",
> - .domains = TGL_PW_4_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_pw_4,
> .ops = &hsw_power_well_ops,
> .has_fuses = true,
> .irq_pipe_mask = BIT(PIPE_C),
> @@ -1785,7 +1814,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> }
> }, {
> .name = "PW_5",
> - .domains = TGL_PW_5_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_pw_5,
> .ops = &hsw_power_well_ops,
> .has_fuses = true,
> .irq_pipe_mask = BIT(PIPE_D),
> @@ -1814,54 +1843,66 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> * to top. This allows pipes to be power gated independently.
> */
>
> -#define XELPD_PW_D_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_D) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define XELPD_PW_C_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define XELPD_PW_B_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define XELPD_PW_A_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define XELPD_PW_2_POWER_DOMAINS ( \
> - XELPD_PW_B_POWER_DOMAINS | \
> - XELPD_PW_C_POWER_DOMAINS | \
> - XELPD_PW_D_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) | \
> - BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +#define XELPD_PW_D_POWER_DOMAINS \
> + POWER_DOMAIN_PIPE_D, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
> + POWER_DOMAIN_TRANSCODER_D
> +
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_d,
> + XELPD_PW_D_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
> +
> +#define XELPD_PW_C_POWER_DOMAINS \
> + POWER_DOMAIN_PIPE_C, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
> + POWER_DOMAIN_TRANSCODER_C
> +
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_c,
> + XELPD_PW_C_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
> +
> +#define XELPD_PW_B_POWER_DOMAINS \
> + POWER_DOMAIN_PIPE_B, \
> + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> + POWER_DOMAIN_TRANSCODER_B
> +
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_b,
> + XELPD_PW_B_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
> + POWER_DOMAIN_PIPE_A,
> + POWER_DOMAIN_PIPE_PANEL_FITTER_A,
> + POWER_DOMAIN_INIT);
> +
> +#define XELPD_PW_2_POWER_DOMAINS \
> + XELPD_PW_B_POWER_DOMAINS, \
> + XELPD_PW_C_POWER_DOMAINS, \
> + XELPD_PW_D_POWER_DOMAINS, \
> + POWER_DOMAIN_PORT_DDI_LANES_C, \
> + POWER_DOMAIN_PORT_DDI_LANES_D_XELPD, \
> + POWER_DOMAIN_PORT_DDI_LANES_E_XELPD, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC1, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC2, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC3, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC4, \
> + POWER_DOMAIN_VGA, \
> + POWER_DOMAIN_AUDIO_PLAYBACK, \
> + POWER_DOMAIN_AUX_C, \
> + POWER_DOMAIN_AUX_D_XELPD, \
> + POWER_DOMAIN_AUX_E_XELPD, \
> + POWER_DOMAIN_AUX_USBC1, \
> + POWER_DOMAIN_AUX_USBC2, \
> + POWER_DOMAIN_AUX_USBC3, \
> + POWER_DOMAIN_AUX_USBC4, \
> + POWER_DOMAIN_AUX_TBT1, \
> + POWER_DOMAIN_AUX_TBT2, \
> + POWER_DOMAIN_AUX_TBT3, \
> + POWER_DOMAIN_AUX_TBT4
> +
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
> + XELPD_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
>
> /*
> * XELPD PW_1/PG_1 domains (under HW/DMC control):
> @@ -1880,45 +1921,46 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> * - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
> */
>
> -#define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - XELPD_PW_2_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
> + XELPD_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_PORT_DSI,
> + POWER_DOMAIN_AUDIO_MMIO,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_AUX_B,
> + POWER_DOMAIN_MODESET,
> + POWER_DOMAIN_INIT);
>
> -#define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
> -#define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
> -#define XELPD_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
> -#define XELPD_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
> -#define XELPD_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
> -#define XELPD_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_d_xelpd, POWER_DOMAIN_AUX_D_XELPD);
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_e_xelpd, POWER_DOMAIN_AUX_E_XELPD);
>
> -#define XELPD_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
> -#define XELPD_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
> -#define XELPD_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
> -#define XELPD_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1);
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2);
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3);
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4);
>
> -#define XELPD_DDI_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D_XELPD)
> -#define XELPD_DDI_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E_XELPD)
> -#define XELPD_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
> -#define XELPD_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
> -#define XELPD_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
> -#define XELPD_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
> +
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_d_xelpd, POWER_DOMAIN_PORT_DDI_IO_D_XELPD);
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_e_xelpd, POWER_DOMAIN_PORT_DDI_IO_E_XELPD);
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1);
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
> +I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
>
> static const struct i915_power_well_desc xelpd_power_wells[] = {
> {
> .name = "always-on",
> - .domains = POWER_DOMAIN_MASK,
> + .domain_list = &i9xx_pwdoms_always_on,
> .ops = &i9xx_always_on_power_well_ops,
> .always_on = true,
> .id = DISP_PW_ID_NONE,
> }, {
> .name = "PW_1",
> /* Handled by the DMC firmware */
> - .domains = 0,
> + .domain_list = I915_PW_DOMAINS_NONE,
> .ops = &hsw_power_well_ops,
> .always_on = true,
> .has_fuses = true,
> @@ -1928,12 +1970,12 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "DC_off",
> - .domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_dc_off,
> .ops = &gen9_dc_off_power_well_ops,
> .id = SKL_DISP_DC_OFF,
> }, {
> .name = "PW_2",
> - .domains = XELPD_PW_2_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_pw_2,
> .ops = &hsw_power_well_ops,
> .has_vga = true,
> .has_fuses = true,
> @@ -1943,7 +1985,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "PW_A",
> - .domains = XELPD_PW_A_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_pw_a,
> .ops = &hsw_power_well_ops,
> .irq_pipe_mask = BIT(PIPE_A),
> .has_fuses = true,
> @@ -1953,7 +1995,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "PW_B",
> - .domains = XELPD_PW_B_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_pw_b,
> .ops = &hsw_power_well_ops,
> .irq_pipe_mask = BIT(PIPE_B),
> .has_fuses = true,
> @@ -1963,7 +2005,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "PW_C",
> - .domains = XELPD_PW_C_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_pw_c,
> .ops = &hsw_power_well_ops,
> .irq_pipe_mask = BIT(PIPE_C),
> .has_fuses = true,
> @@ -1973,7 +2015,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "PW_D",
> - .domains = XELPD_PW_D_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_pw_d,
> .ops = &hsw_power_well_ops,
> .irq_pipe_mask = BIT(PIPE_D),
> .has_fuses = true,
> @@ -1983,7 +2025,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "DDI_IO_A",
> - .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_a,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1991,7 +2033,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_B",
> - .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_b,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -1999,7 +2041,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_C",
> - .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_ddi_io_c,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -2007,7 +2049,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_D_XELPD",
> - .domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_ddi_io_d_xelpd,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -2015,7 +2057,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_E_XELPD",
> - .domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_ddi_io_e_xelpd,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -2023,7 +2065,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_TC1",
> - .domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_ddi_io_tc1,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -2031,7 +2073,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_TC2",
> - .domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_ddi_io_tc2,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -2039,7 +2081,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_TC3",
> - .domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_ddi_io_tc3,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -2047,7 +2089,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> }
> }, {
> .name = "DDI_IO_TC4",
> - .domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_ddi_io_tc4,
> .ops = &icl_ddi_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -2055,7 +2097,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> }
> }, {
> .name = "AUX_A",
> - .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_aux_a,
> .ops = &icl_aux_power_well_ops,
> .fixed_enable_delay = true,
> .id = DISP_PW_ID_NONE,
> @@ -2064,7 +2106,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "AUX_B",
> - .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> + .domain_list = &icl_pwdoms_aux_b,
> .ops = &icl_aux_power_well_ops,
> .fixed_enable_delay = true,
> .id = DISP_PW_ID_NONE,
> @@ -2073,7 +2115,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "AUX_C",
> - .domains = TGL_AUX_C_IO_POWER_DOMAINS,
> + .domain_list = &tgl_pwdoms_aux_c,
> .ops = &icl_aux_power_well_ops,
> .fixed_enable_delay = true,
> .id = DISP_PW_ID_NONE,
> @@ -2082,7 +2124,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "AUX_D_XELPD",
> - .domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_aux_d_xelpd,
> .ops = &icl_aux_power_well_ops,
> .fixed_enable_delay = true,
> .id = DISP_PW_ID_NONE,
> @@ -2091,7 +2133,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "AUX_E_XELPD",
> - .domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_aux_e_xelpd,
> .ops = &icl_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -2099,7 +2141,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "AUX_USBC1",
> - .domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_aux_usbc1,
> .ops = &icl_aux_power_well_ops,
> .fixed_enable_delay = true,
> .id = DISP_PW_ID_NONE,
> @@ -2108,7 +2150,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "AUX_USBC2",
> - .domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_aux_usbc2,
> .ops = &icl_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -2116,7 +2158,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "AUX_USBC3",
> - .domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_aux_usbc3,
> .ops = &icl_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -2124,7 +2166,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "AUX_USBC4",
> - .domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_aux_usbc4,
> .ops = &icl_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -2132,7 +2174,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "AUX_TBT1",
> - .domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_aux_tbt1,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = true,
> .id = DISP_PW_ID_NONE,
> @@ -2141,7 +2183,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "AUX_TBT2",
> - .domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_aux_tbt2,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = true,
> .id = DISP_PW_ID_NONE,
> @@ -2150,7 +2192,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "AUX_TBT3",
> - .domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_aux_tbt3,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = true,
> .id = DISP_PW_ID_NONE,
> @@ -2159,7 +2201,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> }, {
> .name = "AUX_TBT4",
> - .domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
> + .domain_list = &xelpd_pwdoms_aux_tbt4,
> .ops = &icl_aux_power_well_ops,
> .is_tc_tbt = true,
> .id = DISP_PW_ID_NONE,
> @@ -2169,6 +2211,24 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> },
> };
>
> +static void init_power_well_domains(const struct i915_power_well_desc *desc,
> + struct i915_power_well *power_well)
> +{
> + int j;
> +
> + if (!desc->domain_list)
> + return;
> +
> + if (desc->domain_list->count == 0) {
> + power_well->domains = GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0);
> +
> + return;
> + }
> +
> + for (j = 0; j < desc->domain_list->count; j++)
> + power_well->domains |= BIT_ULL(desc->domain_list->list[j]);
> +}
> +
> static int
> __set_power_wells(struct i915_power_domains *power_domains,
> const struct i915_power_well_desc *power_well_descs,
> @@ -2199,9 +2259,13 @@ __set_power_wells(struct i915_power_domains *power_domains,
> if (BIT_ULL(id) & skip_mask)
> continue;
>
> - power_domains->power_wells[plt_idx++].desc =
> + power_domains->power_wells[plt_idx].desc =
> &power_well_descs[i];
>
> + init_power_well_domains(&power_well_descs[i], &power_domains->power_wells[plt_idx]);
> +
> + plt_idx++;
> +
> if (id == DISP_PW_ID_NONE)
> continue;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 10/19] drm/i915: Convert the u64 power well domains mask to a bitmap
2022-01-28 11:49 ` [Intel-gfx] [PATCH 10/19] drm/i915: Convert the u64 power well domains mask to a bitmap Imre Deak
@ 2022-02-01 11:20 ` Jani Nikula
2022-02-03 18:22 ` Imre Deak
0 siblings, 1 reply; 32+ messages in thread
From: Jani Nikula @ 2022-02-01 11:20 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On Fri, 28 Jan 2022, Imre Deak <imre.deak@intel.com> wrote:
> To remove the aliasing of the power domain enum values in a follow-up
> patch in this patchset (requiring a bigger mask) and allow for defining
> additional power domains in the future (at least some upcoming TypeC
> changes requires this) convert the u64 i915_power_well_desc::domains
> mask to a bitmap.
>
> For simplicity I changed the for_each_power_domain_well() macros to
> accept one domain only instead of a mask, as there isn't any current
> user passing multiple domains.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 65 ++++-----
> .../drm/i915/display/intel_display_power.c | 123 +++++++++++-------
> .../drm/i915/display/intel_display_power.h | 16 ++-
> .../display/intel_display_power_internal.h | 2 +-
> .../i915/display/intel_display_power_map.c | 4 +-
> 5 files changed, 119 insertions(+), 91 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 3094cfc668c81..d0b9618383ce3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2372,66 +2372,71 @@ intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
> }
> }
>
> -static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> +static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
> + intel_power_domain_mask_t *mask)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> struct drm_encoder *encoder;
> enum pipe pipe = crtc->pipe;
> - u64 mask;
> +
> + bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
>
> if (!crtc_state->hw.active)
> - return 0;
> + return;
>
> - mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
> - mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(cpu_transcoder));
> + set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
> + set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
> if (crtc_state->pch_pfit.enabled ||
> crtc_state->pch_pfit.force_thru)
> - mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
> + set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
>
> drm_for_each_encoder_mask(encoder, &dev_priv->drm,
> crtc_state->uapi.encoder_mask) {
> struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
>
> - mask |= BIT_ULL(intel_encoder->power_domain);
> + set_bit(intel_encoder->power_domain, mask->bits);
> }
>
> if (HAS_DDI(dev_priv) && crtc_state->has_audio)
> - mask |= BIT_ULL(POWER_DOMAIN_AUDIO_MMIO);
> + set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
>
> if (crtc_state->shared_dpll)
> - mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
> + set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
>
> if (crtc_state->dsc.compression_enable)
> - mask |= BIT_ULL(intel_dsc_power_domain(crtc, cpu_transcoder));
> -
> - return mask;
> + set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
> }
>
> -static u64
> -modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> +static void
> +modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
> + intel_power_domain_mask_t *old_domains)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum intel_display_power_domain domain;
> - u64 domains, new_domains, old_domains;
> + intel_power_domain_mask_t domains, new_domains;
>
> - domains = get_crtc_power_domains(crtc_state);
> + get_crtc_power_domains(crtc_state, &domains);
>
> - new_domains = domains & ~crtc->enabled_power_domains.mask;
> - old_domains = crtc->enabled_power_domains.mask & ~domains;
> + bitmap_andnot(new_domains.bits,
> + domains.bits,
> + crtc->enabled_power_domains.mask.bits,
> + POWER_DOMAIN_NUM);
> + bitmap_andnot(old_domains->bits,
> + crtc->enabled_power_domains.mask.bits,
> + domains.bits,
> + POWER_DOMAIN_NUM);
>
> - for_each_power_domain(domain, new_domains)
> + for_each_power_domain(domain, &new_domains)
> intel_display_power_get_in_set(dev_priv,
> &crtc->enabled_power_domains,
> domain);
> -
> - return old_domains;
> }
>
> static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
> - u64 domains)
> + intel_power_domain_mask_t *domains)
> {
> intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
> &crtc->enabled_power_domains,
> @@ -8628,7 +8633,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> struct intel_crtc *crtc;
> - u64 put_domains[I915_MAX_PIPES] = {};
> + intel_power_domain_mask_t put_domains[I915_MAX_PIPES] = {};
> intel_wakeref_t wakeref = 0;
> int i;
>
> @@ -8645,9 +8650,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> new_crtc_state, i) {
> if (intel_crtc_needs_modeset(new_crtc_state) ||
> new_crtc_state->update_pipe) {
> -
> - put_domains[crtc->pipe] =
> - modeset_get_crtc_power_domains(new_crtc_state);
> + modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
> }
> }
>
> @@ -8746,7 +8749,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> intel_post_plane_update(state, crtc);
>
> - modeset_put_crtc_power_domains(crtc, put_domains[crtc->pipe]);
> + modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
>
> intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
>
> @@ -10702,11 +10705,11 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
> for_each_intel_crtc(dev, crtc) {
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
> - u64 put_domains;
> + intel_power_domain_mask_t put_domains;
>
> - put_domains = modeset_get_crtc_power_domains(crtc_state);
> - if (drm_WARN_ON(dev, put_domains))
> - modeset_put_crtc_power_domains(crtc, put_domains);
> + modeset_get_crtc_power_domains(crtc_state, &put_domains);
> + if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
> + modeset_put_crtc_power_domains(crtc, &put_domains);
> }
>
> intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index a370ef8376410..cf014d79682ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -38,13 +38,13 @@
> (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
> (__power_well)--)
>
> -#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
> +#define for_each_power_domain_well(__dev_priv, __power_well, __domain) \
> for_each_power_well(__dev_priv, __power_well) \
> - for_each_if((__power_well)->domains & (__domain_mask))
> + for_each_if(test_bit((__domain), (__power_well)->domains.bits))
>
> -#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
> +#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \
> for_each_power_well_reverse(__dev_priv, __power_well) \
> - for_each_if((__power_well)->domains & (__domain_mask))
> + for_each_if(test_bit((__domain), (__power_well)->domains.bits))
>
> struct i915_power_well_regs {
> i915_reg_t bios;
> @@ -141,7 +141,7 @@ bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
>
> is_enabled = true;
>
> - for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) {
> + for_each_power_domain_well_reverse(dev_priv, power_well, domain) {
> if (power_well->desc->always_on)
> continue;
>
> @@ -460,13 +460,18 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
>
> #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
>
> -static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
> +static void async_put_domains_mask(struct i915_power_domains *power_domains,
> + intel_power_domain_mask_t *mask);
>
> static int power_well_async_ref_count(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - int refs = hweight64(power_well->domains &
> - async_put_domains_mask(&dev_priv->power_domains));
> + intel_power_domain_mask_t domain_mask;
> + int refs;
> +
> + async_put_domains_mask(&dev_priv->power_domains, &domain_mask);
> + bitmap_and(domain_mask.bits, domain_mask.bits, power_well->domains.bits, POWER_DOMAIN_NUM);
> + refs = bitmap_weight(domain_mask.bits, POWER_DOMAIN_NUM);
>
> drm_WARN_ON(&dev_priv->drm, refs > power_well->count);
>
> @@ -1869,10 +1874,13 @@ static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
> chv_set_pipe_power_well(dev_priv, power_well, false);
> }
>
> -static u64 __async_put_domains_mask(struct i915_power_domains *power_domains)
> +static void __async_put_domains_mask(struct i915_power_domains *power_domains,
> + intel_power_domain_mask_t *mask)
> {
> - return power_domains->async_put_domains[0] |
> - power_domains->async_put_domains[1];
> + bitmap_or(mask->bits,
> + power_domains->async_put_domains[0].bits,
> + power_domains->async_put_domains[1].bits,
> + POWER_DOMAIN_NUM);
> }
>
> #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> @@ -1883,8 +1891,11 @@ assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
> struct drm_i915_private *i915 = container_of(power_domains,
> struct drm_i915_private,
> power_domains);
> - return !drm_WARN_ON(&i915->drm, power_domains->async_put_domains[0] &
> - power_domains->async_put_domains[1]);
> +
> + return !drm_WARN_ON(&i915->drm,
> + bitmap_intersects(power_domains->async_put_domains[0].bits,
> + power_domains->async_put_domains[1].bits,
> + POWER_DOMAIN_NUM));
> }
>
> static bool
> @@ -1893,14 +1904,17 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
> struct drm_i915_private *i915 = container_of(power_domains,
> struct drm_i915_private,
> power_domains);
> + intel_power_domain_mask_t async_put_mask;
> enum intel_display_power_domain domain;
> bool err = false;
>
> err |= !assert_async_put_domain_masks_disjoint(power_domains);
> - err |= drm_WARN_ON(&i915->drm, !!power_domains->async_put_wakeref !=
> - !!__async_put_domains_mask(power_domains));
> + __async_put_domains_mask(power_domains, &async_put_mask);
> + err |= drm_WARN_ON(&i915->drm,
> + !!power_domains->async_put_wakeref !=
> + !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM));
>
> - for_each_power_domain(domain, __async_put_domains_mask(power_domains))
> + for_each_power_domain(domain, &async_put_mask)
> err |= drm_WARN_ON(&i915->drm,
> power_domains->domain_use_count[domain] != 1);
>
> @@ -1908,14 +1922,14 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
> }
>
> static void print_power_domains(struct i915_power_domains *power_domains,
> - const char *prefix, u64 mask)
> + const char *prefix, intel_power_domain_mask_t *mask)
> {
> struct drm_i915_private *i915 = container_of(power_domains,
> struct drm_i915_private,
> power_domains);
> enum intel_display_power_domain domain;
>
> - drm_dbg(&i915->drm, "%s (%lu):\n", prefix, hweight64(mask));
> + drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
> for_each_power_domain(domain, mask)
> drm_dbg(&i915->drm, "%s use_count %d\n",
> intel_display_power_domain_str(domain),
> @@ -1933,9 +1947,9 @@ print_async_put_domains_state(struct i915_power_domains *power_domains)
> power_domains->async_put_wakeref);
>
> print_power_domains(power_domains, "async_put_domains[0]",
> - power_domains->async_put_domains[0]);
> + &power_domains->async_put_domains[0]);
> print_power_domains(power_domains, "async_put_domains[1]",
> - power_domains->async_put_domains[1]);
> + &power_domains->async_put_domains[1]);
> }
>
> static void
> @@ -1959,11 +1973,13 @@ verify_async_put_domains_state(struct i915_power_domains *power_domains)
>
> #endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */
>
> -static u64 async_put_domains_mask(struct i915_power_domains *power_domains)
> +static void async_put_domains_mask(struct i915_power_domains *power_domains,
> + intel_power_domain_mask_t *mask)
> +
> {
> assert_async_put_domain_masks_disjoint(power_domains);
>
> - return __async_put_domains_mask(power_domains);
> + __async_put_domains_mask(power_domains, mask);
> }
>
> static void
> @@ -1972,8 +1988,8 @@ async_put_domains_clear_domain(struct i915_power_domains *power_domains,
> {
> assert_async_put_domain_masks_disjoint(power_domains);
>
> - power_domains->async_put_domains[0] &= ~BIT_ULL(domain);
> - power_domains->async_put_domains[1] &= ~BIT_ULL(domain);
> + clear_bit(domain, power_domains->async_put_domains[0].bits);
> + clear_bit(domain, power_domains->async_put_domains[1].bits);
> }
>
> static bool
> @@ -1981,16 +1997,19 @@ intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
> enum intel_display_power_domain domain)
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> + intel_power_domain_mask_t async_put_mask;
> bool ret = false;
>
> - if (!(async_put_domains_mask(power_domains) & BIT_ULL(domain)))
> + async_put_domains_mask(power_domains, &async_put_mask);
> + if (!test_bit(domain, async_put_mask.bits))
> goto out_verify;
>
> async_put_domains_clear_domain(power_domains, domain);
>
> ret = true;
>
> - if (async_put_domains_mask(power_domains))
> + async_put_domains_mask(power_domains, &async_put_mask);
> + if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM))
> goto out_verify;
>
> cancel_delayed_work(&power_domains->async_put_work);
> @@ -2012,7 +2031,7 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
> if (intel_display_power_grab_async_put_ref(dev_priv, domain))
> return;
>
> - for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
> + for_each_power_domain_well(dev_priv, power_well, domain)
> intel_power_well_get(dev_priv, power_well);
>
> power_domains->domain_use_count[domain]++;
> @@ -2093,20 +2112,22 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
> struct i915_power_domains *power_domains;
> struct i915_power_well *power_well;
> const char *name = intel_display_power_domain_str(domain);
> + intel_power_domain_mask_t async_put_mask;
>
> power_domains = &dev_priv->power_domains;
>
> drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain],
> "Use count on domain %s is already zero\n",
> name);
> + async_put_domains_mask(power_domains, &async_put_mask);
> drm_WARN(&dev_priv->drm,
> - async_put_domains_mask(power_domains) & BIT_ULL(domain),
> + test_bit(domain, async_put_mask.bits),
> "Async disabling of domain %s is pending\n",
> name);
>
> power_domains->domain_use_count[domain]--;
>
> - for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain))
> + for_each_power_domain_well_reverse(dev_priv, power_well, domain)
> intel_power_well_put(dev_priv, power_well);
> }
>
> @@ -2135,7 +2156,7 @@ queue_async_put_domains_work(struct i915_power_domains *power_domains,
> }
>
> static void
> -release_async_put_domains(struct i915_power_domains *power_domains, u64 mask)
> +release_async_put_domains(struct i915_power_domains *power_domains, intel_power_domain_mask_t *mask)
> {
> struct drm_i915_private *dev_priv =
> container_of(power_domains, struct drm_i915_private,
> @@ -2183,12 +2204,15 @@ intel_display_power_put_async_work(struct work_struct *work)
> goto out_verify;
>
> release_async_put_domains(power_domains,
> - power_domains->async_put_domains[0]);
> + &power_domains->async_put_domains[0]);
>
> /* Requeue the work if more domains were async put meanwhile. */
> - if (power_domains->async_put_domains[1]) {
> - power_domains->async_put_domains[0] =
> - fetch_and_zero(&power_domains->async_put_domains[1]);
> + if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) {
> + bitmap_copy(power_domains->async_put_domains[0].bits,
> + power_domains->async_put_domains[1].bits,
> + POWER_DOMAIN_NUM);
> + bitmap_zero(power_domains->async_put_domains[1].bits,
> + POWER_DOMAIN_NUM);
> queue_async_put_domains_work(power_domains,
> fetch_and_zero(&new_work_wakeref));
> } else {
> @@ -2240,9 +2264,9 @@ void __intel_display_power_put_async(struct drm_i915_private *i915,
>
> /* Let a pending work requeue itself or queue a new one. */
> if (power_domains->async_put_wakeref) {
> - power_domains->async_put_domains[1] |= BIT_ULL(domain);
> + set_bit(domain, power_domains->async_put_domains[1].bits);
> } else {
> - power_domains->async_put_domains[0] |= BIT_ULL(domain);
> + set_bit(domain, power_domains->async_put_domains[0].bits);
> queue_async_put_domains_work(power_domains,
> fetch_and_zero(&work_wakeref));
> }
> @@ -2273,6 +2297,7 @@ void __intel_display_power_put_async(struct drm_i915_private *i915,
> void intel_display_power_flush_work(struct drm_i915_private *i915)
> {
> struct i915_power_domains *power_domains = &i915->power_domains;
> + intel_power_domain_mask_t async_put_mask;
> intel_wakeref_t work_wakeref;
>
> mutex_lock(&power_domains->lock);
> @@ -2281,8 +2306,8 @@ void intel_display_power_flush_work(struct drm_i915_private *i915)
> if (!work_wakeref)
> goto out_verify;
>
> - release_async_put_domains(power_domains,
> - async_put_domains_mask(power_domains));
> + async_put_domains_mask(power_domains, &async_put_mask);
> + release_async_put_domains(power_domains, &async_put_mask);
> cancel_delayed_work(&power_domains->async_put_work);
>
> out_verify:
> @@ -2361,13 +2386,13 @@ intel_display_power_get_in_set(struct drm_i915_private *i915,
> {
> intel_wakeref_t __maybe_unused wf;
>
> - drm_WARN_ON(&i915->drm, power_domain_set->mask & BIT_ULL(domain));
> + drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
>
> wf = intel_display_power_get(i915, domain);
> #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> power_domain_set->wakerefs[domain] = wf;
> #endif
> - power_domain_set->mask |= BIT_ULL(domain);
> + set_bit(domain, power_domain_set->mask.bits);
> }
>
> bool
> @@ -2377,7 +2402,7 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
> {
> intel_wakeref_t wf;
>
> - drm_WARN_ON(&i915->drm, power_domain_set->mask & BIT_ULL(domain));
> + drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
>
> wf = intel_display_power_get_if_enabled(i915, domain);
> if (!wf)
> @@ -2386,7 +2411,7 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
> #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> power_domain_set->wakerefs[domain] = wf;
> #endif
> - power_domain_set->mask |= BIT_ULL(domain);
> + set_bit(domain, power_domain_set->mask.bits);
>
> return true;
> }
> @@ -2394,11 +2419,11 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
> void
> intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> struct intel_display_power_domain_set *power_domain_set,
> - u64 mask)
> + intel_power_domain_mask_t *mask)
> {
> enum intel_display_power_domain domain;
>
> - drm_WARN_ON(&i915->drm, mask & ~power_domain_set->mask);
> + drm_WARN_ON(&i915->drm, !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
>
> for_each_power_domain(domain, mask) {
> intel_wakeref_t __maybe_unused wf = -1;
> @@ -2407,7 +2432,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
> #endif
> intel_display_power_put(i915, domain, wf);
> - power_domain_set->mask &= ~BIT_ULL(domain);
> + clear_bit(domain, power_domain_set->mask.bits);
> }
> }
>
> @@ -2711,8 +2736,6 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> dev_priv->dmc.target_dc_state =
> sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
>
> - BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
> -
> mutex_init(&power_domains->lock);
>
> INIT_DELAYED_WORK(&power_domains->async_put_work,
> @@ -3805,7 +3828,7 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
> drm_dbg(&i915->drm, "%-25s %d\n",
> power_well->desc->name, power_well->count);
>
> - for_each_power_domain(domain, power_well->domains)
> + for_each_power_domain(domain, &power_well->domains)
> drm_dbg(&i915->drm, " %-23s %d\n",
> intel_display_power_domain_str(domain),
> power_domains->domain_use_count[domain]);
> @@ -3847,7 +3870,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
> power_well->count, enabled);
>
> domains_count = 0;
> - for_each_power_domain(domain, power_well->domains)
> + for_each_power_domain(domain, &power_well->domains)
> domains_count += power_domains->domain_use_count[domain];
>
> if (power_well->count != domains_count) {
> @@ -3962,7 +3985,7 @@ void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m
> seq_printf(m, "%-25s %d\n", power_well->desc->name,
> power_well->count);
>
> - for_each_power_domain(power_domain, power_well->domains)
> + for_each_power_domain(power_domain, &power_well->domains)
> seq_printf(m, " %-23s %d\n",
> intel_display_power_domain_str(power_domain),
> power_domains->domain_use_count[power_domain]);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index c3232809b95f9..c7155801f9bc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -164,6 +164,8 @@ enum i915_power_well_id {
> ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
> (tran) + POWER_DOMAIN_TRANSCODER_A)
>
> +typedef struct { DECLARE_BITMAP(bits, POWER_DOMAIN_NUM); } intel_power_domain_mask_t;
I think the typedef is overkill here, and they should only be used for
totally opaque objects anyway per coding style.
I guess having the struct makes it easier to manage it in parameters and
declarations, so it would be:
struct intel_power_domain_mask {
DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
};
BR,
Jani.
> +
> struct i915_power_domains {
> /*
> * Power wells needed for initialization at driver init and suspend
> @@ -181,21 +183,21 @@ struct i915_power_domains {
>
> struct delayed_work async_put_work;
> intel_wakeref_t async_put_wakeref;
> - u64 async_put_domains[2];
> + intel_power_domain_mask_t async_put_domains[2];
>
> struct i915_power_well *power_wells;
> };
>
> struct intel_display_power_domain_set {
> - u64 mask;
> + intel_power_domain_mask_t mask;
> #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
> intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
> #endif
> };
>
> -#define for_each_power_domain(domain, mask) \
> - for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
> - for_each_if(BIT_ULL(domain) & (mask))
> +#define for_each_power_domain(__domain, __mask) \
> + for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \
> + for_each_if(test_bit((__domain), (__mask)->bits))
>
> /* intel_display_power.c */
> int intel_power_domains_init(struct drm_i915_private *dev_priv);
> @@ -278,13 +280,13 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
> void
> intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> struct intel_display_power_domain_set *power_domain_set,
> - u64 mask);
> + intel_power_domain_mask_t *mask);
>
> static inline void
> intel_display_power_put_all_in_set(struct drm_i915_private *i915,
> struct intel_display_power_domain_set *power_domain_set)
> {
> - intel_display_power_put_mask_in_set(i915, power_domain_set, power_domain_set->mask);
> + intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
> }
>
> void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> index 49f6155e62c47..c4167ac2f21f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> @@ -68,7 +68,7 @@ struct i915_power_well_desc {
>
> struct i915_power_well {
> const struct i915_power_well_desc *desc;
> - u64 domains;
> + intel_power_domain_mask_t domains;
> /* power well enable/disable usage count */
> int count;
> /* cached hw enabled state */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index 42f5541c5ecc8..7ec4cafec6ba5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -2220,13 +2220,13 @@ static void init_power_well_domains(const struct i915_power_well_desc *desc,
> return;
>
> if (desc->domain_list->count == 0) {
> - power_well->domains = GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0);
> + bitmap_fill(power_well->domains.bits, POWER_DOMAIN_NUM);
>
> return;
> }
>
> for (j = 0; j < desc->domain_list->count; j++)
> - power_well->domains |= BIT_ULL(desc->domain_list->list[j]);
> + set_bit(desc->domain_list->list[j], power_well->domains.bits);
> }
>
> static int
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 04/19] drm/i915: Move the power domain->well mappings to intel_display_power_map.c
2022-02-01 10:53 ` Jani Nikula
@ 2022-02-01 11:22 ` Jani Nikula
2022-02-03 17:57 ` Imre Deak
0 siblings, 1 reply; 32+ messages in thread
From: Jani Nikula @ 2022-02-01 11:22 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Tue, 01 Feb 2022, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Mon, 31 Jan 2022, Imre Deak <imre.deak@intel.com> wrote:
>> On Mon, Jan 31, 2022 at 02:15:25PM +0200, Jani Nikula wrote:
>>> On Fri, 28 Jan 2022, Imre Deak <imre.deak@intel.com> wrote:
>>> > Move the list of platform specific power domain -> power well
>>> > definitions to intel_display_power_map.c. While at it group the
>>> > platforms' power domain macros with the corresponding power well lists
>>> > and keep all the power domain lists in the same order (matching the enum
>>> > order).
>>> >
>>> > No functional changes.
>>> >
>>> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>>>
>>> The commit message should explain the why.
>>>
>>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
>>> > index b30e6133c66d0..a0e68ae691021 100644
>>> > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>>> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>>> > @@ -197,6 +197,7 @@ struct intel_display_power_domain_set {
>>> > for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
>>> > for_each_if(BIT_ULL(domain) & (mask))
>>> >
>>> > +/* intel_display_power.c */
>>> > int intel_power_domains_init(struct drm_i915_private *dev_priv);
>>> > void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
>>> > void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
>>> > @@ -316,4 +317,8 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
>>> > bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
>>> > enum dpio_channel ch, bool override);
>>> >
>>> > +/* intel_display_power_map.c */
>>> > +const char *
>>> > +intel_display_power_domain_str(enum intel_display_power_domain domain);
>>> > +
>>> > #endif /* __INTEL_DISPLAY_POWER_H__ */
>>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
>>> > new file mode 100644
>>> > index 0000000000000..3fc7c7d0bc9e9
>>> > --- /dev/null
>>> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
>>> > @@ -0,0 +1,93 @@
>>> > +/* SPDX-License-Identifier: MIT */
>>> > +/*
>>> > + * Copyright © 2022 Intel Corporation
>>> > + */
>>> > +
>>> > +#ifndef __INTEL_DISPLAY_POWER_INTERNAL_H__
>>> > +#define __INTEL_DISPLAY_POWER_INTERNAL_H__
>>> > +
>>> > +#include "i915_reg_defs.h"
>>> > +
>>> > +#include "intel_display.h"
>>> > +#include "intel_display_power.h"
>>> > +
>>> > +struct i915_power_well_regs;
>>> > +
>>> > +/* Power well structure for haswell */
>>> > +struct i915_power_well_desc {
>>> > + const char *name;
>>> > + bool always_on;
>>> > + u64 domains;
>>> > + /* unique identifier for this power well */
>>> > + enum i915_power_well_id id;
>>> > + /*
>>> > + * Arbitraty data associated with this power well. Platform and power
>>> > + * well specific.
>>> > + */
>>> > + union {
>>> > + struct {
>>> > + /*
>>> > + * request/status flag index in the PUNIT power well
>>> > + * control/status registers.
>>> > + */
>>> > + u8 idx;
>>> > + } vlv;
>>> > + struct {
>>> > + enum dpio_phy phy;
>>> > + } bxt;
>>> > + struct {
>>> > + /*
>>> > + * request/status flag index in the power well
>>> > + * constrol/status registers.
>>> > + */
>>> > + u8 idx;
>>> > + /* Mask of pipes whose IRQ logic is backed by the pw */
>>> > + u8 irq_pipe_mask;
>>> > + /*
>>> > + * Instead of waiting for the status bit to ack enables,
>>> > + * just wait a specific amount of time and then consider
>>> > + * the well enabled.
>>> > + */
>>> > + u16 fixed_enable_delay;
>>> > + /* The pw is backing the VGA functionality */
>>> > + bool has_vga:1;
>>> > + bool has_fuses:1;
>>> > + /*
>>> > + * The pw is for an ICL+ TypeC PHY port in
>>> > + * Thunderbolt mode.
>>> > + */
>>> > + bool is_tc_tbt:1;
>>> > + } hsw;
>>> > + };
>>> > + const struct i915_power_well_ops *ops;
>>> > +};
>>> > +
>>> > +struct i915_power_well {
>>> > + const struct i915_power_well_desc *desc;
>>> > + /* power well enable/disable usage count */
>>> > + int count;
>>> > + /* cached hw enabled state */
>>> > + bool hw_enabled;
>>> > +};
>>> > +
>>> > +/* intel_display_power.c */
>>>
>>> I've put a lot of effort into splitting our (display) codebase towards
>>> having a 1-to-1 mapping between .c and .h files. This patch adds an odd
>>> split between two headers and two compilation units, and I don't think
>>> it's pretty.
>>
>> This header includes struct definitions used by intel_display_power.c
>> and intel_display_power_map.c. I don't see why this would be a problem,
>> there are many other cases where multiple .c files include a header file
>> for the same reason.
>
> Declaring types is one thing, but I'd like to have the symbols defined
> in intel_foo.c be declared in intel_foo.h, and named intel_foo_*. And by
> symbols I mostly mean functions, preferrably nothing else.
>
> IOW, if you have stuff in intel_display_power_map.c, add
> intel_display_power_map.h that describes the interface to that file.
>
>>
>>> > +extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
>>> > +extern const struct i915_power_well_ops chv_pipe_power_well_ops;
>>> > +extern const struct i915_power_well_ops chv_dpio_cmn_power_well_ops;
>>> > +extern const struct i915_power_well_ops i830_pipes_power_well_ops;
>>> > +extern const struct i915_power_well_ops hsw_power_well_ops;
>>> > +extern const struct i915_power_well_ops hsw_power_well_ops;
>>> > +extern const struct i915_power_well_ops gen9_dc_off_power_well_ops;
>>> > +extern const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops;
>>> > +extern const struct i915_power_well_ops vlv_display_power_well_ops;
>>> > +extern const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops;
>>> > +extern const struct i915_power_well_ops vlv_dpio_power_well_ops;
>>> > +extern const struct i915_power_well_ops icl_ddi_power_well_ops;
>>> > +extern const struct i915_power_well_ops icl_aux_power_well_ops;
>>> > +extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
>>>
>>> Also not happy about this. Data is not an interface.
>>>
>>> We currently have 20 symbols with extern, and this adds 14 more with a
>>> clear path to add more for new platforms. I'd rather we were heading in
>>> the other direction.
>>>
>>> I'm just wondering if the split introduced here is sound. All of the
>>> above would make this turn up when I look for stuff that I think needs
>>> to be refactored. And the commit message does not even say why...
>>
>> The reason is to reduce the size of intel_display_power.c, to make it
>> more readable/manageable. The implementation of the power well
>> enable/disable etc. functionality and the mapping of these power wells
>> to power domains are two distinct parts in that file that can be
>> separated.
>>
>> The externs above are power wells that are mapped to domains, and
>> besides the symbol name are opaque to the mapping code.
>
> I understand the mapping is a complicated and kind of separate part of
> it all. But if I put that aside for a bit, I think I'd consider putting
> the abstraction boundary at struct i915_power_well_desc and everything
> within.
>
> What would the code look like if struct i915_power_well_desc and
> subsequently struct i915_power_well_ops were opaque pointers and split
> out of current intel_display_power.c to a separate file? Add functions
> to access everything in desc and to call the ops.
>
> Just splitting out the mapping still leaves high and low level code in
> the same file, and I think intel_display_power.c would be clarified a
> great deal more if the split was between them instead.
>
> Also, intel_display_power_* functions in the file are a kind of separate
> set of functionality from the intel_power_domains_* functions. I think
> that's a clear candidate for a split too. There's also the dbuf stuff
> that probably belongs somewhere else (lots of it in intel_pm.c but
> that's another rabbit hole).
>
> Long story short, I think there are other, IMHO cleaner, splits to be
> made in intel_display_power.c that should have priority. And they don't
> block us from splitting the mapping as follow-up later, but I think that
> should not be the first thing.
PS. Most of the other cleanup and refactoring is also independent of the
split, and should not be blocked if you want to do them first and think
about this.
>
>
> BR,
> Jani.
>
>
>
>>
>>> BR,
>>> Jani.
>>>
>>>
>>> > +
>>> > +/* intel_display_power_map.c */
>>> > +int intel_init_power_wells(struct i915_power_domains *power_domains);
>>> > +void intel_cleanup_power_wells(struct i915_power_domains *power_domains);
>>> > +
>>> > +#endif
>>>
>>> --
>>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 04/19] drm/i915: Move the power domain->well mappings to intel_display_power_map.c
2022-02-01 11:22 ` Jani Nikula
@ 2022-02-03 17:57 ` Imre Deak
0 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-02-03 17:57 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Feb 01, 2022 at 01:22:41PM +0200, Jani Nikula wrote:
> On Tue, 01 Feb 2022, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Mon, 31 Jan 2022, Imre Deak <imre.deak@intel.com> wrote:
> >> On Mon, Jan 31, 2022 at 02:15:25PM +0200, Jani Nikula wrote:
> >>> On Fri, 28 Jan 2022, Imre Deak <imre.deak@intel.com> wrote:
> >>> > Move the list of platform specific power domain -> power well
> >>> > definitions to intel_display_power_map.c. While at it group the
> >>> > platforms' power domain macros with the corresponding power well lists
> >>> > and keep all the power domain lists in the same order (matching the enum
> >>> > order).
> >>> >
> >>> > No functional changes.
> >>> >
> >>> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> >>>
> >>> The commit message should explain the why.
> >>>
> >>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> >>> > index b30e6133c66d0..a0e68ae691021 100644
> >>> > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> >>> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> >>> > @@ -197,6 +197,7 @@ struct intel_display_power_domain_set {
> >>> > for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
> >>> > for_each_if(BIT_ULL(domain) & (mask))
> >>> >
> >>> > +/* intel_display_power.c */
> >>> > int intel_power_domains_init(struct drm_i915_private *dev_priv);
> >>> > void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
> >>> > void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
> >>> > @@ -316,4 +317,8 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
> >>> > bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> >>> > enum dpio_channel ch, bool override);
> >>> >
> >>> > +/* intel_display_power_map.c */
> >>> > +const char *
> >>> > +intel_display_power_domain_str(enum intel_display_power_domain domain);
> >>> > +
> >>> > #endif /* __INTEL_DISPLAY_POWER_H__ */
> >>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> >>> > new file mode 100644
> >>> > index 0000000000000..3fc7c7d0bc9e9
> >>> > --- /dev/null
> >>> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> >>> > @@ -0,0 +1,93 @@
> >>> > +/* SPDX-License-Identifier: MIT */
> >>> > +/*
> >>> > + * Copyright © 2022 Intel Corporation
> >>> > + */
> >>> > +
> >>> > +#ifndef __INTEL_DISPLAY_POWER_INTERNAL_H__
> >>> > +#define __INTEL_DISPLAY_POWER_INTERNAL_H__
> >>> > +
> >>> > +#include "i915_reg_defs.h"
> >>> > +
> >>> > +#include "intel_display.h"
> >>> > +#include "intel_display_power.h"
> >>> > +
> >>> > +struct i915_power_well_regs;
> >>> > +
> >>> > +/* Power well structure for haswell */
> >>> > +struct i915_power_well_desc {
> >>> > + const char *name;
> >>> > + bool always_on;
> >>> > + u64 domains;
> >>> > + /* unique identifier for this power well */
> >>> > + enum i915_power_well_id id;
> >>> > + /*
> >>> > + * Arbitraty data associated with this power well. Platform and power
> >>> > + * well specific.
> >>> > + */
> >>> > + union {
> >>> > + struct {
> >>> > + /*
> >>> > + * request/status flag index in the PUNIT power well
> >>> > + * control/status registers.
> >>> > + */
> >>> > + u8 idx;
> >>> > + } vlv;
> >>> > + struct {
> >>> > + enum dpio_phy phy;
> >>> > + } bxt;
> >>> > + struct {
> >>> > + /*
> >>> > + * request/status flag index in the power well
> >>> > + * constrol/status registers.
> >>> > + */
> >>> > + u8 idx;
> >>> > + /* Mask of pipes whose IRQ logic is backed by the pw */
> >>> > + u8 irq_pipe_mask;
> >>> > + /*
> >>> > + * Instead of waiting for the status bit to ack enables,
> >>> > + * just wait a specific amount of time and then consider
> >>> > + * the well enabled.
> >>> > + */
> >>> > + u16 fixed_enable_delay;
> >>> > + /* The pw is backing the VGA functionality */
> >>> > + bool has_vga:1;
> >>> > + bool has_fuses:1;
> >>> > + /*
> >>> > + * The pw is for an ICL+ TypeC PHY port in
> >>> > + * Thunderbolt mode.
> >>> > + */
> >>> > + bool is_tc_tbt:1;
> >>> > + } hsw;
> >>> > + };
> >>> > + const struct i915_power_well_ops *ops;
> >>> > +};
> >>> > +
> >>> > +struct i915_power_well {
> >>> > + const struct i915_power_well_desc *desc;
> >>> > + /* power well enable/disable usage count */
> >>> > + int count;
> >>> > + /* cached hw enabled state */
> >>> > + bool hw_enabled;
> >>> > +};
> >>> > +
> >>> > +/* intel_display_power.c */
> >>>
> >>> I've put a lot of effort into splitting our (display) codebase towards
> >>> having a 1-to-1 mapping between .c and .h files. This patch adds an odd
> >>> split between two headers and two compilation units, and I don't think
> >>> it's pretty.
> >>
> >> This header includes struct definitions used by intel_display_power.c
> >> and intel_display_power_map.c. I don't see why this would be a problem,
> >> there are many other cases where multiple .c files include a header file
> >> for the same reason.
> >
> > Declaring types is one thing, but I'd like to have the symbols defined
> > in intel_foo.c be declared in intel_foo.h, and named intel_foo_*. And by
> > symbols I mostly mean functions, preferrably nothing else.
>
> > IOW, if you have stuff in intel_display_power_map.c, add
> > intel_display_power_map.h that describes the interface to that file.
Ok, will add the init/cleanup functions to intel_display_power_map.h
instead. I'd still like to have the definition of ops functions/structs
and the mapping of these to domains in separate files (both are a lot of
code/data and distinct), which requires sharing the ops structs between
the two files. However splitting out also the ops functions along with
other power_well_desc/ops accessor functions as you suggest below, this
can be done from the header file belonging to the .c file actually
defining the structs (so there'd be intel_display_power.[ch],
intel_display_power_well.[ch], intel_display_power_map.[ch]).
> >>> > +extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
> >>> > +extern const struct i915_power_well_ops chv_pipe_power_well_ops;
> >>> > +extern const struct i915_power_well_ops chv_dpio_cmn_power_well_ops;
> >>> > +extern const struct i915_power_well_ops i830_pipes_power_well_ops;
> >>> > +extern const struct i915_power_well_ops hsw_power_well_ops;
> >>> > +extern const struct i915_power_well_ops hsw_power_well_ops;
> >>> > +extern const struct i915_power_well_ops gen9_dc_off_power_well_ops;
> >>> > +extern const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops;
> >>> > +extern const struct i915_power_well_ops vlv_display_power_well_ops;
> >>> > +extern const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops;
> >>> > +extern const struct i915_power_well_ops vlv_dpio_power_well_ops;
> >>> > +extern const struct i915_power_well_ops icl_ddi_power_well_ops;
> >>> > +extern const struct i915_power_well_ops icl_aux_power_well_ops;
> >>> > +extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
> >>>
> >>> Also not happy about this. Data is not an interface.
> >>>
> >>> We currently have 20 symbols with extern, and this adds 14 more with a
> >>> clear path to add more for new platforms. I'd rather we were heading in
> >>> the other direction.
> >>>
> >>> I'm just wondering if the split introduced here is sound. All of the
> >>> above would make this turn up when I look for stuff that I think needs
> >>> to be refactored. And the commit message does not even say why...
> >>
> >> The reason is to reduce the size of intel_display_power.c, to make it
> >> more readable/manageable. The implementation of the power well
> >> enable/disable etc. functionality and the mapping of these power wells
> >> to power domains are two distinct parts in that file that can be
> >> separated.
> >>
> >> The externs above are power wells that are mapped to domains, and
> >> besides the symbol name are opaque to the mapping code.
> >
> > I understand the mapping is a complicated and kind of separate part of
> > it all. But if I put that aside for a bit, I think I'd consider putting
> > the abstraction boundary at struct i915_power_well_desc and everything
> > within.
> >
> > What would the code look like if struct i915_power_well_desc and
> > subsequently struct i915_power_well_ops were opaque pointers and split
> > out of current intel_display_power.c to a separate file? Add functions
> > to access everything in desc and to call the ops.
Yes, this makes sense and, still having it in one commit, it looks ok to
me, so can follow up with it.
> > Just splitting out the mapping still leaves high and low level code in
> > the same file, and I think intel_display_power.c would be clarified a
> > great deal more if the split was between them instead.
Agreed.
> > Also, intel_display_power_* functions in the file are a kind of separate
> > set of functionality from the intel_power_domains_* functions. I think
> > that's a clear candidate for a split too. There's also the dbuf stuff
> > that probably belongs somewhere else (lots of it in intel_pm.c but
> > that's another rabbit hole).
Yes, sounds ok as well, but I suppose all these could be done as a follow up.
> > Long story short, I think there are other, IMHO cleaner, splits to be
> > made in intel_display_power.c that should have priority. And they don't
> > block us from splitting the mapping as follow-up later, but I think that
> > should not be the first thing.
>
> PS. Most of the other cleanup and refactoring is also independent of the
> split, and should not be blocked if you want to do them first and think
> about this.
I went ahead and did the above refactoring as well as you suggested,
can post it after rebasing on it the rest.
> > BR,
> > Jani.
> >
> >
> >
> >>
> >>> BR,
> >>> Jani.
> >>>
> >>>
> >>> > +
> >>> > +/* intel_display_power_map.c */
> >>> > +int intel_init_power_wells(struct i915_power_domains *power_domains);
> >>> > +void intel_cleanup_power_wells(struct i915_power_domains *power_domains);
> >>> > +
> >>> > +#endif
> >>>
> >>> --
> >>> Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 09/19] drm/i915: Convert the power well descriptor domain mask to a list
2022-02-01 11:10 ` Jani Nikula
@ 2022-02-03 18:11 ` Imre Deak
0 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-02-03 18:11 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Feb 01, 2022 at 01:10:18PM +0200, Jani Nikula wrote:
> On Fri, 28 Jan 2022, Imre Deak <imre.deak@intel.com> wrote:
> > The next patch converts the i915_power_well_desc::domain mask from a u64
> > mask to a bitmap. I didn't find a reasonably simple way to initialize
> > bitmaps statically, so prepare for the next patch here by converting the
> > masks to a list and initing the masks from these lists during module
> > loading.
>
> I think "list" is a very specific thing in the kernel, and I find the
> list naming here confusing.
It's an array of enums, so can call it that way instead.
> I'll try to give the initialization thing some thought.
Just for reference, I tried
https://github.com/ideak/linux/commit/de8daa5362ce
but I didn't find it simple/generic/fast-to-compile enough.
There's also the planned
https://www.mail-archive.com/netdev@vger.kernel.org/msg402394.html
and
https://www.mail-archive.com/netdev@vger.kernel.org/msg402398.html
This one requires disabling some 'struct-field-reinited' warning, not
sure if it's getting merged or not.
--Imre
> BR,
> Jani.
>
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > .../drm/i915/display/intel_display_power.c | 12 +-
> > .../display/intel_display_power_internal.h | 6 +-
> > .../i915/display/intel_display_power_map.c | 1426 +++++++++--------
> > 3 files changed, 756 insertions(+), 688 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 69b75752258d9..a370ef8376410 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -40,11 +40,11 @@
> >
> > #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
> > for_each_power_well(__dev_priv, __power_well) \
> > - for_each_if((__power_well)->desc->domains & (__domain_mask))
> > + for_each_if((__power_well)->domains & (__domain_mask))
> >
> > #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
> > for_each_power_well_reverse(__dev_priv, __power_well) \
> > - for_each_if((__power_well)->desc->domains & (__domain_mask))
> > + for_each_if((__power_well)->domains & (__domain_mask))
> >
> > struct i915_power_well_regs {
> > i915_reg_t bios;
> > @@ -465,7 +465,7 @@ static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
> > static int power_well_async_ref_count(struct drm_i915_private *dev_priv,
> > struct i915_power_well *power_well)
> > {
> > - int refs = hweight64(power_well->desc->domains &
> > + int refs = hweight64(power_well->domains &
> > async_put_domains_mask(&dev_priv->power_domains));
> >
> > drm_WARN_ON(&dev_priv->drm, refs > power_well->count);
> > @@ -3805,7 +3805,7 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
> > drm_dbg(&i915->drm, "%-25s %d\n",
> > power_well->desc->name, power_well->count);
> >
> > - for_each_power_domain(domain, power_well->desc->domains)
> > + for_each_power_domain(domain, power_well->domains)
> > drm_dbg(&i915->drm, " %-23s %d\n",
> > intel_display_power_domain_str(domain),
> > power_domains->domain_use_count[domain]);
> > @@ -3847,7 +3847,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
> > power_well->count, enabled);
> >
> > domains_count = 0;
> > - for_each_power_domain(domain, power_well->desc->domains)
> > + for_each_power_domain(domain, power_well->domains)
> > domains_count += power_domains->domain_use_count[domain];
> >
> > if (power_well->count != domains_count) {
> > @@ -3962,7 +3962,7 @@ void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m
> > seq_printf(m, "%-25s %d\n", power_well->desc->name,
> > power_well->count);
> >
> > - for_each_power_domain(power_domain, power_well->desc->domains)
> > + for_each_power_domain(power_domain, power_well->domains)
> > seq_printf(m, " %-23s %d\n",
> > intel_display_power_domain_str(power_domain),
> > power_domains->domain_use_count[power_domain]);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> > index fd1abb64a8a47..49f6155e62c47 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> > @@ -16,7 +16,10 @@ struct i915_power_well_regs;
> > /* Power well structure for haswell */
> > struct i915_power_well_desc {
> > const char *name;
> > - u64 domains;
> > + const struct i915_power_domain_list {
> > + const enum intel_display_power_domain *list;
> > + u8 count;
> > + } *domain_list;
> > /* Mask of pipes whose IRQ logic is backed by the pw */
> > u16 irq_pipe_mask:4;
> > u16 always_on:1;
> > @@ -65,6 +68,7 @@ struct i915_power_well_desc {
> >
> > struct i915_power_well {
> > const struct i915_power_well_desc *desc;
> > + u64 domains;
> > /* power well enable/disable usage count */
> > int count;
> > /* cached hw enabled state */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > index 773b133902e3d..42f5541c5ecc8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > @@ -10,7 +10,24 @@
> > #include "intel_display_power.h"
> > #include "intel_display_power_internal.h"
> >
> > -#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
> > +#define __LIST_INLINE_ELEMS(__elem_type, ...) \
> > + ((__elem_type []){ __VA_ARGS__ })
> > +
> > +#define __LIST(__elems) { \
> > + .list = __elems, \
> > + .count = ARRAY_SIZE(__elems), \
> > +}
> > +
> > +#define I915_PW_DOMAINS(...) \
> > + (const struct i915_power_domain_list) \
> > + __LIST(__LIST_INLINE_ELEMS(enum intel_display_power_domain, __VA_ARGS__))
> > +
> > +#define I915_DECL_PW_DOMAINS(__name, ...) \
> > + static const struct i915_power_domain_list __name = I915_PW_DOMAINS(__VA_ARGS__)
> > +
> > +/* Zero-length list assigns all power domains, a NULL list assigns none. */
> > +#define I915_PW_DOMAINS_NONE NULL
> > +#define I915_PW_DOMAINS_ALL /* zero-length list */
> >
> > const char *
> > intel_display_power_domain_str(enum intel_display_power_domain domain)
> > @@ -150,68 +167,70 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
> > }
> > }
> >
> > +I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
> > +
> > static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
> > {
> > .name = "always-on",
> > - .domains = POWER_DOMAIN_MASK,
> > + .domain_list = &i9xx_pwdoms_always_on,
> > .ops = &i9xx_always_on_power_well_ops,
> > .always_on = true,
> > .id = DISP_PW_ID_NONE,
> > },
> > };
> >
> > -#define I830_PIPES_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
> > + POWER_DOMAIN_PIPE_A,
> > + POWER_DOMAIN_PIPE_B,
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_A,
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_B,
> > + POWER_DOMAIN_TRANSCODER_A,
> > + POWER_DOMAIN_TRANSCODER_B,
> > + POWER_DOMAIN_INIT);
> >
> > static const struct i915_power_well_desc i830_power_wells[] = {
> > {
> > .name = "always-on",
> > - .domains = POWER_DOMAIN_MASK,
> > + .domain_list = &i9xx_pwdoms_always_on,
> > .ops = &i9xx_always_on_power_well_ops,
> > .always_on = true,
> > .id = DISP_PW_ID_NONE,
> > }, {
> > .name = "pipes",
> > - .domains = I830_PIPES_POWER_DOMAINS,
> > + .domain_list = &i830_pwdoms_pipes,
> > .ops = &i830_pipes_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > },
> > };
> >
> > -#define HSW_DISPLAY_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> > - BIT_ULL(POWER_DOMAIN_VGA) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
> > + POWER_DOMAIN_PIPE_B,
> > + POWER_DOMAIN_PIPE_C,
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_A,
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_B,
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_C,
> > + POWER_DOMAIN_TRANSCODER_A,
> > + POWER_DOMAIN_TRANSCODER_B,
> > + POWER_DOMAIN_TRANSCODER_C,
> > + POWER_DOMAIN_PORT_DDI_LANES_B,
> > + POWER_DOMAIN_PORT_DDI_LANES_C,
> > + POWER_DOMAIN_PORT_DDI_LANES_D,
> > + POWER_DOMAIN_PORT_CRT, /* DDI E */
> > + POWER_DOMAIN_VGA,
> > + POWER_DOMAIN_AUDIO_MMIO,
> > + POWER_DOMAIN_AUDIO_PLAYBACK,
> > + POWER_DOMAIN_INIT);
> >
> > static const struct i915_power_well_desc hsw_power_wells[] = {
> > {
> > .name = "always-on",
> > - .domains = POWER_DOMAIN_MASK,
> > + .domain_list = &i9xx_pwdoms_always_on,
> > .ops = &i9xx_always_on_power_well_ops,
> > .always_on = true,
> > .id = DISP_PW_ID_NONE,
> > }, {
> > .name = "display",
> > - .domains = HSW_DISPLAY_POWER_DOMAINS,
> > + .domain_list = &hsw_pwdoms_display,
> > .ops = &hsw_power_well_ops,
> > .has_vga = true,
> > .id = HSW_DISP_PW_GLOBAL,
> > @@ -221,33 +240,33 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
> > },
> > };
> >
> > -#define BDW_DISPLAY_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> > - BIT_ULL(POWER_DOMAIN_VGA) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
> > + POWER_DOMAIN_PIPE_B,
> > + POWER_DOMAIN_PIPE_C,
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_B,
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_C,
> > + POWER_DOMAIN_TRANSCODER_A,
> > + POWER_DOMAIN_TRANSCODER_B,
> > + POWER_DOMAIN_TRANSCODER_C,
> > + POWER_DOMAIN_PORT_DDI_LANES_B,
> > + POWER_DOMAIN_PORT_DDI_LANES_C,
> > + POWER_DOMAIN_PORT_DDI_LANES_D,
> > + POWER_DOMAIN_PORT_CRT, /* DDI E */
> > + POWER_DOMAIN_VGA,
> > + POWER_DOMAIN_AUDIO_MMIO,
> > + POWER_DOMAIN_AUDIO_PLAYBACK,
> > + POWER_DOMAIN_INIT);
> >
> > static const struct i915_power_well_desc bdw_power_wells[] = {
> > {
> > .name = "always-on",
> > - .domains = POWER_DOMAIN_MASK,
> > + .domain_list = &i9xx_pwdoms_always_on,
> > .ops = &i9xx_always_on_power_well_ops,
> > .always_on = true,
> > .id = DISP_PW_ID_NONE,
> > }, {
> > .name = "display",
> > - .domains = BDW_DISPLAY_POWER_DOMAINS,
> > + .domain_list = &bdw_pwdoms_display,
> > .ops = &hsw_power_well_ops,
> > .has_vga = true,
> > .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> > @@ -258,64 +277,51 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
> > },
> > };
> >
> > -#define VLV_DISPLAY_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
> > - BIT_ULL(POWER_DOMAIN_VGA) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > - BIT_ULL(POWER_DOMAIN_GMBUS) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
> > + POWER_DOMAIN_DISPLAY_CORE,
> > + POWER_DOMAIN_PIPE_A,
> > + POWER_DOMAIN_PIPE_B,
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_A,
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_B,
> > + POWER_DOMAIN_TRANSCODER_A,
> > + POWER_DOMAIN_TRANSCODER_B,
> > + POWER_DOMAIN_PORT_DDI_LANES_B,
> > + POWER_DOMAIN_PORT_DDI_LANES_C,
> > + POWER_DOMAIN_PORT_DSI,
> > + POWER_DOMAIN_PORT_CRT,
> > + POWER_DOMAIN_VGA,
> > + POWER_DOMAIN_AUDIO_MMIO,
> > + POWER_DOMAIN_AUDIO_PLAYBACK,
> > + POWER_DOMAIN_AUX_B,
> > + POWER_DOMAIN_AUX_C,
> > + POWER_DOMAIN_GMBUS,
> > + POWER_DOMAIN_INIT);
> >
> > -#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
> > + POWER_DOMAIN_PORT_DDI_LANES_B,
> > + POWER_DOMAIN_PORT_DDI_LANES_C,
> > + POWER_DOMAIN_PORT_CRT,
> > + POWER_DOMAIN_AUX_B,
> > + POWER_DOMAIN_AUX_C,
> > + POWER_DOMAIN_INIT);
> >
> > -#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > -
> > -#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > -
> > -#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > -
> > -#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
> > + POWER_DOMAIN_PORT_DDI_LANES_B,
> > + POWER_DOMAIN_PORT_DDI_LANES_C,
> > + POWER_DOMAIN_AUX_B,
> > + POWER_DOMAIN_AUX_C,
> > + POWER_DOMAIN_INIT);
> >
> > static const struct i915_power_well_desc vlv_power_wells[] = {
> > {
> > .name = "always-on",
> > - .domains = POWER_DOMAIN_MASK,
> > + .domain_list = &i9xx_pwdoms_always_on,
> > .ops = &i9xx_always_on_power_well_ops,
> > .always_on = true,
> > .id = DISP_PW_ID_NONE,
> > }, {
> > .name = "display",
> > - .domains = VLV_DISPLAY_POWER_DOMAINS,
> > + .domain_list = &vlv_pwdoms_display,
> > .ops = &vlv_display_power_well_ops,
> > .id = VLV_DISP_PW_DISP2D,
> > {
> > @@ -323,10 +329,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
> > },
> > }, {
> > .name = "dpio-tx-b-01",
> > - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> > - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> > - VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> > - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> > + .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
> > .ops = &vlv_dpio_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -334,10 +337,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
> > },
> > }, {
> > .name = "dpio-tx-b-23",
> > - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> > - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> > - VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> > - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> > + .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
> > .ops = &vlv_dpio_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -345,10 +345,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
> > },
> > }, {
> > .name = "dpio-tx-c-01",
> > - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> > - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> > - VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> > - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> > + .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
> > .ops = &vlv_dpio_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -356,10 +353,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
> > },
> > }, {
> > .name = "dpio-tx-c-23",
> > - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> > - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> > - VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> > - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> > + .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
> > .ops = &vlv_dpio_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -367,7 +361,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
> > },
> > }, {
> > .name = "dpio-common",
> > - .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
> > + .domain_list = &vlv_pwdoms_dpio_cmn_bc,
> > .ops = &vlv_dpio_cmn_power_well_ops,
> > .id = VLV_DISP_PW_DPIO_CMN_BC,
> > {
> > @@ -376,46 +370,46 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
> > },
> > };
> >
> > -#define CHV_DISPLAY_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> > - BIT_ULL(POWER_DOMAIN_VGA) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> > - BIT_ULL(POWER_DOMAIN_GMBUS) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(chv_pwdoms_display,
> > + POWER_DOMAIN_DISPLAY_CORE,
> > + POWER_DOMAIN_PIPE_A,
> > + POWER_DOMAIN_PIPE_B,
> > + POWER_DOMAIN_PIPE_C,
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_A,
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_B,
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_C,
> > + POWER_DOMAIN_TRANSCODER_A,
> > + POWER_DOMAIN_TRANSCODER_B,
> > + POWER_DOMAIN_TRANSCODER_C,
> > + POWER_DOMAIN_PORT_DDI_LANES_B,
> > + POWER_DOMAIN_PORT_DDI_LANES_C,
> > + POWER_DOMAIN_PORT_DDI_LANES_D,
> > + POWER_DOMAIN_PORT_DSI,
> > + POWER_DOMAIN_VGA,
> > + POWER_DOMAIN_AUDIO_MMIO,
> > + POWER_DOMAIN_AUDIO_PLAYBACK,
> > + POWER_DOMAIN_AUX_B,
> > + POWER_DOMAIN_AUX_C,
> > + POWER_DOMAIN_AUX_D,
> > + POWER_DOMAIN_GMBUS,
> > + POWER_DOMAIN_INIT);
> >
> > -#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
> > + POWER_DOMAIN_PORT_DDI_LANES_B,
> > + POWER_DOMAIN_PORT_DDI_LANES_C,
> > + POWER_DOMAIN_AUX_B,
> > + POWER_DOMAIN_AUX_C,
> > + POWER_DOMAIN_INIT);
> >
> > -#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
> > + POWER_DOMAIN_PORT_DDI_LANES_D,
> > + POWER_DOMAIN_AUX_D,
> > + POWER_DOMAIN_INIT);
> >
> > static const struct i915_power_well_desc chv_power_wells[] = {
> > {
> > .name = "always-on",
> > - .domains = POWER_DOMAIN_MASK,
> > + .domain_list = &i9xx_pwdoms_always_on,
> > .ops = &i9xx_always_on_power_well_ops,
> > .always_on = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -426,12 +420,12 @@ static const struct i915_power_well_desc chv_power_wells[] = {
> > * power wells don't actually exist. Pipe A power well is
> > * required for any pipe to work.
> > */
> > - .domains = CHV_DISPLAY_POWER_DOMAINS,
> > + .domain_list = &chv_pwdoms_display,
> > .ops = &chv_pipe_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > }, {
> > .name = "dpio-common-bc",
> > - .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
> > + .domain_list = &chv_pwdoms_dpio_cmn_bc,
> > .ops = &chv_dpio_cmn_power_well_ops,
> > .id = VLV_DISP_PW_DPIO_CMN_BC,
> > {
> > @@ -439,7 +433,7 @@ static const struct i915_power_well_desc chv_power_wells[] = {
> > },
> > }, {
> > .name = "dpio-common-d",
> > - .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
> > + .domain_list = &chv_pwdoms_dpio_cmn_d,
> > .ops = &chv_dpio_cmn_power_well_ops,
> > .id = CHV_DISP_PW_DPIO_CMN_D,
> > {
> > @@ -448,61 +442,64 @@ static const struct i915_power_well_desc chv_power_wells[] = {
> > },
> > };
> >
> > -#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
> > - BIT_ULL(POWER_DOMAIN_VGA) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +#define SKL_PW_2_POWER_DOMAINS \
> > + POWER_DOMAIN_PIPE_B, \
> > + POWER_DOMAIN_PIPE_C, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
> > + POWER_DOMAIN_TRANSCODER_A, \
> > + POWER_DOMAIN_TRANSCODER_B, \
> > + POWER_DOMAIN_TRANSCODER_C, \
> > + POWER_DOMAIN_PORT_DDI_LANES_B, \
> > + POWER_DOMAIN_PORT_DDI_LANES_C, \
> > + POWER_DOMAIN_PORT_DDI_LANES_D, \
> > + POWER_DOMAIN_PORT_DDI_LANES_E, \
> > + POWER_DOMAIN_VGA, \
> > + POWER_DOMAIN_AUDIO_MMIO, \
> > + POWER_DOMAIN_AUDIO_PLAYBACK, \
> > + POWER_DOMAIN_AUX_B, \
> > + POWER_DOMAIN_AUX_C, \
> > + POWER_DOMAIN_AUX_D
> >
> > -#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_MODESET) | \
> > - BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2,
> > + SKL_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> >
> > -#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off,
> > + SKL_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_MODESET,
> > + POWER_DOMAIN_GT_IRQ,
> > + POWER_DOMAIN_INIT);
> >
> > -#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e,
> > + POWER_DOMAIN_PORT_DDI_IO_A,
> > + POWER_DOMAIN_PORT_DDI_IO_E,
> > + POWER_DOMAIN_INIT);
> >
> > -#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_b,
> > + POWER_DOMAIN_PORT_DDI_IO_B,
> > + POWER_DOMAIN_INIT);
> >
> > -#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_c,
> > + POWER_DOMAIN_PORT_DDI_IO_C,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d,
> > + POWER_DOMAIN_PORT_DDI_IO_D,
> > + POWER_DOMAIN_INIT);
> >
> > static const struct i915_power_well_desc skl_power_wells[] = {
> > {
> > .name = "always-on",
> > - .domains = POWER_DOMAIN_MASK,
> > + .domain_list = &i9xx_pwdoms_always_on,
> > .ops = &i9xx_always_on_power_well_ops,
> > .always_on = true,
> > .id = DISP_PW_ID_NONE,
> > }, {
> > .name = "PW_1",
> > /* Handled by the DMC firmware */
> > - .domains = 0,
> > + .domain_list = I915_PW_DOMAINS_NONE,
> > .ops = &hsw_power_well_ops,
> > .always_on = true,
> > .has_fuses = true,
> > @@ -513,7 +510,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> > }, {
> > .name = "MISC_IO",
> > /* Handled by the DMC firmware */
> > - .domains = 0,
> > + .domain_list = I915_PW_DOMAINS_NONE,
> > .ops = &hsw_power_well_ops,
> > .always_on = true,
> > .id = SKL_DISP_PW_MISC_IO,
> > @@ -522,12 +519,12 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> > },
> > }, {
> > .name = "DC_off",
> > - .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .domain_list = &skl_pwdoms_dc_off,
> > .ops = &gen9_dc_off_power_well_ops,
> > .id = SKL_DISP_DC_OFF,
> > }, {
> > .name = "PW_2",
> > - .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> > + .domain_list = &skl_pwdoms_pw_2,
> > .ops = &hsw_power_well_ops,
> > .has_vga = true,
> > .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> > @@ -538,7 +535,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_A_E",
> > - .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
> > + .domain_list = &skl_pwdoms_ddi_io_a_e,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -546,7 +543,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_B",
> > - .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
> > + .domain_list = &skl_pwdoms_ddi_io_b,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -554,7 +551,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_C",
> > - .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
> > + .domain_list = &skl_pwdoms_ddi_io_c,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -562,7 +559,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_D",
> > - .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
> > + .domain_list = &skl_pwdoms_ddi_io_d,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -571,54 +568,57 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> > },
> > };
> >
> > -#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> > - BIT_ULL(POWER_DOMAIN_VGA) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +#define BXT_PW_2_POWER_DOMAINS \
> > + POWER_DOMAIN_PIPE_B, \
> > + POWER_DOMAIN_PIPE_C, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
> > + POWER_DOMAIN_TRANSCODER_A, \
> > + POWER_DOMAIN_TRANSCODER_B, \
> > + POWER_DOMAIN_TRANSCODER_C, \
> > + POWER_DOMAIN_PORT_DDI_LANES_B, \
> > + POWER_DOMAIN_PORT_DDI_LANES_C, \
> > + POWER_DOMAIN_VGA, \
> > + POWER_DOMAIN_AUDIO_MMIO, \
> > + POWER_DOMAIN_AUDIO_PLAYBACK, \
> > + POWER_DOMAIN_AUX_B, \
> > + POWER_DOMAIN_AUX_C
> >
> > -#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > - BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_GMBUS) | \
> > - BIT_ULL(POWER_DOMAIN_MODESET) | \
> > - BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(bxt_pwdoms_pw_2,
> > + BXT_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> >
> > -#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off,
> > + BXT_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_GMBUS,
> > + POWER_DOMAIN_MODESET,
> > + POWER_DOMAIN_GT_IRQ,
> > + POWER_DOMAIN_INIT);
> >
> > -#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
> > + POWER_DOMAIN_PORT_DDI_LANES_A,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
> > + POWER_DOMAIN_PORT_DDI_LANES_B,
> > + POWER_DOMAIN_PORT_DDI_LANES_C,
> > + POWER_DOMAIN_AUX_B,
> > + POWER_DOMAIN_AUX_C,
> > + POWER_DOMAIN_INIT);
> >
> > static const struct i915_power_well_desc bxt_power_wells[] = {
> > {
> > .name = "always-on",
> > - .domains = POWER_DOMAIN_MASK,
> > + .domain_list = &i9xx_pwdoms_always_on,
> > .ops = &i9xx_always_on_power_well_ops,
> > .always_on = true,
> > .id = DISP_PW_ID_NONE,
> > }, {
> > .name = "PW_1",
> > /* Handled by the DMC firmware */
> > - .domains = 0,
> > + .domain_list = I915_PW_DOMAINS_NONE,
> > .ops = &hsw_power_well_ops,
> > .always_on = true,
> > .has_fuses = true,
> > @@ -628,12 +628,12 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
> > },
> > }, {
> > .name = "DC_off",
> > - .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .domain_list = &bxt_pwdoms_dc_off,
> > .ops = &gen9_dc_off_power_well_ops,
> > .id = SKL_DISP_DC_OFF,
> > }, {
> > .name = "PW_2",
> > - .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> > + .domain_list = &bxt_pwdoms_pw_2,
> > .ops = &hsw_power_well_ops,
> > .has_vga = true,
> > .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> > @@ -644,7 +644,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
> > },
> > }, {
> > .name = "dpio-common-a",
> > - .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
> > + .domain_list = &bxt_pwdoms_dpio_cmn_a,
> > .ops = &bxt_dpio_cmn_power_well_ops,
> > .id = BXT_DISP_PW_DPIO_CMN_A,
> > {
> > @@ -652,7 +652,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
> > },
> > }, {
> > .name = "dpio-common-bc",
> > - .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
> > + .domain_list = &bxt_pwdoms_dpio_cmn_bc,
> > .ops = &bxt_dpio_cmn_power_well_ops,
> > .id = VLV_DISP_PW_DPIO_CMN_BC,
> > {
> > @@ -661,74 +661,77 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
> > },
> > };
> >
> > -#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> > - BIT_ULL(POWER_DOMAIN_VGA) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > -
> > -#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > - GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_GMBUS) | \
> > - BIT_ULL(POWER_DOMAIN_MODESET) | \
> > - BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > -
> > -#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
> > -#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
> > -#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
> > -
> > -#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > -
> > -#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > -
> > -#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > -
> > -#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > -
> > -#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > -
> > -#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +#define GLK_PW_2_POWER_DOMAINS \
> > + POWER_DOMAIN_PIPE_B, \
> > + POWER_DOMAIN_PIPE_C, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
> > + POWER_DOMAIN_TRANSCODER_A, \
> > + POWER_DOMAIN_TRANSCODER_B, \
> > + POWER_DOMAIN_TRANSCODER_C, \
> > + POWER_DOMAIN_PORT_DDI_LANES_B, \
> > + POWER_DOMAIN_PORT_DDI_LANES_C, \
> > + POWER_DOMAIN_VGA, \
> > + POWER_DOMAIN_AUDIO_MMIO, \
> > + POWER_DOMAIN_AUDIO_PLAYBACK, \
> > + POWER_DOMAIN_AUX_B, \
> > + POWER_DOMAIN_AUX_C
> > +
> > +I915_DECL_PW_DOMAINS(glk_pwdoms_pw_2,
> > + GLK_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off,
> > + GLK_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_GMBUS,
> > + POWER_DOMAIN_MODESET,
> > + POWER_DOMAIN_GT_IRQ,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A);
> > +I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B);
> > +I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C);
> > +
> > +I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
> > + POWER_DOMAIN_PORT_DDI_LANES_A,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
> > + POWER_DOMAIN_PORT_DDI_LANES_B,
> > + POWER_DOMAIN_AUX_B,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
> > + POWER_DOMAIN_PORT_DDI_LANES_C,
> > + POWER_DOMAIN_AUX_C,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_AUX_IO_A,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
> > + POWER_DOMAIN_AUX_B,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
> > + POWER_DOMAIN_AUX_C,
> > + POWER_DOMAIN_INIT);
> >
> > static const struct i915_power_well_desc glk_power_wells[] = {
> > {
> > .name = "always-on",
> > - .domains = POWER_DOMAIN_MASK,
> > + .domain_list = &i9xx_pwdoms_always_on,
> > .ops = &i9xx_always_on_power_well_ops,
> > .always_on = true,
> > .id = DISP_PW_ID_NONE,
> > }, {
> > .name = "PW_1",
> > /* Handled by the DMC firmware */
> > - .domains = 0,
> > + .domain_list = I915_PW_DOMAINS_NONE,
> > .ops = &hsw_power_well_ops,
> > .always_on = true,
> > .has_fuses = true,
> > @@ -738,12 +741,12 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> > },
> > }, {
> > .name = "DC_off",
> > - .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .domain_list = &glk_pwdoms_dc_off,
> > .ops = &gen9_dc_off_power_well_ops,
> > .id = SKL_DISP_DC_OFF,
> > }, {
> > .name = "PW_2",
> > - .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> > + .domain_list = &glk_pwdoms_pw_2,
> > .ops = &hsw_power_well_ops,
> > .has_vga = true,
> > .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> > @@ -754,7 +757,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> > },
> > }, {
> > .name = "dpio-common-a",
> > - .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
> > + .domain_list = &glk_pwdoms_dpio_cmn_a,
> > .ops = &bxt_dpio_cmn_power_well_ops,
> > .id = BXT_DISP_PW_DPIO_CMN_A,
> > {
> > @@ -762,7 +765,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> > },
> > }, {
> > .name = "dpio-common-b",
> > - .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
> > + .domain_list = &glk_pwdoms_dpio_cmn_b,
> > .ops = &bxt_dpio_cmn_power_well_ops,
> > .id = VLV_DISP_PW_DPIO_CMN_BC,
> > {
> > @@ -770,7 +773,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> > },
> > }, {
> > .name = "dpio-common-c",
> > - .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
> > + .domain_list = &glk_pwdoms_dpio_cmn_c,
> > .ops = &bxt_dpio_cmn_power_well_ops,
> > .id = GLK_DISP_PW_DPIO_CMN_C,
> > {
> > @@ -778,7 +781,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_A",
> > - .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
> > + .domain_list = &glk_pwdoms_aux_a,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -786,7 +789,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_B",
> > - .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
> > + .domain_list = &glk_pwdoms_aux_b,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -794,7 +797,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_C",
> > - .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
> > + .domain_list = &glk_pwdoms_aux_c,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -802,7 +805,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_A",
> > - .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
> > + .domain_list = &glk_pwdoms_ddi_io_a,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -810,7 +813,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_B",
> > - .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
> > + .domain_list = &glk_pwdoms_ddi_io_b,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -818,7 +821,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_C",
> > - .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
> > + .domain_list = &glk_pwdoms_ddi_io_c,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -841,89 +844,97 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> > * - DDI_A
> > * - FBC
> > */
> > -#define ICL_PW_4_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +#define ICL_PW_4_POWER_DOMAINS \
> > + POWER_DOMAIN_PIPE_C, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_C
> > +
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
> > + ICL_PW_4_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> > /* VDSC/joining */
> >
> > -#define ICL_PW_3_POWER_DOMAINS ( \
> > - ICL_PW_4_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_F) | \
> > - BIT_ULL(POWER_DOMAIN_VGA) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_E) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_F) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT_C) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT_D) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT_E) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT_F) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +#define ICL_PW_3_POWER_DOMAINS \
> > + ICL_PW_4_POWER_DOMAINS, \
> > + POWER_DOMAIN_PIPE_B, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> > + POWER_DOMAIN_TRANSCODER_A, \
> > + POWER_DOMAIN_TRANSCODER_B, \
> > + POWER_DOMAIN_TRANSCODER_C, \
> > + POWER_DOMAIN_PORT_DDI_LANES_B, \
> > + POWER_DOMAIN_PORT_DDI_LANES_C, \
> > + POWER_DOMAIN_PORT_DDI_LANES_D, \
> > + POWER_DOMAIN_PORT_DDI_LANES_E, \
> > + POWER_DOMAIN_PORT_DDI_LANES_F, \
> > + POWER_DOMAIN_VGA, \
> > + POWER_DOMAIN_AUDIO_MMIO, \
> > + POWER_DOMAIN_AUDIO_PLAYBACK, \
> > + POWER_DOMAIN_AUX_B, \
> > + POWER_DOMAIN_AUX_C, \
> > + POWER_DOMAIN_AUX_D, \
> > + POWER_DOMAIN_AUX_E, \
> > + POWER_DOMAIN_AUX_F, \
> > + POWER_DOMAIN_AUX_TBT_C, \
> > + POWER_DOMAIN_AUX_TBT_D, \
> > + POWER_DOMAIN_AUX_TBT_E, \
> > + POWER_DOMAIN_AUX_TBT_F
> > +
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3,
> > + ICL_PW_3_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> > /*
> > * - transcoder WD
> > * - KVMR (HW control)
> > */
> >
> > -#define ICL_PW_2_POWER_DOMAINS ( \
> > - ICL_PW_3_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +#define ICL_PW_2_POWER_DOMAINS \
> > + ICL_PW_3_POWER_DOMAINS, \
> > + POWER_DOMAIN_TRANSCODER_VDSC_PW2
> > +
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2,
> > + ICL_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> > /*
> > * - KVMR (HW control)
> > */
> >
> > -#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > - ICL_PW_2_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_MODESET) | \
> > - BIT_ULL(POWER_DOMAIN_DC_OFF) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off,
> > + ICL_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_MODESET,
> > + POWER_DOMAIN_DC_OFF,
> > + POWER_DOMAIN_INIT);
> >
> > -#define ICL_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
> > -#define ICL_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
> > -#define ICL_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
> > -#define ICL_DDI_IO_D_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D)
> > -#define ICL_DDI_IO_E_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E)
> > -#define ICL_DDI_IO_F_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_F)
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d, POWER_DOMAIN_PORT_DDI_IO_D);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e, POWER_DOMAIN_PORT_DDI_IO_E);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f, POWER_DOMAIN_PORT_DDI_IO_F);
> >
> > -#define ICL_AUX_A_IO_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_IO_A))
> > -
> > -#define ICL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_B)
> > -#define ICL_AUX_C_TC1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C)
> > -#define ICL_AUX_D_TC2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D)
> > -#define ICL_AUX_E_TC3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E)
> > -#define ICL_AUX_F_TC4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F)
> > -#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_C)
> > -#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_D)
> > -#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_E)
> > -#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_F)
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_AUX_IO_A);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b, POWER_DOMAIN_AUX_B);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d, POWER_DOMAIN_AUX_D);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e, POWER_DOMAIN_AUX_E);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f, POWER_DOMAIN_AUX_F);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT_C);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT_D);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT_E);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT_F);
> >
> > static const struct i915_power_well_desc icl_power_wells[] = {
> > {
> > .name = "always-on",
> > - .domains = POWER_DOMAIN_MASK,
> > + .domain_list = &i9xx_pwdoms_always_on,
> > .ops = &i9xx_always_on_power_well_ops,
> > .always_on = true,
> > .id = DISP_PW_ID_NONE,
> > }, {
> > .name = "PW_1",
> > /* Handled by the DMC firmware */
> > - .domains = 0,
> > + .domain_list = I915_PW_DOMAINS_NONE,
> > .ops = &hsw_power_well_ops,
> > .always_on = true,
> > .has_fuses = true,
> > @@ -933,12 +944,12 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "DC_off",
> > - .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_dc_off,
> > .ops = &gen9_dc_off_power_well_ops,
> > .id = SKL_DISP_DC_OFF,
> > }, {
> > .name = "PW_2",
> > - .domains = ICL_PW_2_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_pw_2,
> > .ops = &hsw_power_well_ops,
> > .has_fuses = true,
> > .id = SKL_DISP_PW_2,
> > @@ -947,7 +958,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "PW_3",
> > - .domains = ICL_PW_3_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_pw_3,
> > .ops = &hsw_power_well_ops,
> > .has_vga = true,
> > .irq_pipe_mask = BIT(PIPE_B),
> > @@ -958,7 +969,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_A",
> > - .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_a,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -966,7 +977,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_B",
> > - .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_b,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -974,7 +985,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_C",
> > - .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_c,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -982,7 +993,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_D",
> > - .domains = ICL_DDI_IO_D_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_d,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -990,7 +1001,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_E",
> > - .domains = ICL_DDI_IO_E_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_e,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -998,7 +1009,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_F",
> > - .domains = ICL_DDI_IO_F_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_f,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1006,7 +1017,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_A",
> > - .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_aux_a,
> > .ops = &icl_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1014,7 +1025,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_B",
> > - .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_aux_b,
> > .ops = &icl_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1022,7 +1033,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_C",
> > - .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_aux_c,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = false,
> > .id = DISP_PW_ID_NONE,
> > @@ -1031,7 +1042,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_D",
> > - .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_aux_d,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = false,
> > .id = DISP_PW_ID_NONE,
> > @@ -1040,7 +1051,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_E",
> > - .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_aux_e,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = false,
> > .id = DISP_PW_ID_NONE,
> > @@ -1049,7 +1060,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_F",
> > - .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_aux_f,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = false,
> > .id = DISP_PW_ID_NONE,
> > @@ -1058,7 +1069,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_TBT1",
> > - .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_aux_tbt1,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -1067,7 +1078,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_TBT2",
> > - .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_aux_tbt2,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -1076,7 +1087,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_TBT3",
> > - .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_aux_tbt3,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -1085,7 +1096,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_TBT4",
> > - .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_aux_tbt4,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -1094,7 +1105,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > }, {
> > .name = "PW_4",
> > - .domains = ICL_PW_4_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_pw_4,
> > .ops = &hsw_power_well_ops,
> > .irq_pipe_mask = BIT(PIPE_C),
> > .has_fuses = true,
> > @@ -1105,113 +1116,122 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > },
> > };
> >
> > -#define TGL_PW_5_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PIPE_D) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +#define TGL_PW_5_POWER_DOMAINS \
> > + POWER_DOMAIN_PIPE_D, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
> > + POWER_DOMAIN_TRANSCODER_D
> >
> > -#define TGL_PW_4_POWER_DOMAINS ( \
> > - TGL_PW_5_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_5,
> > + TGL_PW_5_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> >
> > -#define TGL_PW_3_POWER_DOMAINS ( \
> > - TGL_PW_4_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
> > - BIT_ULL(POWER_DOMAIN_VGA) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +#define TGL_PW_4_POWER_DOMAINS \
> > + TGL_PW_5_POWER_DOMAINS, \
> > + POWER_DOMAIN_PIPE_C, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
> > + POWER_DOMAIN_TRANSCODER_C
> >
> > -#define TGL_PW_2_POWER_DOMAINS ( \
> > - TGL_PW_3_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_4,
> > + TGL_PW_4_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> >
> > -#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > - TGL_PW_3_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > - BIT_ULL(POWER_DOMAIN_MODESET) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +#define TGL_PW_3_POWER_DOMAINS \
> > + TGL_PW_4_POWER_DOMAINS, \
> > + POWER_DOMAIN_PIPE_B, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> > + POWER_DOMAIN_TRANSCODER_B, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC1, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC2, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC3, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC4, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC5, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC6, \
> > + POWER_DOMAIN_VGA, \
> > + POWER_DOMAIN_AUDIO_MMIO, \
> > + POWER_DOMAIN_AUDIO_PLAYBACK, \
> > + POWER_DOMAIN_AUX_USBC1, \
> > + POWER_DOMAIN_AUX_USBC2, \
> > + POWER_DOMAIN_AUX_USBC3, \
> > + POWER_DOMAIN_AUX_USBC4, \
> > + POWER_DOMAIN_AUX_USBC5, \
> > + POWER_DOMAIN_AUX_USBC6, \
> > + POWER_DOMAIN_AUX_TBT1, \
> > + POWER_DOMAIN_AUX_TBT2, \
> > + POWER_DOMAIN_AUX_TBT3, \
> > + POWER_DOMAIN_AUX_TBT4, \
> > + POWER_DOMAIN_AUX_TBT5, \
> > + POWER_DOMAIN_AUX_TBT6
> >
> > -#define TGL_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
> > -#define TGL_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
> > -#define TGL_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
> > -#define TGL_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
> > -#define TGL_DDI_IO_TC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC5)
> > -#define TGL_DDI_IO_TC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC6)
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_3,
> > + TGL_PW_3_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> >
> > -#define TGL_AUX_A_IO_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_IO_A))
> > -#define TGL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_B)
> > -#define TGL_AUX_C_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C)
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_2,
> > + TGL_PW_3_POWER_DOMAINS,
> > + POWER_DOMAIN_TRANSCODER_VDSC_PW2,
> > + POWER_DOMAIN_INIT);
> >
> > -#define TGL_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
> > -#define TGL_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
> > -#define TGL_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
> > -#define TGL_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
> > -#define TGL_AUX_IO_USBC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC5)
> > -#define TGL_AUX_IO_USBC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC6)
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off,
> > + TGL_PW_3_POWER_DOMAINS,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_AUX_B,
> > + POWER_DOMAIN_AUX_C,
> > + POWER_DOMAIN_MODESET,
> > + POWER_DOMAIN_INIT);
> >
> > -#define TGL_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
> > -#define TGL_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
> > -#define TGL_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
> > -#define TGL_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
> > -#define TGL_AUX_IO_TBT5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT5)
> > -#define TGL_AUX_IO_TBT6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT6)
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5, POWER_DOMAIN_PORT_DDI_IO_TC5);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6, POWER_DOMAIN_PORT_DDI_IO_TC6);
> >
> > -#define TGL_TC_COLD_OFF_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
> > - BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_a,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_AUX_IO_A);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_b, POWER_DOMAIN_AUX_B);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
> > +
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5, POWER_DOMAIN_AUX_USBC5);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6, POWER_DOMAIN_AUX_USBC6);
> > +
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5, POWER_DOMAIN_AUX_TBT5);
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6, POWER_DOMAIN_AUX_TBT6);
> > +
> > +I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off,
> > + POWER_DOMAIN_AUX_USBC1,
> > + POWER_DOMAIN_AUX_USBC2,
> > + POWER_DOMAIN_AUX_USBC3,
> > + POWER_DOMAIN_AUX_USBC4,
> > + POWER_DOMAIN_AUX_USBC5,
> > + POWER_DOMAIN_AUX_USBC6,
> > + POWER_DOMAIN_AUX_TBT1,
> > + POWER_DOMAIN_AUX_TBT2,
> > + POWER_DOMAIN_AUX_TBT3,
> > + POWER_DOMAIN_AUX_TBT4,
> > + POWER_DOMAIN_AUX_TBT5,
> > + POWER_DOMAIN_AUX_TBT6,
> > + POWER_DOMAIN_TC_COLD_OFF);
> >
> > static const struct i915_power_well_desc tgl_power_wells[] = {
> > {
> > .name = "always-on",
> > - .domains = POWER_DOMAIN_MASK,
> > + .domain_list = &i9xx_pwdoms_always_on,
> > .ops = &i9xx_always_on_power_well_ops,
> > .always_on = true,
> > .id = DISP_PW_ID_NONE,
> > }, {
> > .name = "PW_1",
> > /* Handled by the DMC firmware */
> > - .domains = 0,
> > + .domain_list = I915_PW_DOMAINS_NONE,
> > .ops = &hsw_power_well_ops,
> > .always_on = true,
> > .has_fuses = true,
> > @@ -1221,12 +1241,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "DC_off",
> > - .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_dc_off,
> > .ops = &gen9_dc_off_power_well_ops,
> > .id = SKL_DISP_DC_OFF,
> > }, {
> > .name = "PW_2",
> > - .domains = TGL_PW_2_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_pw_2,
> > .ops = &hsw_power_well_ops,
> > .has_fuses = true,
> > .id = SKL_DISP_PW_2,
> > @@ -1235,7 +1255,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "PW_3",
> > - .domains = TGL_PW_3_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_pw_3,
> > .ops = &hsw_power_well_ops,
> > .has_vga = true,
> > .irq_pipe_mask = BIT(PIPE_B),
> > @@ -1246,7 +1266,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_A",
> > - .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_a,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1254,7 +1274,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_B",
> > - .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_b,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1262,7 +1282,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_C",
> > - .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_c,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1270,7 +1290,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_TC1",
> > - .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_ddi_io_tc1,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1278,7 +1298,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_TC2",
> > - .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_ddi_io_tc2,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1286,7 +1306,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_TC3",
> > - .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_ddi_io_tc3,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1294,7 +1314,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_TC4",
> > - .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_ddi_io_tc4,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1302,7 +1322,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_TC5",
> > - .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_ddi_io_tc5,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1310,7 +1330,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_TC6",
> > - .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_ddi_io_tc6,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1318,12 +1338,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "TC_cold_off",
> > - .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_tc_cold_off,
> > .ops = &tgl_tc_cold_off_ops,
> > .id = TGL_DISP_PW_TC_COLD_OFF,
> > }, {
> > .name = "AUX_A",
> > - .domains = TGL_AUX_A_IO_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_a,
> > .ops = &icl_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1331,7 +1351,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_B",
> > - .domains = TGL_AUX_B_IO_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_b,
> > .ops = &icl_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1339,7 +1359,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_C",
> > - .domains = TGL_AUX_C_IO_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_c,
> > .ops = &icl_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1347,7 +1367,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_USBC1",
> > - .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_usbc1,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = false,
> > .id = DISP_PW_ID_NONE,
> > @@ -1356,7 +1376,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_USBC2",
> > - .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_usbc2,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = false,
> > .id = DISP_PW_ID_NONE,
> > @@ -1365,7 +1385,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_USBC3",
> > - .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_usbc3,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = false,
> > .id = DISP_PW_ID_NONE,
> > @@ -1374,7 +1394,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_USBC4",
> > - .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_usbc4,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = false,
> > .id = DISP_PW_ID_NONE,
> > @@ -1383,7 +1403,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_USBC5",
> > - .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_usbc5,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = false,
> > .id = DISP_PW_ID_NONE,
> > @@ -1392,7 +1412,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_USBC6",
> > - .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_usbc6,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = false,
> > .id = DISP_PW_ID_NONE,
> > @@ -1401,7 +1421,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_TBT1",
> > - .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_tbt1,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -1410,7 +1430,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_TBT2",
> > - .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_tbt2,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -1419,7 +1439,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_TBT3",
> > - .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_tbt3,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -1428,7 +1448,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_TBT4",
> > - .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_tbt4,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -1437,7 +1457,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_TBT5",
> > - .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_tbt5,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -1446,7 +1466,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_TBT6",
> > - .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_tbt6,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -1455,7 +1475,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > }, {
> > .name = "PW_4",
> > - .domains = TGL_PW_4_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_pw_4,
> > .ops = &hsw_power_well_ops,
> > .has_fuses = true,
> > .irq_pipe_mask = BIT(PIPE_C),
> > @@ -1465,7 +1485,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > }
> > }, {
> > .name = "PW_5",
> > - .domains = TGL_PW_5_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_pw_5,
> > .ops = &hsw_power_well_ops,
> > .has_fuses = true,
> > .irq_pipe_mask = BIT(PIPE_D),
> > @@ -1476,25 +1496,31 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > },
> > };
> >
> > -#define RKL_PW_4_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +#define RKL_PW_4_POWER_DOMAINS \
> > + POWER_DOMAIN_PIPE_C, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
> > + POWER_DOMAIN_TRANSCODER_C
> >
> > -#define RKL_PW_3_POWER_DOMAINS ( \
> > - RKL_PW_4_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> > - BIT_ULL(POWER_DOMAIN_VGA) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_4,
> > + RKL_PW_4_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> > +
> > +#define RKL_PW_3_POWER_DOMAINS \
> > + RKL_PW_4_POWER_DOMAINS, \
> > + POWER_DOMAIN_PIPE_B, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> > + POWER_DOMAIN_TRANSCODER_B, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC1, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC2, \
> > + POWER_DOMAIN_VGA, \
> > + POWER_DOMAIN_AUDIO_MMIO, \
> > + POWER_DOMAIN_AUDIO_PLAYBACK, \
> > + POWER_DOMAIN_AUX_USBC1, \
> > + POWER_DOMAIN_AUX_USBC2
> > +
> > +I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_3,
> > + RKL_PW_3_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> >
> > /*
> > * There is no PW_2/PG_2 on RKL.
> > @@ -1517,24 +1543,24 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
> > */
> >
> > -#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > - RKL_PW_3_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_MODESET) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
> > + RKL_PW_3_POWER_DOMAINS,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_AUX_B,
> > + POWER_DOMAIN_MODESET,
> > + POWER_DOMAIN_INIT);
> >
> > static const struct i915_power_well_desc rkl_power_wells[] = {
> > {
> > .name = "always-on",
> > - .domains = POWER_DOMAIN_MASK,
> > + .domain_list = &i9xx_pwdoms_always_on,
> > .ops = &i9xx_always_on_power_well_ops,
> > .always_on = true,
> > .id = DISP_PW_ID_NONE,
> > }, {
> > .name = "PW_1",
> > /* Handled by the DMC firmware */
> > - .domains = 0,
> > + .domain_list = I915_PW_DOMAINS_NONE,
> > .ops = &hsw_power_well_ops,
> > .always_on = true,
> > .has_fuses = true,
> > @@ -1544,12 +1570,12 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> > },
> > }, {
> > .name = "DC_off",
> > - .domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .domain_list = &rkl_pwdoms_dc_off,
> > .ops = &gen9_dc_off_power_well_ops,
> > .id = SKL_DISP_DC_OFF,
> > }, {
> > .name = "PW_3",
> > - .domains = RKL_PW_3_POWER_DOMAINS,
> > + .domain_list = &rkl_pwdoms_pw_3,
> > .ops = &hsw_power_well_ops,
> > .irq_pipe_mask = BIT(PIPE_B),
> > .has_vga = true,
> > @@ -1560,7 +1586,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> > },
> > }, {
> > .name = "PW_4",
> > - .domains = RKL_PW_4_POWER_DOMAINS,
> > + .domain_list = &rkl_pwdoms_pw_4,
> > .ops = &hsw_power_well_ops,
> > .has_fuses = true,
> > .irq_pipe_mask = BIT(PIPE_C),
> > @@ -1570,7 +1596,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_A",
> > - .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_a,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1578,7 +1604,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_B",
> > - .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_b,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1586,7 +1612,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_TC1",
> > - .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_ddi_io_tc1,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1594,7 +1620,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_TC2",
> > - .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_ddi_io_tc2,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1602,7 +1628,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_A",
> > - .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_aux_a,
> > .ops = &icl_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1610,7 +1636,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_B",
> > - .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_aux_b,
> > .ops = &icl_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1618,7 +1644,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_USBC1",
> > - .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_usbc1,
> > .ops = &icl_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1626,7 +1652,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_USBC2",
> > - .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_usbc2,
> > .ops = &icl_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1638,43 +1664,46 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> > /*
> > * DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
> > */
> > -#define DG1_PW_3_POWER_DOMAINS ( \
> > - TGL_PW_4_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> > - BIT_ULL(POWER_DOMAIN_VGA) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +#define DG1_PW_3_POWER_DOMAINS \
> > + TGL_PW_4_POWER_DOMAINS, \
> > + POWER_DOMAIN_PIPE_B, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> > + POWER_DOMAIN_TRANSCODER_B, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC1, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC2, \
> > + POWER_DOMAIN_VGA, \
> > + POWER_DOMAIN_AUDIO_PLAYBACK, \
> > + POWER_DOMAIN_AUX_USBC1, \
> > + POWER_DOMAIN_AUX_USBC2
> >
> > -#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > - DG1_PW_3_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_MODESET) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_3,
> > + DG1_PW_3_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> >
> > -#define DG1_PW_2_POWER_DOMAINS ( \
> > - DG1_PW_3_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off,
> > + DG1_PW_3_POWER_DOMAINS,
> > + POWER_DOMAIN_AUDIO_MMIO,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_AUX_B,
> > + POWER_DOMAIN_MODESET,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
> > + DG1_PW_3_POWER_DOMAINS,
> > + POWER_DOMAIN_TRANSCODER_VDSC_PW2,
> > + POWER_DOMAIN_INIT);
> >
> > static const struct i915_power_well_desc dg1_power_wells[] = {
> > {
> > .name = "always-on",
> > - .domains = POWER_DOMAIN_MASK,
> > + .domain_list = &i9xx_pwdoms_always_on,
> > .ops = &i9xx_always_on_power_well_ops,
> > .always_on = true,
> > .id = DISP_PW_ID_NONE,
> > }, {
> > .name = "PW_1",
> > /* Handled by the DMC firmware */
> > - .domains = 0,
> > + .domain_list = I915_PW_DOMAINS_NONE,
> > .ops = &hsw_power_well_ops,
> > .always_on = true,
> > .has_fuses = true,
> > @@ -1684,12 +1713,12 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> > },
> > }, {
> > .name = "DC_off",
> > - .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .domain_list = &dg1_pwdoms_dc_off,
> > .ops = &gen9_dc_off_power_well_ops,
> > .id = SKL_DISP_DC_OFF,
> > }, {
> > .name = "PW_2",
> > - .domains = DG1_PW_2_POWER_DOMAINS,
> > + .domain_list = &dg1_pwdoms_pw_2,
> > .ops = &hsw_power_well_ops,
> > .has_fuses = true,
> > .id = SKL_DISP_PW_2,
> > @@ -1698,7 +1727,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> > },
> > }, {
> > .name = "PW_3",
> > - .domains = DG1_PW_3_POWER_DOMAINS,
> > + .domain_list = &dg1_pwdoms_pw_3,
> > .ops = &hsw_power_well_ops,
> > .irq_pipe_mask = BIT(PIPE_B),
> > .has_vga = true,
> > @@ -1709,7 +1738,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_A",
> > - .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_a,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1717,7 +1746,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_B",
> > - .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_b,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1725,7 +1754,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_TC1",
> > - .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_ddi_io_tc1,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1733,7 +1762,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_TC2",
> > - .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_ddi_io_tc2,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1741,7 +1770,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_A",
> > - .domains = TGL_AUX_A_IO_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_a,
> > .ops = &icl_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1749,7 +1778,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_B",
> > - .domains = TGL_AUX_B_IO_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_b,
> > .ops = &icl_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1757,7 +1786,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_USBC1",
> > - .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_usbc1,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = false,
> > .id = DISP_PW_ID_NONE,
> > @@ -1766,7 +1795,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_USBC2",
> > - .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_usbc2,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = false,
> > .id = DISP_PW_ID_NONE,
> > @@ -1775,7 +1804,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> > },
> > }, {
> > .name = "PW_4",
> > - .domains = TGL_PW_4_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_pw_4,
> > .ops = &hsw_power_well_ops,
> > .has_fuses = true,
> > .irq_pipe_mask = BIT(PIPE_C),
> > @@ -1785,7 +1814,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> > }
> > }, {
> > .name = "PW_5",
> > - .domains = TGL_PW_5_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_pw_5,
> > .ops = &hsw_power_well_ops,
> > .has_fuses = true,
> > .irq_pipe_mask = BIT(PIPE_D),
> > @@ -1814,54 +1843,66 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> > * to top. This allows pipes to be power gated independently.
> > */
> >
> > -#define XELPD_PW_D_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PIPE_D) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > -
> > -#define XELPD_PW_C_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > -
> > -#define XELPD_PW_B_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
> > - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > -
> > -#define XELPD_PW_A_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> > - BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > -
> > -#define XELPD_PW_2_POWER_DOMAINS ( \
> > - XELPD_PW_B_POWER_DOMAINS | \
> > - XELPD_PW_C_POWER_DOMAINS | \
> > - XELPD_PW_D_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
> > - BIT_ULL(POWER_DOMAIN_VGA) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +#define XELPD_PW_D_POWER_DOMAINS \
> > + POWER_DOMAIN_PIPE_D, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
> > + POWER_DOMAIN_TRANSCODER_D
> > +
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_d,
> > + XELPD_PW_D_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> > +
> > +#define XELPD_PW_C_POWER_DOMAINS \
> > + POWER_DOMAIN_PIPE_C, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
> > + POWER_DOMAIN_TRANSCODER_C
> > +
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_c,
> > + XELPD_PW_C_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> > +
> > +#define XELPD_PW_B_POWER_DOMAINS \
> > + POWER_DOMAIN_PIPE_B, \
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
> > + POWER_DOMAIN_TRANSCODER_B
> > +
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_b,
> > + XELPD_PW_B_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
> > + POWER_DOMAIN_PIPE_A,
> > + POWER_DOMAIN_PIPE_PANEL_FITTER_A,
> > + POWER_DOMAIN_INIT);
> > +
> > +#define XELPD_PW_2_POWER_DOMAINS \
> > + XELPD_PW_B_POWER_DOMAINS, \
> > + XELPD_PW_C_POWER_DOMAINS, \
> > + XELPD_PW_D_POWER_DOMAINS, \
> > + POWER_DOMAIN_PORT_DDI_LANES_C, \
> > + POWER_DOMAIN_PORT_DDI_LANES_D_XELPD, \
> > + POWER_DOMAIN_PORT_DDI_LANES_E_XELPD, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC1, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC2, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC3, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC4, \
> > + POWER_DOMAIN_VGA, \
> > + POWER_DOMAIN_AUDIO_PLAYBACK, \
> > + POWER_DOMAIN_AUX_C, \
> > + POWER_DOMAIN_AUX_D_XELPD, \
> > + POWER_DOMAIN_AUX_E_XELPD, \
> > + POWER_DOMAIN_AUX_USBC1, \
> > + POWER_DOMAIN_AUX_USBC2, \
> > + POWER_DOMAIN_AUX_USBC3, \
> > + POWER_DOMAIN_AUX_USBC4, \
> > + POWER_DOMAIN_AUX_TBT1, \
> > + POWER_DOMAIN_AUX_TBT2, \
> > + POWER_DOMAIN_AUX_TBT3, \
> > + POWER_DOMAIN_AUX_TBT4
> > +
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
> > + XELPD_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> >
> > /*
> > * XELPD PW_1/PG_1 domains (under HW/DMC control):
> > @@ -1880,45 +1921,46 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
> > * - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
> > */
> >
> > -#define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > - XELPD_PW_2_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> > - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > - BIT_ULL(POWER_DOMAIN_MODESET) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
> > + XELPD_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_PORT_DSI,
> > + POWER_DOMAIN_AUDIO_MMIO,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_AUX_B,
> > + POWER_DOMAIN_MODESET,
> > + POWER_DOMAIN_INIT);
> >
> > -#define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
> > -#define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
> > -#define XELPD_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
> > -#define XELPD_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
> > -#define XELPD_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
> > -#define XELPD_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_d_xelpd, POWER_DOMAIN_AUX_D_XELPD);
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_e_xelpd, POWER_DOMAIN_AUX_E_XELPD);
> >
> > -#define XELPD_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
> > -#define XELPD_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
> > -#define XELPD_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
> > -#define XELPD_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1);
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2);
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3);
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4);
> >
> > -#define XELPD_DDI_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D_XELPD)
> > -#define XELPD_DDI_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E_XELPD)
> > -#define XELPD_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
> > -#define XELPD_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
> > -#define XELPD_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
> > -#define XELPD_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
> > +
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_d_xelpd, POWER_DOMAIN_PORT_DDI_IO_D_XELPD);
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_e_xelpd, POWER_DOMAIN_PORT_DDI_IO_E_XELPD);
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1);
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
> > +I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
> >
> > static const struct i915_power_well_desc xelpd_power_wells[] = {
> > {
> > .name = "always-on",
> > - .domains = POWER_DOMAIN_MASK,
> > + .domain_list = &i9xx_pwdoms_always_on,
> > .ops = &i9xx_always_on_power_well_ops,
> > .always_on = true,
> > .id = DISP_PW_ID_NONE,
> > }, {
> > .name = "PW_1",
> > /* Handled by the DMC firmware */
> > - .domains = 0,
> > + .domain_list = I915_PW_DOMAINS_NONE,
> > .ops = &hsw_power_well_ops,
> > .always_on = true,
> > .has_fuses = true,
> > @@ -1928,12 +1970,12 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "DC_off",
> > - .domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_dc_off,
> > .ops = &gen9_dc_off_power_well_ops,
> > .id = SKL_DISP_DC_OFF,
> > }, {
> > .name = "PW_2",
> > - .domains = XELPD_PW_2_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_pw_2,
> > .ops = &hsw_power_well_ops,
> > .has_vga = true,
> > .has_fuses = true,
> > @@ -1943,7 +1985,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "PW_A",
> > - .domains = XELPD_PW_A_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_pw_a,
> > .ops = &hsw_power_well_ops,
> > .irq_pipe_mask = BIT(PIPE_A),
> > .has_fuses = true,
> > @@ -1953,7 +1995,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "PW_B",
> > - .domains = XELPD_PW_B_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_pw_b,
> > .ops = &hsw_power_well_ops,
> > .irq_pipe_mask = BIT(PIPE_B),
> > .has_fuses = true,
> > @@ -1963,7 +2005,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "PW_C",
> > - .domains = XELPD_PW_C_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_pw_c,
> > .ops = &hsw_power_well_ops,
> > .irq_pipe_mask = BIT(PIPE_C),
> > .has_fuses = true,
> > @@ -1973,7 +2015,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "PW_D",
> > - .domains = XELPD_PW_D_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_pw_d,
> > .ops = &hsw_power_well_ops,
> > .irq_pipe_mask = BIT(PIPE_D),
> > .has_fuses = true,
> > @@ -1983,7 +2025,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "DDI_IO_A",
> > - .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_a,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1991,7 +2033,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_B",
> > - .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_b,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -1999,7 +2041,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_C",
> > - .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_ddi_io_c,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -2007,7 +2049,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_D_XELPD",
> > - .domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_ddi_io_d_xelpd,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -2015,7 +2057,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_E_XELPD",
> > - .domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_ddi_io_e_xelpd,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -2023,7 +2065,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_TC1",
> > - .domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_ddi_io_tc1,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -2031,7 +2073,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_TC2",
> > - .domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_ddi_io_tc2,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -2039,7 +2081,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_TC3",
> > - .domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_ddi_io_tc3,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -2047,7 +2089,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > }
> > }, {
> > .name = "DDI_IO_TC4",
> > - .domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_ddi_io_tc4,
> > .ops = &icl_ddi_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -2055,7 +2097,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > }
> > }, {
> > .name = "AUX_A",
> > - .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_aux_a,
> > .ops = &icl_aux_power_well_ops,
> > .fixed_enable_delay = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -2064,7 +2106,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_B",
> > - .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> > + .domain_list = &icl_pwdoms_aux_b,
> > .ops = &icl_aux_power_well_ops,
> > .fixed_enable_delay = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -2073,7 +2115,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_C",
> > - .domains = TGL_AUX_C_IO_POWER_DOMAINS,
> > + .domain_list = &tgl_pwdoms_aux_c,
> > .ops = &icl_aux_power_well_ops,
> > .fixed_enable_delay = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -2082,7 +2124,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_D_XELPD",
> > - .domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_aux_d_xelpd,
> > .ops = &icl_aux_power_well_ops,
> > .fixed_enable_delay = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -2091,7 +2133,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_E_XELPD",
> > - .domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_aux_e_xelpd,
> > .ops = &icl_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -2099,7 +2141,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_USBC1",
> > - .domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_aux_usbc1,
> > .ops = &icl_aux_power_well_ops,
> > .fixed_enable_delay = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -2108,7 +2150,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_USBC2",
> > - .domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_aux_usbc2,
> > .ops = &icl_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -2116,7 +2158,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_USBC3",
> > - .domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_aux_usbc3,
> > .ops = &icl_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -2124,7 +2166,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_USBC4",
> > - .domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_aux_usbc4,
> > .ops = &icl_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -2132,7 +2174,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_TBT1",
> > - .domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_aux_tbt1,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -2141,7 +2183,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_TBT2",
> > - .domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_aux_tbt2,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -2150,7 +2192,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_TBT3",
> > - .domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_aux_tbt3,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -2159,7 +2201,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > }, {
> > .name = "AUX_TBT4",
> > - .domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
> > + .domain_list = &xelpd_pwdoms_aux_tbt4,
> > .ops = &icl_aux_power_well_ops,
> > .is_tc_tbt = true,
> > .id = DISP_PW_ID_NONE,
> > @@ -2169,6 +2211,24 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> > },
> > };
> >
> > +static void init_power_well_domains(const struct i915_power_well_desc *desc,
> > + struct i915_power_well *power_well)
> > +{
> > + int j;
> > +
> > + if (!desc->domain_list)
> > + return;
> > +
> > + if (desc->domain_list->count == 0) {
> > + power_well->domains = GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0);
> > +
> > + return;
> > + }
> > +
> > + for (j = 0; j < desc->domain_list->count; j++)
> > + power_well->domains |= BIT_ULL(desc->domain_list->list[j]);
> > +}
> > +
> > static int
> > __set_power_wells(struct i915_power_domains *power_domains,
> > const struct i915_power_well_desc *power_well_descs,
> > @@ -2199,9 +2259,13 @@ __set_power_wells(struct i915_power_domains *power_domains,
> > if (BIT_ULL(id) & skip_mask)
> > continue;
> >
> > - power_domains->power_wells[plt_idx++].desc =
> > + power_domains->power_wells[plt_idx].desc =
> > &power_well_descs[i];
> >
> > + init_power_well_domains(&power_well_descs[i], &power_domains->power_wells[plt_idx]);
> > +
> > + plt_idx++;
> > +
> > if (id == DISP_PW_ID_NONE)
> > continue;
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 10/19] drm/i915: Convert the u64 power well domains mask to a bitmap
2022-02-01 11:20 ` Jani Nikula
@ 2022-02-03 18:22 ` Imre Deak
0 siblings, 0 replies; 32+ messages in thread
From: Imre Deak @ 2022-02-03 18:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Feb 01, 2022 at 01:20:50PM +0200, Jani Nikula wrote:
> On Fri, 28 Jan 2022, Imre Deak <imre.deak@intel.com> wrote:
> > To remove the aliasing of the power domain enum values in a follow-up
> > patch in this patchset (requiring a bigger mask) and allow for defining
> > additional power domains in the future (at least some upcoming TypeC
> > changes requires this) convert the u64 i915_power_well_desc::domains
> > mask to a bitmap.
> >
> > For simplicity I changed the for_each_power_domain_well() macros to
> > accept one domain only instead of a mask, as there isn't any current
> > user passing multiple domains.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 65 ++++-----
> > .../drm/i915/display/intel_display_power.c | 123 +++++++++++-------
> > .../drm/i915/display/intel_display_power.h | 16 ++-
> > .../display/intel_display_power_internal.h | 2 +-
> > .../i915/display/intel_display_power_map.c | 4 +-
> > 5 files changed, 119 insertions(+), 91 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 3094cfc668c81..d0b9618383ce3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -2372,66 +2372,71 @@ intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
> > }
> > }
> >
> > -static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> > +static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
> > + intel_power_domain_mask_t *mask)
> > {
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > struct drm_encoder *encoder;
> > enum pipe pipe = crtc->pipe;
> > - u64 mask;
> > +
> > + bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
> >
> > if (!crtc_state->hw.active)
> > - return 0;
> > + return;
> >
> > - mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
> > - mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(cpu_transcoder));
> > + set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
> > + set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
> > if (crtc_state->pch_pfit.enabled ||
> > crtc_state->pch_pfit.force_thru)
> > - mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
> > + set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
> >
> > drm_for_each_encoder_mask(encoder, &dev_priv->drm,
> > crtc_state->uapi.encoder_mask) {
> > struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
> >
> > - mask |= BIT_ULL(intel_encoder->power_domain);
> > + set_bit(intel_encoder->power_domain, mask->bits);
> > }
> >
> > if (HAS_DDI(dev_priv) && crtc_state->has_audio)
> > - mask |= BIT_ULL(POWER_DOMAIN_AUDIO_MMIO);
> > + set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
> >
> > if (crtc_state->shared_dpll)
> > - mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
> > + set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
> >
> > if (crtc_state->dsc.compression_enable)
> > - mask |= BIT_ULL(intel_dsc_power_domain(crtc, cpu_transcoder));
> > -
> > - return mask;
> > + set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
> > }
> >
> > -static u64
> > -modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> > +static void
> > +modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
> > + intel_power_domain_mask_t *old_domains)
> > {
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum intel_display_power_domain domain;
> > - u64 domains, new_domains, old_domains;
> > + intel_power_domain_mask_t domains, new_domains;
> >
> > - domains = get_crtc_power_domains(crtc_state);
> > + get_crtc_power_domains(crtc_state, &domains);
> >
> > - new_domains = domains & ~crtc->enabled_power_domains.mask;
> > - old_domains = crtc->enabled_power_domains.mask & ~domains;
> > + bitmap_andnot(new_domains.bits,
> > + domains.bits,
> > + crtc->enabled_power_domains.mask.bits,
> > + POWER_DOMAIN_NUM);
> > + bitmap_andnot(old_domains->bits,
> > + crtc->enabled_power_domains.mask.bits,
> > + domains.bits,
> > + POWER_DOMAIN_NUM);
> >
> > - for_each_power_domain(domain, new_domains)
> > + for_each_power_domain(domain, &new_domains)
> > intel_display_power_get_in_set(dev_priv,
> > &crtc->enabled_power_domains,
> > domain);
> > -
> > - return old_domains;
> > }
> >
> > static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
> > - u64 domains)
> > + intel_power_domain_mask_t *domains)
> > {
> > intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
> > &crtc->enabled_power_domains,
> > @@ -8628,7 +8633,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> > struct intel_crtc *crtc;
> > - u64 put_domains[I915_MAX_PIPES] = {};
> > + intel_power_domain_mask_t put_domains[I915_MAX_PIPES] = {};
> > intel_wakeref_t wakeref = 0;
> > int i;
> >
> > @@ -8645,9 +8650,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > new_crtc_state, i) {
> > if (intel_crtc_needs_modeset(new_crtc_state) ||
> > new_crtc_state->update_pipe) {
> > -
> > - put_domains[crtc->pipe] =
> > - modeset_get_crtc_power_domains(new_crtc_state);
> > + modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
> > }
> > }
> >
> > @@ -8746,7 +8749,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> > intel_post_plane_update(state, crtc);
> >
> > - modeset_put_crtc_power_domains(crtc, put_domains[crtc->pipe]);
> > + modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
> >
> > intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
> >
> > @@ -10702,11 +10705,11 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
> > for_each_intel_crtc(dev, crtc) {
> > struct intel_crtc_state *crtc_state =
> > to_intel_crtc_state(crtc->base.state);
> > - u64 put_domains;
> > + intel_power_domain_mask_t put_domains;
> >
> > - put_domains = modeset_get_crtc_power_domains(crtc_state);
> > - if (drm_WARN_ON(dev, put_domains))
> > - modeset_put_crtc_power_domains(crtc, put_domains);
> > + modeset_get_crtc_power_domains(crtc_state, &put_domains);
> > + if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
> > + modeset_put_crtc_power_domains(crtc, &put_domains);
> > }
> >
> > intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index a370ef8376410..cf014d79682ca 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -38,13 +38,13 @@
> > (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
> > (__power_well)--)
> >
> > -#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
> > +#define for_each_power_domain_well(__dev_priv, __power_well, __domain) \
> > for_each_power_well(__dev_priv, __power_well) \
> > - for_each_if((__power_well)->domains & (__domain_mask))
> > + for_each_if(test_bit((__domain), (__power_well)->domains.bits))
> >
> > -#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
> > +#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \
> > for_each_power_well_reverse(__dev_priv, __power_well) \
> > - for_each_if((__power_well)->domains & (__domain_mask))
> > + for_each_if(test_bit((__domain), (__power_well)->domains.bits))
> >
> > struct i915_power_well_regs {
> > i915_reg_t bios;
> > @@ -141,7 +141,7 @@ bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
> >
> > is_enabled = true;
> >
> > - for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) {
> > + for_each_power_domain_well_reverse(dev_priv, power_well, domain) {
> > if (power_well->desc->always_on)
> > continue;
> >
> > @@ -460,13 +460,18 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
> >
> > #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> >
> > -static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
> > +static void async_put_domains_mask(struct i915_power_domains *power_domains,
> > + intel_power_domain_mask_t *mask);
> >
> > static int power_well_async_ref_count(struct drm_i915_private *dev_priv,
> > struct i915_power_well *power_well)
> > {
> > - int refs = hweight64(power_well->domains &
> > - async_put_domains_mask(&dev_priv->power_domains));
> > + intel_power_domain_mask_t domain_mask;
> > + int refs;
> > +
> > + async_put_domains_mask(&dev_priv->power_domains, &domain_mask);
> > + bitmap_and(domain_mask.bits, domain_mask.bits, power_well->domains.bits, POWER_DOMAIN_NUM);
> > + refs = bitmap_weight(domain_mask.bits, POWER_DOMAIN_NUM);
> >
> > drm_WARN_ON(&dev_priv->drm, refs > power_well->count);
> >
> > @@ -1869,10 +1874,13 @@ static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
> > chv_set_pipe_power_well(dev_priv, power_well, false);
> > }
> >
> > -static u64 __async_put_domains_mask(struct i915_power_domains *power_domains)
> > +static void __async_put_domains_mask(struct i915_power_domains *power_domains,
> > + intel_power_domain_mask_t *mask)
> > {
> > - return power_domains->async_put_domains[0] |
> > - power_domains->async_put_domains[1];
> > + bitmap_or(mask->bits,
> > + power_domains->async_put_domains[0].bits,
> > + power_domains->async_put_domains[1].bits,
> > + POWER_DOMAIN_NUM);
> > }
> >
> > #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > @@ -1883,8 +1891,11 @@ assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
> > struct drm_i915_private *i915 = container_of(power_domains,
> > struct drm_i915_private,
> > power_domains);
> > - return !drm_WARN_ON(&i915->drm, power_domains->async_put_domains[0] &
> > - power_domains->async_put_domains[1]);
> > +
> > + return !drm_WARN_ON(&i915->drm,
> > + bitmap_intersects(power_domains->async_put_domains[0].bits,
> > + power_domains->async_put_domains[1].bits,
> > + POWER_DOMAIN_NUM));
> > }
> >
> > static bool
> > @@ -1893,14 +1904,17 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
> > struct drm_i915_private *i915 = container_of(power_domains,
> > struct drm_i915_private,
> > power_domains);
> > + intel_power_domain_mask_t async_put_mask;
> > enum intel_display_power_domain domain;
> > bool err = false;
> >
> > err |= !assert_async_put_domain_masks_disjoint(power_domains);
> > - err |= drm_WARN_ON(&i915->drm, !!power_domains->async_put_wakeref !=
> > - !!__async_put_domains_mask(power_domains));
> > + __async_put_domains_mask(power_domains, &async_put_mask);
> > + err |= drm_WARN_ON(&i915->drm,
> > + !!power_domains->async_put_wakeref !=
> > + !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM));
> >
> > - for_each_power_domain(domain, __async_put_domains_mask(power_domains))
> > + for_each_power_domain(domain, &async_put_mask)
> > err |= drm_WARN_ON(&i915->drm,
> > power_domains->domain_use_count[domain] != 1);
> >
> > @@ -1908,14 +1922,14 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
> > }
> >
> > static void print_power_domains(struct i915_power_domains *power_domains,
> > - const char *prefix, u64 mask)
> > + const char *prefix, intel_power_domain_mask_t *mask)
> > {
> > struct drm_i915_private *i915 = container_of(power_domains,
> > struct drm_i915_private,
> > power_domains);
> > enum intel_display_power_domain domain;
> >
> > - drm_dbg(&i915->drm, "%s (%lu):\n", prefix, hweight64(mask));
> > + drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
> > for_each_power_domain(domain, mask)
> > drm_dbg(&i915->drm, "%s use_count %d\n",
> > intel_display_power_domain_str(domain),
> > @@ -1933,9 +1947,9 @@ print_async_put_domains_state(struct i915_power_domains *power_domains)
> > power_domains->async_put_wakeref);
> >
> > print_power_domains(power_domains, "async_put_domains[0]",
> > - power_domains->async_put_domains[0]);
> > + &power_domains->async_put_domains[0]);
> > print_power_domains(power_domains, "async_put_domains[1]",
> > - power_domains->async_put_domains[1]);
> > + &power_domains->async_put_domains[1]);
> > }
> >
> > static void
> > @@ -1959,11 +1973,13 @@ verify_async_put_domains_state(struct i915_power_domains *power_domains)
> >
> > #endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */
> >
> > -static u64 async_put_domains_mask(struct i915_power_domains *power_domains)
> > +static void async_put_domains_mask(struct i915_power_domains *power_domains,
> > + intel_power_domain_mask_t *mask)
> > +
> > {
> > assert_async_put_domain_masks_disjoint(power_domains);
> >
> > - return __async_put_domains_mask(power_domains);
> > + __async_put_domains_mask(power_domains, mask);
> > }
> >
> > static void
> > @@ -1972,8 +1988,8 @@ async_put_domains_clear_domain(struct i915_power_domains *power_domains,
> > {
> > assert_async_put_domain_masks_disjoint(power_domains);
> >
> > - power_domains->async_put_domains[0] &= ~BIT_ULL(domain);
> > - power_domains->async_put_domains[1] &= ~BIT_ULL(domain);
> > + clear_bit(domain, power_domains->async_put_domains[0].bits);
> > + clear_bit(domain, power_domains->async_put_domains[1].bits);
> > }
> >
> > static bool
> > @@ -1981,16 +1997,19 @@ intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
> > enum intel_display_power_domain domain)
> > {
> > struct i915_power_domains *power_domains = &dev_priv->power_domains;
> > + intel_power_domain_mask_t async_put_mask;
> > bool ret = false;
> >
> > - if (!(async_put_domains_mask(power_domains) & BIT_ULL(domain)))
> > + async_put_domains_mask(power_domains, &async_put_mask);
> > + if (!test_bit(domain, async_put_mask.bits))
> > goto out_verify;
> >
> > async_put_domains_clear_domain(power_domains, domain);
> >
> > ret = true;
> >
> > - if (async_put_domains_mask(power_domains))
> > + async_put_domains_mask(power_domains, &async_put_mask);
> > + if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM))
> > goto out_verify;
> >
> > cancel_delayed_work(&power_domains->async_put_work);
> > @@ -2012,7 +2031,7 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
> > if (intel_display_power_grab_async_put_ref(dev_priv, domain))
> > return;
> >
> > - for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
> > + for_each_power_domain_well(dev_priv, power_well, domain)
> > intel_power_well_get(dev_priv, power_well);
> >
> > power_domains->domain_use_count[domain]++;
> > @@ -2093,20 +2112,22 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
> > struct i915_power_domains *power_domains;
> > struct i915_power_well *power_well;
> > const char *name = intel_display_power_domain_str(domain);
> > + intel_power_domain_mask_t async_put_mask;
> >
> > power_domains = &dev_priv->power_domains;
> >
> > drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain],
> > "Use count on domain %s is already zero\n",
> > name);
> > + async_put_domains_mask(power_domains, &async_put_mask);
> > drm_WARN(&dev_priv->drm,
> > - async_put_domains_mask(power_domains) & BIT_ULL(domain),
> > + test_bit(domain, async_put_mask.bits),
> > "Async disabling of domain %s is pending\n",
> > name);
> >
> > power_domains->domain_use_count[domain]--;
> >
> > - for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain))
> > + for_each_power_domain_well_reverse(dev_priv, power_well, domain)
> > intel_power_well_put(dev_priv, power_well);
> > }
> >
> > @@ -2135,7 +2156,7 @@ queue_async_put_domains_work(struct i915_power_domains *power_domains,
> > }
> >
> > static void
> > -release_async_put_domains(struct i915_power_domains *power_domains, u64 mask)
> > +release_async_put_domains(struct i915_power_domains *power_domains, intel_power_domain_mask_t *mask)
> > {
> > struct drm_i915_private *dev_priv =
> > container_of(power_domains, struct drm_i915_private,
> > @@ -2183,12 +2204,15 @@ intel_display_power_put_async_work(struct work_struct *work)
> > goto out_verify;
> >
> > release_async_put_domains(power_domains,
> > - power_domains->async_put_domains[0]);
> > + &power_domains->async_put_domains[0]);
> >
> > /* Requeue the work if more domains were async put meanwhile. */
> > - if (power_domains->async_put_domains[1]) {
> > - power_domains->async_put_domains[0] =
> > - fetch_and_zero(&power_domains->async_put_domains[1]);
> > + if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) {
> > + bitmap_copy(power_domains->async_put_domains[0].bits,
> > + power_domains->async_put_domains[1].bits,
> > + POWER_DOMAIN_NUM);
> > + bitmap_zero(power_domains->async_put_domains[1].bits,
> > + POWER_DOMAIN_NUM);
> > queue_async_put_domains_work(power_domains,
> > fetch_and_zero(&new_work_wakeref));
> > } else {
> > @@ -2240,9 +2264,9 @@ void __intel_display_power_put_async(struct drm_i915_private *i915,
> >
> > /* Let a pending work requeue itself or queue a new one. */
> > if (power_domains->async_put_wakeref) {
> > - power_domains->async_put_domains[1] |= BIT_ULL(domain);
> > + set_bit(domain, power_domains->async_put_domains[1].bits);
> > } else {
> > - power_domains->async_put_domains[0] |= BIT_ULL(domain);
> > + set_bit(domain, power_domains->async_put_domains[0].bits);
> > queue_async_put_domains_work(power_domains,
> > fetch_and_zero(&work_wakeref));
> > }
> > @@ -2273,6 +2297,7 @@ void __intel_display_power_put_async(struct drm_i915_private *i915,
> > void intel_display_power_flush_work(struct drm_i915_private *i915)
> > {
> > struct i915_power_domains *power_domains = &i915->power_domains;
> > + intel_power_domain_mask_t async_put_mask;
> > intel_wakeref_t work_wakeref;
> >
> > mutex_lock(&power_domains->lock);
> > @@ -2281,8 +2306,8 @@ void intel_display_power_flush_work(struct drm_i915_private *i915)
> > if (!work_wakeref)
> > goto out_verify;
> >
> > - release_async_put_domains(power_domains,
> > - async_put_domains_mask(power_domains));
> > + async_put_domains_mask(power_domains, &async_put_mask);
> > + release_async_put_domains(power_domains, &async_put_mask);
> > cancel_delayed_work(&power_domains->async_put_work);
> >
> > out_verify:
> > @@ -2361,13 +2386,13 @@ intel_display_power_get_in_set(struct drm_i915_private *i915,
> > {
> > intel_wakeref_t __maybe_unused wf;
> >
> > - drm_WARN_ON(&i915->drm, power_domain_set->mask & BIT_ULL(domain));
> > + drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> >
> > wf = intel_display_power_get(i915, domain);
> > #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > power_domain_set->wakerefs[domain] = wf;
> > #endif
> > - power_domain_set->mask |= BIT_ULL(domain);
> > + set_bit(domain, power_domain_set->mask.bits);
> > }
> >
> > bool
> > @@ -2377,7 +2402,7 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
> > {
> > intel_wakeref_t wf;
> >
> > - drm_WARN_ON(&i915->drm, power_domain_set->mask & BIT_ULL(domain));
> > + drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> >
> > wf = intel_display_power_get_if_enabled(i915, domain);
> > if (!wf)
> > @@ -2386,7 +2411,7 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
> > #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > power_domain_set->wakerefs[domain] = wf;
> > #endif
> > - power_domain_set->mask |= BIT_ULL(domain);
> > + set_bit(domain, power_domain_set->mask.bits);
> >
> > return true;
> > }
> > @@ -2394,11 +2419,11 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
> > void
> > intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> > struct intel_display_power_domain_set *power_domain_set,
> > - u64 mask)
> > + intel_power_domain_mask_t *mask)
> > {
> > enum intel_display_power_domain domain;
> >
> > - drm_WARN_ON(&i915->drm, mask & ~power_domain_set->mask);
> > + drm_WARN_ON(&i915->drm, !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
> >
> > for_each_power_domain(domain, mask) {
> > intel_wakeref_t __maybe_unused wf = -1;
> > @@ -2407,7 +2432,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> > wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
> > #endif
> > intel_display_power_put(i915, domain, wf);
> > - power_domain_set->mask &= ~BIT_ULL(domain);
> > + clear_bit(domain, power_domain_set->mask.bits);
> > }
> > }
> >
> > @@ -2711,8 +2736,6 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> > dev_priv->dmc.target_dc_state =
> > sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
> >
> > - BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
> > -
> > mutex_init(&power_domains->lock);
> >
> > INIT_DELAYED_WORK(&power_domains->async_put_work,
> > @@ -3805,7 +3828,7 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
> > drm_dbg(&i915->drm, "%-25s %d\n",
> > power_well->desc->name, power_well->count);
> >
> > - for_each_power_domain(domain, power_well->domains)
> > + for_each_power_domain(domain, &power_well->domains)
> > drm_dbg(&i915->drm, " %-23s %d\n",
> > intel_display_power_domain_str(domain),
> > power_domains->domain_use_count[domain]);
> > @@ -3847,7 +3870,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
> > power_well->count, enabled);
> >
> > domains_count = 0;
> > - for_each_power_domain(domain, power_well->domains)
> > + for_each_power_domain(domain, &power_well->domains)
> > domains_count += power_domains->domain_use_count[domain];
> >
> > if (power_well->count != domains_count) {
> > @@ -3962,7 +3985,7 @@ void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m
> > seq_printf(m, "%-25s %d\n", power_well->desc->name,
> > power_well->count);
> >
> > - for_each_power_domain(power_domain, power_well->domains)
> > + for_each_power_domain(power_domain, &power_well->domains)
> > seq_printf(m, " %-23s %d\n",
> > intel_display_power_domain_str(power_domain),
> > power_domains->domain_use_count[power_domain]);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> > index c3232809b95f9..c7155801f9bc6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > @@ -164,6 +164,8 @@ enum i915_power_well_id {
> > ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
> > (tran) + POWER_DOMAIN_TRANSCODER_A)
> >
> > +typedef struct { DECLARE_BITMAP(bits, POWER_DOMAIN_NUM); } intel_power_domain_mask_t;
>
> I think the typedef is overkill here, and they should only be used for
> totally opaque objects anyway per coding style.
>
> I guess having the struct makes it easier to manage it in parameters and
> declarations, so it would be:
>
> struct intel_power_domain_mask {
> DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
> };
Ok. Btw, I found having a struct useful after forgetting to convert
if (domains) ...
to
if (!bitmap_empty(domains)) ...
--Imre
>
>
> BR,
> Jani.
>
> > +
> > struct i915_power_domains {
> > /*
> > * Power wells needed for initialization at driver init and suspend
> > @@ -181,21 +183,21 @@ struct i915_power_domains {
> >
> > struct delayed_work async_put_work;
> > intel_wakeref_t async_put_wakeref;
> > - u64 async_put_domains[2];
> > + intel_power_domain_mask_t async_put_domains[2];
> >
> > struct i915_power_well *power_wells;
> > };
> >
> > struct intel_display_power_domain_set {
> > - u64 mask;
> > + intel_power_domain_mask_t mask;
> > #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
> > intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
> > #endif
> > };
> >
> > -#define for_each_power_domain(domain, mask) \
> > - for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
> > - for_each_if(BIT_ULL(domain) & (mask))
> > +#define for_each_power_domain(__domain, __mask) \
> > + for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \
> > + for_each_if(test_bit((__domain), (__mask)->bits))
> >
> > /* intel_display_power.c */
> > int intel_power_domains_init(struct drm_i915_private *dev_priv);
> > @@ -278,13 +280,13 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
> > void
> > intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> > struct intel_display_power_domain_set *power_domain_set,
> > - u64 mask);
> > + intel_power_domain_mask_t *mask);
> >
> > static inline void
> > intel_display_power_put_all_in_set(struct drm_i915_private *i915,
> > struct intel_display_power_domain_set *power_domain_set)
> > {
> > - intel_display_power_put_mask_in_set(i915, power_domain_set, power_domain_set->mask);
> > + intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
> > }
> >
> > void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_internal.h b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> > index 49f6155e62c47..c4167ac2f21f8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_internal.h
> > @@ -68,7 +68,7 @@ struct i915_power_well_desc {
> >
> > struct i915_power_well {
> > const struct i915_power_well_desc *desc;
> > - u64 domains;
> > + intel_power_domain_mask_t domains;
> > /* power well enable/disable usage count */
> > int count;
> > /* cached hw enabled state */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > index 42f5541c5ecc8..7ec4cafec6ba5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > @@ -2220,13 +2220,13 @@ static void init_power_well_domains(const struct i915_power_well_desc *desc,
> > return;
> >
> > if (desc->domain_list->count == 0) {
> > - power_well->domains = GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0);
> > + bitmap_fill(power_well->domains.bits, POWER_DOMAIN_NUM);
> >
> > return;
> > }
> >
> > for (j = 0; j < desc->domain_list->count; j++)
> > - power_well->domains |= BIT_ULL(desc->domain_list->list[j]);
> > + set_bit(desc->domain_list->list[j], power_well->domains.bits);
> > }
> >
> > static int
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2022-02-03 18:25 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-28 11:48 [Intel-gfx] [PATCH 00/19] drm/i915: Refactor the display power domain mappings Imre Deak
2022-01-28 11:48 ` [Intel-gfx] [PATCH 01/19] drm/i915: Fix the VDSC_PW2 power domain enum value Imre Deak
2022-01-28 11:48 ` [Intel-gfx] [PATCH 02/19] drm/i915: Unexport the for_each_power_well() macros Imre Deak
2022-01-28 11:48 ` [Intel-gfx] [PATCH 03/19] drm/i915: Move the i915_power_well_regs struct into i915_power_well_ops Imre Deak
2022-01-28 11:48 ` [Intel-gfx] [PATCH 04/19] drm/i915: Move the power domain->well mappings to intel_display_power_map.c Imre Deak
2022-01-31 12:15 ` Jani Nikula
2022-01-31 16:00 ` Imre Deak
2022-02-01 10:53 ` Jani Nikula
2022-02-01 11:22 ` Jani Nikula
2022-02-03 17:57 ` Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 05/19] drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 06/19] drm/i915: Move the HSW power well flags " Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 07/19] drm/i915: Rename the power domain names to end with pipes/ports Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 08/19] drm/i915: Sanitize the power well names Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 09/19] drm/i915: Convert the power well descriptor domain mask to a list Imre Deak
2022-02-01 11:10 ` Jani Nikula
2022-02-03 18:11 ` Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 10/19] drm/i915: Convert the u64 power well domains mask to a bitmap Imre Deak
2022-02-01 11:20 ` Jani Nikula
2022-02-03 18:22 ` Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 11/19] drm/i915: Simplify power well definitions by adding power well instances Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 12/19] drm/i915: Allow platforms to share power well descriptors Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 13/19] drm/i915: Simplify the DG1 " Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 14/19] drm/i915: Sanitize the ADL-S power well definition Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 15/19] drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 16/19] drm/i915: Remove the aliasing of power domain enum values Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 17/19] drm/i915: Remove the ICL specific TBT power domains Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 18/19] drm/i915: Remove duplicate DDI/AUX power domain mappings Imre Deak
2022-01-28 11:49 ` [Intel-gfx] [PATCH 19/19] drm/i915: Remove the XELPD specific AUX and DDI power domains Imre Deak
2022-01-28 12:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Refactor the display power domain mappings Patchwork
2022-01-28 12:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-28 13:27 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.