From: Mika Kuoppala <mika.kuoppala@linux.intel.com> To: Matthew Auld <matthew.auld@intel.com>, intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: Re: [PATCH] drm/i915/gtt: add some flushing for the 64K GTT path Date: Fri, 03 Sep 2021 19:29:42 +0300 [thread overview] Message-ID: <871r65ipvt.fsf@gaia.fi.intel.com> (raw) In-Reply-To: <20210903155317.1854012-1-matthew.auld@intel.com> Matthew Auld <matthew.auld@intel.com> writes: > If we need to mark the PDE as operating in 64K GTT mode, we should be > paranoid and flush the extra writes, like we already do for the PTEs. On > some platforms the clflush can apparently add the just the right amount > of magical delay to force the GPU to see the updated entry. > > Signed-off-by: Matthew Auld <matthew.auld@intel.com> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Makes sense to follow the same pattern as the other writes. Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > index 6e0e52eeb87a..6a5af995f5b1 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > @@ -548,6 +548,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma, > I915_GTT_PAGE_SIZE_2M)))) { > vaddr = px_vaddr(pd); > vaddr[maybe_64K] |= GEN8_PDE_IPS_64K; > + clflush_cache_range(vaddr, PAGE_SIZE); > page_size = I915_GTT_PAGE_SIZE_64K; > > /* > @@ -568,6 +569,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma, > for (i = 1; i < index; i += 16) > memset64(vaddr + i, encode, 15); > > + clflush_cache_range(vaddr, PAGE_SIZE); > } > } > > -- > 2.26.3
WARNING: multiple messages have this Message-ID (diff)
From: Mika Kuoppala <mika.kuoppala@linux.intel.com> To: Matthew Auld <matthew.auld@intel.com>, intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH] drm/i915/gtt: add some flushing for the 64K GTT path Date: Fri, 03 Sep 2021 19:29:42 +0300 [thread overview] Message-ID: <871r65ipvt.fsf@gaia.fi.intel.com> (raw) In-Reply-To: <20210903155317.1854012-1-matthew.auld@intel.com> Matthew Auld <matthew.auld@intel.com> writes: > If we need to mark the PDE as operating in 64K GTT mode, we should be > paranoid and flush the extra writes, like we already do for the PTEs. On > some platforms the clflush can apparently add the just the right amount > of magical delay to force the GPU to see the updated entry. > > Signed-off-by: Matthew Auld <matthew.auld@intel.com> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Makes sense to follow the same pattern as the other writes. Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > index 6e0e52eeb87a..6a5af995f5b1 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > @@ -548,6 +548,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma, > I915_GTT_PAGE_SIZE_2M)))) { > vaddr = px_vaddr(pd); > vaddr[maybe_64K] |= GEN8_PDE_IPS_64K; > + clflush_cache_range(vaddr, PAGE_SIZE); > page_size = I915_GTT_PAGE_SIZE_64K; > > /* > @@ -568,6 +569,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma, > for (i = 1; i < index; i += 16) > memset64(vaddr + i, encode, 15); > > + clflush_cache_range(vaddr, PAGE_SIZE); > } > } > > -- > 2.26.3
next prev parent reply other threads:[~2021-09-03 16:31 UTC|newest] Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-03 15:53 [PATCH] drm/i915/gtt: add some flushing for the 64K GTT path Matthew Auld 2021-09-03 15:53 ` [Intel-gfx] " Matthew Auld 2021-09-03 16:29 ` Mika Kuoppala [this message] 2021-09-03 16:29 ` Mika Kuoppala 2021-09-03 18:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork 2021-09-03 20:41 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2021-09-07 19:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gtt: add some flushing for the 64K GTT path (rev2) Patchwork 2021-09-07 22:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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