[PATCH 1/3] drm/i915: Sink rate read should be saved in deca-kHz

[PATCH 1/3] drm/i915: Sink rate read should be saved in deca-kHz

[Sonika Jindal]

The sink rate read from supported link rate table is in KHz as per spec
while in drm, the saved clock is in deca-KHz. So divide the link rate by
10 before storing.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
Just resending it along with the other intermediate link rate patches
(It was posted orginally on 21st April)

Thanks,
Sonika

 drivers/gpu/drm/i915/intel_dp.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bacdec5..6bd5afb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3906,7 +3906,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 			if (val == 0)
 				break;
 
-			intel_dp->sink_rates[i] = val * 200;
+			/* Value read is in kHz while drm clock is saved in deca-kHz */
+			intel_dp->sink_rates[i] = (val * 200) / 10;
 		}
 		intel_dp->num_sink_rates = i;
 	}
-- 
1.7.10.4

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[PATCH 2/3] drm/i915: Rename dp rates array as per platform

[Sonika Jindal]

Renaming gen9_rates to skl_rates because other platforms may have different
supported rates.

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c |   10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6bd5afb..c9d50d1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -84,8 +84,8 @@ static const struct dp_link_dpll chv_dpll[] = {
 	{ DP_LINK_BW_5_4,	/* m2_int = 27, m2_fraction = 0 */
 		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
 };
-/* Skylake supports following rates */
-static const int gen9_rates[] = { 162000, 216000, 270000,
+
+static const int skl_rates[] = { 162000, 216000, 270000,
 				  324000, 432000, 540000 };
 static const int chv_rates[] = { 162000, 202500, 210000, 216000,
 				 243000, 270000, 324000, 405000,
@@ -1161,9 +1161,9 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 static int
 intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 {
-	if (INTEL_INFO(dev)->gen >= 9) {
-		*source_rates = gen9_rates;
-		return ARRAY_SIZE(gen9_rates);
+	if (IS_SKYLAKE(dev)) {
+		*source_rates = skl_rates;
+		return ARRAY_SIZE(skl_rates);
 	} else if (IS_CHERRYVIEW(dev)) {
 		*source_rates = chv_rates;
 		return ARRAY_SIZE(chv_rates);
-- 
1.7.10.4

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[PATCH 3/3] drm/i915/bxt: edp1.4 Intermediate Freq support

[Sonika Jindal]

BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |   44 ++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_dp.c  |    7 +++++-
 2 files changed, 48 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9c1e74a..c0cb5f7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1397,8 +1397,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
 			clk_div.lanestagger = 0x04;
 		else
 			clk_div.lanestagger = 0x02;
-	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
-			intel_encoder->type == INTEL_OUTPUT_EDP) {
+	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
 		struct drm_encoder *encoder = &intel_encoder->base;
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
@@ -1416,8 +1415,49 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
 			clk_div = bxt_dp_clk_val[0];
 			DRM_ERROR("Unknown link rate\n");
 		}
+	} else if (intel_encoder->type == INTEL_OUTPUT_EDP) {
+		struct drm_encoder *encoder = &intel_encoder->base;
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+		int link_rate;
+
+		/*
+		 * If edp1.4 intermediate frequency support is present, we set
+		 * link_bw to 0 and a valid rate index in rate_select.
+		 */
+		if (intel_dp->link_bw)
+			link_rate = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
+		else
+			link_rate = intel_dp->sink_rates[intel_dp->rate_select];
+
+		switch (link_rate) {
+		case 162000:
+			clk_div = bxt_dp_clk_val[0];
+			break;
+		case 216000:
+			clk_div = bxt_dp_clk_val[3];
+			break;
+		case 243000:
+			clk_div = bxt_dp_clk_val[4];
+			break;
+		case 270000:
+			clk_div = bxt_dp_clk_val[1];
+			break;
+		case 324000:
+			clk_div = bxt_dp_clk_val[5];
+			break;
+		case 432000:
+			clk_div = bxt_dp_clk_val[6];
+			break;
+		case 540000:
+			clk_div = bxt_dp_clk_val[2];
+			break;
+		default:
+			clk_div = bxt_dp_clk_val[0];
+			DRM_ERROR("Unknown link rate\n");
+		}
 	}
 
+
 	crtc_state->dpll_hw_state.ebb0 =
 		PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
 	crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c9d50d1..e6ee7c6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -85,6 +85,8 @@ static const struct dp_link_dpll chv_dpll[] = {
 		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
 };
 
+static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
+				  324000, 432000, 540000 };
 static const int skl_rates[] = { 162000, 216000, 270000,
 				  324000, 432000, 540000 };
 static const int chv_rates[] = { 162000, 202500, 210000, 216000,
@@ -1161,7 +1163,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 static int
 intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 {
-	if (IS_SKYLAKE(dev)) {
+	if (IS_BROXTON(dev)) {
+		*source_rates = bxt_rates;
+		return ARRAY_SIZE(bxt_rates);
+	} else if (IS_SKYLAKE(dev)) {
 		*source_rates = skl_rates;
 		return ARRAY_SIZE(skl_rates);
 	} else if (IS_CHERRYVIEW(dev)) {
-- 
1.7.10.4

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Re: [PATCH 1/3] drm/i915: Sink rate read should be saved in deca-kHz

[Jani Nikula]

On Thu, 07 May 2015, Sonika Jindal <sonika.jindal@intel.com> wrote:
> The sink rate read from supported link rate table is in KHz as per spec
> while in drm, the saved clock is in deca-KHz. So divide the link rate by
> 10 before storing.

Please refer to the commit which broke things. git blame is your
friend. We need the information to know which kernel version the bug has
landed or is about to land to, so we can queue the fix in the same
place.

If developers don't do this, maintainers will have to anyway, which
doesn't scale well, which leads to grumpy maintainers. ;)

Thanks,
Jani.


>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
> Just resending it along with the other intermediate link rate patches
> (It was posted orginally on 21st April)
>
> Thanks,
> Sonika
>
>  drivers/gpu/drm/i915/intel_dp.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index bacdec5..6bd5afb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3906,7 +3906,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>  			if (val == 0)
>  				break;
>  
> -			intel_dp->sink_rates[i] = val * 200;
> +			/* Value read is in kHz while drm clock is saved in deca-kHz */
> +			intel_dp->sink_rates[i] = (val * 200) / 10;
>  		}
>  		intel_dp->num_sink_rates = i;
>  	}
> -- 
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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[PATCH] drm/i915: Sink rate read should be saved in deca-kHz

[Sonika Jindal]

The sink rate read from supported link rate table is in KHz as per spec
while in drm, the saved clock is in deca-KHz. So divide the link rate by
10 before storing.

Reading of rates was added by:
commit fc0f8e25318f ("drm/i915/skl: Read sink supported rates from edp
panel")

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bacdec5..6bd5afb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3906,7 +3906,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 			if (val == 0)
 				break;
 
-			intel_dp->sink_rates[i] = val * 200;
+			/* Value read is in kHz while drm clock is saved in deca-kHz */
+			intel_dp->sink_rates[i] = (val * 200) / 10;
 		}
 		intel_dp->num_sink_rates = i;
 	}
-- 
1.7.10.4

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Re: [PATCH 1/3] drm/i915: Sink rate read should be saved in deca-kHz

[Ville Syrjälä]

On Thu, May 07, 2015 at 11:10:30AM +0300, Jani Nikula wrote:
> On Thu, 07 May 2015, Sonika Jindal <sonika.jindal@intel.com> wrote:
> > The sink rate read from supported link rate table is in KHz as per spec
> > while in drm, the saved clock is in deca-KHz. So divide the link rate by
> > 10 before storing.
> 
> Please refer to the commit which broke things. git blame is your
> friend. We need the information to know which kernel version the bug has
> landed or is about to land to, so we can queue the fix in the same
> place.
> 
> If developers don't do this, maintainers will have to anyway, which
> doesn't scale well, which leads to grumpy maintainers. ;)

Indeed, now I wonder if I broke it during the refactoring or was it
already like that before that. Hmm. Doesn't look like it was me, but
I did fail to spot it during the review :(

Anyway, with the commit msg amended to Jani's liking this is:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> Thanks,
> Jani.
> 
> 
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> > ---
> > Just resending it along with the other intermediate link rate patches
> > (It was posted orginally on 21st April)
> >
> > Thanks,
> > Sonika
> >
> >  drivers/gpu/drm/i915/intel_dp.c |    3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index bacdec5..6bd5afb 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3906,7 +3906,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
> >  			if (val == 0)
> >  				break;
> >  
> > -			intel_dp->sink_rates[i] = val * 200;
> > +			/* Value read is in kHz while drm clock is saved in deca-kHz */
> > +			intel_dp->sink_rates[i] = (val * 200) / 10;
> >  		}
> >  		intel_dp->num_sink_rates = i;
> >  	}
> > -- 
> > 1.7.10.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 2/3] drm/i915: Rename dp rates array as per platform

[Ville Syrjälä]

On Thu, May 07, 2015 at 09:52:08AM +0530, Sonika Jindal wrote:
> Renaming gen9_rates to skl_rates because other platforms may have different
> supported rates.
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c |   10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 6bd5afb..c9d50d1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -84,8 +84,8 @@ static const struct dp_link_dpll chv_dpll[] = {
>  	{ DP_LINK_BW_5_4,	/* m2_int = 27, m2_fraction = 0 */
>  		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>  };
> -/* Skylake supports following rates */
> -static const int gen9_rates[] = { 162000, 216000, 270000,
> +
> +static const int skl_rates[] = { 162000, 216000, 270000,
>  				  324000, 432000, 540000 };
>  static const int chv_rates[] = { 162000, 202500, 210000, 216000,
>  				 243000, 270000, 324000, 405000,
> @@ -1161,9 +1161,9 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>  static int
>  intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>  {
> -	if (INTEL_INFO(dev)->gen >= 9) {
> -		*source_rates = gen9_rates;
> -		return ARRAY_SIZE(gen9_rates);
> +	if (IS_SKYLAKE(dev)) {
> +		*source_rates = skl_rates;
> +		return ARRAY_SIZE(skl_rates);
>  	} else if (IS_CHERRYVIEW(dev)) {
>  		*source_rates = chv_rates;
>  		return ARRAY_SIZE(chv_rates);
> -- 
> 1.7.10.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 3/3] drm/i915/bxt: edp1.4 Intermediate Freq support

[Ville Syrjälä]

On Thu, May 07, 2015 at 09:52:09AM +0530, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c |   44 ++++++++++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_dp.c  |    7 +++++-
>  2 files changed, 48 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 9c1e74a..c0cb5f7 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1397,8 +1397,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>  			clk_div.lanestagger = 0x04;
>  		else
>  			clk_div.lanestagger = 0x02;
> -	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
> -			intel_encoder->type == INTEL_OUTPUT_EDP) {
> +	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
>  		struct drm_encoder *encoder = &intel_encoder->base;
>  		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  
> @@ -1416,8 +1415,49 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>  			clk_div = bxt_dp_clk_val[0];
>  			DRM_ERROR("Unknown link rate\n");
>  		}
> +	} else if (intel_encoder->type == INTEL_OUTPUT_EDP) {
> +		struct drm_encoder *encoder = &intel_encoder->base;
> +		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +		int link_rate;
> +
> +		/*
> +		 * If edp1.4 intermediate frequency support is present, we set
> +		 * link_bw to 0 and a valid rate index in rate_select.
> +		 */
> +		if (intel_dp->link_bw)
> +			link_rate = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
> +		else
> +			link_rate = intel_dp->sink_rates[intel_dp->rate_select];

The chosen clock should already be passed in, so no there should be no
need for this. I see the DP case does has the same issue.

> +
> +		switch (link_rate) {
> +		case 162000:
> +			clk_div = bxt_dp_clk_val[0];
> +			break;
> +		case 216000:
> +			clk_div = bxt_dp_clk_val[3];
> +			break;
> +		case 243000:
> +			clk_div = bxt_dp_clk_val[4];
> +			break;
> +		case 270000:
> +			clk_div = bxt_dp_clk_val[1];
> +			break;
> +		case 324000:
> +			clk_div = bxt_dp_clk_val[5];
> +			break;
> +		case 432000:
> +			clk_div = bxt_dp_clk_val[6];
> +			break;
> +		case 540000:
> +			clk_div = bxt_dp_clk_val[2];
> +			break;
> +		default:
> +			clk_div = bxt_dp_clk_val[0];
> +			DRM_ERROR("Unknown link rate\n");
> +		}

This looks rather fragile. I would suggest storing the link rate in
the bxt_clk_div structure and just looping through the array looking for
the correct rate. That will also work for normal DP, so less code in the
end.

>  	}
>  
> +

Spurious whitespace.

>  	crtc_state->dpll_hw_state.ebb0 =
>  		PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
>  	crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c9d50d1..e6ee7c6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -85,6 +85,8 @@ static const struct dp_link_dpll chv_dpll[] = {
>  		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>  };
>  
> +static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
> +				  324000, 432000, 540000 };
>  static const int skl_rates[] = { 162000, 216000, 270000,
>  				  324000, 432000, 540000 };
>  static const int chv_rates[] = { 162000, 202500, 210000, 216000,
> @@ -1161,7 +1163,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>  static int
>  intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>  {
> -	if (IS_SKYLAKE(dev)) {
> +	if (IS_BROXTON(dev)) {
> +		*source_rates = bxt_rates;
> +		return ARRAY_SIZE(bxt_rates);
> +	} else if (IS_SKYLAKE(dev)) {
>  		*source_rates = skl_rates;
>  		return ARRAY_SIZE(skl_rates);
>  	} else if (IS_CHERRYVIEW(dev)) {
> -- 
> 1.7.10.4
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Intel OTC
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Re: [PATCH 3/3] drm/i915/bxt: edp1.4 Intermediate Freq support

[Jindal, Sonika]

On 5/7/2015 2:11 PM, Ville Syrjälä wrote:
> On Thu, May 07, 2015 at 09:52:09AM +0530, Sonika Jindal wrote:
>> BXT supports following intermediate link rates for edp:
>> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
>> Adding support for programming the intermediate rates.
>>
>> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_ddi.c |   44 ++++++++++++++++++++++++++++++++++++--
>>   drivers/gpu/drm/i915/intel_dp.c  |    7 +++++-
>>   2 files changed, 48 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index 9c1e74a..c0cb5f7 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -1397,8 +1397,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>>   			clk_div.lanestagger = 0x04;
>>   		else
>>   			clk_div.lanestagger = 0x02;
>> -	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
>> -			intel_encoder->type == INTEL_OUTPUT_EDP) {
>> +	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
>>   		struct drm_encoder *encoder = &intel_encoder->base;
>>   		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>
>> @@ -1416,8 +1415,49 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>>   			clk_div = bxt_dp_clk_val[0];
>>   			DRM_ERROR("Unknown link rate\n");
>>   		}
>> +	} else if (intel_encoder->type == INTEL_OUTPUT_EDP) {
>> +		struct drm_encoder *encoder = &intel_encoder->base;
>> +		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> +		int link_rate;
>> +
>> +		/*
>> +		 * If edp1.4 intermediate frequency support is present, we set
>> +		 * link_bw to 0 and a valid rate index in rate_select.
>> +		 */
>> +		if (intel_dp->link_bw)
>> +			link_rate = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
>> +		else
>> +			link_rate = intel_dp->sink_rates[intel_dp->rate_select];
>
> The chosen clock should already be passed in, so no there should be no
> need for this. I see the DP case does has the same issue.
Yes it was copied from DP :)

>
>> +
>> +		switch (link_rate) {
>> +		case 162000:
>> +			clk_div = bxt_dp_clk_val[0];
>> +			break;
>> +		case 216000:
>> +			clk_div = bxt_dp_clk_val[3];
>> +			break;
>> +		case 243000:
>> +			clk_div = bxt_dp_clk_val[4];
>> +			break;
>> +		case 270000:
>> +			clk_div = bxt_dp_clk_val[1];
>> +			break;
>> +		case 324000:
>> +			clk_div = bxt_dp_clk_val[5];
>> +			break;
>> +		case 432000:
>> +			clk_div = bxt_dp_clk_val[6];
>> +			break;
>> +		case 540000:
>> +			clk_div = bxt_dp_clk_val[2];
>> +			break;
>> +		default:
>> +			clk_div = bxt_dp_clk_val[0];
>> +			DRM_ERROR("Unknown link rate\n");
>> +		}
>
> This looks rather fragile. I would suggest storing the link rate in
> the bxt_clk_div structure and just looping through the array looking for
> the correct rate. That will also work for normal DP, so less code in the
> end.
Ok, I will do that.

>
>>   	}
>>
>> +
>
> Spurious whitespace.
:(
>
>>   	crtc_state->dpll_hw_state.ebb0 =
>>   		PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
>>   	crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index c9d50d1..e6ee7c6 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -85,6 +85,8 @@ static const struct dp_link_dpll chv_dpll[] = {
>>   		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>>   };
>>
>> +static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
>> +				  324000, 432000, 540000 };
>>   static const int skl_rates[] = { 162000, 216000, 270000,
>>   				  324000, 432000, 540000 };
>>   static const int chv_rates[] = { 162000, 202500, 210000, 216000,
>> @@ -1161,7 +1163,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>>   static int
>>   intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>>   {
>> -	if (IS_SKYLAKE(dev)) {
>> +	if (IS_BROXTON(dev)) {
>> +		*source_rates = bxt_rates;
>> +		return ARRAY_SIZE(bxt_rates);
>> +	} else if (IS_SKYLAKE(dev)) {
>>   		*source_rates = skl_rates;
>>   		return ARRAY_SIZE(skl_rates);
>>   	} else if (IS_CHERRYVIEW(dev)) {
>> --
>> 1.7.10.4
>>
>> _______________________________________________
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>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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Re: [PATCH] drm/i915: Sink rate read should be saved in deca-kHz

[Jani Nikula]

On Thu, 07 May 2015, Sonika Jindal <sonika.jindal@intel.com> wrote:
> The sink rate read from supported link rate table is in KHz as per spec
> while in drm, the saved clock is in deca-KHz. So divide the link rate by
> 10 before storing.
>
> Reading of rates was added by:
> commit fc0f8e25318f ("drm/i915/skl: Read sink supported rates from edp
> panel")

Thanks; now this git spell

$ git tag --contains fc0f8e25318f | grep ^v[0-9] | sort -V | head -n 1
v4.1-rc1

will tell me I need to queue this one to v4.1 through drm-intel-fixes
while the rest is for Daniel to merge to drm-intel-next-queued.

Pushed, thanks for the patch and review.

BR,
Jani.


>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index bacdec5..6bd5afb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3906,7 +3906,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>  			if (val == 0)
>  				break;
>  
> -			intel_dp->sink_rates[i] = val * 200;
> +			/* Value read is in kHz while drm clock is saved in deca-kHz */
> +			intel_dp->sink_rates[i] = (val * 200) / 10;
>  		}
>  		intel_dp->num_sink_rates = i;
>  	}
> -- 
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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[PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Sonika Jindal]

BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.

v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |   45 +++++++++++++++++++++-----------------
 drivers/gpu/drm/i915/intel_dp.c  |    7 +++++-
 2 files changed, 31 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9c1e74a..7b9d226 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1327,6 +1327,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 
 /* bxt clock parameters */
 struct bxt_clk_div {
+	int clock;
 	uint32_t p1;
 	uint32_t p2;
 	uint32_t m2_int;
@@ -1342,13 +1343,13 @@ struct bxt_clk_div {
 
 /* pre-calculated values for DP linkrates */
 static struct bxt_clk_div bxt_dp_clk_val[7] = {
-	/* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 270 */ {4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
-	/* 540 */ {2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
-	/* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
+	{162000, 4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	{270000, 4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
+	{540000, 2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
+	{216000, 3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	{243000, 4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
+	{324000, 4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	{432000, 3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
 };
 
 static bool
@@ -1401,20 +1402,24 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
 			intel_encoder->type == INTEL_OUTPUT_EDP) {
 		struct drm_encoder *encoder = &intel_encoder->base;
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+		int link_rate;
+		int i;
 
-		switch (intel_dp->link_bw) {
-		case DP_LINK_BW_1_62:
-			clk_div = bxt_dp_clk_val[0];
-			break;
-		case DP_LINK_BW_2_7:
-			clk_div = bxt_dp_clk_val[1];
-			break;
-		case DP_LINK_BW_5_4:
-			clk_div = bxt_dp_clk_val[2];
-			break;
-		default:
-			clk_div = bxt_dp_clk_val[0];
-			DRM_ERROR("Unknown link rate\n");
+		/*
+		 * If edp1.4 intermediate frequency support is present, we set
+		 * link_bw to 0 and a valid rate index in rate_select.
+		 */
+		if (intel_dp->link_bw)
+			link_rate = clock;
+		else
+			link_rate = intel_dp->sink_rates[intel_dp->rate_select];
+
+		clk_div = bxt_dp_clk_val[0];
+		for (i = 0; i < 7; ++i) {
+			if (bxt_dp_clk_val[i].clock == link_rate) {
+				clk_div = bxt_dp_clk_val[i];
+				break;
+			}
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c9d50d1..e6ee7c6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -85,6 +85,8 @@ static const struct dp_link_dpll chv_dpll[] = {
 		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
 };
 
+static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
+				  324000, 432000, 540000 };
 static const int skl_rates[] = { 162000, 216000, 270000,
 				  324000, 432000, 540000 };
 static const int chv_rates[] = { 162000, 202500, 210000, 216000,
@@ -1161,7 +1163,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 static int
 intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 {
-	if (IS_SKYLAKE(dev)) {
+	if (IS_BROXTON(dev)) {
+		*source_rates = bxt_rates;
+		return ARRAY_SIZE(bxt_rates);
+	} else if (IS_SKYLAKE(dev)) {
 		*source_rates = skl_rates;
 		return ARRAY_SIZE(skl_rates);
 	} else if (IS_CHERRYVIEW(dev)) {
-- 
1.7.10.4

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Re: [PATCH 2/3] drm/i915: Rename dp rates array as per platform

[Daniel Vetter]

On Thu, May 07, 2015 at 11:35:40AM +0300, Ville Syrjälä wrote:
> On Thu, May 07, 2015 at 09:52:08AM +0530, Sonika Jindal wrote:
> > Renaming gen9_rates to skl_rates because other platforms may have different
> > supported rates.
> > 
> > Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Ville Syrjälä]

On Thu, May 07, 2015 at 04:36:48PM +0530, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
> 
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> required rate (Ville)
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c |   45 +++++++++++++++++++++-----------------
>  drivers/gpu/drm/i915/intel_dp.c  |    7 +++++-
>  2 files changed, 31 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 9c1e74a..7b9d226 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1327,6 +1327,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>  
>  /* bxt clock parameters */
>  struct bxt_clk_div {
> +	int clock;
>  	uint32_t p1;
>  	uint32_t p2;
>  	uint32_t m2_int;
> @@ -1342,13 +1343,13 @@ struct bxt_clk_div {
>  
>  /* pre-calculated values for DP linkrates */
>  static struct bxt_clk_div bxt_dp_clk_val[7] = {
> -	/* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> -	/* 270 */ {4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
> -	/* 540 */ {2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
> -	/* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> -	/* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
> -	/* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> -	/* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
> +	{162000, 4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> +	{270000, 4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
> +	{540000, 2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
> +	{216000, 3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> +	{243000, 4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
> +	{324000, 4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> +	{432000, 3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
>  };
>  
>  static bool
> @@ -1401,20 +1402,24 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>  			intel_encoder->type == INTEL_OUTPUT_EDP) {
>  		struct drm_encoder *encoder = &intel_encoder->base;
>  		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +		int link_rate;
> +		int i;
>  
> -		switch (intel_dp->link_bw) {
> -		case DP_LINK_BW_1_62:
> -			clk_div = bxt_dp_clk_val[0];
> -			break;
> -		case DP_LINK_BW_2_7:
> -			clk_div = bxt_dp_clk_val[1];
> -			break;
> -		case DP_LINK_BW_5_4:
> -			clk_div = bxt_dp_clk_val[2];
> -			break;
> -		default:
> -			clk_div = bxt_dp_clk_val[0];
> -			DRM_ERROR("Unknown link rate\n");
> +		/*
> +		 * If edp1.4 intermediate frequency support is present, we set
> +		 * link_bw to 0 and a valid rate index in rate_select.
> +		 */
> +		if (intel_dp->link_bw)
> +			link_rate = clock;
> +		else
> +			link_rate = intel_dp->sink_rates[intel_dp->rate_select];

'clock' should be correct in either case.

> +
> +		clk_div = bxt_dp_clk_val[0];
> +		for (i = 0; i < 7; ++i) {
> +			if (bxt_dp_clk_val[i].clock == link_rate) {
> +				clk_div = bxt_dp_clk_val[i];
> +				break;
> +			}
>  		}
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c9d50d1..e6ee7c6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -85,6 +85,8 @@ static const struct dp_link_dpll chv_dpll[] = {
>  		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>  };
>  
> +static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
> +				  324000, 432000, 540000 };
>  static const int skl_rates[] = { 162000, 216000, 270000,
>  				  324000, 432000, 540000 };
>  static const int chv_rates[] = { 162000, 202500, 210000, 216000,
> @@ -1161,7 +1163,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>  static int
>  intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>  {
> -	if (IS_SKYLAKE(dev)) {
> +	if (IS_BROXTON(dev)) {
> +		*source_rates = bxt_rates;
> +		return ARRAY_SIZE(bxt_rates);
> +	} else if (IS_SKYLAKE(dev)) {
>  		*source_rates = skl_rates;
>  		return ARRAY_SIZE(skl_rates);
>  	} else if (IS_CHERRYVIEW(dev)) {
> -- 
> 1.7.10.4

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 3/3] drm/i915/bxt: edp1.4 Intermediate Freq support

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6338
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  302/302              302/302
SNB                                  316/316              316/316
IVB                                  342/342              342/342
BYT                                  286/286              286/286
BDW                                  321/321              321/321
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
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[PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Sonika Jindal]

BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.

v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
v3: 'clock' has the selected value, no need to use link_bw or rate_select
for selecting pll(Ville)

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |   37 +++++++++++++++----------------------
 drivers/gpu/drm/i915/intel_dp.c  |    7 ++++++-
 2 files changed, 21 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9c1e74a..83bb04d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1327,6 +1327,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 
 /* bxt clock parameters */
 struct bxt_clk_div {
+	int clock;
 	uint32_t p1;
 	uint32_t p2;
 	uint32_t m2_int;
@@ -1342,13 +1343,13 @@ struct bxt_clk_div {
 
 /* pre-calculated values for DP linkrates */
 static struct bxt_clk_div bxt_dp_clk_val[7] = {
-	/* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 270 */ {4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
-	/* 540 */ {2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
-	/* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
+	{162000, 4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	{270000, 4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
+	{540000, 2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
+	{216000, 3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	{243000, 4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
+	{324000, 4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	{432000, 3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
 };
 
 static bool
@@ -1399,22 +1400,14 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
 			clk_div.lanestagger = 0x02;
 	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
 			intel_encoder->type == INTEL_OUTPUT_EDP) {
-		struct drm_encoder *encoder = &intel_encoder->base;
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+		int i;
 
-		switch (intel_dp->link_bw) {
-		case DP_LINK_BW_1_62:
-			clk_div = bxt_dp_clk_val[0];
-			break;
-		case DP_LINK_BW_2_7:
-			clk_div = bxt_dp_clk_val[1];
-			break;
-		case DP_LINK_BW_5_4:
-			clk_div = bxt_dp_clk_val[2];
-			break;
-		default:
-			clk_div = bxt_dp_clk_val[0];
-			DRM_ERROR("Unknown link rate\n");
+		clk_div = bxt_dp_clk_val[0];
+		for (i = 0; i < 7; ++i) {
+			if (bxt_dp_clk_val[i].clock == clock) {
+				clk_div = bxt_dp_clk_val[i];
+				break;
+			}
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c9d50d1..e6ee7c6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -85,6 +85,8 @@ static const struct dp_link_dpll chv_dpll[] = {
 		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
 };
 
+static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
+				  324000, 432000, 540000 };
 static const int skl_rates[] = { 162000, 216000, 270000,
 				  324000, 432000, 540000 };
 static const int chv_rates[] = { 162000, 202500, 210000, 216000,
@@ -1161,7 +1163,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 static int
 intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 {
-	if (IS_SKYLAKE(dev)) {
+	if (IS_BROXTON(dev)) {
+		*source_rates = bxt_rates;
+		return ARRAY_SIZE(bxt_rates);
+	} else if (IS_SKYLAKE(dev)) {
 		*source_rates = skl_rates;
 		return ARRAY_SIZE(skl_rates);
 	} else if (IS_CHERRYVIEW(dev)) {
-- 
1.7.10.4

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Re: [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6344
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  302/302              302/302
SNB                                  316/316              316/316
IVB                                  342/342              342/342
BYT                                  286/286              286/286
BDW                                  321/321              321/321
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
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Re: [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Ville Syrjälä]

On Fri, May 08, 2015 at 11:04:06AM +0530, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
> 
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> required rate (Ville)
> v3: 'clock' has the selected value, no need to use link_bw or rate_select
> for selecting pll(Ville)
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c |   37 +++++++++++++++----------------------
>  drivers/gpu/drm/i915/intel_dp.c  |    7 ++++++-
>  2 files changed, 21 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 9c1e74a..83bb04d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1327,6 +1327,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>  
>  /* bxt clock parameters */
>  struct bxt_clk_div {
> +	int clock;
>  	uint32_t p1;
>  	uint32_t p2;
>  	uint32_t m2_int;
> @@ -1342,13 +1343,13 @@ struct bxt_clk_div {
>  
>  /* pre-calculated values for DP linkrates */
>  static struct bxt_clk_div bxt_dp_clk_val[7] = {

Just noticed someone forgot to make this array const. Please do that too.
Also no need to specify an explict size for it.

> -	/* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> -	/* 270 */ {4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
> -	/* 540 */ {2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
> -	/* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> -	/* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
> -	/* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> -	/* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
> +	{162000, 4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> +	{270000, 4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
> +	{540000, 2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
> +	{216000, 3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> +	{243000, 4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
> +	{324000, 4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> +	{432000, 3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
>  };
>  
>  static bool
> @@ -1399,22 +1400,14 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>  			clk_div.lanestagger = 0x02;
>  	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
>  			intel_encoder->type == INTEL_OUTPUT_EDP) {
> -		struct drm_encoder *encoder = &intel_encoder->base;
> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +		int i;
>  
> -		switch (intel_dp->link_bw) {
> -		case DP_LINK_BW_1_62:
> -			clk_div = bxt_dp_clk_val[0];
> -			break;
> -		case DP_LINK_BW_2_7:
> -			clk_div = bxt_dp_clk_val[1];
> -			break;
> -		case DP_LINK_BW_5_4:
> -			clk_div = bxt_dp_clk_val[2];
> -			break;
> -		default:
> -			clk_div = bxt_dp_clk_val[0];
> -			DRM_ERROR("Unknown link rate\n");
> +		clk_div = bxt_dp_clk_val[0];
> +		for (i = 0; i < 7; ++i) {

ARRAY_SIZE()

With that stuff changed this is 
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +			if (bxt_dp_clk_val[i].clock == clock) {
> +				clk_div = bxt_dp_clk_val[i];
> +				break;
> +			}
>  		}
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c9d50d1..e6ee7c6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -85,6 +85,8 @@ static const struct dp_link_dpll chv_dpll[] = {
>  		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>  };
>  
> +static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
> +				  324000, 432000, 540000 };
>  static const int skl_rates[] = { 162000, 216000, 270000,
>  				  324000, 432000, 540000 };
>  static const int chv_rates[] = { 162000, 202500, 210000, 216000,
> @@ -1161,7 +1163,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>  static int
>  intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>  {
> -	if (IS_SKYLAKE(dev)) {
> +	if (IS_BROXTON(dev)) {
> +		*source_rates = bxt_rates;
> +		return ARRAY_SIZE(bxt_rates);
> +	} else if (IS_SKYLAKE(dev)) {
>  		*source_rates = skl_rates;
>  		return ARRAY_SIZE(skl_rates);
>  	} else if (IS_CHERRYVIEW(dev)) {
> -- 
> 1.7.10.4

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6354
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  302/302              302/302
SNB                                  316/316              316/316
IVB                                  342/342              342/342
BYT                                  286/286              286/286
BDW                                  321/321              321/321
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
_______________________________________________
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[PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Sonika Jindal]

BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.

v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
v3: 'clock' has the selected value, no need to use link_bw or rate_select
for selecting pll(Ville)
v4: Make bxt_dp_clk_val const and remove size (Ville)

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |   39 ++++++++++++++++----------------------
 drivers/gpu/drm/i915/intel_dp.c  |    7 ++++++-
 2 files changed, 22 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9c1e74a..c648289 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1327,6 +1327,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 
 /* bxt clock parameters */
 struct bxt_clk_div {
+	int clock;
 	uint32_t p1;
 	uint32_t p2;
 	uint32_t m2_int;
@@ -1341,14 +1342,14 @@ struct bxt_clk_div {
 };
 
 /* pre-calculated values for DP linkrates */
-static struct bxt_clk_div bxt_dp_clk_val[7] = {
-	/* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 270 */ {4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
-	/* 540 */ {2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
-	/* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
-	/* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
+static const struct bxt_clk_div bxt_dp_clk_val[] = {
+	{162000, 4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	{270000, 4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
+	{540000, 2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
+	{216000, 3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	{243000, 4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
+	{324000, 4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	{432000, 3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
 };
 
 static bool
@@ -1399,22 +1400,14 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
 			clk_div.lanestagger = 0x02;
 	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
 			intel_encoder->type == INTEL_OUTPUT_EDP) {
-		struct drm_encoder *encoder = &intel_encoder->base;
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+		int i;
 
-		switch (intel_dp->link_bw) {
-		case DP_LINK_BW_1_62:
-			clk_div = bxt_dp_clk_val[0];
-			break;
-		case DP_LINK_BW_2_7:
-			clk_div = bxt_dp_clk_val[1];
-			break;
-		case DP_LINK_BW_5_4:
-			clk_div = bxt_dp_clk_val[2];
-			break;
-		default:
-			clk_div = bxt_dp_clk_val[0];
-			DRM_ERROR("Unknown link rate\n");
+		clk_div = bxt_dp_clk_val[0];
+		for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
+			if (bxt_dp_clk_val[i].clock == clock) {
+				clk_div = bxt_dp_clk_val[i];
+				break;
+			}
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c9d50d1..e6ee7c6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -85,6 +85,8 @@ static const struct dp_link_dpll chv_dpll[] = {
 		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
 };
 
+static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
+				  324000, 432000, 540000 };
 static const int skl_rates[] = { 162000, 216000, 270000,
 				  324000, 432000, 540000 };
 static const int chv_rates[] = { 162000, 202500, 210000, 216000,
@@ -1161,7 +1163,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 static int
 intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 {
-	if (IS_SKYLAKE(dev)) {
+	if (IS_BROXTON(dev)) {
+		*source_rates = bxt_rates;
+		return ARRAY_SIZE(bxt_rates);
+	} else if (IS_SKYLAKE(dev)) {
 		*source_rates = skl_rates;
 		return ARRAY_SIZE(skl_rates);
 	} else if (IS_CHERRYVIEW(dev)) {
-- 
1.7.10.4

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Re: [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Daniel Vetter]

On Mon, May 11, 2015 at 01:21:43PM +0530, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
> 
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> required rate (Ville)
> v3: 'clock' has the selected value, no need to use link_bw or rate_select
> for selecting pll(Ville)
> v4: Make bxt_dp_clk_val const and remove size (Ville)
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6379
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -3              272/272              269/272
ILK                                  302/302              302/302
SNB                 -1              315/315              314/315
IVB                                  343/343              343/343
BYT                                  287/287              287/287
BDW                                  317/317              317/317
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt@gem_tiled_pread_pwrite      PASS(2)      FAIL(1)
*PNV  igt@gem_userptr_blits@coherency-sync      PASS(2)      CRASH(1)
*PNV  igt@gem_userptr_blits@coherency-unsync      PASS(2)      CRASH(1)
 SNB  igt@pm_rpm@dpms-mode-unset-non-lpsp      DMESG_WARN(7)PASS(1)      DMESG_WARN(1)
(dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/intel_uncore.c:#assert_device_not_suspended[i915]()@WARNING:.* at .* assert_device_not_suspended+0x
Note: You need to pay more attention to line start with '*'
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[PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Sonika Jindal]

BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.

v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
v3: 'clock' has the selected value, no need to use link_bw or rate_select
for selecting pll(Ville)
v4: Make bxt_dp_clk_val const and remove size (Ville)
v5: Rebased

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |   40 +++++++++++++++-----------------------
 drivers/gpu/drm/i915/intel_dp.c  |    7 ++++++-
 2 files changed, 22 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cacb07b..eb3238a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1334,6 +1334,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 
 /* bxt clock parameters */
 struct bxt_clk_div {
+	int clock;
 	uint32_t p1;
 	uint32_t p2;
 	uint32_t m2_int;
@@ -1343,14 +1344,14 @@ struct bxt_clk_div {
 };
 
 /* pre-calculated values for DP linkrates */
-static struct bxt_clk_div bxt_dp_clk_val[7] = {
-	/* 162 */ {4, 2, 32, 1677722, 1, 1},
-	/* 270 */ {4, 1, 27,       0, 0, 1},
-	/* 540 */ {2, 1, 27,       0, 0, 1},
-	/* 216 */ {3, 2, 32, 1677722, 1, 1},
-	/* 243 */ {4, 1, 24, 1258291, 1, 1},
-	/* 324 */ {4, 1, 32, 1677722, 1, 1},
-	/* 432 */ {3, 1, 32, 1677722, 1, 1}
+static const struct bxt_clk_div bxt_dp_clk_val[] = {
+	{162000, 4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	{270000, 4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
+	{540000, 2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
+	{216000, 3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	{243000, 4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
+	{324000, 4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
+	{432000, 3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
 };
 
 static bool
@@ -1390,24 +1391,15 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
 		vco = best_clock.vco;
 	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
 			intel_encoder->type == INTEL_OUTPUT_EDP) {
-		struct drm_encoder *encoder = &intel_encoder->base;
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+		int i;
 
-		switch (intel_dp->link_bw) {
-		case DP_LINK_BW_1_62:
-			clk_div = bxt_dp_clk_val[0];
-			break;
-		case DP_LINK_BW_2_7:
-			clk_div = bxt_dp_clk_val[1];
-			break;
-		case DP_LINK_BW_5_4:
-			clk_div = bxt_dp_clk_val[2];
-			break;
-		default:
-			clk_div = bxt_dp_clk_val[0];
-			DRM_ERROR("Unknown link rate\n");
+		clk_div = bxt_dp_clk_val[0];
+		for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
+			if (bxt_dp_clk_val[i].clock == clock) {
+				clk_div = bxt_dp_clk_val[i];
+				break;
+			}
 		}
-		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
 	}
 
 	dco_amp = 15;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index abd442a..bd0f958 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -91,6 +91,8 @@ static const struct dp_link_dpll chv_dpll[] = {
 		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
 };
 
+static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
+				  324000, 432000, 540000 };
 static const int skl_rates[] = { 162000, 216000, 270000,
 				  324000, 432000, 540000 };
 static const int chv_rates[] = { 162000, 202500, 210000, 216000,
@@ -1170,7 +1172,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 static int
 intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 {
-	if (IS_SKYLAKE(dev)) {
+	if (IS_BROXTON(dev)) {
+		*source_rates = bxt_rates;
+		return ARRAY_SIZE(bxt_rates);
+	} else if (IS_SKYLAKE(dev)) {
 		*source_rates = skl_rates;
 		return ARRAY_SIZE(skl_rates);
 	} else if (IS_CHERRYVIEW(dev)) {
-- 
1.7.10.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Daniel Vetter]

On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
> 
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> required rate (Ville)
> v3: 'clock' has the selected value, no need to use link_bw or rate_select
> for selecting pll(Ville)
> v4: Make bxt_dp_clk_val const and remove size (Ville)
> v5: Rebased
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

This time applied for really. Somehow the previous attempt fell short, and
digging into git reflog didn't reveal any clues. Sorry for the mess I've
made.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_ddi.c |   40 +++++++++++++++-----------------------
>  drivers/gpu/drm/i915/intel_dp.c  |    7 ++++++-
>  2 files changed, 22 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cacb07b..eb3238a 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1334,6 +1334,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>  
>  /* bxt clock parameters */
>  struct bxt_clk_div {
> +	int clock;
>  	uint32_t p1;
>  	uint32_t p2;
>  	uint32_t m2_int;
> @@ -1343,14 +1344,14 @@ struct bxt_clk_div {
>  };
>  
>  /* pre-calculated values for DP linkrates */
> -static struct bxt_clk_div bxt_dp_clk_val[7] = {
> -	/* 162 */ {4, 2, 32, 1677722, 1, 1},
> -	/* 270 */ {4, 1, 27,       0, 0, 1},
> -	/* 540 */ {2, 1, 27,       0, 0, 1},
> -	/* 216 */ {3, 2, 32, 1677722, 1, 1},
> -	/* 243 */ {4, 1, 24, 1258291, 1, 1},
> -	/* 324 */ {4, 1, 32, 1677722, 1, 1},
> -	/* 432 */ {3, 1, 32, 1677722, 1, 1}
> +static const struct bxt_clk_div bxt_dp_clk_val[] = {
> +	{162000, 4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> +	{270000, 4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
> +	{540000, 2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
> +	{216000, 3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> +	{243000, 4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
> +	{324000, 4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> +	{432000, 3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
>  };
>  
>  static bool
> @@ -1390,24 +1391,15 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>  		vco = best_clock.vco;
>  	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
>  			intel_encoder->type == INTEL_OUTPUT_EDP) {
> -		struct drm_encoder *encoder = &intel_encoder->base;
> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +		int i;
>  
> -		switch (intel_dp->link_bw) {
> -		case DP_LINK_BW_1_62:
> -			clk_div = bxt_dp_clk_val[0];
> -			break;
> -		case DP_LINK_BW_2_7:
> -			clk_div = bxt_dp_clk_val[1];
> -			break;
> -		case DP_LINK_BW_5_4:
> -			clk_div = bxt_dp_clk_val[2];
> -			break;
> -		default:
> -			clk_div = bxt_dp_clk_val[0];
> -			DRM_ERROR("Unknown link rate\n");
> +		clk_div = bxt_dp_clk_val[0];
> +		for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
> +			if (bxt_dp_clk_val[i].clock == clock) {
> +				clk_div = bxt_dp_clk_val[i];
> +				break;
> +			}
>  		}
> -		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
>  	}
>  
>  	dco_amp = 15;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index abd442a..bd0f958 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -91,6 +91,8 @@ static const struct dp_link_dpll chv_dpll[] = {
>  		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>  };
>  
> +static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
> +				  324000, 432000, 540000 };
>  static const int skl_rates[] = { 162000, 216000, 270000,
>  				  324000, 432000, 540000 };
>  static const int chv_rates[] = { 162000, 202500, 210000, 216000,
> @@ -1170,7 +1172,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>  static int
>  intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>  {
> -	if (IS_SKYLAKE(dev)) {
> +	if (IS_BROXTON(dev)) {
> +		*source_rates = bxt_rates;
> +		return ARRAY_SIZE(bxt_rates);
> +	} else if (IS_SKYLAKE(dev)) {
>  		*source_rates = skl_rates;
>  		return ARRAY_SIZE(skl_rates);
>  	} else if (IS_CHERRYVIEW(dev)) {
> -- 
> 1.7.10.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Jani Nikula]

On Tue, 26 May 2015, Sonika Jindal <sonika.jindal@intel.com> wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
>
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> required rate (Ville)
> v3: 'clock' has the selected value, no need to use link_bw or rate_select
> for selecting pll(Ville)
> v4: Make bxt_dp_clk_val const and remove size (Ville)
> v5: Rebased
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c |   40 +++++++++++++++-----------------------
>  drivers/gpu/drm/i915/intel_dp.c  |    7 ++++++-
>  2 files changed, 22 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cacb07b..eb3238a 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1334,6 +1334,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>  
>  /* bxt clock parameters */
>  struct bxt_clk_div {
> +	int clock;
>  	uint32_t p1;
>  	uint32_t p2;
>  	uint32_t m2_int;
> @@ -1343,14 +1344,14 @@ struct bxt_clk_div {
>  };
>  
>  /* pre-calculated values for DP linkrates */
> -static struct bxt_clk_div bxt_dp_clk_val[7] = {
> -	/* 162 */ {4, 2, 32, 1677722, 1, 1},
> -	/* 270 */ {4, 1, 27,       0, 0, 1},
> -	/* 540 */ {2, 1, 27,       0, 0, 1},
> -	/* 216 */ {3, 2, 32, 1677722, 1, 1},
> -	/* 243 */ {4, 1, 24, 1258291, 1, 1},
> -	/* 324 */ {4, 1, 32, 1677722, 1, 1},
> -	/* 432 */ {3, 1, 32, 1677722, 1, 1}
> +static const struct bxt_clk_div bxt_dp_clk_val[] = {
> +	{162000, 4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> +	{270000, 4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
> +	{540000, 2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
> +	{216000, 3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> +	{243000, 4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
> +	{324000, 4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> +	{432000, 3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
>  };
>  
>  static bool
> @@ -1390,24 +1391,15 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>  		vco = best_clock.vco;
>  	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
>  			intel_encoder->type == INTEL_OUTPUT_EDP) {
> -		struct drm_encoder *encoder = &intel_encoder->base;
> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +		int i;
>  
> -		switch (intel_dp->link_bw) {
> -		case DP_LINK_BW_1_62:
> -			clk_div = bxt_dp_clk_val[0];
> -			break;
> -		case DP_LINK_BW_2_7:
> -			clk_div = bxt_dp_clk_val[1];
> -			break;
> -		case DP_LINK_BW_5_4:
> -			clk_div = bxt_dp_clk_val[2];
> -			break;
> -		default:
> -			clk_div = bxt_dp_clk_val[0];
> -			DRM_ERROR("Unknown link rate\n");
> +		clk_div = bxt_dp_clk_val[0];
> +		for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
> +			if (bxt_dp_clk_val[i].clock == clock) {
> +				clk_div = bxt_dp_clk_val[i];
> +				break;
> +			}
>  		}
> -		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;


Without vco set, won't this hit the DRM_ERROR("Invalid VCO\n"); path
right below?

BR,
Jani.



>  	}
>  
>  	dco_amp = 15;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index abd442a..bd0f958 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -91,6 +91,8 @@ static const struct dp_link_dpll chv_dpll[] = {
>  		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>  };
>  
> +static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
> +				  324000, 432000, 540000 };
>  static const int skl_rates[] = { 162000, 216000, 270000,
>  				  324000, 432000, 540000 };
>  static const int chv_rates[] = { 162000, 202500, 210000, 216000,
> @@ -1170,7 +1172,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>  static int
>  intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>  {
> -	if (IS_SKYLAKE(dev)) {
> +	if (IS_BROXTON(dev)) {
> +		*source_rates = bxt_rates;
> +		return ARRAY_SIZE(bxt_rates);
> +	} else if (IS_SKYLAKE(dev)) {
>  		*source_rates = skl_rates;
>  		return ARRAY_SIZE(skl_rates);
>  	} else if (IS_CHERRYVIEW(dev)) {
> -- 
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Jani Nikula]

On Tue, 26 May 2015, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote:
>> BXT supports following intermediate link rates for edp:
>> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
>> Adding support for programming the intermediate rates.
>> 
>> v2: Adding clock in bxt_clk_div struct and then look for the entry with
>> required rate (Ville)
>> v3: 'clock' has the selected value, no need to use link_bw or rate_select
>> for selecting pll(Ville)
>> v4: Make bxt_dp_clk_val const and remove size (Ville)
>> v5: Rebased
>> 
>> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> This time applied for really. Somehow the previous attempt fell short, and
> digging into git reflog didn't reveal any clues. Sorry for the mess I've
> made.

Please drop this, the rebase does not take into account

commit b6dc71f38a84e36c5445b95f9f7a2dac6b25636f
Author: Vandana Kannan <vandana.kannan@intel.com>
Date:   Wed May 13 12:18:52 2015 +0530

    drm/i915/bxt: Port PLL programming BUN

and now leaves vco at zero.


BR,
Jani.


> -Daniel
>
>> ---
>>  drivers/gpu/drm/i915/intel_ddi.c |   40 +++++++++++++++-----------------------
>>  drivers/gpu/drm/i915/intel_dp.c  |    7 ++++++-
>>  2 files changed, 22 insertions(+), 25 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index cacb07b..eb3238a 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -1334,6 +1334,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>>  
>>  /* bxt clock parameters */
>>  struct bxt_clk_div {
>> +	int clock;
>>  	uint32_t p1;
>>  	uint32_t p2;
>>  	uint32_t m2_int;
>> @@ -1343,14 +1344,14 @@ struct bxt_clk_div {
>>  };
>>  
>>  /* pre-calculated values for DP linkrates */
>> -static struct bxt_clk_div bxt_dp_clk_val[7] = {
>> -	/* 162 */ {4, 2, 32, 1677722, 1, 1},
>> -	/* 270 */ {4, 1, 27,       0, 0, 1},
>> -	/* 540 */ {2, 1, 27,       0, 0, 1},
>> -	/* 216 */ {3, 2, 32, 1677722, 1, 1},
>> -	/* 243 */ {4, 1, 24, 1258291, 1, 1},
>> -	/* 324 */ {4, 1, 32, 1677722, 1, 1},
>> -	/* 432 */ {3, 1, 32, 1677722, 1, 1}
>> +static const struct bxt_clk_div bxt_dp_clk_val[] = {
>> +	{162000, 4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
>> +	{270000, 4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
>> +	{540000, 2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
>> +	{216000, 3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
>> +	{243000, 4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
>> +	{324000, 4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
>> +	{432000, 3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
>>  };
>>  
>>  static bool
>> @@ -1390,24 +1391,15 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>>  		vco = best_clock.vco;
>>  	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
>>  			intel_encoder->type == INTEL_OUTPUT_EDP) {
>> -		struct drm_encoder *encoder = &intel_encoder->base;
>> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> +		int i;
>>  
>> -		switch (intel_dp->link_bw) {
>> -		case DP_LINK_BW_1_62:
>> -			clk_div = bxt_dp_clk_val[0];
>> -			break;
>> -		case DP_LINK_BW_2_7:
>> -			clk_div = bxt_dp_clk_val[1];
>> -			break;
>> -		case DP_LINK_BW_5_4:
>> -			clk_div = bxt_dp_clk_val[2];
>> -			break;
>> -		default:
>> -			clk_div = bxt_dp_clk_val[0];
>> -			DRM_ERROR("Unknown link rate\n");
>> +		clk_div = bxt_dp_clk_val[0];
>> +		for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
>> +			if (bxt_dp_clk_val[i].clock == clock) {
>> +				clk_div = bxt_dp_clk_val[i];
>> +				break;
>> +			}
>>  		}
>> -		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
>>  	}
>>  
>>  	dco_amp = 15;
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index abd442a..bd0f958 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -91,6 +91,8 @@ static const struct dp_link_dpll chv_dpll[] = {
>>  		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>>  };
>>  
>> +static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
>> +				  324000, 432000, 540000 };
>>  static const int skl_rates[] = { 162000, 216000, 270000,
>>  				  324000, 432000, 540000 };
>>  static const int chv_rates[] = { 162000, 202500, 210000, 216000,
>> @@ -1170,7 +1172,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>>  static int
>>  intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>>  {
>> -	if (IS_SKYLAKE(dev)) {
>> +	if (IS_BROXTON(dev)) {
>> +		*source_rates = bxt_rates;
>> +		return ARRAY_SIZE(bxt_rates);
>> +	} else if (IS_SKYLAKE(dev)) {
>>  		*source_rates = skl_rates;
>>  		return ARRAY_SIZE(skl_rates);
>>  	} else if (IS_CHERRYVIEW(dev)) {
>> -- 
>> 1.7.10.4
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Daniel Vetter]

On Tue, May 26, 2015 at 12:57:26PM +0300, Jani Nikula wrote:
> On Tue, 26 May 2015, Daniel Vetter <daniel@ffwll.ch> wrote:
> > On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote:
> >> BXT supports following intermediate link rates for edp:
> >> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> >> Adding support for programming the intermediate rates.
> >> 
> >> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> >> required rate (Ville)
> >> v3: 'clock' has the selected value, no need to use link_bw or rate_select
> >> for selecting pll(Ville)
> >> v4: Make bxt_dp_clk_val const and remove size (Ville)
> >> v5: Rebased
> >> 
> >> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> >> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > This time applied for really. Somehow the previous attempt fell short, and
> > digging into git reflog didn't reveal any clues. Sorry for the mess I've
> > made.
> 
> Please drop this, the rebase does not take into account
> 
> commit b6dc71f38a84e36c5445b95f9f7a2dac6b25636f
> Author: Vandana Kannan <vandana.kannan@intel.com>
> Date:   Wed May 13 12:18:52 2015 +0530
> 
>     drm/i915/bxt: Port PLL programming BUN
> 
> and now leaves vco at zero.

Yeah dropped again. I didn't do the rebase myself because of these
functional conflicts, but then totally forgot to check that Sonika
bothered to run the patch first.

Generally when I ask for a rebase it means that there's something
nontrivial going on ...

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Jindal, Sonika]

On 5/26/2015 3:29 PM, Daniel Vetter wrote:
> On Tue, May 26, 2015 at 12:57:26PM +0300, Jani Nikula wrote:
>> On Tue, 26 May 2015, Daniel Vetter <daniel@ffwll.ch> wrote:
>>> On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote:
>>>> BXT supports following intermediate link rates for edp:
>>>> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
>>>> Adding support for programming the intermediate rates.
>>>>
>>>> v2: Adding clock in bxt_clk_div struct and then look for the entry with
>>>> required rate (Ville)
>>>> v3: 'clock' has the selected value, no need to use link_bw or rate_select
>>>> for selecting pll(Ville)
>>>> v4: Make bxt_dp_clk_val const and remove size (Ville)
>>>> v5: Rebased
>>>>
>>>> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
>>>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> This time applied for really. Somehow the previous attempt fell short, and
>>> digging into git reflog didn't reveal any clues. Sorry for the mess I've
>>> made.
>>
>> Please drop this, the rebase does not take into account
>>
>> commit b6dc71f38a84e36c5445b95f9f7a2dac6b25636f
>> Author: Vandana Kannan <vandana.kannan@intel.com>
>> Date:   Wed May 13 12:18:52 2015 +0530
>>
>>      drm/i915/bxt: Port PLL programming BUN
>>
>> and now leaves vco at zero.
>
> Yeah dropped again. I didn't do the rebase myself because of these
> functional conflicts, but then totally forgot to check that Sonika
> bothered to run the patch first.
>
> Generally when I ask for a rebase it means that there's something
> nontrivial going on ...
>
:( Completely my mistake. Removed that line by mistake :(

> Thanks, Daniel
>
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[PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Sonika Jindal]

BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.

v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
v3: 'clock' has the selected value, no need to use link_bw or rate_select
for selecting pll(Ville)
v4: Make bxt_dp_clk_val const and remove size (Ville)
v5: Rebased
v6: Removed setting of vco while rebasing in v5, adding it back

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>(v4)
---
 drivers/gpu/drm/i915/intel_ddi.c |   39 ++++++++++++++++----------------------
 drivers/gpu/drm/i915/intel_dp.c  |    7 ++++++-
 2 files changed, 22 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cacb07b..2a2518d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1334,6 +1334,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 
 /* bxt clock parameters */
 struct bxt_clk_div {
+	int clock;
 	uint32_t p1;
 	uint32_t p2;
 	uint32_t m2_int;
@@ -1343,14 +1344,14 @@ struct bxt_clk_div {
 };
 
 /* pre-calculated values for DP linkrates */
-static struct bxt_clk_div bxt_dp_clk_val[7] = {
-	/* 162 */ {4, 2, 32, 1677722, 1, 1},
-	/* 270 */ {4, 1, 27,       0, 0, 1},
-	/* 540 */ {2, 1, 27,       0, 0, 1},
-	/* 216 */ {3, 2, 32, 1677722, 1, 1},
-	/* 243 */ {4, 1, 24, 1258291, 1, 1},
-	/* 324 */ {4, 1, 32, 1677722, 1, 1},
-	/* 432 */ {3, 1, 32, 1677722, 1, 1}
+static const struct bxt_clk_div bxt_dp_clk_val[] = {
+	{162000, 4, 2, 32, 1677722, 1, 1},
+	{270000, 4, 1, 27,       0, 0, 1},
+	{540000, 2, 1, 27,       0, 0, 1},
+	{216000, 3, 2, 32, 1677722, 1, 1},
+	{243000, 4, 1, 24, 1258291, 1, 1},
+	{324000, 4, 1, 32, 1677722, 1, 1},
+	{432000, 3, 1, 32, 1677722, 1, 1}
 };
 
 static bool
@@ -1390,22 +1391,14 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
 		vco = best_clock.vco;
 	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
 			intel_encoder->type == INTEL_OUTPUT_EDP) {
-		struct drm_encoder *encoder = &intel_encoder->base;
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+		int i;
 
-		switch (intel_dp->link_bw) {
-		case DP_LINK_BW_1_62:
-			clk_div = bxt_dp_clk_val[0];
-			break;
-		case DP_LINK_BW_2_7:
-			clk_div = bxt_dp_clk_val[1];
-			break;
-		case DP_LINK_BW_5_4:
-			clk_div = bxt_dp_clk_val[2];
-			break;
-		default:
-			clk_div = bxt_dp_clk_val[0];
-			DRM_ERROR("Unknown link rate\n");
+		clk_div = bxt_dp_clk_val[0];
+		for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
+			if (bxt_dp_clk_val[i].clock == clock) {
+				clk_div = bxt_dp_clk_val[i];
+				break;
+			}
 		}
 		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
 	}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index abd442a..bd0f958 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -91,6 +91,8 @@ static const struct dp_link_dpll chv_dpll[] = {
 		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
 };
 
+static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
+				  324000, 432000, 540000 };
 static const int skl_rates[] = { 162000, 216000, 270000,
 				  324000, 432000, 540000 };
 static const int chv_rates[] = { 162000, 202500, 210000, 216000,
@@ -1170,7 +1172,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 static int
 intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 {
-	if (IS_SKYLAKE(dev)) {
+	if (IS_BROXTON(dev)) {
+		*source_rates = bxt_rates;
+		return ARRAY_SIZE(bxt_rates);
+	} else if (IS_SKYLAKE(dev)) {
 		*source_rates = skl_rates;
 		return ARRAY_SIZE(skl_rates);
 	} else if (IS_CHERRYVIEW(dev)) {
-- 
1.7.10.4

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Re: [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Jindal, Sonika]

Hi Vandana,

Can you please review the v6 of this patch?

This was rebased recently on top of your patch:
  commit b6dc71f38a84e36c5445b95f9f7a2dac6b25636f
  Author: Vandana Kannan <vandana.kannan@intel.com>
  Date:   Wed May 13 12:18:52 2015 +0530

       drm/i915/bxt: Port PLL programming BUN

Thanks,
Sonika

On 5/26/2015 5:50 PM, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
>
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> required rate (Ville)
> v3: 'clock' has the selected value, no need to use link_bw or rate_select
> for selecting pll(Ville)
> v4: Make bxt_dp_clk_val const and remove size (Ville)
> v5: Rebased
> v6: Removed setting of vco while rebasing in v5, adding it back
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>(v4)
> ---
>   drivers/gpu/drm/i915/intel_ddi.c |   39 ++++++++++++++++----------------------
>   drivers/gpu/drm/i915/intel_dp.c  |    7 ++++++-
>   2 files changed, 22 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cacb07b..2a2518d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1334,6 +1334,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>
>   /* bxt clock parameters */
>   struct bxt_clk_div {
> +	int clock;
>   	uint32_t p1;
>   	uint32_t p2;
>   	uint32_t m2_int;
> @@ -1343,14 +1344,14 @@ struct bxt_clk_div {
>   };
>
>   /* pre-calculated values for DP linkrates */
> -static struct bxt_clk_div bxt_dp_clk_val[7] = {
> -	/* 162 */ {4, 2, 32, 1677722, 1, 1},
> -	/* 270 */ {4, 1, 27,       0, 0, 1},
> -	/* 540 */ {2, 1, 27,       0, 0, 1},
> -	/* 216 */ {3, 2, 32, 1677722, 1, 1},
> -	/* 243 */ {4, 1, 24, 1258291, 1, 1},
> -	/* 324 */ {4, 1, 32, 1677722, 1, 1},
> -	/* 432 */ {3, 1, 32, 1677722, 1, 1}
> +static const struct bxt_clk_div bxt_dp_clk_val[] = {
> +	{162000, 4, 2, 32, 1677722, 1, 1},
> +	{270000, 4, 1, 27,       0, 0, 1},
> +	{540000, 2, 1, 27,       0, 0, 1},
> +	{216000, 3, 2, 32, 1677722, 1, 1},
> +	{243000, 4, 1, 24, 1258291, 1, 1},
> +	{324000, 4, 1, 32, 1677722, 1, 1},
> +	{432000, 3, 1, 32, 1677722, 1, 1}
>   };
>
>   static bool
> @@ -1390,22 +1391,14 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>   		vco = best_clock.vco;
>   	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
>   			intel_encoder->type == INTEL_OUTPUT_EDP) {
> -		struct drm_encoder *encoder = &intel_encoder->base;
> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +		int i;
>
> -		switch (intel_dp->link_bw) {
> -		case DP_LINK_BW_1_62:
> -			clk_div = bxt_dp_clk_val[0];
> -			break;
> -		case DP_LINK_BW_2_7:
> -			clk_div = bxt_dp_clk_val[1];
> -			break;
> -		case DP_LINK_BW_5_4:
> -			clk_div = bxt_dp_clk_val[2];
> -			break;
> -		default:
> -			clk_div = bxt_dp_clk_val[0];
> -			DRM_ERROR("Unknown link rate\n");
> +		clk_div = bxt_dp_clk_val[0];
> +		for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
> +			if (bxt_dp_clk_val[i].clock == clock) {
> +				clk_div = bxt_dp_clk_val[i];
> +				break;
> +			}
>   		}
>   		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
>   	}
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index abd442a..bd0f958 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -91,6 +91,8 @@ static const struct dp_link_dpll chv_dpll[] = {
>   		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>   };
>
> +static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
> +				  324000, 432000, 540000 };
>   static const int skl_rates[] = { 162000, 216000, 270000,
>   				  324000, 432000, 540000 };
>   static const int chv_rates[] = { 162000, 202500, 210000, 216000,
> @@ -1170,7 +1172,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>   static int
>   intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>   {
> -	if (IS_SKYLAKE(dev)) {
> +	if (IS_BROXTON(dev)) {
> +		*source_rates = bxt_rates;
> +		return ARRAY_SIZE(bxt_rates);
> +	} else if (IS_SKYLAKE(dev)) {
>   		*source_rates = skl_rates;
>   		return ARRAY_SIZE(skl_rates);
>   	} else if (IS_CHERRYVIEW(dev)) {
>
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Re: [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Kannan, Vandana]

On 5/26/2015 5:50 PM, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
>
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> required rate (Ville)
> v3: 'clock' has the selected value, no need to use link_bw or rate_select
> for selecting pll(Ville)
> v4: Make bxt_dp_clk_val const and remove size (Ville)
> v5: Rebased
> v6: Removed setting of vco while rebasing in v5, adding it back
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>(v4)
> ---
>   drivers/gpu/drm/i915/intel_ddi.c |   39 ++++++++++++++++----------------------
>   drivers/gpu/drm/i915/intel_dp.c  |    7 ++++++-
>   2 files changed, 22 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cacb07b..2a2518d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1334,6 +1334,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>
>   /* bxt clock parameters */
>   struct bxt_clk_div {
> +	int clock;
>   	uint32_t p1;
>   	uint32_t p2;
>   	uint32_t m2_int;
> @@ -1343,14 +1344,14 @@ struct bxt_clk_div {
>   };
>
>   /* pre-calculated values for DP linkrates */
> -static struct bxt_clk_div bxt_dp_clk_val[7] = {
> -	/* 162 */ {4, 2, 32, 1677722, 1, 1},
> -	/* 270 */ {4, 1, 27,       0, 0, 1},
> -	/* 540 */ {2, 1, 27,       0, 0, 1},
> -	/* 216 */ {3, 2, 32, 1677722, 1, 1},
> -	/* 243 */ {4, 1, 24, 1258291, 1, 1},
> -	/* 324 */ {4, 1, 32, 1677722, 1, 1},
> -	/* 432 */ {3, 1, 32, 1677722, 1, 1}
> +static const struct bxt_clk_div bxt_dp_clk_val[] = {
> +	{162000, 4, 2, 32, 1677722, 1, 1},
> +	{270000, 4, 1, 27,       0, 0, 1},
> +	{540000, 2, 1, 27,       0, 0, 1},
> +	{216000, 3, 2, 32, 1677722, 1, 1},
> +	{243000, 4, 1, 24, 1258291, 1, 1},
> +	{324000, 4, 1, 32, 1677722, 1, 1},
> +	{432000, 3, 1, 32, 1677722, 1, 1}
>   };
>
>   static bool
> @@ -1390,22 +1391,14 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>   		vco = best_clock.vco;
>   	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
>   			intel_encoder->type == INTEL_OUTPUT_EDP) {
> -		struct drm_encoder *encoder = &intel_encoder->base;
> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +		int i;
>
> -		switch (intel_dp->link_bw) {
> -		case DP_LINK_BW_1_62:
> -			clk_div = bxt_dp_clk_val[0];
> -			break;
> -		case DP_LINK_BW_2_7:
> -			clk_div = bxt_dp_clk_val[1];
> -			break;
> -		case DP_LINK_BW_5_4:
> -			clk_div = bxt_dp_clk_val[2];
> -			break;
> -		default:
> -			clk_div = bxt_dp_clk_val[0];
> -			DRM_ERROR("Unknown link rate\n");
> +		clk_div = bxt_dp_clk_val[0];
> +		for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
> +			if (bxt_dp_clk_val[i].clock == clock) {
> +				clk_div = bxt_dp_clk_val[i];
> +				break;
> +			}
>   		}
>   		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
>   	}
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index abd442a..bd0f958 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -91,6 +91,8 @@ static const struct dp_link_dpll chv_dpll[] = {
>   		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>   };
>
> +static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
> +				  324000, 432000, 540000 };
>   static const int skl_rates[] = { 162000, 216000, 270000,
>   				  324000, 432000, 540000 };
>   static const int chv_rates[] = { 162000, 202500, 210000, 216000,
> @@ -1170,7 +1172,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>   static int
>   intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>   {
> -	if (IS_SKYLAKE(dev)) {
> +	if (IS_BROXTON(dev)) {
> +		*source_rates = bxt_rates;
> +		return ARRAY_SIZE(bxt_rates);
> +	} else if (IS_SKYLAKE(dev)) {
>   		*source_rates = skl_rates;
>   		return ARRAY_SIZE(skl_rates);
>   	} else if (IS_CHERRYVIEW(dev)) {
>
Reviewed-by: Vandana Kannan <vandana.kannan@intel.com>
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Re: [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

[Jani Nikula]

On Wed, 03 Jun 2015, "Kannan, Vandana" <vandana.kannan@intel.com> wrote:
> On 5/26/2015 5:50 PM, Sonika Jindal wrote:
>> BXT supports following intermediate link rates for edp:
>> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
>> Adding support for programming the intermediate rates.
>>
>> v2: Adding clock in bxt_clk_div struct and then look for the entry with
>> required rate (Ville)
>> v3: 'clock' has the selected value, no need to use link_bw or rate_select
>> for selecting pll(Ville)
>> v4: Make bxt_dp_clk_val const and remove size (Ville)
>> v5: Rebased
>> v6: Removed setting of vco while rebasing in v5, adding it back
>>
>> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>(v4)

Pushed to drm-intel-next-queued, thanks for the patch and review.

BR,
Jani.

>> ---
>>   drivers/gpu/drm/i915/intel_ddi.c |   39 ++++++++++++++++----------------------
>>   drivers/gpu/drm/i915/intel_dp.c  |    7 ++++++-
>>   2 files changed, 22 insertions(+), 24 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index cacb07b..2a2518d 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -1334,6 +1334,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>>
>>   /* bxt clock parameters */
>>   struct bxt_clk_div {
>> +	int clock;
>>   	uint32_t p1;
>>   	uint32_t p2;
>>   	uint32_t m2_int;
>> @@ -1343,14 +1344,14 @@ struct bxt_clk_div {
>>   };
>>
>>   /* pre-calculated values for DP linkrates */
>> -static struct bxt_clk_div bxt_dp_clk_val[7] = {
>> -	/* 162 */ {4, 2, 32, 1677722, 1, 1},
>> -	/* 270 */ {4, 1, 27,       0, 0, 1},
>> -	/* 540 */ {2, 1, 27,       0, 0, 1},
>> -	/* 216 */ {3, 2, 32, 1677722, 1, 1},
>> -	/* 243 */ {4, 1, 24, 1258291, 1, 1},
>> -	/* 324 */ {4, 1, 32, 1677722, 1, 1},
>> -	/* 432 */ {3, 1, 32, 1677722, 1, 1}
>> +static const struct bxt_clk_div bxt_dp_clk_val[] = {
>> +	{162000, 4, 2, 32, 1677722, 1, 1},
>> +	{270000, 4, 1, 27,       0, 0, 1},
>> +	{540000, 2, 1, 27,       0, 0, 1},
>> +	{216000, 3, 2, 32, 1677722, 1, 1},
>> +	{243000, 4, 1, 24, 1258291, 1, 1},
>> +	{324000, 4, 1, 32, 1677722, 1, 1},
>> +	{432000, 3, 1, 32, 1677722, 1, 1}
>>   };
>>
>>   static bool
>> @@ -1390,22 +1391,14 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>>   		vco = best_clock.vco;
>>   	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
>>   			intel_encoder->type == INTEL_OUTPUT_EDP) {
>> -		struct drm_encoder *encoder = &intel_encoder->base;
>> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> +		int i;
>>
>> -		switch (intel_dp->link_bw) {
>> -		case DP_LINK_BW_1_62:
>> -			clk_div = bxt_dp_clk_val[0];
>> -			break;
>> -		case DP_LINK_BW_2_7:
>> -			clk_div = bxt_dp_clk_val[1];
>> -			break;
>> -		case DP_LINK_BW_5_4:
>> -			clk_div = bxt_dp_clk_val[2];
>> -			break;
>> -		default:
>> -			clk_div = bxt_dp_clk_val[0];
>> -			DRM_ERROR("Unknown link rate\n");
>> +		clk_div = bxt_dp_clk_val[0];
>> +		for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
>> +			if (bxt_dp_clk_val[i].clock == clock) {
>> +				clk_div = bxt_dp_clk_val[i];
>> +				break;
>> +			}
>>   		}
>>   		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
>>   	}
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index abd442a..bd0f958 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -91,6 +91,8 @@ static const struct dp_link_dpll chv_dpll[] = {
>>   		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>>   };
>>
>> +static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
>> +				  324000, 432000, 540000 };
>>   static const int skl_rates[] = { 162000, 216000, 270000,
>>   				  324000, 432000, 540000 };
>>   static const int chv_rates[] = { 162000, 202500, 210000, 216000,
>> @@ -1170,7 +1172,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>>   static int
>>   intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>>   {
>> -	if (IS_SKYLAKE(dev)) {
>> +	if (IS_BROXTON(dev)) {
>> +		*source_rates = bxt_rates;
>> +		return ARRAY_SIZE(bxt_rates);
>> +	} else if (IS_SKYLAKE(dev)) {
>>   		*source_rates = skl_rates;
>>   		return ARRAY_SIZE(skl_rates);
>>   	} else if (IS_CHERRYVIEW(dev)) {
>>
> Reviewed-by: Vandana Kannan <vandana.kannan@intel.com>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH] drm/i915: Sink rate read should be saved in deca-kHz

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6242
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  302/302              302/302
SNB                                  318/318              318/318
IVB                                  341/341              341/341
BYT                                  287/287              287/287
BDW                                  318/318              318/318
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
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[PATCH] drm/i915: Sink rate read should be saved in deca-kHz

[Sonika Jindal]

The sink rate read from supported link rate table is in KHz as per spec
while in drm, the saved clock is in deca-KHz. So divide the link rate by
10 before storing.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 14cdd00..ae2cfc3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3833,7 +3833,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 			if (val == 0)
 				break;
 
-			intel_dp->sink_rates[i] = val * 200;
+			/* Value read is in kHz while drm clock is saved in deca-kHz */
+			intel_dp->sink_rates[i] = (val * 200) / 10;
 		}
 		intel_dp->num_sink_rates = i;
 	}
-- 
1.7.10.4

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