[PATCH] drm/i915/glk: CDCLK calculation changes for glk

[PATCH] drm/i915/glk: CDCLK calculation changes for glk

[Madhav Chauhan]

As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
Practically we can achive only 99% of these cdclk values. So cdclk
should be calculated for the given pixclk as per that otherwise it may
lead to screen corruption for some scenarios.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 45e5874..2e1bfe9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6544,9 +6544,9 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
 
 static int glk_calc_cdclk(int max_pixclk)
 {
-	if (max_pixclk > 2 * 158400)
+	if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
 		return 316800;
-	else if (max_pixclk > 2 * 79200)
+	else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
 		return 158400;
 	else
 		return 79200;
-- 
1.9.1

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✓ Fi.CI.BAT: success for drm/i915/glk: CDCLK calculation changes for glk

[Patchwork]

== Series Details ==

Series: drm/i915/glk: CDCLK calculation changes for glk
URL   : https://patchwork.freedesktop.org/series/19226/
State : success

== Summary ==

Series 19226v1 drm/i915/glk: CDCLK calculation changes for glk
https://patchwork.freedesktop.org/api/1.0/series/19226/revisions/1/mbox/

Test kms_pipe_crc_basic:
        Subgroup nonblocking-crc-pipe-b:
                dmesg-warn -> PASS       (fi-snb-2520m)

fi-bdw-5557u     total:252  pass:238  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050     total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:252  pass:230  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700     total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900     total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r     total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-ilk-650       total:252  pass:199  dwarn:0   dfail:0   fail:0   skip:53 
fi-ivb-3520m     total:252  pass:231  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770      total:252  pass:231  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u     total:252  pass:229  dwarn:0   dfail:0   fail:2   skip:21 
fi-skl-6260u     total:252  pass:239  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hq    total:252  pass:232  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k     total:252  pass:227  dwarn:4   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:252  pass:239  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m     total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600      total:252  pass:220  dwarn:0   dfail:0   fail:0   skip:32 

4b60513d8a00fc960a2d837fcccf6a63c861d9ec drm-tip: 2017y-02m-06d-22h-40m-55s UTC integration manifest
8543195 drm/i915/glk: CDCLK calculation changes for glk

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3720/
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Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk

[Ville Syrjälä]

On Tue, Feb 07, 2017 at 05:48:46AM -0500, Madhav Chauhan wrote:
> As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
> Practically we can achive only 99% of these cdclk values. So cdclk
> should be calculated for the given pixclk as per that otherwise it may
> lead to screen corruption for some scenarios.

I this caused by the hw actually requiring some guardband or simply
because of our sucky DPLL code not updating the dotclock with the actual
value the hw is going to produce?

If it's a genuine hw limitation is it documented? And if not has
someone filed a spec issue for it? And what about other platforms
(GLK isn't the only one without a guardband in our code after all)?

> 
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 45e5874..2e1bfe9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6544,9 +6544,9 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>  
>  static int glk_calc_cdclk(int max_pixclk)
>  {
> -	if (max_pixclk > 2 * 158400)
> +	if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
>  		return 316800;
> -	else if (max_pixclk > 2 * 79200)
> +	else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
>  		return 158400;
>  	else
>  		return 79200;
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk

[Jani Nikula]

On Tue, 07 Feb 2017, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Feb 07, 2017 at 05:48:46AM -0500, Madhav Chauhan wrote:
>> As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
>> Practically we can achive only 99% of these cdclk values. So cdclk
>> should be calculated for the given pixclk as per that otherwise it may
>> lead to screen corruption for some scenarios.
>
> I this caused by the hw actually requiring some guardband or simply
> because of our sucky DPLL code not updating the dotclock with the actual
> value the hw is going to produce?
>
> If it's a genuine hw limitation is it documented? And if not has
> someone filed a spec issue for it? And what about other platforms
> (GLK isn't the only one without a guardband in our code after all)?

Indeed. What's the 99% based on? Where is it documented?

BR,
Jani.

>
>> 
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 45e5874..2e1bfe9 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -6544,9 +6544,9 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>>  
>>  static int glk_calc_cdclk(int max_pixclk)
>>  {
>> -	if (max_pixclk > 2 * 158400)
>> +	if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
>>  		return 316800;
>> -	else if (max_pixclk > 2 * 79200)
>> +	else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
>>  		return 158400;
>>  	else
>>  		return 79200;
>> -- 
>> 1.9.1
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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[PATCH] drm/i915/glk: CDCLK calculation changes for glk

[Madhav Chauhan]

As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
Practically we can achive only 99% of these cdclk values(HW team
checking on this). So cdclk should be calculated for the given pixclk as
per that otherwise it may lead to screen corruption for some scenarios.

v2: Rebased to new CDLCK code framework

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index d643c0c..834df68 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int max_pixclk)
 
 static int glk_calc_cdclk(int max_pixclk)
 {
-	if (max_pixclk > 2 * 158400)
+	if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
 		return 316800;
-	else if (max_pixclk > 2 * 79200)
+	else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
 		return 158400;
 	else
 		return 79200;
-- 
1.9.1

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Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk

[Jani Nikula]

On Thu, 16 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
> Practically we can achive only 99% of these cdclk values(HW team
> checking on this). So cdclk should be calculated for the given pixclk as
> per that otherwise it may lead to screen corruption for some scenarios.
>
> v2: Rebased to new CDLCK code framework
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index d643c0c..834df68 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int max_pixclk)
>  
>  static int glk_calc_cdclk(int max_pixclk)
>  {
> -	if (max_pixclk > 2 * 158400)
> +	if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))

Where do we ensure we don't use pixel clock 312841..316800? Clearly we
shouldn't use that because we can't guarantee it works, right?

Before we get the spec update to confirm what to do, I think we need a
comment here explaining what's going on.

BR,
Jani.

>  		return 316800;
> -	else if (max_pixclk > 2 * 79200)
> +	else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
>  		return 158400;
>  	else
>  		return 79200;

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk

[Chauhan, Madhav]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Thursday, February 16, 2017 9:03 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Conselvan De Oliveira, Ander <ander.conselvan.de.oliveira@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
> <indranil.mukherjee@intel.com>; Sharma, Shashank
> <shashank.sharma@intel.com>; Chauhan, Madhav
> <madhav.chauhan@intel.com>; ville.syrjala@linux.intel.com
> Subject: Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk
> 
> On Thu, 16 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com>
> wrote:
> > As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
> > Practically we can achive only 99% of these cdclk values(HW team
> > checking on this). So cdclk should be calculated for the given pixclk
> > as per that otherwise it may lead to screen corruption for some scenarios.
> >
> > v2: Rebased to new CDLCK code framework
> >
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > index d643c0c..834df68 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int max_pixclk)
> >
> >  static int glk_calc_cdclk(int max_pixclk)  {
> > -	if (max_pixclk > 2 * 158400)
> > +	if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
> 
> Where do we ensure we don't use pixel clock 312841..316800? Clearly we
> shouldn't use that because we can't guarantee it works, right?
Why do we need to ensure that ?? Can you please elaborate more on this?  
Here we are finding one of  the defined CDCLK value for a pixel clock
> 
> Before we get the spec update to confirm what to do, I think we need a
> comment here explaining what's going on.
Will add the following comment, if that's fine, will send the rebased patch:
"For GLK platform, only 99% of the defined CDCLK value can be achieved 
  So calculate pixel clock on that basis"

Regards,
Madhav
> 
> BR,
> Jani.
> 
> >  		return 316800;
> > -	else if (max_pixclk > 2 * 79200)
> > +	else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
> >  		return 158400;
> >  	else
> >  		return 79200;
> 
> --
> Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk

[Jani Nikula]

On Thu, 16 Mar 2017, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani
>> Sent: Thursday, February 16, 2017 9:03 PM
>> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: Conselvan De Oliveira, Ander <ander.conselvan.de.oliveira@intel.com>;
>> Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
>> <indranil.mukherjee@intel.com>; Sharma, Shashank
>> <shashank.sharma@intel.com>; Chauhan, Madhav
>> <madhav.chauhan@intel.com>; ville.syrjala@linux.intel.com
>> Subject: Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk
>> 
>> On Thu, 16 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com>
>> wrote:
>> > As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
>> > Practically we can achive only 99% of these cdclk values(HW team
>> > checking on this). So cdclk should be calculated for the given pixclk
>> > as per that otherwise it may lead to screen corruption for some scenarios.
>> >
>> > v2: Rebased to new CDLCK code framework
>> >
>> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
>> >  1 file changed, 2 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
>> > b/drivers/gpu/drm/i915/intel_cdclk.c
>> > index d643c0c..834df68 100644
>> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
>> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>> > @@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int max_pixclk)
>> >
>> >  static int glk_calc_cdclk(int max_pixclk)  {
>> > -	if (max_pixclk > 2 * 158400)
>> > +	if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
>> 
>> Where do we ensure we don't use pixel clock 312841..316800? Clearly we
>> shouldn't use that because we can't guarantee it works, right?
> Why do we need to ensure that ?? Can you please elaborate more on this?  
> Here we are finding one of  the defined CDCLK value for a pixel clock

I probably had some great idea a month ago when I wrote that, but I can
no longer remember what it was. :(

BR,
Jani.


>> 
>> Before we get the spec update to confirm what to do, I think we need a
>> comment here explaining what's going on.
> Will add the following comment, if that's fine, will send the rebased patch:
> "For GLK platform, only 99% of the defined CDCLK value can be achieved 
>   So calculate pixel clock on that basis"
>
> Regards,
> Madhav
>> 
>> BR,
>> Jani.
>> 
>> >  		return 316800;
>> > -	else if (max_pixclk > 2 * 79200)
>> > +	else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
>> >  		return 158400;
>> >  	else
>> >  		return 79200;
>> 
>> --
>> Jani Nikula, Intel Open Source Technology Center

-- 
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Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk

[Ander Conselvan De Oliveira]

On Thu, 2017-03-16 at 15:10 +0200, Jani Nikula wrote:
> On Thu, 16 Mar 2017, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
> > > -----Original Message-----
> > > From: Nikula, Jani
> > > Sent: Thursday, February 16, 2017 9:03 PM
> > > To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> > > gfx@lists.freedesktop.org
> > > Cc: Conselvan De Oliveira, Ander <ander.conselvan.de.oliveira@intel.com>;
> > > Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
> > > <indranil.mukherjee@intel.com>; Sharma, Shashank
> > > <shashank.sharma@intel.com>; Chauhan, Madhav
> > > <madhav.chauhan@intel.com>; ville.syrjala@linux.intel.com
> > > Subject: Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk
> > > 
> > > On Thu, 16 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com>
> > > wrote:
> > > > As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
> > > > Practically we can achive only 99% of these cdclk values(HW team
> > > > checking on this). So cdclk should be calculated for the given pixclk
> > > > as per that otherwise it may lead to screen corruption for some scenarios.
> > > > 
> > > > v2: Rebased to new CDLCK code framework
> > > > 
> > > > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
> > > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > > > b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > index d643c0c..834df68 100644
> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > @@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int max_pixclk)
> > > > 
> > > >  static int glk_calc_cdclk(int max_pixclk)  {
> > > > -	if (max_pixclk > 2 * 158400)
> > > > +	if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
> > > 
> > > Where do we ensure we don't use pixel clock 312841..316800? Clearly we
> > > shouldn't use that because we can't guarantee it works, right?
> > 
> > Why do we need to ensure that ?? Can you please elaborate more on this?  
> > Here we are finding one of  the defined CDCLK value for a pixel clock
> 
> I probably had some great idea a month ago when I wrote that, but I can
> no longer remember what it was. :(

I'm not sure if that is what you meant, but if the hardware can't handle it,
intel_compute_max_dotclk() needs to take the 99% limitation into account too.
I.e., max dot clock would be .99 * 2 *  316800 = 627264.

Ander

> 
> BR,
> Jani.
> 
> 
> > > 
> > > Before we get the spec update to confirm what to do, I think we need a
> > > comment here explaining what's going on.
> > 
> > Will add the following comment, if that's fine, will send the rebased patch:
> > "For GLK platform, only 99% of the defined CDCLK value can be achieved 
> >   So calculate pixel clock on that basis"
> > 
> > Regards,
> > Madhav
> > > 
> > > BR,
> > > Jani.
> > > 
> > > >  		return 316800;
> > > > -	else if (max_pixclk > 2 * 79200)
> > > > +	else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
> > > >  		return 158400;
> > > >  	else
> > > >  		return 79200;
> > > 
> > > --
> > > Jani Nikula, Intel Open Source Technology Center
> 
> 
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Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk

[Jani Nikula]

On Thu, 16 Mar 2017, Ander Conselvan De Oliveira <conselvan2@gmail.com> wrote:
> On Thu, 2017-03-16 at 15:10 +0200, Jani Nikula wrote:
>> On Thu, 16 Mar 2017, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
>> > > -----Original Message-----
>> > > From: Nikula, Jani
>> > > Sent: Thursday, February 16, 2017 9:03 PM
>> > > To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
>> > > gfx@lists.freedesktop.org
>> > > Cc: Conselvan De Oliveira, Ander <ander.conselvan.de.oliveira@intel.com>;
>> > > Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
>> > > <indranil.mukherjee@intel.com>; Sharma, Shashank
>> > > <shashank.sharma@intel.com>; Chauhan, Madhav
>> > > <madhav.chauhan@intel.com>; ville.syrjala@linux.intel.com
>> > > Subject: Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk
>> > > 
>> > > On Thu, 16 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com>
>> > > wrote:
>> > > > As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
>> > > > Practically we can achive only 99% of these cdclk values(HW team
>> > > > checking on this). So cdclk should be calculated for the given pixclk
>> > > > as per that otherwise it may lead to screen corruption for some scenarios.
>> > > > 
>> > > > v2: Rebased to new CDLCK code framework
>> > > > 
>> > > > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> > > > ---
>> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
>> > > >  1 file changed, 2 insertions(+), 2 deletions(-)
>> > > > 
>> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
>> > > > b/drivers/gpu/drm/i915/intel_cdclk.c
>> > > > index d643c0c..834df68 100644
>> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
>> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>> > > > @@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int max_pixclk)
>> > > > 
>> > > >  static int glk_calc_cdclk(int max_pixclk)  {
>> > > > -	if (max_pixclk > 2 * 158400)
>> > > > +	if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
>> > > 
>> > > Where do we ensure we don't use pixel clock 312841..316800? Clearly we
>> > > shouldn't use that because we can't guarantee it works, right?
>> > 
>> > Why do we need to ensure that ?? Can you please elaborate more on this?  
>> > Here we are finding one of  the defined CDCLK value for a pixel clock
>> 
>> I probably had some great idea a month ago when I wrote that, but I can
>> no longer remember what it was. :(
>
> I'm not sure if that is what you meant, but if the hardware can't handle it,
> intel_compute_max_dotclk() needs to take the 99% limitation into account too.
> I.e., max dot clock would be .99 * 2 *  316800 = 627264.

Yes, thank you!

Jani.

>
> Ander
>
>> 
>> BR,
>> Jani.
>> 
>> 
>> > > 
>> > > Before we get the spec update to confirm what to do, I think we need a
>> > > comment here explaining what's going on.
>> > 
>> > Will add the following comment, if that's fine, will send the rebased patch:
>> > "For GLK platform, only 99% of the defined CDCLK value can be achieved 
>> >   So calculate pixel clock on that basis"
>> > 
>> > Regards,
>> > Madhav
>> > > 
>> > > BR,
>> > > Jani.
>> > > 
>> > > >  		return 316800;
>> > > > -	else if (max_pixclk > 2 * 79200)
>> > > > +	else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
>> > > >  		return 158400;
>> > > >  	else
>> > > >  		return 79200;
>> > > 
>> > > --
>> > > Jani Nikula, Intel Open Source Technology Center
>> 
>> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk

[Chauhan, Madhav]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Thursday, March 16, 2017 7:00 PM
> To: Ander Conselvan De Oliveira <conselvan2@gmail.com>; Chauhan,
> Madhav <madhav.chauhan@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for
> glk
> 
> On Thu, 16 Mar 2017, Ander Conselvan De Oliveira
> <conselvan2@gmail.com> wrote:
> > On Thu, 2017-03-16 at 15:10 +0200, Jani Nikula wrote:
> >> On Thu, 16 Mar 2017, "Chauhan, Madhav"
> <madhav.chauhan@intel.com> wrote:
> >> > > -----Original Message-----
> >> > > From: Nikula, Jani
> >> > > Sent: Thursday, February 16, 2017 9:03 PM
> >> > > To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> >> > > gfx@lists.freedesktop.org
> >> > > Cc: Conselvan De Oliveira, Ander
> >> > > <ander.conselvan.de.oliveira@intel.com>;
> >> > > Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
> >> > > <indranil.mukherjee@intel.com>; Sharma, Shashank
> >> > > <shashank.sharma@intel.com>; Chauhan, Madhav
> >> > > <madhav.chauhan@intel.com>; ville.syrjala@linux.intel.com
> >> > > Subject: Re: [PATCH] drm/i915/glk: CDCLK calculation changes for
> >> > > glk
> >> > >
> >> > > On Thu, 16 Feb 2017, Madhav Chauhan
> <madhav.chauhan@intel.com>
> >> > > wrote:
> >> > > > As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
> >> > > > Practically we can achive only 99% of these cdclk values(HW
> >> > > > team checking on this). So cdclk should be calculated for the
> >> > > > given pixclk as per that otherwise it may lead to screen corruption
> for some scenarios.
> >> > > >
> >> > > > v2: Rebased to new CDLCK code framework
> >> > > >
> >> > > > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> >> > > > ---
> >> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
> >> > > >  1 file changed, 2 insertions(+), 2 deletions(-)
> >> > > >
> >> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> >> > > > b/drivers/gpu/drm/i915/intel_cdclk.c
> >> > > > index d643c0c..834df68 100644
> >> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> >> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> >> > > > @@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int max_pixclk)
> >> > > >
> >> > > >  static int glk_calc_cdclk(int max_pixclk)  {
> >> > > > -	if (max_pixclk > 2 * 158400)
> >> > > > +	if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
> >> > >
> >> > > Where do we ensure we don't use pixel clock 312841..316800?
> >> > > Clearly we shouldn't use that because we can't guarantee it works,
> right?
> >> >
> >> > Why do we need to ensure that ?? Can you please elaborate more on
> this?
> >> > Here we are finding one of  the defined CDCLK value for a pixel
> >> > clock
> >>
> >> I probably had some great idea a month ago when I wrote that, but I
> >> can no longer remember what it was. :(
> >
> > I'm not sure if that is what you meant, but if the hardware can't
> > handle it,
> > intel_compute_max_dotclk() needs to take the 99% limitation into account
> too.
> > I.e., max dot clock would be .99 * 2 *  316800 = 627264.
> 
> Yes, thank you!

Ok. Will include this change as well along with additional comments
for explaining 99% usage of cdclk inside glk_calc_cdclk.
Thanks for review.

> 
> Jani.
> 
> >
> > Ander
> >
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >> > >
> >> > > Before we get the spec update to confirm what to do, I think we
> >> > > need a comment here explaining what's going on.
> >> >
> >> > Will add the following comment, if that's fine, will send the rebased
> patch:
> >> > "For GLK platform, only 99% of the defined CDCLK value can be achieved
> >> >   So calculate pixel clock on that basis"
> >> >
> >> > Regards,
> >> > Madhav
> >> > >
> >> > > BR,
> >> > > Jani.
> >> > >
> >> > > >  		return 316800;
> >> > > > -	else if (max_pixclk > 2 * 79200)
> >> > > > +	else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
> >> > > >  		return 158400;
> >> > > >  	else
> >> > > >  		return 79200;
> >> > >
> >> > > --
> >> > > Jani Nikula, Intel Open Source Technology Center
> >>
> >>
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH] drm/i915/glk: CDCLK calculation changes for glk

[Chauhan, Madhav]

> -----Original Message-----
> From: Chauhan, Madhav
> Sent: Friday, March 17, 2017 7:11 PM
> To: Nikula, Jani <jani.nikula@intel.com>; Ander Conselvan De Oliveira
> <conselvan2@gmail.com>; intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation changes for
> glk
> 
> > -----Original Message-----
> > From: Nikula, Jani
> > Sent: Thursday, March 16, 2017 7:00 PM
> > To: Ander Conselvan De Oliveira <conselvan2@gmail.com>; Chauhan,
> > Madhav <madhav.chauhan@intel.com>; intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/glk: CDCLK calculation
> > changes for glk
> >
> > On Thu, 16 Mar 2017, Ander Conselvan De Oliveira
> > <conselvan2@gmail.com> wrote:
> > > On Thu, 2017-03-16 at 15:10 +0200, Jani Nikula wrote:
> > >> On Thu, 16 Mar 2017, "Chauhan, Madhav"
> > <madhav.chauhan@intel.com> wrote:
> > >> > > -----Original Message-----
> > >> > > From: Nikula, Jani
> > >> > > Sent: Thursday, February 16, 2017 9:03 PM
> > >> > > To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> > >> > > gfx@lists.freedesktop.org
> > >> > > Cc: Conselvan De Oliveira, Ander
> > >> > > <ander.conselvan.de.oliveira@intel.com>;
> > >> > > Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
> > >> > > <indranil.mukherjee@intel.com>; Sharma, Shashank
> > >> > > <shashank.sharma@intel.com>; Chauhan, Madhav
> > >> > > <madhav.chauhan@intel.com>; ville.syrjala@linux.intel.com
> > >> > > Subject: Re: [PATCH] drm/i915/glk: CDCLK calculation changes
> > >> > > for glk
> > >> > >
> > >> > > On Thu, 16 Feb 2017, Madhav Chauhan
> > <madhav.chauhan@intel.com>
> > >> > > wrote:
> > >> > > > As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
> > >> > > > Practically we can achive only 99% of these cdclk values(HW
> > >> > > > team checking on this). So cdclk should be calculated for the
> > >> > > > given pixclk as per that otherwise it may lead to screen
> > >> > > > corruption
> > for some scenarios.
> > >> > > >
> > >> > > > v2: Rebased to new CDLCK code framework
> > >> > > >
> > >> > > > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > >> > > > ---
> > >> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
> > >> > > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > >> > > >
> > >> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > >> > > > b/drivers/gpu/drm/i915/intel_cdclk.c
> > >> > > > index d643c0c..834df68 100644
> > >> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > >> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > >> > > > @@ -1071,9 +1071,9 @@ static int bxt_calc_cdclk(int
> > >> > > > max_pixclk)
> > >> > > >
> > >> > > >  static int glk_calc_cdclk(int max_pixclk)  {
> > >> > > > -	if (max_pixclk > 2 * 158400)
> > >> > > > +	if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
> > >> > >
> > >> > > Where do we ensure we don't use pixel clock 312841..316800?
> > >> > > Clearly we shouldn't use that because we can't guarantee it
> > >> > > works,
> > right?
> > >> >
> > >> > Why do we need to ensure that ?? Can you please elaborate more on
> > this?
> > >> > Here we are finding one of  the defined CDCLK value for a pixel
> > >> > clock
> > >>
> > >> I probably had some great idea a month ago when I wrote that, but I
> > >> can no longer remember what it was. :(
> > >
> > > I'm not sure if that is what you meant, but if the hardware can't
> > > handle it,
> > > intel_compute_max_dotclk() needs to take the 99% limitation into
> > > account
> > too.
> > > I.e., max dot clock would be .99 * 2 *  316800 = 627264.
> >
> > Yes, thank you!

Tested this change on drm-tip. Found that 1-2 times MIPI didn't come up (might be some error 
during testing) after that it works  fine every time.
Could this change have some sort of impact on MIPI functionality?? Looked at code, found nothing
from that front.

> 
> Ok. Will include this change as well along with additional comments for
> explaining 99% usage of cdclk inside glk_calc_cdclk.
> Thanks for review.
> 
> >
> > Jani.
> >
> > >
> > > Ander
> > >
> > >>
> > >> BR,
> > >> Jani.
> > >>
> > >>
> > >> > >
> > >> > > Before we get the spec update to confirm what to do, I think we
> > >> > > need a comment here explaining what's going on.
> > >> >
> > >> > Will add the following comment, if that's fine, will send the
> > >> > rebased
> > patch:
> > >> > "For GLK platform, only 99% of the defined CDCLK value can be
> achieved
> > >> >   So calculate pixel clock on that basis"
> > >> >
> > >> > Regards,
> > >> > Madhav
> > >> > >
> > >> > > BR,
> > >> > > Jani.
> > >> > >
> > >> > > >  		return 316800;
> > >> > > > -	else if (max_pixclk > 2 * 79200)
> > >> > > > +	else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
> > >> > > >  		return 158400;
> > >> > > >  	else
> > >> > > >  		return 79200;
> > >> > >
> > >> > > --
> > >> > > Jani Nikula, Intel Open Source Technology Center
> > >>
> > >>
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Jani Nikula, Intel Open Source Technology Center
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[PATCH] drm/i915/glk: CDCLK calculation changes for glk

[Madhav Chauhan]

As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
Practically we can achive only 99% of these cdclk values(HW team
checking on this). So cdclk should be calculated for the given pixclk as
per that otherwise it may lead to screen corruption for some scenarios.

v2: Rebased to new CDLCK code framework
v3: Addressed review comments from Ander/Jani
    - Add comment in code about 99% usage of CDCLK
    - Calculate max dot clock as well with 99% limit

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index c2cc33f..a661c7e 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1071,9 +1071,13 @@ static int bxt_calc_cdclk(int max_pixclk)
 
 static int glk_calc_cdclk(int max_pixclk)
 {
-	if (max_pixclk > 2 * 158400)
+	/*
+	 * For GLK platform 316.8, 158.4, 79.2 MHz are the CDCLK values
+	 * as per BSPEC. But practically we can only achieve 99% of these.
+	 */
+	if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
 		return 316800;
-	else if (max_pixclk > 2 * 79200)
+	else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
 		return 158400;
 	else
 		return 79200;
@@ -1613,7 +1617,6 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
 		cdclk = bxt_calc_cdclk(max_pixclk);
 		vco = bxt_de_pll_vco(dev_priv, cdclk);
 	}
-
 	if (cdclk > dev_priv->max_cdclk_freq) {
 		DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
 			      cdclk, dev_priv->max_cdclk_freq);
@@ -1647,7 +1650,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
 	int max_cdclk_freq = dev_priv->max_cdclk_freq;
 
 	if (IS_GEMINILAKE(dev_priv))
-		return 2 * max_cdclk_freq;
+		return 2 * max_cdclk_freq * 99/100;
 	else if (INTEL_INFO(dev_priv)->gen >= 9 ||
 		 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		return max_cdclk_freq;
-- 
1.9.1

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