From: Marc Zyngier <maz@kernel.org>
To: Guo Ren <guoren@kernel.org>
Cc: "Samuel Holland" <samuel@sholland.org>,
"Anup Patel" <anup@brainfault.org>,
"Atish Patra" <atish.patra@wdc.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Heiko Stübner" <heiko@sntech.de>,
"Rob Herring" <robh@kernel.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
"Guo Ren" <guoren@linux.alibaba.com>
Subject: Re: [PATCH V4 1/3] irqchip/sifive-plic: Add thead,c900-plic support
Date: Wed, 20 Oct 2021 14:34:05 +0100 [thread overview]
Message-ID: <875ytrddma.wl-maz@kernel.org> (raw)
In-Reply-To: <CAJF2gTSmyu9nA5M3QLeR1LdGMkeGb7jE93Z9zjixcpb_freLMw@mail.gmail.com>
On Tue, 19 Oct 2021 14:27:02 +0100,
Guo Ren <guoren@kernel.org> wrote:
>
> On Tue, Oct 19, 2021 at 6:18 PM Marc Zyngier <maz@kernel.org> wrote:
> >
> > On Tue, 19 Oct 2021 10:33:49 +0100,
> > Guo Ren <guoren@kernel.org> wrote:
> >
> > > > If you have an 'automask' behavior and yet the HW doesn't record this
> > > > in a separate bit, then you need to track this by yourself in the
> > > > irq_eoi() callback instead. I guess that you would skip the write to
> > > > the CLAIM register in this case, though I have no idea whether this
> > > > breaks
> > > > the HW interrupt state or not.
> > > The problem is when enable bit is 0 for that irq_number,
> > > "writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM)" wouldn't affect
> > > the hw state machine. Then this irq would enter in ack state and no
> > > continues irqs could come in.
> >
> > Really? This means that you cannot mask an interrupt while it is being
> > handled? How great...
> If the completion ID does not match an interrupt source that is
> currently enabled for the target, the completion is silently ignored.
> So, C9xx completion depends on enable-bit.
Is that what the PLIC spec says? Or what your implementation does? I
can understand that one implementation would be broken, but if the
PLIC architecture itself is broken, that's far more concerning.
M.
--
Without deviation from the norm, progress is not possible.
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Guo Ren <guoren@kernel.org>
Cc: "Samuel Holland" <samuel@sholland.org>,
"Anup Patel" <anup@brainfault.org>,
"Atish Patra" <atish.patra@wdc.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Heiko Stübner" <heiko@sntech.de>,
"Rob Herring" <robh@kernel.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
"Guo Ren" <guoren@linux.alibaba.com>
Subject: Re: [PATCH V4 1/3] irqchip/sifive-plic: Add thead,c900-plic support
Date: Wed, 20 Oct 2021 14:34:05 +0100 [thread overview]
Message-ID: <875ytrddma.wl-maz@kernel.org> (raw)
In-Reply-To: <CAJF2gTSmyu9nA5M3QLeR1LdGMkeGb7jE93Z9zjixcpb_freLMw@mail.gmail.com>
On Tue, 19 Oct 2021 14:27:02 +0100,
Guo Ren <guoren@kernel.org> wrote:
>
> On Tue, Oct 19, 2021 at 6:18 PM Marc Zyngier <maz@kernel.org> wrote:
> >
> > On Tue, 19 Oct 2021 10:33:49 +0100,
> > Guo Ren <guoren@kernel.org> wrote:
> >
> > > > If you have an 'automask' behavior and yet the HW doesn't record this
> > > > in a separate bit, then you need to track this by yourself in the
> > > > irq_eoi() callback instead. I guess that you would skip the write to
> > > > the CLAIM register in this case, though I have no idea whether this
> > > > breaks
> > > > the HW interrupt state or not.
> > > The problem is when enable bit is 0 for that irq_number,
> > > "writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM)" wouldn't affect
> > > the hw state machine. Then this irq would enter in ack state and no
> > > continues irqs could come in.
> >
> > Really? This means that you cannot mask an interrupt while it is being
> > handled? How great...
> If the completion ID does not match an interrupt source that is
> currently enabled for the target, the completion is silently ignored.
> So, C9xx completion depends on enable-bit.
Is that what the PLIC spec says? Or what your implementation does? I
can understand that one implementation would be broken, but if the
PLIC architecture itself is broken, that's far more concerning.
M.
--
Without deviation from the norm, progress is not possible.
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next prev parent reply other threads:[~2021-10-20 13:34 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-16 3:21 [PATCH V4 0/3] irqchip: riscv: Add thead,c900-plic support guoren
2021-10-16 3:21 ` guoren
2021-10-16 3:21 ` [PATCH V4 1/3] irqchip/sifive-plic: " guoren
2021-10-16 3:21 ` guoren
2021-10-18 5:17 ` Samuel Holland
2021-10-18 5:17 ` Samuel Holland
2021-10-18 5:40 ` Anup Patel
2021-10-18 5:40 ` Anup Patel
2021-10-18 7:05 ` Guo Ren
2021-10-18 7:05 ` Guo Ren
2021-10-18 7:21 ` Marc Zyngier
2021-10-18 7:21 ` Marc Zyngier
2021-10-19 9:33 ` Guo Ren
2021-10-19 9:33 ` Guo Ren
2021-10-19 10:18 ` Marc Zyngier
2021-10-19 10:18 ` Marc Zyngier
2021-10-19 13:27 ` Guo Ren
2021-10-19 13:27 ` Guo Ren
2021-10-20 13:34 ` Marc Zyngier [this message]
2021-10-20 13:34 ` Marc Zyngier
2021-10-20 14:19 ` Guo Ren
2021-10-20 14:19 ` Guo Ren
2021-10-20 14:59 ` Darius Rad
2021-10-20 14:59 ` Darius Rad
2021-10-20 16:18 ` Anup Patel
2021-10-20 16:18 ` Anup Patel
2021-10-20 18:01 ` Darius Rad
2021-10-20 18:01 ` Darius Rad
2021-10-21 8:47 ` Anup Patel
2021-10-21 8:47 ` Anup Patel
2021-10-20 14:33 ` Anup Patel
2021-10-20 14:33 ` Anup Patel
2021-10-20 15:08 ` Marc Zyngier
2021-10-20 15:08 ` Marc Zyngier
2021-10-20 16:08 ` Anup Patel
2021-10-20 16:08 ` Anup Patel
2021-10-20 16:48 ` Marc Zyngier
2021-10-20 16:48 ` Marc Zyngier
2021-10-21 8:52 ` Anup Patel
2021-10-21 8:52 ` Anup Patel
2021-10-21 1:46 ` Guo Ren
2021-10-21 1:46 ` Guo Ren
2021-10-21 2:00 ` Guo Ren
2021-10-21 2:00 ` Guo Ren
2021-10-21 8:33 ` Marc Zyngier
2021-10-21 8:33 ` Marc Zyngier
2021-10-21 9:43 ` Guo Ren
2021-10-21 9:43 ` Guo Ren
2021-10-16 3:21 ` [PATCH V4 2/3] dt-bindings: update riscv plic compatible string guoren
2021-10-16 3:21 ` guoren
2021-10-16 7:07 ` Andreas Schwab
2021-10-16 7:07 ` Andreas Schwab
2021-10-16 9:16 ` Guo Ren
2021-10-16 9:16 ` Guo Ren
2021-10-16 10:34 ` Heiko Stuebner
2021-10-16 10:34 ` Heiko Stuebner
2021-10-16 12:56 ` Guo Ren
2021-10-16 12:56 ` Guo Ren
2021-10-16 16:31 ` Heiko Stuebner
2021-10-16 16:31 ` Heiko Stuebner
2021-10-20 12:15 ` Guo Ren
2021-10-20 12:15 ` Guo Ren
2021-10-18 12:02 ` Rob Herring
2021-10-18 12:02 ` Rob Herring
2021-10-19 0:55 ` Guo Ren
2021-10-19 0:55 ` Guo Ren
2021-10-16 3:22 ` [PATCH V4 3/3] dt-bindings: vendor-prefixes: add T-Head Semiconductor guoren
2021-10-16 3:22 ` guoren
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