* [Intel-gfx] [PATCH 1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations
@ 2021-12-09 14:43 Ville Syrjala
2021-12-09 14:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Use the correct plane source width in watermark calculations Ville Syrjala
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Ville Syrjala @ 2021-12-09 14:43 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use pixel_rate rather than crtc_clock in the watermark calculations.
These are actually identical on gmch platforms for now since
we don't adjust the pixel rate based on pfit downscaling. But
pixel_rate is the thing we are actually interested here so use
the proper name for it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 52 ++++++++++++++-------------------
1 file changed, 22 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 434b1f8b7fe3..b5d5b625a321 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -915,15 +915,13 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
crtc = single_enabled_crtc(dev_priv);
if (crtc) {
- const struct drm_display_mode *pipe_mode =
- &crtc->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
+ int pixel_rate = crtc->config->pixel_rate;
int cpp = fb->format->cpp[0];
- int clock = pipe_mode->crtc_clock;
/* Display SR */
- wm = intel_calculate_wm(clock, &pnv_display_wm,
+ wm = intel_calculate_wm(pixel_rate, &pnv_display_wm,
pnv_display_wm.fifo_size,
cpp, latency->display_sr);
reg = intel_uncore_read(&dev_priv->uncore, DSPFW1);
@@ -933,7 +931,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
/* cursor SR */
- wm = intel_calculate_wm(clock, &pnv_cursor_wm,
+ wm = intel_calculate_wm(pixel_rate, &pnv_cursor_wm,
pnv_display_wm.fifo_size,
4, latency->cursor_sr);
reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
@@ -942,7 +940,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
/* Display HPLL off SR */
- wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
+ wm = intel_calculate_wm(pixel_rate, &pnv_display_hplloff_wm,
pnv_display_hplloff_wm.fifo_size,
cpp, latency->display_hpll_disable);
reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
@@ -951,7 +949,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
/* cursor HPLL off SR */
- wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
+ wm = intel_calculate_wm(pixel_rate, &pnv_cursor_hplloff_wm,
pnv_display_hplloff_wm.fifo_size,
4, latency->cursor_hpll_disable);
reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
@@ -1154,7 +1152,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
const struct drm_display_mode *pipe_mode =
&crtc_state->hw.pipe_mode;
unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
- unsigned int clock, htotal, cpp, width, wm;
+ unsigned int pixel_rate, htotal, cpp, width, wm;
if (latency == 0)
return USHRT_MAX;
@@ -1175,21 +1173,21 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
level != G4X_WM_LEVEL_NORMAL)
cpp = max(cpp, 4u);
- clock = pipe_mode->crtc_clock;
+ pixel_rate = crtc_state->pixel_rate;
htotal = pipe_mode->crtc_htotal;
width = drm_rect_width(&plane_state->uapi.dst);
if (plane->id == PLANE_CURSOR) {
- wm = intel_wm_method2(clock, htotal, width, cpp, latency);
+ wm = intel_wm_method2(pixel_rate, htotal, width, cpp, latency);
} else if (plane->id == PLANE_PRIMARY &&
level == G4X_WM_LEVEL_NORMAL) {
- wm = intel_wm_method1(clock, cpp, latency);
+ wm = intel_wm_method1(pixel_rate, cpp, latency);
} else {
unsigned int small, large;
- small = intel_wm_method1(clock, cpp, latency);
- large = intel_wm_method2(clock, htotal, width, cpp, latency);
+ small = intel_wm_method1(pixel_rate, cpp, latency);
+ large = intel_wm_method2(pixel_rate, htotal, width, cpp, latency);
wm = min(small, large);
}
@@ -1674,7 +1672,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_display_mode *pipe_mode =
&crtc_state->hw.pipe_mode;
- unsigned int clock, htotal, cpp, width, wm;
+ unsigned int pixel_rate, htotal, cpp, width, wm;
if (dev_priv->wm.pri_latency[level] == 0)
return USHRT_MAX;
@@ -1683,7 +1681,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
return 0;
cpp = plane_state->hw.fb->format->cpp[0];
- clock = pipe_mode->crtc_clock;
+ pixel_rate = crtc_state->pixel_rate;
htotal = pipe_mode->crtc_htotal;
width = crtc_state->pipe_src_w;
@@ -1696,7 +1694,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
*/
wm = 63;
} else {
- wm = vlv_wm_method2(clock, htotal, width, cpp,
+ wm = vlv_wm_method2(pixel_rate, htotal, width, cpp,
dev_priv->wm.pri_latency[level] * 10);
}
@@ -2277,13 +2275,13 @@ static void i965_update_wm(struct drm_i915_private *dev_priv)
&crtc->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
- int clock = pipe_mode->crtc_clock;
+ int pixel_rate = crtc->config->pixel_rate;
int htotal = pipe_mode->crtc_htotal;
int hdisplay = crtc->config->pipe_src_w;
int cpp = fb->format->cpp[0];
int entries;
- entries = intel_wm_method2(clock, htotal,
+ entries = intel_wm_method2(pixel_rate, htotal,
hdisplay, cpp, sr_latency_ns / 100);
entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
srwm = I965_FIFO_SIZE - entries;
@@ -2294,7 +2292,7 @@ static void i965_update_wm(struct drm_i915_private *dev_priv)
"self-refresh entries: %d, wm: %d\n",
entries, srwm);
- entries = intel_wm_method2(clock, htotal,
+ entries = intel_wm_method2(pixel_rate, htotal,
crtc->base.cursor->state->crtc_w, 4,
sr_latency_ns / 100);
entries = DIV_ROUND_UP(entries,
@@ -2373,8 +2371,6 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
crtc = intel_crtc_for_plane(dev_priv, PLANE_A);
if (intel_crtc_active(crtc)) {
- const struct drm_display_mode *pipe_mode =
- &crtc->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
int cpp;
@@ -2384,7 +2380,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
else
cpp = fb->format->cpp[0];
- planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
+ planea_wm = intel_calculate_wm(crtc->config->pixel_rate,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
enabled = crtc;
@@ -2403,8 +2399,6 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
crtc = intel_crtc_for_plane(dev_priv, PLANE_B);
if (intel_crtc_active(crtc)) {
- const struct drm_display_mode *pipe_mode =
- &crtc->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
int cpp;
@@ -2414,7 +2408,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
else
cpp = fb->format->cpp[0];
- planeb_wm = intel_calculate_wm(pipe_mode->crtc_clock,
+ planeb_wm = intel_calculate_wm(crtc->config->pixel_rate,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
if (enabled == NULL)
@@ -2456,7 +2450,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
&enabled->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
enabled->base.primary->state->fb;
- int clock = pipe_mode->crtc_clock;
+ int pixel_rate = enabled->config->pixel_rate;
int htotal = pipe_mode->crtc_htotal;
int hdisplay = enabled->config->pipe_src_w;
int cpp;
@@ -2467,7 +2461,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
else
cpp = fb->format->cpp[0];
- entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
+ entries = intel_wm_method2(pixel_rate, htotal, hdisplay, cpp,
sr_latency_ns / 100);
entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
drm_dbg_kms(&dev_priv->drm,
@@ -2504,7 +2498,6 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
static void i845_update_wm(struct drm_i915_private *dev_priv)
{
struct intel_crtc *crtc;
- const struct drm_display_mode *pipe_mode;
u32 fwater_lo;
int planea_wm;
@@ -2512,8 +2505,7 @@ static void i845_update_wm(struct drm_i915_private *dev_priv)
if (crtc == NULL)
return;
- pipe_mode = &crtc->config->hw.pipe_mode;
- planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
+ planea_wm = intel_calculate_wm(crtc->config->pixel_rate,
&i845_wm_info,
i845_get_fifo_size(dev_priv, PLANE_A),
4, pessimal_latency_ns);
--
2.32.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915: Use the correct plane source width in watermark calculations
2021-12-09 14:43 [Intel-gfx] [PATCH 1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations Ville Syrjala
@ 2021-12-09 14:43 ` Ville Syrjala
2021-12-09 14:43 ` [Intel-gfx] [PATCH 3/3] drm/i915: Use single_enabled_crtc() in i9xx_update_wm() Ville Syrjala
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Ville Syrjala @ 2021-12-09 14:43 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currently we sometimes use the plane destination width, or just the
pipe src width as the plane source width in the watermark calculatons.
Use the correct thing everywhere.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b5d5b625a321..baa5f9fdf17c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1175,8 +1175,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
pixel_rate = crtc_state->pixel_rate;
htotal = pipe_mode->crtc_htotal;
-
- width = drm_rect_width(&plane_state->uapi.dst);
+ width = drm_rect_width(&plane_state->uapi.src) >> 16;
if (plane->id == PLANE_CURSOR) {
wm = intel_wm_method2(pixel_rate, htotal, width, cpp, latency);
@@ -1683,7 +1682,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
cpp = plane_state->hw.fb->format->cpp[0];
pixel_rate = crtc_state->pixel_rate;
htotal = pipe_mode->crtc_htotal;
- width = crtc_state->pipe_src_w;
+ width = drm_rect_width(&plane_state->uapi.src) >> 16;
if (plane->id == PLANE_CURSOR) {
/*
@@ -2277,12 +2276,12 @@ static void i965_update_wm(struct drm_i915_private *dev_priv)
crtc->base.primary->state->fb;
int pixel_rate = crtc->config->pixel_rate;
int htotal = pipe_mode->crtc_htotal;
- int hdisplay = crtc->config->pipe_src_w;
+ int width = drm_rect_width(&crtc->base.primary->state->src) >> 16;
int cpp = fb->format->cpp[0];
int entries;
entries = intel_wm_method2(pixel_rate, htotal,
- hdisplay, cpp, sr_latency_ns / 100);
+ width, cpp, sr_latency_ns / 100);
entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
srwm = I965_FIFO_SIZE - entries;
if (srwm < 0)
@@ -2452,7 +2451,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
enabled->base.primary->state->fb;
int pixel_rate = enabled->config->pixel_rate;
int htotal = pipe_mode->crtc_htotal;
- int hdisplay = enabled->config->pipe_src_w;
+ int width = drm_rect_width(&enabled->base.primary->state->src) >> 16;
int cpp;
int entries;
@@ -2461,7 +2460,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
else
cpp = fb->format->cpp[0];
- entries = intel_wm_method2(pixel_rate, htotal, hdisplay, cpp,
+ entries = intel_wm_method2(pixel_rate, htotal, width, cpp,
sr_latency_ns / 100);
entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
drm_dbg_kms(&dev_priv->drm,
@@ -2596,7 +2595,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
method2 = ilk_wm_method2(crtc_state->pixel_rate,
crtc_state->hw.pipe_mode.crtc_htotal,
- drm_rect_width(&plane_state->uapi.dst),
+ drm_rect_width(&plane_state->uapi.src) >> 16,
cpp, mem_value);
return min(method1, method2);
@@ -2624,7 +2623,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
method2 = ilk_wm_method2(crtc_state->pixel_rate,
crtc_state->hw.pipe_mode.crtc_htotal,
- drm_rect_width(&plane_state->uapi.dst),
+ drm_rect_width(&plane_state->uapi.src) >> 16,
cpp, mem_value);
return min(method1, method2);
}
--
2.32.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915: Use single_enabled_crtc() in i9xx_update_wm()
2021-12-09 14:43 [Intel-gfx] [PATCH 1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations Ville Syrjala
2021-12-09 14:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Use the correct plane source width in watermark calculations Ville Syrjala
@ 2021-12-09 14:43 ` Ville Syrjala
2021-12-10 3:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Ville Syrjala @ 2021-12-09 14:43 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Replace the ad-hoc single_enabled_crtc() thing in i9xx_update_wm()
with the real thing, just like we do in the other legacy wm functions.
We can also nuke the extra 'enabled' variable.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 26 +++++++++++---------------
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index baa5f9fdf17c..26b81268d948 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2355,7 +2355,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
int cwm, srwm = 1;
int fifo_size;
int planea_wm, planeb_wm;
- struct intel_crtc *crtc, *enabled = NULL;
+ struct intel_crtc *crtc;
if (IS_I945GM(dev_priv))
wm_info = &i945_wm_info;
@@ -2382,7 +2382,6 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
planea_wm = intel_calculate_wm(crtc->config->pixel_rate,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
- enabled = crtc;
} else {
planea_wm = fifo_size - wm_info->guard_size;
if (planea_wm > (long)wm_info->max_wm)
@@ -2410,10 +2409,6 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
planeb_wm = intel_calculate_wm(crtc->config->pixel_rate,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
- if (enabled == NULL)
- enabled = crtc;
- else
- enabled = NULL;
} else {
planeb_wm = fifo_size - wm_info->guard_size;
if (planeb_wm > (long)wm_info->max_wm)
@@ -2423,14 +2418,15 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm,
"FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
- if (IS_I915GM(dev_priv) && enabled) {
+ crtc = single_enabled_crtc(dev_priv);
+ if (IS_I915GM(dev_priv) && crtc) {
struct drm_i915_gem_object *obj;
- obj = intel_fb_obj(enabled->base.primary->state->fb);
+ obj = intel_fb_obj(crtc->base.primary->state->fb);
/* self-refresh seems busted with untiled */
if (!i915_gem_object_is_tiled(obj))
- enabled = NULL;
+ crtc = NULL;
}
/*
@@ -2442,16 +2438,16 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
intel_set_memory_cxsr(dev_priv, false);
/* Calc sr entries for one plane configs */
- if (HAS_FW_BLC(dev_priv) && enabled) {
+ if (HAS_FW_BLC(dev_priv) && crtc) {
/* self-refresh has much higher latency */
static const int sr_latency_ns = 6000;
const struct drm_display_mode *pipe_mode =
- &enabled->config->hw.pipe_mode;
+ &crtc->config->hw.pipe_mode;
const struct drm_framebuffer *fb =
- enabled->base.primary->state->fb;
- int pixel_rate = enabled->config->pixel_rate;
+ crtc->base.primary->state->fb;
+ int pixel_rate = crtc->config->pixel_rate;
int htotal = pipe_mode->crtc_htotal;
- int width = drm_rect_width(&enabled->base.primary->state->src) >> 16;
+ int width = drm_rect_width(&crtc->base.primary->state->src) >> 16;
int cpp;
int entries;
@@ -2490,7 +2486,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
intel_uncore_write(&dev_priv->uncore, FW_BLC2, fwater_hi);
- if (enabled)
+ if (crtc)
intel_set_memory_cxsr(dev_priv, true);
}
--
2.32.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations
2021-12-09 14:43 [Intel-gfx] [PATCH 1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations Ville Syrjala
2021-12-09 14:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Use the correct plane source width in watermark calculations Ville Syrjala
2021-12-09 14:43 ` [Intel-gfx] [PATCH 3/3] drm/i915: Use single_enabled_crtc() in i9xx_update_wm() Ville Syrjala
@ 2021-12-10 3:23 ` Patchwork
2021-12-10 12:37 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-01-26 14:50 ` [Intel-gfx] [PATCH 1/3] " Jani Nikula
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-12-10 3:23 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6039 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations
URL : https://patchwork.freedesktop.org/series/97808/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10984 -> Patchwork_21804
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/index.html
Participating hosts (44 -> 34)
------------------------------
Additional (1): fi-tgl-u2
Missing (11): fi-ilk-m540 bat-dg1-6 fi-hsw-4200u fi-icl-u2 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 bat-jsl-2 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_21804 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: NOTRUN -> [INCOMPLETE][1] ([i915#4006])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [PASS][2] -> [FAIL][3] ([i915#4547])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][4] ([i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/fi-tgl-u2/igt@gem_lmem_swapping@verify-random.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-u2: NOTRUN -> [SKIP][6] ([fdo#109284] / [fdo#111827]) +8 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/fi-tgl-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][7] ([i915#4103]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][8] ([fdo#109285])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#295]) +11 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][11] ([i915#3301])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/fi-tgl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][12] ([i915#3363] / [i915#4312])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/fi-skl-6600u/igt@runner@aborted.html
- fi-tgl-u2: NOTRUN -> [FAIL][13] ([i915#2722] / [i915#4312])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/fi-tgl-u2/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0:
- fi-glk-dsi: [DMESG-WARN][14] ([i915#2943]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/fi-glk-dsi/igt@gem_exec_suspend@basic-s0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/fi-glk-dsi/igt@gem_exec_suspend@basic-s0.html
- fi-tgl-1115g4: [FAIL][16] ([i915#1888]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2943]: https://gitlab.freedesktop.org/drm/intel/issues/2943
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#4006]: https://gitlab.freedesktop.org/drm/intel/issues/4006
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
Build changes
-------------
* Linux: CI_DRM_10984 -> Patchwork_21804
CI-20190529: 20190529
CI_DRM_10984: d7b5243a6417de5fc244d7dc45109f6835aa7c88 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6304: ef0df2fbe5847fe5c4426b8a86a0b101588d0586 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21804: 6875486e8e58c69cd8bd5415d88aea48a39b3ce9 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6875486e8e58 drm/i915: Use single_enabled_crtc() in i9xx_update_wm()
5c2106aa7c63 drm/i915: Use the correct plane source width in watermark calculations
1d3ec797d602 drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/index.html
[-- Attachment #2: Type: text/html, Size: 7033 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations
2021-12-09 14:43 [Intel-gfx] [PATCH 1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations Ville Syrjala
` (2 preceding siblings ...)
2021-12-10 3:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations Patchwork
@ 2021-12-10 12:37 ` Patchwork
2022-01-26 14:50 ` [Intel-gfx] [PATCH 1/3] " Jani Nikula
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-12-10 12:37 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30316 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations
URL : https://patchwork.freedesktop.org/series/97808/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10984_full -> Patchwork_21804_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_21804_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][1] -> [TIMEOUT][2] ([i915#3063] / [i915#3648])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-tglb1/igt@gem_eio@unwedge-stress.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-tglb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_capture@pi@vcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][3] ([i915#4547])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl8/igt@gem_exec_capture@pi@vcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2846])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-glk2/igt@gem_exec_fair@basic-deadline.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-glk5/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb5/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-tglb6/igt@gem_exec_fair@basic-pace@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-tglb8/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-glk2/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_params@no-vebox:
- shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271]) +31 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl6/igt@gem_exec_params@no-vebox.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][14] -> [SKIP][15] ([i915#2190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-tglb1/igt@gem_huc_copy@huc-copy.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl9/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_render_copy@y-tiled-to-vebox-linear:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#768])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb5/igt@gem_render_copy@y-tiled-to-vebox-linear.html
* igt@gen7_exec_parse@load-register-reg:
- shard-iclb: NOTRUN -> [SKIP][18] ([fdo#109289])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb5/igt@gen7_exec_parse@load-register-reg.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1436] / [i915#716])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-skl9/igt@gen9_exec_parse@allowed-single.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl10/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#109506] / [i915#2411])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-tglb2/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-skl: [PASS][22] -> [INCOMPLETE][23] ([i915#151])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-skl8/igt@i915_pm_rpm@system-suspend-modeset.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl8/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [PASS][24] -> [FAIL][25] ([i915#2521])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-0:
- shard-glk: [PASS][26] -> [DMESG-WARN][27] ([i915#118]) +3 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-glk1/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-glk8/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0:
- shard-glk: [PASS][28] -> [FAIL][29] ([i915#1888] / [i915#3653])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-glk1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-glk8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3777])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-kbl3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3777])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-apl1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][32] ([fdo#109278]) +7 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb5/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#109278] / [i915#3886]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb5/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3886]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl6/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@vga-edid-read:
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109284] / [fdo#111827]) +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb5/igt@kms_chamelium@vga-edid-read.html
* igt@kms_color@pipe-a-ctm-red-to-blue:
- shard-skl: [PASS][36] -> [DMESG-WARN][37] ([i915#1982])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-skl6/igt@kms_color@pipe-a-ctm-red-to-blue.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl6/igt@kms_color@pipe-a-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-a-ctm-0-5:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-apl1/igt@kms_color_chamelium@pipe-a-ctm-0-5.html
* igt@kms_color_chamelium@pipe-b-ctm-0-25:
- shard-skl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl9/igt@kms_color_chamelium@pipe-b-ctm-0-25.html
* igt@kms_color_chamelium@pipe-b-ctm-limited-range:
- shard-kbl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-kbl3/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html
* igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen:
- shard-iclb: NOTRUN -> [SKIP][41] ([fdo#109278] / [fdo#109279])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb5/igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][42] -> [DMESG-WARN][43] ([i915#180]) +2 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][44] -> [FAIL][45] ([i915#72])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-iclb: NOTRUN -> [SKIP][46] ([fdo#109274]) +2 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb5/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][47] -> [DMESG-WARN][48] ([i915#180]) +4 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271]) +27 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-msflip-blt:
- shard-iclb: NOTRUN -> [SKIP][50] ([fdo#109280]) +5 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-skl: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#533])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl6/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-kbl: NOTRUN -> [DMESG-WARN][52] ([i915#180]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][53] ([fdo#108145] / [i915#265])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][54] ([i915#265])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
- shard-kbl: NOTRUN -> [FAIL][55] ([i915#265])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-kbl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#658])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-kbl3/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-p010:
- shard-skl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#658])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl9/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][58] -> [SKIP][59] ([fdo#109441]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb4/igt@kms_psr@psr2_cursor_render.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109441])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb5/igt@kms_psr@psr2_sprite_blt.html
* igt@nouveau_crc@pipe-c-ctx-flip-detection:
- shard-iclb: NOTRUN -> [SKIP][61] ([i915#2530])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb5/igt@nouveau_crc@pipe-c-ctx-flip-detection.html
* igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
- shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271]) +32 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-apl1/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
* igt@prime_vgem@fence-write-hang:
- shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109295])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb5/igt@prime_vgem@fence-write-hang.html
* igt@sysfs_clients@fair-0:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#2994])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-apl1/igt@sysfs_clients@fair-0.html
- shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2994])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-kbl3/igt@sysfs_clients@fair-0.html
#### Possible fixes ####
* igt@feature_discovery@psr1:
- {shard-rkl}: [SKIP][66] ([i915#658]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-1/igt@feature_discovery@psr1.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-rkl-6/igt@feature_discovery@psr1.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [TIMEOUT][68] ([i915#3063]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-tglb2/igt@gem_eio@in-flight-contexts-10ms.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-tglb7/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [INCOMPLETE][70] ([i915#4547]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-skl1/igt@gem_exec_capture@pi@rcs0.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl8/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: [FAIL][72] ([i915#2842]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-glk3/igt@gem_exec_fair@basic-none@rcs0.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-glk5/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-kbl: [FAIL][74] ([i915#2842]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-kbl2/igt@gem_exec_fair@basic-none@vcs1.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-kbl2/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][76] ([i915#2842]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-apl1/igt@gem_exec_fair@basic-none@vecs0.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-apl1/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [SKIP][78] ([fdo#109271]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
- shard-iclb: [FAIL][80] ([i915#2842]) -> [PASS][81] +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-iclb5/igt@gem_exec_fair@basic-pace@vecs0.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb7/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@i915_pm_backlight@basic-brightness:
- {shard-rkl}: [SKIP][82] ([i915#3012]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-1/igt@i915_pm_backlight@basic-brightness.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-rkl-6/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {shard-rkl}: ([SKIP][84], [SKIP][85]) ([fdo#109308]) -> [PASS][86]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-4/igt@i915_pm_rpm@basic-pci-d3-state.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-1/igt@i915_pm_rpm@basic-pci-d3-state.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-rkl-6/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [INCOMPLETE][87] ([i915#151]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-skl4/igt@i915_pm_rpm@system-suspend-execbuf.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl9/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-glk: [DMESG-WARN][89] ([i915#118]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-glk6/igt@kms_big_fb@linear-32bpp-rotate-0.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-glk8/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_color@pipe-c-invalid-gamma-lut-sizes:
- {shard-rkl}: ([SKIP][91], [PASS][92]) ([i915#4070]) -> [PASS][93]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-2/igt@kms_color@pipe-c-invalid-gamma-lut-sizes.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-4/igt@kms_color@pipe-c-invalid-gamma-lut-sizes.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-rkl-4/igt@kms_color@pipe-c-invalid-gamma-lut-sizes.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen:
- {shard-rkl}: [SKIP][94] ([fdo#112022] / [i915#4070]) -> [PASS][95] +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-1/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][96] ([i915#180]) -> [PASS][97] +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge:
- {shard-rkl}: [SKIP][98] ([i915#1849] / [i915#4070]) -> [PASS][99] +1 similar issue
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-1/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html
* igt@kms_cursor_legacy@cursora-vs-flipa-legacy:
- {shard-rkl}: [SKIP][100] ([fdo#111825] / [i915#4070]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-1/igt@kms_cursor_legacy@cursora-vs-flipa-legacy.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipa-legacy.html
* igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled:
- {shard-rkl}: [SKIP][102] ([fdo#111314]) -> [PASS][103] +3 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-1/igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled.html
* igt@kms_fbcon_fbt@psr-suspend:
- {shard-rkl}: [SKIP][104] ([fdo#110189] / [i915#3955]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][106] ([i915#79]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [FAIL][108] ([i915#79]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [DMESG-WARN][110] ([i915#180]) -> [PASS][111] +2 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@flip-vs-suspend@c-edp1:
- shard-skl: [INCOMPLETE][112] ([i915#198]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-skl4/igt@kms_flip@flip-vs-suspend@c-edp1.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl6/igt@kms_flip@flip-vs-suspend@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-iclb: [SKIP][114] ([i915#3701]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
- {shard-rkl}: [SKIP][116] ([i915#1849]) -> [PASS][117] +4 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][118] ([i915#1188] / [i915#1888]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-skl9/igt@kms_hdr@bpc-switch.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl10/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-dpms:
- {shard-rkl}: ([SKIP][120], [SKIP][121]) ([i915#1845]) -> [PASS][122]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-4/igt@kms_hdr@bpc-switch-dpms.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-1/igt@kms_hdr@bpc-switch-dpms.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-rkl-6/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-b:
- {shard-rkl}: ([SKIP][123], [SKIP][124]) ([i915#1849] / [i915#4098]) -> [PASS][125] +1 similar issue
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-1/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-b.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-4/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-b.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-rkl-6/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][126] ([fdo#108145] / [i915#265]) -> [PASS][127] +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- {shard-rkl}: [SKIP][128] ([i915#3558] / [i915#4070]) -> [PASS][129] +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-1/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-rkl-6/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][130] ([fdo#109441]) -> [PASS][131] +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_psr@sprite_mmap_cpu:
- {shard-rkl}: [SKIP][132] ([i915#1072]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-1/igt@kms_psr@sprite_mmap_cpu.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-rkl-6/igt@kms_psr@sprite_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-glk: [FAIL][134] ([i915#31]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-glk9/igt@kms_setmode@basic.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-glk9/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][136] ([i915#180] / [i915#295]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-ts-continuation-modeset-hang:
- {shard-rkl}: [SKIP][138] ([i915#1845]) -> [PASS][139] +4 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-rkl-1/igt@kms_vblank@pipe-b-ts-continuation-modeset-hang.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-rkl-6/igt@kms_vblank@pipe-b-ts-continuation-modeset-hang.html
* igt@perf@polling:
- shard-skl: [FAIL][140] ([i915#1542]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-skl9/igt@perf@polling.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl10/igt@perf@polling.html
* igt@perf@polling-small-buf:
- shard-skl: [FAIL][142] ([i915#1722]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-skl10/igt@perf@polling-small-buf.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-skl8/igt@perf@polling-small-buf.html
#### Warnings ####
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][144] ([i915#2842]) -> [FAIL][145] ([i915#2849])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-kbl: [INCOMPLETE][146] ([i915#636]) -> [DMESG-WARN][147] ([i915#180])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-glk: [SKIP][148] ([fdo#109271] / [i915#1888]) -> [SKIP][149] ([fdo#109271])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-glk3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/shard-glk5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][150] ([i915#2920]) -> [SKIP][151] ([i915#658]) +2 similar issues
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10984/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwo
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21804/index.html
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* Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations
2021-12-09 14:43 [Intel-gfx] [PATCH 1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations Ville Syrjala
` (3 preceding siblings ...)
2021-12-10 12:37 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2022-01-26 14:50 ` Jani Nikula
4 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2022-01-26 14:50 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 09 Dec 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use pixel_rate rather than crtc_clock in the watermark calculations.
> These are actually identical on gmch platforms for now since
> we don't adjust the pixel rate based on pfit downscaling. But
> pixel_rate is the thing we are actually interested here so use
> the proper name for it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
On the series,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 52 ++++++++++++++-------------------
> 1 file changed, 22 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 434b1f8b7fe3..b5d5b625a321 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -915,15 +915,13 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
>
> crtc = single_enabled_crtc(dev_priv);
> if (crtc) {
> - const struct drm_display_mode *pipe_mode =
> - &crtc->config->hw.pipe_mode;
> const struct drm_framebuffer *fb =
> crtc->base.primary->state->fb;
> + int pixel_rate = crtc->config->pixel_rate;
> int cpp = fb->format->cpp[0];
> - int clock = pipe_mode->crtc_clock;
>
> /* Display SR */
> - wm = intel_calculate_wm(clock, &pnv_display_wm,
> + wm = intel_calculate_wm(pixel_rate, &pnv_display_wm,
> pnv_display_wm.fifo_size,
> cpp, latency->display_sr);
> reg = intel_uncore_read(&dev_priv->uncore, DSPFW1);
> @@ -933,7 +931,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
> drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
>
> /* cursor SR */
> - wm = intel_calculate_wm(clock, &pnv_cursor_wm,
> + wm = intel_calculate_wm(pixel_rate, &pnv_cursor_wm,
> pnv_display_wm.fifo_size,
> 4, latency->cursor_sr);
> reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> @@ -942,7 +940,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
> intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
>
> /* Display HPLL off SR */
> - wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
> + wm = intel_calculate_wm(pixel_rate, &pnv_display_hplloff_wm,
> pnv_display_hplloff_wm.fifo_size,
> cpp, latency->display_hpll_disable);
> reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> @@ -951,7 +949,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
> intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
>
> /* cursor HPLL off SR */
> - wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
> + wm = intel_calculate_wm(pixel_rate, &pnv_cursor_hplloff_wm,
> pnv_display_hplloff_wm.fifo_size,
> 4, latency->cursor_hpll_disable);
> reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> @@ -1154,7 +1152,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
> const struct drm_display_mode *pipe_mode =
> &crtc_state->hw.pipe_mode;
> unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
> - unsigned int clock, htotal, cpp, width, wm;
> + unsigned int pixel_rate, htotal, cpp, width, wm;
>
> if (latency == 0)
> return USHRT_MAX;
> @@ -1175,21 +1173,21 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
> level != G4X_WM_LEVEL_NORMAL)
> cpp = max(cpp, 4u);
>
> - clock = pipe_mode->crtc_clock;
> + pixel_rate = crtc_state->pixel_rate;
> htotal = pipe_mode->crtc_htotal;
>
> width = drm_rect_width(&plane_state->uapi.dst);
>
> if (plane->id == PLANE_CURSOR) {
> - wm = intel_wm_method2(clock, htotal, width, cpp, latency);
> + wm = intel_wm_method2(pixel_rate, htotal, width, cpp, latency);
> } else if (plane->id == PLANE_PRIMARY &&
> level == G4X_WM_LEVEL_NORMAL) {
> - wm = intel_wm_method1(clock, cpp, latency);
> + wm = intel_wm_method1(pixel_rate, cpp, latency);
> } else {
> unsigned int small, large;
>
> - small = intel_wm_method1(clock, cpp, latency);
> - large = intel_wm_method2(clock, htotal, width, cpp, latency);
> + small = intel_wm_method1(pixel_rate, cpp, latency);
> + large = intel_wm_method2(pixel_rate, htotal, width, cpp, latency);
>
> wm = min(small, large);
> }
> @@ -1674,7 +1672,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> const struct drm_display_mode *pipe_mode =
> &crtc_state->hw.pipe_mode;
> - unsigned int clock, htotal, cpp, width, wm;
> + unsigned int pixel_rate, htotal, cpp, width, wm;
>
> if (dev_priv->wm.pri_latency[level] == 0)
> return USHRT_MAX;
> @@ -1683,7 +1681,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
> return 0;
>
> cpp = plane_state->hw.fb->format->cpp[0];
> - clock = pipe_mode->crtc_clock;
> + pixel_rate = crtc_state->pixel_rate;
> htotal = pipe_mode->crtc_htotal;
> width = crtc_state->pipe_src_w;
>
> @@ -1696,7 +1694,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
> */
> wm = 63;
> } else {
> - wm = vlv_wm_method2(clock, htotal, width, cpp,
> + wm = vlv_wm_method2(pixel_rate, htotal, width, cpp,
> dev_priv->wm.pri_latency[level] * 10);
> }
>
> @@ -2277,13 +2275,13 @@ static void i965_update_wm(struct drm_i915_private *dev_priv)
> &crtc->config->hw.pipe_mode;
> const struct drm_framebuffer *fb =
> crtc->base.primary->state->fb;
> - int clock = pipe_mode->crtc_clock;
> + int pixel_rate = crtc->config->pixel_rate;
> int htotal = pipe_mode->crtc_htotal;
> int hdisplay = crtc->config->pipe_src_w;
> int cpp = fb->format->cpp[0];
> int entries;
>
> - entries = intel_wm_method2(clock, htotal,
> + entries = intel_wm_method2(pixel_rate, htotal,
> hdisplay, cpp, sr_latency_ns / 100);
> entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
> srwm = I965_FIFO_SIZE - entries;
> @@ -2294,7 +2292,7 @@ static void i965_update_wm(struct drm_i915_private *dev_priv)
> "self-refresh entries: %d, wm: %d\n",
> entries, srwm);
>
> - entries = intel_wm_method2(clock, htotal,
> + entries = intel_wm_method2(pixel_rate, htotal,
> crtc->base.cursor->state->crtc_w, 4,
> sr_latency_ns / 100);
> entries = DIV_ROUND_UP(entries,
> @@ -2373,8 +2371,6 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
> fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
> crtc = intel_crtc_for_plane(dev_priv, PLANE_A);
> if (intel_crtc_active(crtc)) {
> - const struct drm_display_mode *pipe_mode =
> - &crtc->config->hw.pipe_mode;
> const struct drm_framebuffer *fb =
> crtc->base.primary->state->fb;
> int cpp;
> @@ -2384,7 +2380,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
> else
> cpp = fb->format->cpp[0];
>
> - planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
> + planea_wm = intel_calculate_wm(crtc->config->pixel_rate,
> wm_info, fifo_size, cpp,
> pessimal_latency_ns);
> enabled = crtc;
> @@ -2403,8 +2399,6 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
> fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
> crtc = intel_crtc_for_plane(dev_priv, PLANE_B);
> if (intel_crtc_active(crtc)) {
> - const struct drm_display_mode *pipe_mode =
> - &crtc->config->hw.pipe_mode;
> const struct drm_framebuffer *fb =
> crtc->base.primary->state->fb;
> int cpp;
> @@ -2414,7 +2408,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
> else
> cpp = fb->format->cpp[0];
>
> - planeb_wm = intel_calculate_wm(pipe_mode->crtc_clock,
> + planeb_wm = intel_calculate_wm(crtc->config->pixel_rate,
> wm_info, fifo_size, cpp,
> pessimal_latency_ns);
> if (enabled == NULL)
> @@ -2456,7 +2450,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
> &enabled->config->hw.pipe_mode;
> const struct drm_framebuffer *fb =
> enabled->base.primary->state->fb;
> - int clock = pipe_mode->crtc_clock;
> + int pixel_rate = enabled->config->pixel_rate;
> int htotal = pipe_mode->crtc_htotal;
> int hdisplay = enabled->config->pipe_src_w;
> int cpp;
> @@ -2467,7 +2461,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
> else
> cpp = fb->format->cpp[0];
>
> - entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
> + entries = intel_wm_method2(pixel_rate, htotal, hdisplay, cpp,
> sr_latency_ns / 100);
> entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
> drm_dbg_kms(&dev_priv->drm,
> @@ -2504,7 +2498,6 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
> static void i845_update_wm(struct drm_i915_private *dev_priv)
> {
> struct intel_crtc *crtc;
> - const struct drm_display_mode *pipe_mode;
> u32 fwater_lo;
> int planea_wm;
>
> @@ -2512,8 +2505,7 @@ static void i845_update_wm(struct drm_i915_private *dev_priv)
> if (crtc == NULL)
> return;
>
> - pipe_mode = &crtc->config->hw.pipe_mode;
> - planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
> + planea_wm = intel_calculate_wm(crtc->config->pixel_rate,
> &i845_wm_info,
> i845_get_fifo_size(dev_priv, PLANE_A),
> 4, pessimal_latency_ns);
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-01-26 14:51 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-09 14:43 [Intel-gfx] [PATCH 1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations Ville Syrjala
2021-12-09 14:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Use the correct plane source width in watermark calculations Ville Syrjala
2021-12-09 14:43 ` [Intel-gfx] [PATCH 3/3] drm/i915: Use single_enabled_crtc() in i9xx_update_wm() Ville Syrjala
2021-12-10 3:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations Patchwork
2021-12-10 12:37 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-01-26 14:50 ` [Intel-gfx] [PATCH 1/3] " Jani Nikula
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