* [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2020-11-23 18:26 Imre Deak
2020-11-23 18:26 ` [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Clear Color support for TGL Render Decompression Imre Deak
` (7 more replies)
0 siblings, 8 replies; 31+ messages in thread
From: Imre Deak @ 2020-11-23 18:26 UTC (permalink / raw)
To: intel-gfx
Cc: Nanley Chery, Rafael Antognolli, Dhinakaran Pandiyan, Kalyan Kondapally
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Gen12 display can decompress surfaces compressed by render engine with
Clear Color, add a new modifier as the driver needs to know the surface
was compressed by render engine.
V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
v4: Fix trailing whitespaces
v5: Explain Clear Color in the documentation.
v6: Documentation Nitpicks(Nanley)
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index ca48ed0e6bc1..0a1b2c4c4bee 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -527,6 +527,25 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
+ * compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates
+ * the converted clear color of size 64 bits. The first 32 bits store the Lower
+ * Converted Clear Color value and the next 32 bits store the Higher Converted
+ * Clear Color value when applicable. The Converted Clear Color values are
+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable
+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.25.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
2020-11-23 18:26 [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color Imre Deak
@ 2020-11-23 18:26 ` Imre Deak
2020-11-27 9:27 ` Kahola, Mika
2020-12-01 12:34 ` Chris Wilson
2020-11-23 20:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color Patchwork
` (6 subsequent siblings)
7 siblings, 2 replies; 31+ messages in thread
From: Imre Deak @ 2020-11-23 18:26 UTC (permalink / raw)
To: intel-gfx
Cc: Nanley G Chery, Rafael Antognolli, Chris Wilson,
Dhinakaran Pandiyan, Ville Syrjala, Shashank Sharma
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.
v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
plane config(Matt). Fix Lookup error.
v3: Fix the panic while running kms_cube
v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
v5: Fix typos and wrap comments(Matt)
v6:
- Use format block descriptors to get the subsampling calculations for
the CCS surface right.
- Use helpers to convert between main and CCS surfaces.
- Prevent coordinate checks for the CC surface.
- Simplify reading CC value from surface map, add description of CC val
layout.
- Remove redundant ccval variable from skl_program_plane().
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjala <ville.syrjala@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com> (v5)
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 72 +++++++++++++++++--
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_sprite.c | 10 ++-
drivers/gpu/drm/i915/i915_reg.h | 9 +++
4 files changed, 89 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 595183f7b60f..f190f6f4cdf5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1968,8 +1968,8 @@ static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
static bool is_gen12_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
-
}
static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
@@ -1977,6 +1977,12 @@ static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
}
+static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
+{
+ return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
+ plane == 2;
+}
+
static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
{
if (is_ccs_modifier(fb->modifier))
@@ -1998,6 +2004,9 @@ static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
ccs_plane < fb->format->num_planes / 2);
+ if (is_gen12_ccs_cc_plane(fb, ccs_plane))
+ return 0;
+
return ccs_plane - fb->format->num_planes / 2;
}
@@ -2048,6 +2057,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 128;
fallthrough;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
if (is_ccs_plane(fb, color_plane))
return 64;
@@ -2204,6 +2214,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
return intel_tile_row_size(fb, color_plane);
fallthrough;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2608,6 +2619,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return I915_TILING_Y;
default:
@@ -2686,6 +2698,25 @@ static const struct drm_format_info gen12_ccs_formats[] = {
.hsub = 2, .vsub = 2, .is_yuv = true },
};
+/*
+ * Same as gen12_ccs_formats[] above, but with additional surface used
+ * to pass Clear Color information in plane 2 with 64 bits of data.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2714,6 +2745,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return lookup_format_info(gen12_ccs_cc_formats,
+ ARRAY_SIZE(gen12_ccs_cc_formats),
+ cmd->pixel_format);
default:
return NULL;
}
@@ -2722,6 +2757,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
@@ -2940,7 +2976,7 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
int ccs_x, ccs_y;
int main_x, main_y;
- if (!is_ccs_plane(fb, ccs_plane))
+ if (!is_ccs_plane(fb, ccs_plane) || is_gen12_ccs_cc_plane(fb, ccs_plane))
return 0;
intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
@@ -3067,6 +3103,18 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int x, y;
int ret;
+ /*
+ * Plane 2 of Render Compression with Clear Color fb modifier
+ * is consumed by the driver and not passed to DE. Skip the
+ * arithmetic related to alignment and offset calculation.
+ */
+ if (is_gen12_ccs_cc_plane(fb, i)) {
+ if (IS_ALIGNED(fb->offsets[i], PAGE_SIZE))
+ continue;
+ else
+ return -EINVAL;
+ }
+
cpp = fb->format->cpp[i];
intel_fb_plane_dims(&width, &height, fb, i);
@@ -3991,7 +4039,8 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
int hsub, vsub;
int x, y;
- if (!is_ccs_plane(fb, ccs_plane))
+ if (!is_ccs_plane(fb, ccs_plane) ||
+ is_gen12_ccs_cc_plane(fb, ccs_plane))
continue;
intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
@@ -4647,6 +4696,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return PLANE_CTL_TILED_Y |
@@ -16647,6 +16697,20 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
plane_state->vma = vma;
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+ void *map = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
+ fb->offsets[2] >> PAGE_SHIFT));
+
+ /*
+ * The layout of the fast clear color value expected by HW:
+ * - 4 x 4 bytes per-channel value (in surface type specific float/int format)
+ * - 8 bytes native color value used by the display (converted/written by GPU during
+ * a fast clear operation using the above per-channel values)
+ */
+ plane_state->ccval = *(u64 *)(map + 16);
+ kunmap_atomic(map);
+ }
+
return 0;
}
@@ -17997,7 +18061,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
goto err;
}
- if (is_gen12_ccs_plane(fb, i)) {
+ if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
if (fb->pitches[i] != ccs_aux_stride) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ce82d654d0f2..a3f4b945a306 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -604,6 +604,9 @@ struct intel_plane_state {
u32 planar_slave;
struct drm_intel_sprite_colorkey ckey;
+
+ /* Clear Color Value */
+ u64 ccval;
};
struct intel_initial_plane_config {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 019a2d6d807a..2dc699e75816 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -851,6 +851,10 @@ skl_program_plane(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ intel_uncore_write64_fw(&dev_priv->uncore,
+ PLANE_CC_VAL(pipe, plane_id), plane_state->ccval);
+
skl_write_plane_wm(plane, crtc_state);
intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
@@ -2350,7 +2354,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
drm_dbg_kms(&dev_priv->drm,
"Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
@@ -2840,6 +2845,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2848,6 +2854,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -3038,6 +3045,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
break;
default:
return false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5375b219cc3b..edabb55d1586 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7070,6 +7070,8 @@ enum {
#define _PLANE_KEYMAX_1_A 0x701a0
#define _PLANE_KEYMAX_2_A 0x702a0
#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
+#define _PLANE_CC_VAL_1_A 0x701b4
+#define _PLANE_CC_VAL_2_A 0x702b4
#define _PLANE_AUX_DIST_1_A 0x701c0
#define _PLANE_AUX_DIST_2_A 0x702c0
#define _PLANE_AUX_OFFSET_1_A 0x701c4
@@ -7111,6 +7113,13 @@ enum {
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
#define _PLANE_NV12_BUF_CFG_2_A 0x70378
+#define _PLANE_CC_VAL_1_B 0x711b4
+#define _PLANE_CC_VAL_2_B 0x712b4
+#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
+#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
+
/* Input CSC Register Definitions */
#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-11-23 18:26 [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color Imre Deak
2020-11-23 18:26 ` [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Clear Color support for TGL Render Decompression Imre Deak
@ 2020-11-23 20:54 ` Patchwork
2020-11-23 20:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (5 subsequent siblings)
7 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2020-11-23 20:54 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
URL : https://patchwork.freedesktop.org/series/84183/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a3b4d1336125 drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
0dba847db9d2 drm/i915/tgl: Add Clear Color support for TGL Render Decompression
-:304: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#304: FILE: drivers/gpu/drm/i915/i915_reg.h:7120:
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
total: 0 errors, 0 warnings, 1 checks, 233 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-11-23 18:26 [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color Imre Deak
2020-11-23 18:26 ` [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Clear Color support for TGL Render Decompression Imre Deak
2020-11-23 20:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color Patchwork
@ 2020-11-23 20:56 ` Patchwork
2020-11-23 21:24 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (4 subsequent siblings)
7 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2020-11-23 20:56 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
URL : https://patchwork.freedesktop.org/series/84183/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1398:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1398:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1398:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1399:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1399:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1399:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1458:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1458:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1458:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:268:16: error: incompatible types in comparison expression (different type sizes):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:268:16: unsigned long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:268:16: unsigned long long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:274:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:274:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:274:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:330:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:330:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:330:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c:142:1: warning: no newline at end of file
+drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h:92:56: error: marked inline, but without a definition
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: st
_______________________________________________
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^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-11-23 18:26 [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color Imre Deak
` (2 preceding siblings ...)
2020-11-23 20:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-11-23 21:24 ` Patchwork
2020-11-24 15:12 ` Imre Deak
2020-11-24 17:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
7 siblings, 1 reply; 31+ messages in thread
From: Patchwork @ 2020-11-23 21:24 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 6129 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
URL : https://patchwork.freedesktop.org/series/84183/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9378 -> Patchwork_18961
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18961 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18961, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18961:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_fence@basic-await@rcs0:
- fi-skl-lmem: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-skl-lmem/igt@gem_exec_fence@basic-await@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-skl-lmem/igt@gem_exec_fence@basic-await@rcs0.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
New tests
---------
New tests have been introduced between CI_DRM_9378 and Patchwork_18961:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18961 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_busy@basic@flip:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@kms_busy@basic@flip.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
#### Possible fixes ####
* igt@kms_busy@basic@modeset:
- fi-tgl-y: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@kms_busy@basic@modeset.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@kms_busy@basic@modeset.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- {fi-kbl-7560u}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@prime_vgem@basic-write:
- fi-tgl-y: [DMESG-WARN][19] ([i915#402]) -> [PASS][20] +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@prime_vgem@basic-write.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@prime_vgem@basic-write.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (44 -> 40)
------------------------------
Missing (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_9378 -> Patchwork_18961
CI-20190529: 20190529
CI_DRM_9378: efc7f880143d6fe75922ad393045665c8ea60f57 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5868: 36b5fc05c30dbfd9242069fd6e51ebb419b386bc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18961: 0dba847db9d24c6d2d706379ac2f842b8f4a6bdb @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0dba847db9d2 drm/i915/tgl: Add Clear Color support for TGL Render Decompression
a3b4d1336125 drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/index.html
[-- Attachment #1.2: Type: text/html, Size: 7447 bytes --]
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_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-11-23 21:24 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2020-11-24 15:12 ` Imre Deak
2020-11-24 17:15 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 31+ messages in thread
From: Imre Deak @ 2020-11-24 15:12 UTC (permalink / raw)
To: intel-gfx, Lakshminarayana Vudum
Hi,
On Mon, Nov 23, 2020 at 09:24:31PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
> URL : https://patchwork.freedesktop.org/series/84183/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9378 -> Patchwork_18961
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_18961 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_18961, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/index.html
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_18961:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@gem_exec_fence@basic-await@rcs0:
> - fi-skl-lmem: [PASS][1] -> [INCOMPLETE][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-skl-lmem/igt@gem_exec_fence@basic-await@rcs0.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-skl-lmem/igt@gem_exec_fence@basic-await@rcs0.html
>
> * igt@kms_chamelium@common-hpd-after-suspend:
> - fi-kbl-7500u: [PASS][3] -> [FAIL][4]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
the patchset adds a new framebuffer modifier used only on TGL, so the
above two failures happen on unaffected platforms.
>
>
> New tests
> ---------
>
> New tests have been introduced between CI_DRM_9378 and Patchwork_18961:
>
> ### New CI tests (1) ###
>
> * boot:
> - Statuses : 40 pass(s)
> - Exec time: [0.0] s
>
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_18961 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@kms_busy@basic@flip:
> - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@kms_busy@basic@flip.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@kms_busy@basic@flip.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
> - fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
>
> * igt@prime_self_import@basic-with_one_bo_two_files:
> - fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +1 similar issue
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
>
>
> #### Possible fixes ####
>
> * igt@kms_busy@basic@modeset:
> - fi-tgl-y: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1 similar issue
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@kms_busy@basic@modeset.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@kms_busy@basic@modeset.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
> - fi-byt-j1900: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
> - {fi-kbl-7560u}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
>
> * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
> - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
>
> * igt@prime_vgem@basic-write:
> - fi-tgl-y: [DMESG-WARN][19] ([i915#402]) -> [PASS][20] +1 similar issue
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@prime_vgem@basic-write.html
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@prime_vgem@basic-write.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
> [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
>
>
> Participating hosts (44 -> 40)
> ------------------------------
>
> Missing (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_9378 -> Patchwork_18961
>
> CI-20190529: 20190529
> CI_DRM_9378: efc7f880143d6fe75922ad393045665c8ea60f57 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5868: 36b5fc05c30dbfd9242069fd6e51ebb419b386bc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_18961: 0dba847db9d24c6d2d706379ac2f842b8f4a6bdb @ git://anongit.freedesktop.org/gfx-ci/linux
>
>
> == Linux commits ==
>
> 0dba847db9d2 drm/i915/tgl: Add Clear Color support for TGL Render Decompression
> a3b4d1336125 drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-11-23 18:26 [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color Imre Deak
` (3 preceding siblings ...)
2020-11-23 21:24 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2020-11-24 17:12 ` Patchwork
2020-11-24 21:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2020-11-24 17:12 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5813 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
URL : https://patchwork.freedesktop.org/series/84183/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9378 -> Patchwork_18961
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/index.html
New tests
---------
New tests have been introduced between CI_DRM_9378 and Patchwork_18961:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18961 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fence@basic-await@rcs0:
- fi-skl-lmem: [PASS][1] -> [INCOMPLETE][2] ([i915#2708])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-skl-lmem/igt@gem_exec_fence@basic-await@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-skl-lmem/igt@gem_exec_fence@basic-await@rcs0.html
* igt@kms_busy@basic@flip:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@kms_busy@basic@flip.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@kms_busy@basic@flip.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([i915#2128])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
#### Possible fixes ####
* igt@kms_busy@basic@modeset:
- fi-tgl-y: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@kms_busy@basic@modeset.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@kms_busy@basic@modeset.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- {fi-kbl-7560u}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@prime_vgem@basic-write:
- fi-tgl-y: [DMESG-WARN][19] ([i915#402]) -> [PASS][20] +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@prime_vgem@basic-write.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@prime_vgem@basic-write.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2128]: https://gitlab.freedesktop.org/drm/intel/issues/2128
[i915#2708]: https://gitlab.freedesktop.org/drm/intel/issues/2708
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (44 -> 40)
------------------------------
Missing (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_9378 -> Patchwork_18961
CI-20190529: 20190529
CI_DRM_9378: efc7f880143d6fe75922ad393045665c8ea60f57 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5868: 36b5fc05c30dbfd9242069fd6e51ebb419b386bc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18961: 0dba847db9d24c6d2d706379ac2f842b8f4a6bdb @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0dba847db9d2 drm/i915/tgl: Add Clear Color support for TGL Render Decompression
a3b4d1336125 drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/index.html
[-- Attachment #1.2: Type: text/html, Size: 7107 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-11-24 15:12 ` Imre Deak
@ 2020-11-24 17:15 ` Vudum, Lakshminarayana
0 siblings, 0 replies; 31+ messages in thread
From: Vudum, Lakshminarayana @ 2020-11-24 17:15 UTC (permalink / raw)
To: Deak, Imre, intel-gfx
Re-reported.
-----Original Message-----
From: Imre Deak <imre.deak@intel.com>
Sent: Tuesday, November 24, 2020 7:13 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
Hi,
On Mon, Nov 23, 2020 at 09:24:31PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
> URL : https://patchwork.freedesktop.org/series/84183/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9378 -> Patchwork_18961
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_18961 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_18961, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/index.html
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_18961:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@gem_exec_fence@basic-await@rcs0:
> - fi-skl-lmem: [PASS][1] -> [INCOMPLETE][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-skl-lmem/igt@gem_exec_fence@basic-await@rcs0.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-skl-lmem/i
> gt@gem_exec_fence@basic-await@rcs0.html
>
> * igt@kms_chamelium@common-hpd-after-suspend:
> - fi-kbl-7500u: [PASS][3] -> [FAIL][4]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
> [4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-kbl-7500u/
> igt@kms_chamelium@common-hpd-after-suspend.html
the patchset adds a new framebuffer modifier used only on TGL, so the above two failures happen on unaffected platforms.
>
>
> New tests
> ---------
>
> New tests have been introduced between CI_DRM_9378 and Patchwork_18961:
>
> ### New CI tests (1) ###
>
> * boot:
> - Statuses : 40 pass(s)
> - Exec time: [0.0] s
>
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_18961 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@kms_busy@basic@flip:
> - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@kms_busy@basic@flip.html
> [6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@
> kms_busy@basic@flip.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
> - fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
> [8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-icl-u2/igt
> @kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
>
> * igt@prime_self_import@basic-with_one_bo_two_files:
> - fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +1 similar issue
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
> [10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@
> prime_self_import@basic-with_one_bo_two_files.html
>
>
> #### Possible fixes ####
>
> * igt@kms_busy@basic@modeset:
> - fi-tgl-y: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1 similar issue
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@kms_busy@basic@modeset.html
> [12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@
> kms_busy@basic@modeset.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
> - fi-byt-j1900: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
> - {fi-kbl-7560u}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
> [16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-kbl-7560u/
> igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
>
> * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
> - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
> [18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-icl-u2/igt
> @kms_cursor_legacy@basic-flip-after-cursor-legacy.html
>
> * igt@prime_vgem@basic-write:
> - fi-tgl-y: [DMESG-WARN][19] ([i915#402]) -> [PASS][20] +1 similar issue
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/fi-tgl-y/igt@prime_vgem@basic-write.html
> [20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/fi-tgl-y/igt@
> prime_vgem@basic-write.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
> [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
>
>
> Participating hosts (44 -> 40)
> ------------------------------
>
> Missing (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_9378 -> Patchwork_18961
>
> CI-20190529: 20190529
> CI_DRM_9378: efc7f880143d6fe75922ad393045665c8ea60f57 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5868: 36b5fc05c30dbfd9242069fd6e51ebb419b386bc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_18961: 0dba847db9d24c6d2d706379ac2f842b8f4a6bdb @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> == Linux commits ==
>
> 0dba847db9d2 drm/i915/tgl: Add Clear Color support for TGL Render
> Decompression
> a3b4d1336125 drm/framebuffer: Format modifier for Intel Gen 12 render
> compression with Clear Color
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-11-23 18:26 [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color Imre Deak
` (4 preceding siblings ...)
2020-11-24 17:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-11-24 21:57 ` Patchwork
2020-11-26 8:24 ` [Intel-gfx] [PATCH 1/2] " Kahola, Mika
2020-11-27 14:31 ` Imre Deak
7 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2020-11-24 21:57 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 19344 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
URL : https://patchwork.freedesktop.org/series/84183/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9378_full -> Patchwork_18961_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18961_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_userptr_blits@vma-merge}:
- shard-snb: [FAIL][1] ([i915#1635]) -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-snb2/igt@gem_userptr_blits@vma-merge.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-snb6/igt@gem_userptr_blits@vma-merge.html
New tests
---------
New tests have been introduced between CI_DRM_9378_full and Patchwork_18961_full:
### New CI tests (1) ###
* boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18961_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-hsw: [PASS][3] -> [FAIL][4] ([i915#2389])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-hsw6/igt@gem_exec_reloc@basic-many-active@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-hsw5/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +16 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-skl2/igt@i915_module_load@reload-with-fault-injection.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl2/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][7] -> [FAIL][8] ([i915#454])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@fences-dpms:
- shard-hsw: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-hsw1/igt@i915_pm_rpm@fences-dpms.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-hsw1/igt@i915_pm_rpm@fences-dpms.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen:
- shard-skl: [PASS][11] -> [FAIL][12] ([i915#54]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#2346])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions:
- shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-tglb8/igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-tglb8/igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#2122]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
- shard-glk: [PASS][19] -> [FAIL][20] ([i915#49])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-glk5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-glk3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
- shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-iclb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-iclb8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#1188])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-skl5/igt@kms_hdr@bpc-switch-suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-glk: [PASS][25] -> [DMESG-WARN][26] ([i915#1982])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-glk4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-glk8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant:
- shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#1635] / [i915#1982]) +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-a:
- shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-kbl7/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-kbl7/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html
* igt@perf@short-reads:
- shard-hsw: [PASS][33] -> [FAIL][34] ([i915#51])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-hsw6/igt@perf@short-reads.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-hsw6/igt@perf@short-reads.html
#### Possible fixes ####
* igt@gem_exec_whisper@basic-contexts-all:
- shard-glk: [DMESG-WARN][35] ([i915#118] / [i915#95]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-glk4/igt@gem_exec_whisper@basic-contexts-all.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-glk8/igt@gem_exec_whisper@basic-contexts-all.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-hsw: [WARN][37] ([i915#1519]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-hsw2/igt@i915_pm_rc6_residency@rc6-fence.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-hsw1/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-270:
- shard-kbl: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-kbl4/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-kbl1/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-iclb: [INCOMPLETE][41] ([i915#1185] / [i915#2295]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-iclb3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-iclb7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen:
- shard-skl: [FAIL][43] ([i915#54]) -> [PASS][44] +4 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl9/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html
* igt@kms_cursor_edge_walk@pipe-b-128x128-right-edge:
- shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-skl2/igt@kms_cursor_edge_walk@pipe-b-128x128-right-edge.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl3/igt@kms_cursor_edge_walk@pipe-b-128x128-right-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- shard-skl: [FAIL][47] ([i915#2346]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-glk3/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible@ab-hdmi-a1-hdmi-a2.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-glk8/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-dp1:
- shard-apl: [DMESG-WARN][51] ([i915#1635] / [i915#1982]) -> [PASS][52] +3 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-apl2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-dp1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-apl2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2:
- shard-glk: [FAIL][53] ([i915#79]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-glk8/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-glk4/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [FAIL][55] ([i915#79]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [FAIL][57] ([i915#2122]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-tglb: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][63] ([fdo#108145] / [i915#265]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [DMESG-FAIL][65] ([fdo#108145] / [i915#1982]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-iclb4/igt@kms_psr@psr2_cursor_plane_move.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][69] -> [WARN][70] ([i915#1804])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [DMESG-WARN][71] ([i915#1982]) -> [DMESG-FAIL][72] ([i915#1982]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][73] ([fdo#109349]) -> [DMESG-WARN][74] ([i915#1226])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-iclb7/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@runner@aborted:
- shard-glk: ([FAIL][75], [FAIL][76], [FAIL][77]) ([i915#1814] / [i915#2295] / [i915#483] / [i915#86] / [k.org#202321]) -> ([FAIL][78], [FAIL][79]) ([i915#2295] / [i915#86] / [k.org#202321])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-glk3/igt@runner@aborted.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-glk8/igt@runner@aborted.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-glk9/igt@runner@aborted.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-glk6/igt@runner@aborted.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-glk8/igt@runner@aborted.html
- shard-skl: [FAIL][80] ([i915#2295] / [i915#483]) -> ([FAIL][81], [FAIL][82]) ([i915#1814] / [i915#2029] / [i915#2295])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9378/shard-skl3/igt@runner@aborted.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl3/igt@runner@aborted.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/shard-skl8/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#1519]: https://gitlab.freedesktop.org/drm/intel/issues/1519
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#86]: https://gitlab.freedesktop.org/drm/intel/issues/86
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9378 -> Patchwork_18961
CI-20190529: 20190529
CI_DRM_9378: efc7f880143d6fe75922ad393045665c8ea60f57 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5868: 36b5fc05c30dbfd9242069fd6e51ebb419b386bc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18961: 0dba847db9d24c6d2d706379ac2f842b8f4a6bdb @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18961/index.html
[-- Attachment #1.2: Type: text/html, Size: 23156 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-11-23 18:26 [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color Imre Deak
` (5 preceding siblings ...)
2020-11-24 21:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-11-26 8:24 ` Kahola, Mika
2020-11-27 14:31 ` Imre Deak
7 siblings, 0 replies; 31+ messages in thread
From: Kahola, Mika @ 2020-11-26 8:24 UTC (permalink / raw)
To: Deak, Imre, intel-gfx
Cc: Rafael Antognolli, Kondapally, Kalyan, Chery, Nanley G, Pandiyan,
Dhinakaran
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre
> Deak
> Sent: Monday, November 23, 2020 8:27 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Chery, Nanley G <nanley.g.chery@intel.com>; Rafael Antognolli
> <rafael.antognolli@intel.com>; Pandiyan, Dhinakaran
> <dhinakaran.pandiyan@intel.com>; Kondapally, Kalyan
> <kalyan.kondapally@intel.com>
> Subject: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel
> Gen 12 render compression with Clear Color
>
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> Gen12 display can decompress surfaces compressed by render engine with
> Clear Color, add a new modifier as the driver needs to know the surface was
> compressed by render engine.
>
> V2: Description changes as suggested by Rafael.
> V3: Mention the Clear Color size of 64 bits in the comments(DK)
> v4: Fix trailing whitespaces
> v5: Explain Clear Color in the documentation.
> v6: Documentation Nitpicks(Nanley)
>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Nanley Chery <nanley.g.chery@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h
> b/include/uapi/drm/drm_fourcc.h index ca48ed0e6bc1..0a1b2c4c4bee
> 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -527,6 +527,25 @@ extern "C" {
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> fourcc_mod_code(INTEL, 7)
>
> +/*
> + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> + * compression.
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS is
> +linear
> + * and at index 1. The clear color is stored at index 2, and the pitch
> +should
> + * be ignored. The clear color structure is 256 bits. The first 128
> +bits
> + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> +represented
> + * by 32 bits. The raw clear color is consumed by the 3d engine and
> +generates
> + * the converted clear color of size 64 bits. The first 32 bits store
> +the Lower
> + * Converted Clear Color value and the next 32 bits store the Higher
> +Converted
> + * Clear Color value when applicable. The Converted Clear Color values
> +are
> + * consumed by the DE. The last 64 bits are used to store Color Discard
> +Enable
> + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache
> +line
> + * corresponds to an area of 4x1 tiles in the main surface. The main
> +surface
> + * pitch is required to be a multiple of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> fourcc_mod_code(INTEL,
> +8)
> +
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> *
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
2020-11-23 18:26 ` [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Clear Color support for TGL Render Decompression Imre Deak
@ 2020-11-27 9:27 ` Kahola, Mika
2020-12-01 12:34 ` Chris Wilson
1 sibling, 0 replies; 31+ messages in thread
From: Kahola, Mika @ 2020-11-27 9:27 UTC (permalink / raw)
To: Deak, Imre, intel-gfx
Cc: Syrjala, Ville, Rafael Antognolli, Chris Wilson, Pandiyan,
Dhinakaran, Chery, Nanley G, Shashank Sharma
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre
> Deak
> Sent: Monday, November 23, 2020 8:27 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Chery, Nanley G <nanley.g.chery@intel.com>; Rafael Antognolli
> <rafael.antognolli@intel.com>; Chris Wilson <chris@chris-wilson.co.uk>;
> Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>; Syrjala, Ville
> <ville.syrjala@intel.com>; Shashank Sharma <shashank.sharma@intel.com>
> Subject: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Clear Color support for TGL
> Render Decompression
>
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> Render Decompression is supported with Y-Tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a ratio of
> 1:256. Additional Clear Color information is passed from the user-space
> through an offset in the GEM BO. Add a new modifier to identify and parse
> new Clear Color information and extend Gen12 render decompression
> functionality to the newly added modifier.
>
> v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> plane config(Matt). Fix Lookup error.
> v3: Fix the panic while running kms_cube
> v4: Add alignment check and reuse the comments for
> ge12_ccs_formats(Matt)
> v5: Fix typos and wrap comments(Matt)
> v6:
> - Use format block descriptors to get the subsampling calculations for
> the CCS surface right.
> - Use helpers to convert between main and CCS surfaces.
> - Prevent coordinate checks for the CC surface.
> - Simplify reading CC value from surface map, add description of CC val
> layout.
> - Remove redundant ccval variable from skl_program_plane().
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Ville Syrjala <ville.syrjala@intel.com>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> (v5)
Reviewed-by: Mika Kahola <mika.kahola@intel.com> (v6)
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 72 +++++++++++++++++--
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 10 ++-
> drivers/gpu/drm/i915/i915_reg.h | 9 +++
> 4 files changed, 89 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 595183f7b60f..f190f6f4cdf5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1968,8 +1968,8 @@ static bool is_ccs_plane(const struct
> drm_framebuffer *fb, int plane) static bool is_gen12_ccs_modifier(u64
> modifier) {
> return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> -
> }
>
> static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
> @@ -1977,6 +1977,12 @@ static bool is_gen12_ccs_plane(const struct
> drm_framebuffer *fb, int plane)
> return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb,
> plane); }
>
> +static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int
> +plane) {
> + return fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
> + plane == 2;
> +}
> +
> static bool is_aux_plane(const struct drm_framebuffer *fb, int plane) {
> if (is_ccs_modifier(fb->modifier))
> @@ -1998,6 +2004,9 @@ static int ccs_to_main_plane(const struct
> drm_framebuffer *fb, int ccs_plane)
> drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
> ccs_plane < fb->format->num_planes / 2);
>
> + if (is_gen12_ccs_cc_plane(fb, ccs_plane))
> + return 0;
> +
> return ccs_plane - fb->format->num_planes / 2; }
>
> @@ -2048,6 +2057,7 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
> return 128;
> fallthrough;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> if (is_ccs_plane(fb, color_plane))
> return 64;
> @@ -2204,6 +2214,7 @@ static unsigned int intel_surf_alignment(const
> struct drm_framebuffer *fb,
> return intel_tile_row_size(fb, color_plane);
> fallthrough;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return 16 * 1024;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -2608,6 +2619,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
> fb_modifier)
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> return I915_TILING_Y;
> default:
> @@ -2686,6 +2698,25 @@ static const struct drm_format_info
> gen12_ccs_formats[] = {
> .hsub = 2, .vsub = 2, .is_yuv = true }, };
>
> +/*
> + * Same as gen12_ccs_formats[] above, but with additional surface used
> + * to pass Clear Color information in plane 2 with 64 bits of data.
> + */
> +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1
> },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1
> },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1
> },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1
> },
> + .hsub = 1, .vsub = 1, .has_alpha = true }, };
> +
> static const struct drm_format_info *
> lookup_format_info(const struct drm_format_info formats[],
> int num_formats, u32 format)
> @@ -2714,6 +2745,10 @@ intel_get_format_info(const struct
> drm_mode_fb_cmd2 *cmd)
> return lookup_format_info(gen12_ccs_formats,
> ARRAY_SIZE(gen12_ccs_formats),
> cmd->pixel_format);
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> + return lookup_format_info(gen12_ccs_cc_formats,
> + ARRAY_SIZE(gen12_ccs_cc_formats),
> + cmd->pixel_format);
> default:
> return NULL;
> }
> @@ -2722,6 +2757,7 @@ intel_get_format_info(const struct
> drm_mode_fb_cmd2 *cmd) bool is_ccs_modifier(u64 modifier) {
> return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS; @@ -2940,7
> +2976,7 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int
> ccs_plane, int x, int y)
> int ccs_x, ccs_y;
> int main_x, main_y;
>
> - if (!is_ccs_plane(fb, ccs_plane))
> + if (!is_ccs_plane(fb, ccs_plane) || is_gen12_ccs_cc_plane(fb,
> +ccs_plane))
> return 0;
>
> intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height); @@ -3067,6
> +3103,18 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> int x, y;
> int ret;
>
> + /*
> + * Plane 2 of Render Compression with Clear Color fb
> modifier
> + * is consumed by the driver and not passed to DE. Skip the
> + * arithmetic related to alignment and offset calculation.
> + */
> + if (is_gen12_ccs_cc_plane(fb, i)) {
> + if (IS_ALIGNED(fb->offsets[i], PAGE_SIZE))
> + continue;
> + else
> + return -EINVAL;
> + }
> +
> cpp = fb->format->cpp[i];
> intel_fb_plane_dims(&width, &height, fb, i);
>
> @@ -3991,7 +4039,8 @@ static int skl_check_ccs_aux_surface(struct
> intel_plane_state *plane_state)
> int hsub, vsub;
> int x, y;
>
> - if (!is_ccs_plane(fb, ccs_plane))
> + if (!is_ccs_plane(fb, ccs_plane) ||
> + is_gen12_ccs_cc_plane(fb, ccs_plane))
> continue;
>
> intel_fb_plane_get_subsampling(&main_hsub, &main_vsub,
> fb, @@ -4647,6 +4696,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> case I915_FORMAT_MOD_Y_TILED:
> return PLANE_CTL_TILED_Y;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return PLANE_CTL_TILED_Y |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> return PLANE_CTL_TILED_Y |
> @@ -16647,6 +16697,20 @@ static int intel_plane_pin_fb(struct
> intel_plane_state *plane_state)
>
> plane_state->vma = vma;
>
> + if (fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> + void *map =
> kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
> + fb->offsets[2]
> >> PAGE_SHIFT));
> +
> + /*
> + * The layout of the fast clear color value expected by HW:
> + * - 4 x 4 bytes per-channel value (in surface type specific
> float/int format)
> + * - 8 bytes native color value used by the display
> (converted/written by GPU during
> + * a fast clear operation using the above per-channel values)
> + */
> + plane_state->ccval = *(u64 *)(map + 16);
> + kunmap_atomic(map);
> + }
> +
> return 0;
> }
>
> @@ -17997,7 +18061,7 @@ static int intel_framebuffer_init(struct
> intel_framebuffer *intel_fb,
> goto err;
> }
>
> - if (is_gen12_ccs_plane(fb, i)) {
> + if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb,
> i)) {
> int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
>
> if (fb->pitches[i] != ccs_aux_stride) { diff --git
> a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ce82d654d0f2..a3f4b945a306 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -604,6 +604,9 @@ struct intel_plane_state {
> u32 planar_slave;
>
> struct drm_intel_sprite_colorkey ckey;
> +
> + /* Clear Color Value */
> + u64 ccval;
> };
>
> struct intel_initial_plane_config {
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 019a2d6d807a..2dc699e75816 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -851,6 +851,10 @@ skl_program_plane(struct intel_plane *plane,
> if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> icl_program_input_csc(plane, crtc_state, plane_state);
>
> + if (fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> + intel_uncore_write64_fw(&dev_priv->uncore,
> + PLANE_CC_VAL(pipe, plane_id),
> plane_state->ccval);
> +
> skl_write_plane_wm(plane, crtc_state);
>
> intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), @@ -
> 2350,7 +2354,8 @@ static int skl_plane_check_fb(const struct
> intel_crtc_state *crtc_state,
> fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
> + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> + fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
> drm_dbg_kms(&dev_priv->drm,
> "Y/Yf tiling not supported in IF-ID mode\n");
> return -EINVAL;
> @@ -2840,6 +2845,7 @@ static const u64 skl_plane_format_modifiers_ccs[]
> = { static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> I915_FORMAT_MOD_Y_TILED,
> I915_FORMAT_MOD_X_TILED,
> DRM_FORMAT_MOD_LINEAR,
> @@ -2848,6 +2854,7 @@ static const u64
> gen12_plane_format_modifiers_mc_ccs[] = {
>
> static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> I915_FORMAT_MOD_Y_TILED,
> I915_FORMAT_MOD_X_TILED,
> DRM_FORMAT_MOD_LINEAR,
> @@ -3038,6 +3045,7 @@ static bool
> gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> break;
> default:
> return false;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 5375b219cc3b..edabb55d1586
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7070,6 +7070,8 @@ enum {
> #define _PLANE_KEYMAX_1_A 0x701a0
> #define _PLANE_KEYMAX_2_A 0x702a0
> #define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
> +#define _PLANE_CC_VAL_1_A 0x701b4
> +#define _PLANE_CC_VAL_2_A 0x702b4
> #define _PLANE_AUX_DIST_1_A 0x701c0
> #define _PLANE_AUX_DIST_2_A 0x702c0
> #define _PLANE_AUX_OFFSET_1_A 0x701c4
> @@ -7111,6 +7113,13 @@ enum {
> #define _PLANE_NV12_BUF_CFG_1_A 0x70278
> #define _PLANE_NV12_BUF_CFG_2_A 0x70378
>
> +#define _PLANE_CC_VAL_1_B 0x711b4
> +#define _PLANE_CC_VAL_2_B 0x712b4
> +#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A,
> _PLANE_CC_VAL_1_B)
> +#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A,
> _PLANE_CC_VAL_2_B)
> +#define PLANE_CC_VAL(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe),
> _PLANE_CC_VAL_2(pipe))
> +
> /* Input CSC Register Definitions */
> #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
> #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-11-23 18:26 [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color Imre Deak
@ 2020-11-27 14:31 ` Imre Deak
2020-11-23 20:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color Patchwork
` (6 subsequent siblings)
7 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2020-11-27 14:31 UTC (permalink / raw)
To: intel-gfx, Jani Nikula, Daniel Vetter
Cc: Rafael Antognolli, Kalyan Kondapally, Nanley Chery,
Dhinakaran Pandiyan, dri-devel
Hi Daniel, Jani,
is it ok to merge this patch along with 2/2 via the i915 tree?
--Imre
On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote:
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> Gen12 display can decompress surfaces compressed by render engine with
> Clear Color, add a new modifier as the driver needs to know the surface
> was compressed by render engine.
>
> V2: Description changes as suggested by Rafael.
> V3: Mention the Clear Color size of 64 bits in the comments(DK)
> v4: Fix trailing whitespaces
> v5: Explain Clear Color in the documentation.
> v6: Documentation Nitpicks(Nanley)
>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Nanley Chery <nanley.g.chery@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index ca48ed0e6bc1..0a1b2c4c4bee 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -527,6 +527,25 @@ extern "C" {
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
>
> +/*
> + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> + * compression.
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
> + * and at index 1. The clear color is stored at index 2, and the pitch should
> + * be ignored. The clear color structure is 256 bits. The first 128 bits
> + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
> + * by 32 bits. The raw clear color is consumed by the 3d engine and generates
> + * the converted clear color of size 64 bits. The first 32 bits store the Lower
> + * Converted Clear Color value and the next 32 bits store the Higher Converted
> + * Clear Color value when applicable. The Converted Clear Color values are
> + * consumed by the DE. The last 64 bits are used to store Color Discard Enable
> + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
> + * corresponds to an area of 4x1 tiles in the main surface. The main surface
> + * pitch is required to be a multiple of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> *
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2020-11-27 14:31 ` Imre Deak
0 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2020-11-27 14:31 UTC (permalink / raw)
To: intel-gfx, Jani Nikula, Daniel Vetter
Cc: Rafael Antognolli, Kalyan Kondapally, Nanley Chery,
Dhinakaran Pandiyan, dri-devel
Hi Daniel, Jani,
is it ok to merge this patch along with 2/2 via the i915 tree?
--Imre
On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote:
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> Gen12 display can decompress surfaces compressed by render engine with
> Clear Color, add a new modifier as the driver needs to know the surface
> was compressed by render engine.
>
> V2: Description changes as suggested by Rafael.
> V3: Mention the Clear Color size of 64 bits in the comments(DK)
> v4: Fix trailing whitespaces
> v5: Explain Clear Color in the documentation.
> v6: Documentation Nitpicks(Nanley)
>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Nanley Chery <nanley.g.chery@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index ca48ed0e6bc1..0a1b2c4c4bee 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -527,6 +527,25 @@ extern "C" {
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
>
> +/*
> + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> + * compression.
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
> + * and at index 1. The clear color is stored at index 2, and the pitch should
> + * be ignored. The clear color structure is 256 bits. The first 128 bits
> + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
> + * by 32 bits. The raw clear color is consumed by the 3d engine and generates
> + * the converted clear color of size 64 bits. The first 32 bits store the Lower
> + * Converted Clear Color value and the next 32 bits store the Higher Converted
> + * Clear Color value when applicable. The Converted Clear Color values are
> + * consumed by the DE. The last 64 bits are used to store Color Discard Enable
> + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
> + * corresponds to an area of 4x1 tiles in the main surface. The main surface
> + * pitch is required to be a multiple of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> *
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-11-27 14:31 ` Imre Deak
@ 2020-11-27 15:19 ` Daniel Vetter
-1 siblings, 0 replies; 31+ messages in thread
From: Daniel Vetter @ 2020-11-27 15:19 UTC (permalink / raw)
To: Imre Deak
Cc: Nanley Chery, Jani Nikula, Daniel Vetter, intel-gfx, dri-devel,
Rafael Antognolli, Dhinakaran Pandiyan, Kalyan Kondapally
On Fri, Nov 27, 2020 at 04:31:00PM +0200, Imre Deak wrote:
> Hi Daniel, Jani,
>
> is it ok to merge this patch along with 2/2 via the i915 tree?
Ack from mesa (userspace in general, but mesa is kinda mandatory) is
missing I think. With that
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> --Imre
>
> On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote:
> > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> >
> > Gen12 display can decompress surfaces compressed by render engine with
> > Clear Color, add a new modifier as the driver needs to know the surface
> > was compressed by render engine.
> >
> > V2: Description changes as suggested by Rafael.
> > V3: Mention the Clear Color size of 64 bits in the comments(DK)
> > v4: Fix trailing whitespaces
> > v5: Explain Clear Color in the documentation.
> > v6: Documentation Nitpicks(Nanley)
> >
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > Cc: Nanley Chery <nanley.g.chery@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index ca48ed0e6bc1..0a1b2c4c4bee 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -527,6 +527,25 @@ extern "C" {
> > */
> > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
> >
> > +/*
> > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> > + * compression.
> > + *
> > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
> > + * and at index 1. The clear color is stored at index 2, and the pitch should
> > + * be ignored. The clear color structure is 256 bits. The first 128 bits
> > + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
> > + * by 32 bits. The raw clear color is consumed by the 3d engine and generates
> > + * the converted clear color of size 64 bits. The first 32 bits store the Lower
> > + * Converted Clear Color value and the next 32 bits store the Higher Converted
> > + * Clear Color value when applicable. The Converted Clear Color values are
> > + * consumed by the DE. The last 64 bits are used to store Color Discard Enable
> > + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
> > + * corresponds to an area of 4x1 tiles in the main surface. The main surface
> > + * pitch is required to be a multiple of 4 tile widths.
> > + */
> > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > +
> > /*
> > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > *
> > --
> > 2.25.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2020-11-27 15:19 ` Daniel Vetter
0 siblings, 0 replies; 31+ messages in thread
From: Daniel Vetter @ 2020-11-27 15:19 UTC (permalink / raw)
To: Imre Deak
Cc: Nanley Chery, Jani Nikula, Daniel Vetter, intel-gfx, dri-devel,
Rafael Antognolli, Dhinakaran Pandiyan, Kalyan Kondapally
On Fri, Nov 27, 2020 at 04:31:00PM +0200, Imre Deak wrote:
> Hi Daniel, Jani,
>
> is it ok to merge this patch along with 2/2 via the i915 tree?
Ack from mesa (userspace in general, but mesa is kinda mandatory) is
missing I think. With that
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> --Imre
>
> On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote:
> > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> >
> > Gen12 display can decompress surfaces compressed by render engine with
> > Clear Color, add a new modifier as the driver needs to know the surface
> > was compressed by render engine.
> >
> > V2: Description changes as suggested by Rafael.
> > V3: Mention the Clear Color size of 64 bits in the comments(DK)
> > v4: Fix trailing whitespaces
> > v5: Explain Clear Color in the documentation.
> > v6: Documentation Nitpicks(Nanley)
> >
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > Cc: Nanley Chery <nanley.g.chery@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index ca48ed0e6bc1..0a1b2c4c4bee 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -527,6 +527,25 @@ extern "C" {
> > */
> > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
> >
> > +/*
> > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> > + * compression.
> > + *
> > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
> > + * and at index 1. The clear color is stored at index 2, and the pitch should
> > + * be ignored. The clear color structure is 256 bits. The first 128 bits
> > + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
> > + * by 32 bits. The raw clear color is consumed by the 3d engine and generates
> > + * the converted clear color of size 64 bits. The first 32 bits store the Lower
> > + * Converted Clear Color value and the next 32 bits store the Higher Converted
> > + * Clear Color value when applicable. The Converted Clear Color values are
> > + * consumed by the DE. The last 64 bits are used to store Color Discard Enable
> > + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
> > + * corresponds to an area of 4x1 tiles in the main surface. The main surface
> > + * pitch is required to be a multiple of 4 tile widths.
> > + */
> > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > +
> > /*
> > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > *
> > --
> > 2.25.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-11-27 15:19 ` Daniel Vetter
@ 2020-11-27 18:06 ` Imre Deak
-1 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2020-11-27 18:06 UTC (permalink / raw)
To: Daniel Vetter, Nanley Chery
Cc: Jani Nikula, Daniel Vetter, intel-gfx, dri-devel,
Rafael Antognolli, Dhinakaran Pandiyan, Kalyan Kondapally
On Fri, Nov 27, 2020 at 04:19:20PM +0100, Daniel Vetter wrote:
> On Fri, Nov 27, 2020 at 04:31:00PM +0200, Imre Deak wrote:
> > Hi Daniel, Jani,
> >
> > is it ok to merge this patch along with 2/2 via the i915 tree?
>
> Ack from mesa (userspace in general, but mesa is kinda mandatory) is
> missing I think. With that
> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Thanks.
Nanley, could you ACK the patchset if they look ok from Mesa's POV? It
works as expected at least with the igt/kms_ccs RC-CC subtest.
--Imre
> > On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote:
> > > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > >
> > > Gen12 display can decompress surfaces compressed by render engine with
> > > Clear Color, add a new modifier as the driver needs to know the surface
> > > was compressed by render engine.
> > >
> > > V2: Description changes as suggested by Rafael.
> > > V3: Mention the Clear Color size of 64 bits in the comments(DK)
> > > v4: Fix trailing whitespaces
> > > v5: Explain Clear Color in the documentation.
> > > v6: Documentation Nitpicks(Nanley)
> > >
> > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> > > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > > Cc: Nanley Chery <nanley.g.chery@intel.com>
> > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> > > 1 file changed, 19 insertions(+)
> > >
> > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > > index ca48ed0e6bc1..0a1b2c4c4bee 100644
> > > --- a/include/uapi/drm/drm_fourcc.h
> > > +++ b/include/uapi/drm/drm_fourcc.h
> > > @@ -527,6 +527,25 @@ extern "C" {
> > > */
> > > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
> > >
> > > +/*
> > > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> > > + * compression.
> > > + *
> > > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
> > > + * and at index 1. The clear color is stored at index 2, and the pitch should
> > > + * be ignored. The clear color structure is 256 bits. The first 128 bits
> > > + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
> > > + * by 32 bits. The raw clear color is consumed by the 3d engine and generates
> > > + * the converted clear color of size 64 bits. The first 32 bits store the Lower
> > > + * Converted Clear Color value and the next 32 bits store the Higher Converted
> > > + * Clear Color value when applicable. The Converted Clear Color values are
> > > + * consumed by the DE. The last 64 bits are used to store Color Discard Enable
> > > + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
> > > + * corresponds to an area of 4x1 tiles in the main surface. The main surface
> > > + * pitch is required to be a multiple of 4 tile widths.
> > > + */
> > > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > > +
> > > /*
> > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > *
> > > --
> > > 2.25.1
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2020-11-27 18:06 ` Imre Deak
0 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2020-11-27 18:06 UTC (permalink / raw)
To: Daniel Vetter, Nanley Chery
Cc: Jani Nikula, Daniel Vetter, intel-gfx, dri-devel,
Rafael Antognolli, Dhinakaran Pandiyan, Kalyan Kondapally
On Fri, Nov 27, 2020 at 04:19:20PM +0100, Daniel Vetter wrote:
> On Fri, Nov 27, 2020 at 04:31:00PM +0200, Imre Deak wrote:
> > Hi Daniel, Jani,
> >
> > is it ok to merge this patch along with 2/2 via the i915 tree?
>
> Ack from mesa (userspace in general, but mesa is kinda mandatory) is
> missing I think. With that
> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Thanks.
Nanley, could you ACK the patchset if they look ok from Mesa's POV? It
works as expected at least with the igt/kms_ccs RC-CC subtest.
--Imre
> > On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote:
> > > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > >
> > > Gen12 display can decompress surfaces compressed by render engine with
> > > Clear Color, add a new modifier as the driver needs to know the surface
> > > was compressed by render engine.
> > >
> > > V2: Description changes as suggested by Rafael.
> > > V3: Mention the Clear Color size of 64 bits in the comments(DK)
> > > v4: Fix trailing whitespaces
> > > v5: Explain Clear Color in the documentation.
> > > v6: Documentation Nitpicks(Nanley)
> > >
> > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> > > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > > Cc: Nanley Chery <nanley.g.chery@intel.com>
> > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> > > 1 file changed, 19 insertions(+)
> > >
> > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > > index ca48ed0e6bc1..0a1b2c4c4bee 100644
> > > --- a/include/uapi/drm/drm_fourcc.h
> > > +++ b/include/uapi/drm/drm_fourcc.h
> > > @@ -527,6 +527,25 @@ extern "C" {
> > > */
> > > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
> > >
> > > +/*
> > > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> > > + * compression.
> > > + *
> > > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
> > > + * and at index 1. The clear color is stored at index 2, and the pitch should
> > > + * be ignored. The clear color structure is 256 bits. The first 128 bits
> > > + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
> > > + * by 32 bits. The raw clear color is consumed by the 3d engine and generates
> > > + * the converted clear color of size 64 bits. The first 32 bits store the Lower
> > > + * Converted Clear Color value and the next 32 bits store the Higher Converted
> > > + * Clear Color value when applicable. The Converted Clear Color values are
> > > + * consumed by the DE. The last 64 bits are used to store Color Discard Enable
> > > + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
> > > + * corresponds to an area of 4x1 tiles in the main surface. The main surface
> > > + * pitch is required to be a multiple of 4 tile widths.
> > > + */
> > > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > > +
> > > /*
> > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > *
> > > --
> > > 2.25.1
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-11-27 15:19 ` Daniel Vetter
@ 2020-11-30 10:00 ` Jani Nikula
-1 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2020-11-30 10:00 UTC (permalink / raw)
To: Daniel Vetter, Imre Deak
Cc: Nanley Chery, Rafael Antognolli, Daniel Vetter, intel-gfx,
dri-devel, Dhinakaran Pandiyan, Kalyan Kondapally
On Fri, 27 Nov 2020, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Fri, Nov 27, 2020 at 04:31:00PM +0200, Imre Deak wrote:
>> Hi Daniel, Jani,
>>
>> is it ok to merge this patch along with 2/2 via the i915 tree?
>
> Ack from mesa (userspace in general, but mesa is kinda mandatory) is
> missing I think. With that
>
> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
With the same conditions,
Acked-by: Jani Nikula <jani.nikula@intel.com>
>
>>
>> --Imre
>>
>> On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote:
>> > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> >
>> > Gen12 display can decompress surfaces compressed by render engine with
>> > Clear Color, add a new modifier as the driver needs to know the surface
>> > was compressed by render engine.
>> >
>> > V2: Description changes as suggested by Rafael.
>> > V3: Mention the Clear Color size of 64 bits in the comments(DK)
>> > v4: Fix trailing whitespaces
>> > v5: Explain Clear Color in the documentation.
>> > v6: Documentation Nitpicks(Nanley)
>> >
>> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> > Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
>> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
>> > Cc: Nanley Chery <nanley.g.chery@intel.com>
>> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>> > ---
>> > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
>> > 1 file changed, 19 insertions(+)
>> >
>> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
>> > index ca48ed0e6bc1..0a1b2c4c4bee 100644
>> > --- a/include/uapi/drm/drm_fourcc.h
>> > +++ b/include/uapi/drm/drm_fourcc.h
>> > @@ -527,6 +527,25 @@ extern "C" {
>> > */
>> > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
>> >
>> > +/*
>> > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
>> > + * compression.
>> > + *
>> > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
>> > + * and at index 1. The clear color is stored at index 2, and the pitch should
>> > + * be ignored. The clear color structure is 256 bits. The first 128 bits
>> > + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
>> > + * by 32 bits. The raw clear color is consumed by the 3d engine and generates
>> > + * the converted clear color of size 64 bits. The first 32 bits store the Lower
>> > + * Converted Clear Color value and the next 32 bits store the Higher Converted
>> > + * Clear Color value when applicable. The Converted Clear Color values are
>> > + * consumed by the DE. The last 64 bits are used to store Color Discard Enable
>> > + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
>> > + * corresponds to an area of 4x1 tiles in the main surface. The main surface
>> > + * pitch is required to be a multiple of 4 tile widths.
>> > + */
>> > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
>> > +
>> > /*
>> > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>> > *
>> > --
>> > 2.25.1
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2020-11-30 10:00 ` Jani Nikula
0 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2020-11-30 10:00 UTC (permalink / raw)
To: Daniel Vetter, Imre Deak
Cc: Nanley Chery, Rafael Antognolli, Daniel Vetter, intel-gfx,
dri-devel, Dhinakaran Pandiyan, Kalyan Kondapally
On Fri, 27 Nov 2020, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Fri, Nov 27, 2020 at 04:31:00PM +0200, Imre Deak wrote:
>> Hi Daniel, Jani,
>>
>> is it ok to merge this patch along with 2/2 via the i915 tree?
>
> Ack from mesa (userspace in general, but mesa is kinda mandatory) is
> missing I think. With that
>
> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
With the same conditions,
Acked-by: Jani Nikula <jani.nikula@intel.com>
>
>>
>> --Imre
>>
>> On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote:
>> > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> >
>> > Gen12 display can decompress surfaces compressed by render engine with
>> > Clear Color, add a new modifier as the driver needs to know the surface
>> > was compressed by render engine.
>> >
>> > V2: Description changes as suggested by Rafael.
>> > V3: Mention the Clear Color size of 64 bits in the comments(DK)
>> > v4: Fix trailing whitespaces
>> > v5: Explain Clear Color in the documentation.
>> > v6: Documentation Nitpicks(Nanley)
>> >
>> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> > Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
>> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
>> > Cc: Nanley Chery <nanley.g.chery@intel.com>
>> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>> > ---
>> > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
>> > 1 file changed, 19 insertions(+)
>> >
>> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
>> > index ca48ed0e6bc1..0a1b2c4c4bee 100644
>> > --- a/include/uapi/drm/drm_fourcc.h
>> > +++ b/include/uapi/drm/drm_fourcc.h
>> > @@ -527,6 +527,25 @@ extern "C" {
>> > */
>> > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
>> >
>> > +/*
>> > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
>> > + * compression.
>> > + *
>> > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
>> > + * and at index 1. The clear color is stored at index 2, and the pitch should
>> > + * be ignored. The clear color structure is 256 bits. The first 128 bits
>> > + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
>> > + * by 32 bits. The raw clear color is consumed by the 3d engine and generates
>> > + * the converted clear color of size 64 bits. The first 32 bits store the Lower
>> > + * Converted Clear Color value and the next 32 bits store the Higher Converted
>> > + * Clear Color value when applicable. The Converted Clear Color values are
>> > + * consumed by the DE. The last 64 bits are used to store Color Discard Enable
>> > + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
>> > + * corresponds to an area of 4x1 tiles in the main surface. The main surface
>> > + * pitch is required to be a multiple of 4 tile widths.
>> > + */
>> > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
>> > +
>> > /*
>> > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>> > *
>> > --
>> > 2.25.1
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-11-27 18:06 ` Imre Deak
@ 2020-12-01 0:18 ` Chery, Nanley G
-1 siblings, 0 replies; 31+ messages in thread
From: Chery, Nanley G @ 2020-12-01 0:18 UTC (permalink / raw)
To: Deak, Imre, Daniel Vetter
Cc: Nikula, Jani, Daniel Vetter, intel-gfx, dri-devel, Pandiyan,
Dhinakaran, Kondapally, Kalyan
> -----Original Message-----
> From: Imre Deak <imre.deak@intel.com>
> Sent: Friday, November 27, 2020 10:06 AM
> To: Daniel Vetter <daniel@ffwll.ch>; Chery, Nanley G
> <nanley.g.chery@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>; Daniel
> Vetter <daniel.vetter@ffwll.ch>; Rafael Antognolli
> <rafael.antognolli@intel.com>; Kondapally, Kalyan
> <kalyan.kondapally@intel.com>; Pandiyan, Dhinakaran
> <dhinakaran.pandiyan@intel.com>; dri-devel@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel
> Gen 12 render compression with Clear Color
>
> On Fri, Nov 27, 2020 at 04:19:20PM +0100, Daniel Vetter wrote:
> > On Fri, Nov 27, 2020 at 04:31:00PM +0200, Imre Deak wrote:
> > > Hi Daniel, Jani,
> > >
> > > is it ok to merge this patch along with 2/2 via the i915 tree?
> >
> > Ack from mesa (userspace in general, but mesa is kinda mandatory) is
> > missing I think. With that
> > Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> Thanks.
>
> Nanley, could you ACK the patchset if they look ok from Mesa's POV? It
> works as expected at least with the igt/kms_ccs RC-CC subtest.
>
Hi Imre,
I have a question and a couple comments:
Is the map of the clear color address creating a new synchronization point between the GPU and CPU? If so, I wonder how this will impact performance. There was some talk of asynchronously updating the clear color register a while back.
We probably don't have to update the header, but we noticed in our testing that the clear color prefers an alignment greater than 64B. Unfortunately, I can't find any bspec note about this. As long as the buffer creators are aware though, I think we should be fine. I don't know if this is the best forum to bring it up, but I thought I'd share.
Seems like the upper converted clear color is untested due to the lack of RGBX16 support. I suppose that if there are any issues there, they can be fixed later...
-Nanley
> --Imre
>
> > > On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote:
> > > > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > >
> > > > Gen12 display can decompress surfaces compressed by render engine with
> > > > Clear Color, add a new modifier as the driver needs to know the surface
> > > > was compressed by render engine.
> > > >
> > > > V2: Description changes as suggested by Rafael.
> > > > V3: Mention the Clear Color size of 64 bits in the comments(DK)
> > > > v4: Fix trailing whitespaces
> > > > v5: Explain Clear Color in the documentation.
> > > > v6: Documentation Nitpicks(Nanley)
> > > >
> > > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> > > > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > > > Cc: Nanley Chery <nanley.g.chery@intel.com>
> > > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> > > > 1 file changed, 19 insertions(+)
> > > >
> > > > diff --git a/include/uapi/drm/drm_fourcc.h
> b/include/uapi/drm/drm_fourcc.h
> > > > index ca48ed0e6bc1..0a1b2c4c4bee 100644
> > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > @@ -527,6 +527,25 @@ extern "C" {
> > > > */
> > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> fourcc_mod_code(INTEL, 7)
> > > >
> > > > +/*
> > > > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> > > > + * compression.
> > > > + *
> > > > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
> > > > + * and at index 1. The clear color is stored at index 2, and the pitch should
> > > > + * be ignored. The clear color structure is 256 bits. The first 128 bits
> > > > + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> represented
> > > > + * by 32 bits. The raw clear color is consumed by the 3d engine and
> generates
> > > > + * the converted clear color of size 64 bits. The first 32 bits store the
> Lower
> > > > + * Converted Clear Color value and the next 32 bits store the Higher
> Converted
> > > > + * Clear Color value when applicable. The Converted Clear Color values
> are
> > > > + * consumed by the DE. The last 64 bits are used to store Color Discard
> Enable
> > > > + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache
> line
> > > > + * corresponds to an area of 4x1 tiles in the main surface. The main
> surface
> > > > + * pitch is required to be a multiple of 4 tile widths.
> > > > + */
> > > > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> fourcc_mod_code(INTEL, 8)
> > > > +
> > > > /*
> > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > > *
> > > > --
> > > > 2.25.1
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > _______________________________________________
> > > dri-devel mailing list
> > > dri-devel@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2020-12-01 0:18 ` Chery, Nanley G
0 siblings, 0 replies; 31+ messages in thread
From: Chery, Nanley G @ 2020-12-01 0:18 UTC (permalink / raw)
To: Deak, Imre, Daniel Vetter
Cc: Nikula, Jani, Daniel Vetter, intel-gfx, dri-devel, Pandiyan,
Dhinakaran, Kondapally, Kalyan
> -----Original Message-----
> From: Imre Deak <imre.deak@intel.com>
> Sent: Friday, November 27, 2020 10:06 AM
> To: Daniel Vetter <daniel@ffwll.ch>; Chery, Nanley G
> <nanley.g.chery@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>; Daniel
> Vetter <daniel.vetter@ffwll.ch>; Rafael Antognolli
> <rafael.antognolli@intel.com>; Kondapally, Kalyan
> <kalyan.kondapally@intel.com>; Pandiyan, Dhinakaran
> <dhinakaran.pandiyan@intel.com>; dri-devel@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel
> Gen 12 render compression with Clear Color
>
> On Fri, Nov 27, 2020 at 04:19:20PM +0100, Daniel Vetter wrote:
> > On Fri, Nov 27, 2020 at 04:31:00PM +0200, Imre Deak wrote:
> > > Hi Daniel, Jani,
> > >
> > > is it ok to merge this patch along with 2/2 via the i915 tree?
> >
> > Ack from mesa (userspace in general, but mesa is kinda mandatory) is
> > missing I think. With that
> > Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> Thanks.
>
> Nanley, could you ACK the patchset if they look ok from Mesa's POV? It
> works as expected at least with the igt/kms_ccs RC-CC subtest.
>
Hi Imre,
I have a question and a couple comments:
Is the map of the clear color address creating a new synchronization point between the GPU and CPU? If so, I wonder how this will impact performance. There was some talk of asynchronously updating the clear color register a while back.
We probably don't have to update the header, but we noticed in our testing that the clear color prefers an alignment greater than 64B. Unfortunately, I can't find any bspec note about this. As long as the buffer creators are aware though, I think we should be fine. I don't know if this is the best forum to bring it up, but I thought I'd share.
Seems like the upper converted clear color is untested due to the lack of RGBX16 support. I suppose that if there are any issues there, they can be fixed later...
-Nanley
> --Imre
>
> > > On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote:
> > > > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > >
> > > > Gen12 display can decompress surfaces compressed by render engine with
> > > > Clear Color, add a new modifier as the driver needs to know the surface
> > > > was compressed by render engine.
> > > >
> > > > V2: Description changes as suggested by Rafael.
> > > > V3: Mention the Clear Color size of 64 bits in the comments(DK)
> > > > v4: Fix trailing whitespaces
> > > > v5: Explain Clear Color in the documentation.
> > > > v6: Documentation Nitpicks(Nanley)
> > > >
> > > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> > > > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > > > Cc: Nanley Chery <nanley.g.chery@intel.com>
> > > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> > > > 1 file changed, 19 insertions(+)
> > > >
> > > > diff --git a/include/uapi/drm/drm_fourcc.h
> b/include/uapi/drm/drm_fourcc.h
> > > > index ca48ed0e6bc1..0a1b2c4c4bee 100644
> > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > @@ -527,6 +527,25 @@ extern "C" {
> > > > */
> > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> fourcc_mod_code(INTEL, 7)
> > > >
> > > > +/*
> > > > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> > > > + * compression.
> > > > + *
> > > > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
> > > > + * and at index 1. The clear color is stored at index 2, and the pitch should
> > > > + * be ignored. The clear color structure is 256 bits. The first 128 bits
> > > > + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> represented
> > > > + * by 32 bits. The raw clear color is consumed by the 3d engine and
> generates
> > > > + * the converted clear color of size 64 bits. The first 32 bits store the
> Lower
> > > > + * Converted Clear Color value and the next 32 bits store the Higher
> Converted
> > > > + * Clear Color value when applicable. The Converted Clear Color values
> are
> > > > + * consumed by the DE. The last 64 bits are used to store Color Discard
> Enable
> > > > + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache
> line
> > > > + * corresponds to an area of 4x1 tiles in the main surface. The main
> surface
> > > > + * pitch is required to be a multiple of 4 tile widths.
> > > > + */
> > > > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> fourcc_mod_code(INTEL, 8)
> > > > +
> > > > /*
> > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > > *
> > > > --
> > > > 2.25.1
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > _______________________________________________
> > > dri-devel mailing list
> > > dri-devel@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-12-01 0:18 ` Chery, Nanley G
@ 2020-12-01 12:04 ` Imre Deak
-1 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2020-12-01 12:04 UTC (permalink / raw)
To: Chery, Nanley G, Chris Wilson, Ville Syrjälä
Cc: Nikula, Jani, Daniel Vetter, intel-gfx, dri-devel, Pandiyan,
Dhinakaran, Kondapally, Kalyan
Hi Nanley,
thanks for the review.
+Ville, Chris.
On Tue, Dec 01, 2020 at 02:18:26AM +0200, Chery, Nanley G wrote:
> Hi Imre,
>
> I have a question and a couple comments:
>
> Is the map of the clear color address creating a new synchronization
> point between the GPU and CPU? If so, I wonder how this will impact
> performance.
The kmap to read the clear value is not adding any sync overhead if
that's what you mean. But the clear value must be in place before we
read it out and that should be guaranteed by the flush we do anyway to wait
for the render result (even considering the explicit L3/RT flush, depth
stall the spec requires for fast clears).
However now that you mention: atm the kmap/readout happens after the
explicit but before the implicit fence-wait. I think it should happen
after the implicit fence-wait.
Ville, Chris, could you confirm the above and also that the above flush
is enough to ensure the CPU read is coherent?
> There was some talk of asynchronously updating the clear color
> register a while back.
Couldn't find anything with a quick search, do you have a pointer? Just
before the flip we must wait for the render results anyway, as we do
now, so not sure how it could be optimized.
> We probably don't have to update the header, but we noticed in our
> testing that the clear color prefers an alignment greater than 64B.
> Unfortunately, I can't find any bspec note about this. As long as the
> buffer creators are aware though, I think we should be fine. I don't
> know if this is the best forum to bring it up, but I thought I'd
> share.
Yes, would be good to clarify this and get it also to the spec. Then the
driver should also check the alignment of the 3rd FB plane.
> Seems like the upper converted clear color is untested due to the lack
> of RGBX16 support. I suppose that if there are any issues there, they
> can be fixed later...
Yes, a 64bpp RC-CC subtest in IGT is missing, should be easy to add
that.
--Imre
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2020-12-01 12:04 ` Imre Deak
0 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2020-12-01 12:04 UTC (permalink / raw)
To: Chery, Nanley G, Chris Wilson, Ville Syrjälä
Cc: Nikula, Jani, Daniel Vetter, intel-gfx, dri-devel, Pandiyan,
Dhinakaran, Kondapally, Kalyan
Hi Nanley,
thanks for the review.
+Ville, Chris.
On Tue, Dec 01, 2020 at 02:18:26AM +0200, Chery, Nanley G wrote:
> Hi Imre,
>
> I have a question and a couple comments:
>
> Is the map of the clear color address creating a new synchronization
> point between the GPU and CPU? If so, I wonder how this will impact
> performance.
The kmap to read the clear value is not adding any sync overhead if
that's what you mean. But the clear value must be in place before we
read it out and that should be guaranteed by the flush we do anyway to wait
for the render result (even considering the explicit L3/RT flush, depth
stall the spec requires for fast clears).
However now that you mention: atm the kmap/readout happens after the
explicit but before the implicit fence-wait. I think it should happen
after the implicit fence-wait.
Ville, Chris, could you confirm the above and also that the above flush
is enough to ensure the CPU read is coherent?
> There was some talk of asynchronously updating the clear color
> register a while back.
Couldn't find anything with a quick search, do you have a pointer? Just
before the flip we must wait for the render results anyway, as we do
now, so not sure how it could be optimized.
> We probably don't have to update the header, but we noticed in our
> testing that the clear color prefers an alignment greater than 64B.
> Unfortunately, I can't find any bspec note about this. As long as the
> buffer creators are aware though, I think we should be fine. I don't
> know if this is the best forum to bring it up, but I thought I'd
> share.
Yes, would be good to clarify this and get it also to the spec. Then the
driver should also check the alignment of the 3rd FB plane.
> Seems like the upper converted clear color is untested due to the lack
> of RGBX16 support. I suppose that if there are any issues there, they
> can be fixed later...
Yes, a 64bpp RC-CC subtest in IGT is missing, should be easy to add
that.
--Imre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
2020-11-23 18:26 ` [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Clear Color support for TGL Render Decompression Imre Deak
2020-11-27 9:27 ` Kahola, Mika
@ 2020-12-01 12:34 ` Chris Wilson
2020-12-01 20:50 ` Imre Deak
1 sibling, 1 reply; 31+ messages in thread
From: Chris Wilson @ 2020-12-01 12:34 UTC (permalink / raw)
To: Imre Deak, intel-gfx
Cc: Rafael Antognolli, Ville Syrjala, Nanley G Chery,
Dhinakaran Pandiyan, Shashank Sharma
Quoting Imre Deak (2020-11-23 18:26:31)
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> Render Decompression is supported with Y-Tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a
> ratio of 1:256. Additional Clear Color information is passed from the
> user-space through an offset in the GEM BO. Add a new modifier to identify
> and parse new Clear Color information and extend Gen12 render decompression
> functionality to the newly added modifier.
>
> v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> plane config(Matt). Fix Lookup error.
> v3: Fix the panic while running kms_cube
> v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
> v5: Fix typos and wrap comments(Matt)
> v6:
> - Use format block descriptors to get the subsampling calculations for
> the CCS surface right.
> - Use helpers to convert between main and CCS surfaces.
> - Prevent coordinate checks for the CC surface.
> - Simplify reading CC value from surface map, add description of CC val
> layout.
> - Remove redundant ccval variable from skl_program_plane().
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Ville Syrjala <ville.syrjala@intel.com>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> (v5)
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 72 +++++++++++++++++--
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 10 ++-
> drivers/gpu/drm/i915/i915_reg.h | 9 +++
> 4 files changed, 89 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 595183f7b60f..f190f6f4cdf5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1968,8 +1968,8 @@ static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
> static bool is_gen12_ccs_modifier(u64 modifier)
> {
> return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> -
> }
>
> static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
> @@ -1977,6 +1977,12 @@ static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
> return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
> }
>
> +static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
> +{
> + return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
> + plane == 2;
> +}
> +
> static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
> {
> if (is_ccs_modifier(fb->modifier))
> @@ -1998,6 +2004,9 @@ static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
> drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
> ccs_plane < fb->format->num_planes / 2);
>
> + if (is_gen12_ccs_cc_plane(fb, ccs_plane))
> + return 0;
> +
> return ccs_plane - fb->format->num_planes / 2;
> }
>
> @@ -2048,6 +2057,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> return 128;
> fallthrough;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> if (is_ccs_plane(fb, color_plane))
> return 64;
> @@ -2204,6 +2214,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> return intel_tile_row_size(fb, color_plane);
> fallthrough;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return 16 * 1024;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -2608,6 +2619,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> return I915_TILING_Y;
> default:
> @@ -2686,6 +2698,25 @@ static const struct drm_format_info gen12_ccs_formats[] = {
> .hsub = 2, .vsub = 2, .is_yuv = true },
> };
>
> +/*
> + * Same as gen12_ccs_formats[] above, but with additional surface used
> + * to pass Clear Color information in plane 2 with 64 bits of data.
> + */
> +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> +};
> +
> static const struct drm_format_info *
> lookup_format_info(const struct drm_format_info formats[],
> int num_formats, u32 format)
> @@ -2714,6 +2745,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> return lookup_format_info(gen12_ccs_formats,
> ARRAY_SIZE(gen12_ccs_formats),
> cmd->pixel_format);
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> + return lookup_format_info(gen12_ccs_cc_formats,
> + ARRAY_SIZE(gen12_ccs_cc_formats),
> + cmd->pixel_format);
> default:
> return NULL;
> }
> @@ -2722,6 +2757,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> bool is_ccs_modifier(u64 modifier)
> {
> return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> @@ -2940,7 +2976,7 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
> int ccs_x, ccs_y;
> int main_x, main_y;
>
> - if (!is_ccs_plane(fb, ccs_plane))
> + if (!is_ccs_plane(fb, ccs_plane) || is_gen12_ccs_cc_plane(fb, ccs_plane))
> return 0;
>
> intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
> @@ -3067,6 +3103,18 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> int x, y;
> int ret;
>
> + /*
> + * Plane 2 of Render Compression with Clear Color fb modifier
> + * is consumed by the driver and not passed to DE. Skip the
> + * arithmetic related to alignment and offset calculation.
> + */
> + if (is_gen12_ccs_cc_plane(fb, i)) {
> + if (IS_ALIGNED(fb->offsets[i], PAGE_SIZE))
> + continue;
> + else
> + return -EINVAL;
> + }
> +
> cpp = fb->format->cpp[i];
> intel_fb_plane_dims(&width, &height, fb, i);
>
> @@ -3991,7 +4039,8 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
> int hsub, vsub;
> int x, y;
>
> - if (!is_ccs_plane(fb, ccs_plane))
> + if (!is_ccs_plane(fb, ccs_plane) ||
> + is_gen12_ccs_cc_plane(fb, ccs_plane))
> continue;
>
> intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
> @@ -4647,6 +4696,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> case I915_FORMAT_MOD_Y_TILED:
> return PLANE_CTL_TILED_Y;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> return PLANE_CTL_TILED_Y |
> @@ -16647,6 +16697,20 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
>
> plane_state->vma = vma;
>
> + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> + void *map = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
> + fb->offsets[2] >> PAGE_SHIFT));
So at this point in time, we have only queued the wait for render
completion (asynchronous waits) and not actually waited on either the
explicit or implicit fences.
Only at intel_atomic_commit_tail do we know that the GPU [+ccs]
writes will have been flushed.
There's also the matter of coherency. Is the object coherent for reads
from the CPU? -- in most cases it will not be, but you should check
obj->cache_coherency to see if the read requires a preceding
cache_clflush_range() / drm_clflush_virt_range().
Also the page may not exist, not all scanout objects are backed by struct
page. In which case, pulling it from a vmap (i915_gem_object_pin_map, or
iomap) may be required. (A i915_gem_object_read may be very useful for
such small accesses.)
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
2020-12-01 12:34 ` Chris Wilson
@ 2020-12-01 20:50 ` Imre Deak
2020-12-01 21:10 ` Chris Wilson
0 siblings, 1 reply; 31+ messages in thread
From: Imre Deak @ 2020-12-01 20:50 UTC (permalink / raw)
To: Chris Wilson
Cc: Ville Syrjala, Rafael Antognolli, intel-gfx, Dhinakaran Pandiyan,
Nanley G Chery, Shashank Sharma
On Tue, Dec 01, 2020 at 12:34:35PM +0000, Chris Wilson wrote:
> [...]
> > @@ -16647,6 +16697,20 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
> >
> > plane_state->vma = vma;
> >
> > + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> > + void *map = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
> > + fb->offsets[2] >> PAGE_SHIFT));
>
> So at this point in time, we have only queued the wait for render
> completion (asynchronous waits) and not actually waited on either the
> explicit or implicit fences.
>
> Only at intel_atomic_commit_tail do we know that the GPU [+ccs]
> writes will have been flushed.
Ok, so after intel_atomic_commit_fence_wait(). One problem is that
atomic state should not really get modified any more in commit_tail().
But I introduced that already earlier with the TC/TBT PLL selection, so
now I'd add one more exception.
> There's also the matter of coherency. Is the object coherent for reads
> from the CPU? -- in most cases it will not be, but you should check
> obj->cache_coherency to see if the read requires a preceding
> cache_clflush_range() / drm_clflush_virt_range().
Ok, at this point for the TGL-only modifier, we could then just
warn_on(!bo_cache_coherent_for_read) due to HAS_LLC.
> Also the page may not exist, not all scanout objects are backed by struct
> page. In which case, pulling it from a vmap (i915_gem_object_pin_map, or
> iomap) may be required. (A i915_gem_object_read may be very useful for
> such small accesses.)
Ok. Afaiu on TGL this would need the io/vmap special casing for stolen
memory only. That's only used for BIOS FBs, which is unlikely to be
fast-cleared and we haven't even added support to initial_fb for that.
Could we get away with that assumption and keep using kmap_atomic at
least for now?
Thanks for the explanation!
--Imre
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
2020-12-01 20:50 ` Imre Deak
@ 2020-12-01 21:10 ` Chris Wilson
2020-12-01 21:31 ` Imre Deak
0 siblings, 1 reply; 31+ messages in thread
From: Chris Wilson @ 2020-12-01 21:10 UTC (permalink / raw)
To: Imre Deak
Cc: Nanley G Chery, Rafael Antognolli, intel-gfx,
Dhinakaran Pandiyan, Ville Syrjala, Shashank Sharma
Quoting Imre Deak (2020-12-01 20:50:21)
> On Tue, Dec 01, 2020 at 12:34:35PM +0000, Chris Wilson wrote:
> > There's also the matter of coherency. Is the object coherent for reads
> > from the CPU? -- in most cases it will not be, but you should check
> > obj->cache_coherency to see if the read requires a preceding
> > cache_clflush_range() / drm_clflush_virt_range().
>
> Ok, at this point for the TGL-only modifier, we could then just
> warn_on(!bo_cache_coherent_for_read) due to HAS_LLC.
Stupid question, is the same path required for dg1?
That makes everything more difficult as the struct pages are gone.
-Chris
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
2020-12-01 21:10 ` Chris Wilson
@ 2020-12-01 21:31 ` Imre Deak
0 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2020-12-01 21:31 UTC (permalink / raw)
To: Chris Wilson
Cc: Nanley G Chery, Rafael Antognolli, intel-gfx,
Dhinakaran Pandiyan, Ville Syrjala, Shashank Sharma
On Tue, Dec 01, 2020 at 09:10:46PM +0000, Chris Wilson wrote:
> Quoting Imre Deak (2020-12-01 20:50:21)
> > On Tue, Dec 01, 2020 at 12:34:35PM +0000, Chris Wilson wrote:
> > > There's also the matter of coherency. Is the object coherent for reads
> > > from the CPU? -- in most cases it will not be, but you should check
> > > obj->cache_coherency to see if the read requires a preceding
> > > cache_clflush_range() / drm_clflush_virt_range().
> >
> > Ok, at this point for the TGL-only modifier, we could then just
> > warn_on(!bo_cache_coherent_for_read) due to HAS_LLC.
>
> Stupid question, is the same path required for dg1?
>
> That makes everything more difficult as the struct pages are gone.
Yes, same path. So we do need a different way to map.
--Imre
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^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-12-01 12:04 ` Imre Deak
@ 2020-12-11 7:04 ` Chery, Nanley G
-1 siblings, 0 replies; 31+ messages in thread
From: Chery, Nanley G @ 2020-12-11 7:04 UTC (permalink / raw)
To: Deak, Imre, Chris Wilson, Ville Syrjälä
Cc: Nikula, Jani, Daniel Vetter, intel-gfx, dri-devel, Pandiyan, Dhinakaran
> -----Original Message-----
> From: Imre Deak <imre.deak@intel.com>
> Sent: Tuesday, December 1, 2020 4:05 AM
> To: Chery, Nanley G <nanley.g.chery@intel.com>; Chris Wilson <chris@chris-
> wilson.co.uk>; Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org; Nikula,
> Jani <jani.nikula@intel.com>; Daniel Vetter <daniel.vetter@ffwll.ch>;
> Kondapally, Kalyan <kalyan.kondapally@intel.com>; Pandiyan, Dhinakaran
> <dhinakaran.pandiyan@intel.com>; dri-devel@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for
> Intel Gen 12 render compression with Clear Color
>
> Hi Nanley,
>
> thanks for the review.
>
> +Ville, Chris.
>
> On Tue, Dec 01, 2020 at 02:18:26AM +0200, Chery, Nanley G wrote:
> > Hi Imre,
> >
> > I have a question and a couple comments:
> >
> > Is the map of the clear color address creating a new synchronization
> > point between the GPU and CPU? If so, I wonder how this will impact
> > performance.
>
> The kmap to read the clear value is not adding any sync overhead if
> that's what you mean. But the clear value must be in place before we
> read it out and that should be guaranteed by the flush we do anyway to wait
> for the render result (even considering the explicit L3/RT flush, depth
> stall the spec requires for fast clears).
>
> However now that you mention: atm the kmap/readout happens after the
> explicit but before the implicit fence-wait. I think it should happen
> after the implicit fence-wait.
>
> Ville, Chris, could you confirm the above and also that the above flush
> is enough to ensure the CPU read is coherent?
>
> > There was some talk of asynchronously updating the clear color
> > register a while back.
>
> Couldn't find anything with a quick search, do you have a pointer? Just
> before the flip we must wait for the render results anyway, as we do
> now, so not sure how it could be optimized.
>
There were some offline discussions, so I don't have a reference unfortunately.
Though, given what you shared above it seems like it's actually not an issue.
> > We probably don't have to update the header, but we noticed in our
> > testing that the clear color prefers an alignment greater than 64B.
> > Unfortunately, I can't find any bspec note about this. As long as the
> > buffer creators are aware though, I think we should be fine. I don't
> > know if this is the best forum to bring it up, but I thought I'd
> > share.
>
> Yes, would be good to clarify this and get it also to the spec. Then the
> driver should also check the alignment of the 3rd FB plane.
>
I plan to run some more tests and file a bug in the spec.
I see that the IGT test only clears the fb once. Just to confirm, is the
clear color offset read from on every frame? Userspace would like to be
able to pass different clear colors for an fb.
-Nanley
> > Seems like the upper converted clear color is untested due to the lack
> > of RGBX16 support. I suppose that if there are any issues there, they
> > can be fixed later...
>
> Yes, a 64bpp RC-CC subtest in IGT is missing, should be easy to add
> that.
>
> --Imre
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2020-12-11 7:04 ` Chery, Nanley G
0 siblings, 0 replies; 31+ messages in thread
From: Chery, Nanley G @ 2020-12-11 7:04 UTC (permalink / raw)
To: Deak, Imre, Chris Wilson, Ville Syrjälä
Cc: Nikula, Jani, Daniel Vetter, intel-gfx, dri-devel, Pandiyan, Dhinakaran
> -----Original Message-----
> From: Imre Deak <imre.deak@intel.com>
> Sent: Tuesday, December 1, 2020 4:05 AM
> To: Chery, Nanley G <nanley.g.chery@intel.com>; Chris Wilson <chris@chris-
> wilson.co.uk>; Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org; Nikula,
> Jani <jani.nikula@intel.com>; Daniel Vetter <daniel.vetter@ffwll.ch>;
> Kondapally, Kalyan <kalyan.kondapally@intel.com>; Pandiyan, Dhinakaran
> <dhinakaran.pandiyan@intel.com>; dri-devel@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for
> Intel Gen 12 render compression with Clear Color
>
> Hi Nanley,
>
> thanks for the review.
>
> +Ville, Chris.
>
> On Tue, Dec 01, 2020 at 02:18:26AM +0200, Chery, Nanley G wrote:
> > Hi Imre,
> >
> > I have a question and a couple comments:
> >
> > Is the map of the clear color address creating a new synchronization
> > point between the GPU and CPU? If so, I wonder how this will impact
> > performance.
>
> The kmap to read the clear value is not adding any sync overhead if
> that's what you mean. But the clear value must be in place before we
> read it out and that should be guaranteed by the flush we do anyway to wait
> for the render result (even considering the explicit L3/RT flush, depth
> stall the spec requires for fast clears).
>
> However now that you mention: atm the kmap/readout happens after the
> explicit but before the implicit fence-wait. I think it should happen
> after the implicit fence-wait.
>
> Ville, Chris, could you confirm the above and also that the above flush
> is enough to ensure the CPU read is coherent?
>
> > There was some talk of asynchronously updating the clear color
> > register a while back.
>
> Couldn't find anything with a quick search, do you have a pointer? Just
> before the flip we must wait for the render results anyway, as we do
> now, so not sure how it could be optimized.
>
There were some offline discussions, so I don't have a reference unfortunately.
Though, given what you shared above it seems like it's actually not an issue.
> > We probably don't have to update the header, but we noticed in our
> > testing that the clear color prefers an alignment greater than 64B.
> > Unfortunately, I can't find any bspec note about this. As long as the
> > buffer creators are aware though, I think we should be fine. I don't
> > know if this is the best forum to bring it up, but I thought I'd
> > share.
>
> Yes, would be good to clarify this and get it also to the spec. Then the
> driver should also check the alignment of the 3rd FB plane.
>
I plan to run some more tests and file a bug in the spec.
I see that the IGT test only clears the fb once. Just to confirm, is the
clear color offset read from on every frame? Userspace would like to be
able to pass different clear colors for an fb.
-Nanley
> > Seems like the upper converted clear color is untested due to the lack
> > of RGBX16 support. I suppose that if there are any issues there, they
> > can be fixed later...
>
> Yes, a 64bpp RC-CC subtest in IGT is missing, should be easy to add
> that.
>
> --Imre
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2020-12-11 7:04 ` Chery, Nanley G
@ 2020-12-14 16:22 ` Imre Deak
-1 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2020-12-14 16:22 UTC (permalink / raw)
To: Chery, Nanley G
Cc: Nikula, Jani, Daniel Vetter, intel-gfx, dri-devel, Chris Wilson,
Pandiyan, Dhinakaran
On Fri, Dec 11, 2020 at 09:04:02AM +0200, Chery, Nanley G wrote:
> [...]
> > > We probably don't have to update the header, but we noticed in our
> > > testing that the clear color prefers an alignment greater than 64B.
> > > Unfortunately, I can't find any bspec note about this. As long as the
> > > buffer creators are aware though, I think we should be fine. I don't
> > > know if this is the best forum to bring it up, but I thought I'd
> > > share.
> >
> > Yes, would be good to clarify this and get it also to the spec. Then the
> > driver should also check the alignment of the 3rd FB plane.
>
> I plan to run some more tests and file a bug in the spec.
Ok, thanks. Note that this patch has a problem with synchornization and
based on Chris' response I'm planning to update it once I figured out
the proper way to map the CC plane. Until that you could still use it on
TGL if you wait for the RT result explicitly after the fast clear and
before flipping to it (that's what the IGT test does atm).
> I see that the IGT test only clears the fb once. Just to confirm, is the
> clear color offset read from on every frame? Userspace would like to be
> able to pass different clear colors for an fb.
Yes, every time you do a flip the kernel will re-read the CC value and
program it to the display.
--Imre
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2020-12-14 16:22 ` Imre Deak
0 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2020-12-14 16:22 UTC (permalink / raw)
To: Chery, Nanley G
Cc: Nikula, Jani, Daniel Vetter, intel-gfx, dri-devel, Chris Wilson,
Pandiyan, Dhinakaran
On Fri, Dec 11, 2020 at 09:04:02AM +0200, Chery, Nanley G wrote:
> [...]
> > > We probably don't have to update the header, but we noticed in our
> > > testing that the clear color prefers an alignment greater than 64B.
> > > Unfortunately, I can't find any bspec note about this. As long as the
> > > buffer creators are aware though, I think we should be fine. I don't
> > > know if this is the best forum to bring it up, but I thought I'd
> > > share.
> >
> > Yes, would be good to clarify this and get it also to the spec. Then the
> > driver should also check the alignment of the 3rd FB plane.
>
> I plan to run some more tests and file a bug in the spec.
Ok, thanks. Note that this patch has a problem with synchornization and
based on Chris' response I'm planning to update it once I figured out
the proper way to map the CC plane. Until that you could still use it on
TGL if you wait for the RT result explicitly after the fast clear and
before flipping to it (that's what the IGT test does atm).
> I see that the IGT test only clears the fb once. Just to confirm, is the
> clear color offset read from on every frame? Userspace would like to be
> able to pass different clear colors for an fb.
Yes, every time you do a flip the kernel will re-read the CC value and
program it to the display.
--Imre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2020-12-14 16:22 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-23 18:26 [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color Imre Deak
2020-11-23 18:26 ` [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Clear Color support for TGL Render Decompression Imre Deak
2020-11-27 9:27 ` Kahola, Mika
2020-12-01 12:34 ` Chris Wilson
2020-12-01 20:50 ` Imre Deak
2020-12-01 21:10 ` Chris Wilson
2020-12-01 21:31 ` Imre Deak
2020-11-23 20:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color Patchwork
2020-11-23 20:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-11-23 21:24 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-11-24 15:12 ` Imre Deak
2020-11-24 17:15 ` Vudum, Lakshminarayana
2020-11-24 17:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-24 21:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-11-26 8:24 ` [Intel-gfx] [PATCH 1/2] " Kahola, Mika
2020-11-27 14:31 ` Imre Deak
2020-11-27 14:31 ` Imre Deak
2020-11-27 15:19 ` Daniel Vetter
2020-11-27 15:19 ` Daniel Vetter
2020-11-27 18:06 ` Imre Deak
2020-11-27 18:06 ` Imre Deak
2020-12-01 0:18 ` Chery, Nanley G
2020-12-01 0:18 ` Chery, Nanley G
2020-12-01 12:04 ` Imre Deak
2020-12-01 12:04 ` Imre Deak
2020-12-11 7:04 ` Chery, Nanley G
2020-12-11 7:04 ` Chery, Nanley G
2020-12-14 16:22 ` Imre Deak
2020-12-14 16:22 ` Imre Deak
2020-11-30 10:00 ` Jani Nikula
2020-11-30 10:00 ` Jani Nikula
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