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* [Intel-xe] [PATCH 0/5] RPLS and other minor support
@ 2023-05-26 21:17 Anusha Srivatsa
  2023-05-26 21:17 ` [Intel-xe] [PATCH 1/5] drm/xe/adlp: s/ADLP/ALDERLAKE_P Anusha Srivatsa
                   ` (6 more replies)
  0 siblings, 7 replies; 10+ messages in thread
From: Anusha Srivatsa @ 2023-05-26 21:17 UTC (permalink / raw)
  To: intel-xe; +Cc: Anusha Srivatsa

As part of it making some consistent naming changes
so we can continue to use some macro magic moving forward.
It does make the name bigger - ALDERLAKE_P instead of
just ADLP. But this way the platform name is ALDERLAKE_P
everywhere which is easier to remember and use.(previosuly
the driver had ADLP_ usages for some defines - like ADLP_RPLU_* etc)

v2: Squash the addition of platfroms to the kunit tests
in the patch that introduces the platfrom.
- Add missing commit message and move patches accordingly.

Anusha Srivatsa (5):
  drm/xe/adlp: s/ADLP/ALDERLAKE_P
  drm/i915/adlp: s/ADLP/ALDERLAKE_P
  drm/xe/rpls: Add RPLS Support
  drm/xe/rpls: Add Stepping info for RPLS
  drm/xe: Add missing ADL entries to xe_test_wa

 drivers/gpu/drm/i915/display/intel_cdclk.c        |  2 +-
 drivers/gpu/drm/i915/i915_drv.h                   |  2 +-
 drivers/gpu/drm/i915/intel_step.c                 |  2 +-
 drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h |  2 +-
 drivers/gpu/drm/xe/tests/xe_wa_test.c             |  5 +++++
 drivers/gpu/drm/xe/xe_pci.c                       |  9 ++++++++-
 drivers/gpu/drm/xe/xe_platform_types.h            |  3 ++-
 drivers/gpu/drm/xe/xe_step.c                      | 10 +++++++++-
 8 files changed, 28 insertions(+), 7 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 10+ messages in thread
* [Intel-xe] [PATCH 1/5] drm/xe/adlp: s/ADLP/ALDERLAKE_P
  2023-05-26 21:17 [Intel-xe] [PATCH 0/5] RPLS and other minor support Anusha Srivatsa
@ 2023-05-26 21:17 ` Anusha Srivatsa
  2023-05-29  8:00   ` Jani Nikula
  2023-05-26 21:17 ` [Intel-xe] [PATCH 2/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P Anusha Srivatsa
                   ` (5 subsequent siblings)
  6 siblings, 1 reply; 10+ messages in thread
From: Anusha Srivatsa @ 2023-05-26 21:17 UTC (permalink / raw)
  To: intel-xe; +Cc: Anusha Srivatsa, Lucas De Marchi

Inconsistent usage of platform names across the driver.
Changing to use the name convention throughout - ALDERLAKE_P.
This will make it easier for macro magic usages.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 2 +-
 drivers/gpu/drm/xe/xe_pci.c                       | 2 +-
 drivers/gpu/drm/xe/xe_platform_types.h            | 2 +-
 drivers/gpu/drm/xe/xe_step.c                      | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index 74e6f063f741..9d212fbbce26 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -160,7 +160,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
 #define IS_DG2_G10(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G10)
 #define IS_DG2_G11(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G11)
 #define IS_DG2_G12(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G12)
-#define IS_ADLP_RPLU(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_ADLP_RPLU)
+#define IS_ALDERLAKE_P_RPLU(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU)
 #define IS_ICL_WITH_PORT_F(xe) (xe && 0)
 #define HAS_LSPCON(xe) (xe && 0)
 #define HAS_MSO(xe) (xe || 1)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index d8f1213ae1d6..33027091cc30 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -213,7 +213,7 @@ static const struct xe_device_desc adl_p_desc = {
 	.has_llc = true,
 	.require_force_probe = true,
 	.subplatforms = (const struct xe_subplatform_desc[]) {
-		{ XE_SUBPLATFORM_ADLP_RPLU, "RPLU", adlp_rplu_ids },
+		{ XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
 		{},
 	},
 };
diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
index abbb8a1f29a8..cb50e9b77816 100644
--- a/drivers/gpu/drm/xe/xe_platform_types.h
+++ b/drivers/gpu/drm/xe/xe_platform_types.h
@@ -26,7 +26,7 @@ enum xe_platform {
 enum xe_subplatform {
 	XE_SUBPLATFORM_UNINITIALIZED = 0,
 	XE_SUBPLATFORM_NONE,
-	XE_SUBPLATFORM_ADLP_RPLU,
+	XE_SUBPLATFORM_ALDERLAKE_P_RPLU,
 	XE_SUBPLATFORM_DG2_G10,
 	XE_SUBPLATFORM_DG2_G11,
 	XE_SUBPLATFORM_DG2_G12,
diff --git a/drivers/gpu/drm/xe/xe_step.c b/drivers/gpu/drm/xe/xe_step.c
index 1baf79ba02ad..cb0811c8bf22 100644
--- a/drivers/gpu/drm/xe/xe_step.c
+++ b/drivers/gpu/drm/xe/xe_step.c
@@ -143,7 +143,7 @@ struct xe_step_info xe_step_pre_gmdid_get(struct xe_device *xe)
 	} else if (xe->info.platform == XE_ALDERLAKE_N) {
 		revids = adln_revids;
 		size = ARRAY_SIZE(adln_revids);
-	} else if (xe->info.subplatform == XE_SUBPLATFORM_ADLP_RPLU) {
+	} else if (xe->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU) {
 		revids = adlp_rpl_revids;
 		size = ARRAY_SIZE(adlp_rpl_revids);
 	} else if (xe->info.platform == XE_ALDERLAKE_P) {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [Intel-xe] [PATCH 2/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P
  2023-05-26 21:17 [Intel-xe] [PATCH 0/5] RPLS and other minor support Anusha Srivatsa
  2023-05-26 21:17 ` [Intel-xe] [PATCH 1/5] drm/xe/adlp: s/ADLP/ALDERLAKE_P Anusha Srivatsa
@ 2023-05-26 21:17 ` Anusha Srivatsa
  2023-05-29  8:01   ` Jani Nikula
  2023-05-26 21:17 ` [Intel-xe] [PATCH 3/5] drm/xe/rpls: Add RPLS Support Anusha Srivatsa
                   ` (4 subsequent siblings)
  6 siblings, 1 reply; 10+ messages in thread
From: Anusha Srivatsa @ 2023-05-26 21:17 UTC (permalink / raw)
  To: intel-xe; +Cc: Anusha Srivatsa, Lucas De Marchi

Refer to platform with the same consistent name.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h            | 2 +-
 drivers/gpu/drm/i915/intel_step.c          | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f6223d8f13b8..bb0d8cd7034e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3409,7 +3409,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		/* Wa_22011320316:adl-p[a0] */
 		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
-		else if (IS_ADLP_RPLU(dev_priv))
+		else if (IS_ALDERLAKE_P_RPLU(dev_priv))
 			dev_priv->display.cdclk.table = rplu_cdclk_table;
 		else
 			dev_priv->display.cdclk.table = adlp_cdclk_table;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 14c5338c96a6..e870dd412a75 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -578,7 +578,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_N(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
-#define IS_ADLP_RPLP(i915) \
+#define IS_ALDERLAKE_P_RPLU(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_RPLU(i915) \
 	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 84a6fe736a3b..6a8816fbc15a 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -191,7 +191,7 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_ADLP_N(i915)) {
 		revids = adlp_n_revids;
 		size = ARRAY_SIZE(adlp_n_revids);
-	} else if (IS_ADLP_RPLP(i915)) {
+	} else if (IS_ALDERLAKE_P_RPLU(i915)) {
 		revids = adlp_rplp_revids;
 		size = ARRAY_SIZE(adlp_rplp_revids);
 	} else if (IS_ALDERLAKE_P(i915)) {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [Intel-xe] [PATCH 3/5] drm/xe/rpls: Add RPLS Support
  2023-05-26 21:17 [Intel-xe] [PATCH 0/5] RPLS and other minor support Anusha Srivatsa
  2023-05-26 21:17 ` [Intel-xe] [PATCH 1/5] drm/xe/adlp: s/ADLP/ALDERLAKE_P Anusha Srivatsa
  2023-05-26 21:17 ` [Intel-xe] [PATCH 2/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P Anusha Srivatsa
@ 2023-05-26 21:17 ` Anusha Srivatsa
  2023-05-26 21:17 ` [Intel-xe] [PATCH 4/5] drm/xe/rpls: Add Stepping info for RPLS Anusha Srivatsa
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 10+ messages in thread
From: Anusha Srivatsa @ 2023-05-26 21:17 UTC (permalink / raw)
  To: intel-xe; +Cc: Matt Roper, Anusha Srivatsa, Lucas De Marchi

Add RPLS support that was missing apart from the PCI IDs.

v2: s/RPLS/RAPTORLAKE_S (Anusha)
v3: Also add the support in xe_wa_test kunit

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>(v1)
---
 drivers/gpu/drm/xe/tests/xe_wa_test.c  | 1 +
 drivers/gpu/drm/xe/xe_pci.c            | 7 +++++++
 drivers/gpu/drm/xe/xe_platform_types.h | 1 +
 3 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/xe/tests/xe_wa_test.c b/drivers/gpu/drm/xe/tests/xe_wa_test.c
index 7a86be830b93..f654976506c9 100644
--- a/drivers/gpu/drm/xe/tests/xe_wa_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_wa_test.c
@@ -46,6 +46,7 @@ static const struct platform_test_case cases[] = {
 	PLATFORM_CASE(ALDERLAKE_S, B0),
 	PLATFORM_CASE(ALDERLAKE_S, C0),
 	PLATFORM_CASE(ALDERLAKE_S, D0),
+	SUBPLATFORM_CASE(ALDERLAKE_S, RPLS, D0),
 	SUBPLATFORM_CASE(DG2, G10, A0),
 	SUBPLATFORM_CASE(DG2, G10, A1),
 	SUBPLATFORM_CASE(DG2, G10, B0),
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 33027091cc30..0d1dff5896af 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -194,6 +194,8 @@ static const struct xe_device_desc rkl_desc = {
 	.require_force_probe = true,
 };
 
+static const u16 adls_rpls_ids[] = { XE_RPLS_IDS(NOP), 0 };
+
 static const struct xe_device_desc adl_s_desc = {
 	.graphics = &graphics_xelp,
 	.media = &media_xem,
@@ -201,6 +203,10 @@ static const struct xe_device_desc adl_s_desc = {
 	.has_display = true,
 	.has_llc = true,
 	.require_force_probe = true,
+	.subplatforms = (const struct xe_subplatform_desc[]) {
+		{ XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
+		{},
+	},
 };
 
 static const u16 adlp_rplu_ids[] = { XE_RPLU_IDS(NOP), 0 };
@@ -339,6 +345,7 @@ static const struct pci_device_id pciidlist[] = {
 	XE_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
 	XE_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc),
 	XE_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
+	XE_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
 	XE_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc),
 	XE_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
 	XE_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),
diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
index cb50e9b77816..c12ae7243f9f 100644
--- a/drivers/gpu/drm/xe/xe_platform_types.h
+++ b/drivers/gpu/drm/xe/xe_platform_types.h
@@ -27,6 +27,7 @@ enum xe_subplatform {
 	XE_SUBPLATFORM_UNINITIALIZED = 0,
 	XE_SUBPLATFORM_NONE,
 	XE_SUBPLATFORM_ALDERLAKE_P_RPLU,
+	XE_SUBPLATFORM_ALDERLAKE_S_RPLS,
 	XE_SUBPLATFORM_DG2_G10,
 	XE_SUBPLATFORM_DG2_G11,
 	XE_SUBPLATFORM_DG2_G12,
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [Intel-xe] [PATCH 4/5] drm/xe/rpls: Add Stepping info for RPLS
  2023-05-26 21:17 [Intel-xe] [PATCH 0/5] RPLS and other minor support Anusha Srivatsa
                   ` (2 preceding siblings ...)
  2023-05-26 21:17 ` [Intel-xe] [PATCH 3/5] drm/xe/rpls: Add RPLS Support Anusha Srivatsa
@ 2023-05-26 21:17 ` Anusha Srivatsa
  2023-05-26 21:17 ` [Intel-xe] [PATCH 5/5] drm/xe: Add missing ADL entries to xe_test_wa Anusha Srivatsa
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 10+ messages in thread
From: Anusha Srivatsa @ 2023-05-26 21:17 UTC (permalink / raw)
  To: intel-xe; +Cc: Anusha Srivatsa, Matt Roper

Add stepping-substepping info. Though it looks
weird, the revision ID for the newer stepping
is indeed backwards and is in accordance to the spec.

v2: s/RPLS/RAPTORLAKE_S (Anusha)

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>(v1)
---
 drivers/gpu/drm/xe/xe_step.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_step.c b/drivers/gpu/drm/xe/xe_step.c
index cb0811c8bf22..e5d4bc9d64bb 100644
--- a/drivers/gpu/drm/xe/xe_step.c
+++ b/drivers/gpu/drm/xe/xe_step.c
@@ -60,6 +60,11 @@ static const struct xe_step_info adls_revids[] = {
 	[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display = STEP_C0 },
 };
 
+static const struct xe_step_info adls_rpls_revids[] = {
+	[0x4] = { COMMON_GT_MEDIA_STEP(D0), .display = STEP_D0 },
+	[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display = STEP_C0 },
+};
+
 static const struct xe_step_info adlp_revids[] = {
 	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A0 },
 	[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_B0 },
@@ -143,6 +148,9 @@ struct xe_step_info xe_step_pre_gmdid_get(struct xe_device *xe)
 	} else if (xe->info.platform == XE_ALDERLAKE_N) {
 		revids = adln_revids;
 		size = ARRAY_SIZE(adln_revids);
+	} else if (xe->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_S_RPLS) {
+		revids = adls_rpls_revids;
+		size = ARRAY_SIZE(adls_rpls_revids);
 	} else if (xe->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU) {
 		revids = adlp_rpl_revids;
 		size = ARRAY_SIZE(adlp_rpl_revids);
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [Intel-xe] [PATCH 5/5] drm/xe: Add missing ADL entries to xe_test_wa
  2023-05-26 21:17 [Intel-xe] [PATCH 0/5] RPLS and other minor support Anusha Srivatsa
                   ` (3 preceding siblings ...)
  2023-05-26 21:17 ` [Intel-xe] [PATCH 4/5] drm/xe/rpls: Add Stepping info for RPLS Anusha Srivatsa
@ 2023-05-26 21:17 ` Anusha Srivatsa
  2023-05-26 21:17 ` [Intel-xe] ✓ CI.Patch_applied: success for RPLS and other minor support (rev2) Patchwork
  2023-05-26 21:18 ` [Intel-xe] ✗ CI.KUnit: failure " Patchwork
  6 siblings, 0 replies; 10+ messages in thread
From: Anusha Srivatsa @ 2023-05-26 21:17 UTC (permalink / raw)
  To: intel-xe; +Cc: Anusha Srivatsa, Lucas De Marchi

With all ADl platforms and subplatforms added,
also add support to xw_wa_test kunit tests for checking
their WAs.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/xe/tests/xe_wa_test.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/xe/tests/xe_wa_test.c b/drivers/gpu/drm/xe/tests/xe_wa_test.c
index f654976506c9..6e1127b276ea 100644
--- a/drivers/gpu/drm/xe/tests/xe_wa_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_wa_test.c
@@ -46,7 +46,11 @@ static const struct platform_test_case cases[] = {
 	PLATFORM_CASE(ALDERLAKE_S, B0),
 	PLATFORM_CASE(ALDERLAKE_S, C0),
 	PLATFORM_CASE(ALDERLAKE_S, D0),
+	PLATFORM_CASE(ALDERLAKE_P, A0),
+	PLATFORM_CASE(ALDERLAKE_P, B0),
+	PLATFORM_CASE(ALDERLAKE_P, C0),
 	SUBPLATFORM_CASE(ALDERLAKE_S, RPLS, D0),
+	SUBPLATFORM_CASE(ALDERLAKE_P, RPLU, E0),
 	SUBPLATFORM_CASE(DG2, G10, A0),
 	SUBPLATFORM_CASE(DG2, G10, A1),
 	SUBPLATFORM_CASE(DG2, G10, B0),
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [Intel-xe] ✓ CI.Patch_applied: success for RPLS and other minor support (rev2)
  2023-05-26 21:17 [Intel-xe] [PATCH 0/5] RPLS and other minor support Anusha Srivatsa
                   ` (4 preceding siblings ...)
  2023-05-26 21:17 ` [Intel-xe] [PATCH 5/5] drm/xe: Add missing ADL entries to xe_test_wa Anusha Srivatsa
@ 2023-05-26 21:17 ` Patchwork
  2023-05-26 21:18 ` [Intel-xe] ✗ CI.KUnit: failure " Patchwork
  6 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2023-05-26 21:17 UTC (permalink / raw)
  To: Anusha Srivatsa; +Cc: intel-xe

== Series Details ==

Series: RPLS and other minor support (rev2)
URL   : https://patchwork.freedesktop.org/series/118442/
State : success

== Summary ==

=== Applying kernel patches on branch 'drm-xe-next' with base: ===
Base commit: 4b72ead33 drm/xe/pvc: Don't try to invalidate AuxCCS TLB
=== git am output follows ===
Applying: drm/xe/adlp: s/ADLP/ALDERLAKE_P
Applying: drm/i915/adlp: s/ADLP/ALDERLAKE_P
Applying: drm/xe/rpls: Add RPLS Support
Applying: drm/xe/rpls: Add Stepping info for RPLS
Applying: drm/xe: Add missing ADL entries to xe_test_wa



^ permalink raw reply	[flat|nested] 10+ messages in thread
* [Intel-xe] ✗ CI.KUnit: failure for RPLS and other minor support (rev2)
  2023-05-26 21:17 [Intel-xe] [PATCH 0/5] RPLS and other minor support Anusha Srivatsa
                   ` (5 preceding siblings ...)
  2023-05-26 21:17 ` [Intel-xe] ✓ CI.Patch_applied: success for RPLS and other minor support (rev2) Patchwork
@ 2023-05-26 21:18 ` Patchwork
  6 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2023-05-26 21:18 UTC (permalink / raw)
  To: Anusha Srivatsa; +Cc: intel-xe

== Series Details ==

Series: RPLS and other minor support (rev2)
URL   : https://patchwork.freedesktop.org/series/118442/
State : failure

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
stty: 'standard input': Inappropriate ioctl for device
[21:18:10] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:18:14] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[21:18:36] Starting KUnit Kernel (1/1)...
[21:18:36] ============================================================
[21:18:36] ==================== xe_bo (2 subtests) ====================
[21:18:36] [SKIPPED] xe_ccs_migrate_kunit
[21:18:36] [SKIPPED] xe_bo_evict_kunit
[21:18:36] ===================== [SKIPPED] xe_bo ======================
[21:18:36] ================== xe_dma_buf (1 subtest) ==================
[21:18:36] [SKIPPED] xe_dma_buf_kunit
[21:18:36] =================== [SKIPPED] xe_dma_buf ===================
[21:18:36] ================== xe_migrate (1 subtest) ==================
[21:18:36] [SKIPPED] xe_migrate_sanity_kunit
[21:18:36] =================== [SKIPPED] xe_migrate ===================
[21:18:36] =================== xe_pci (2 subtests) ====================
[21:18:36] [PASSED] xe_gmdid_graphics_ip
[21:18:36] [PASSED] xe_gmdid_media_ip
[21:18:36] ===================== [PASSED] xe_pci ======================
[21:18:36] ==================== xe_rtp (1 subtest) ====================
[21:18:36] ================== xe_rtp_process_tests  ===================
[21:18:36] [PASSED] coalesce-same-reg
[21:18:36] [PASSED] no-match-no-add
[21:18:36] [PASSED] no-match-no-add-multiple-rules
[21:18:36] [PASSED] two-regs-two-entries
[21:18:36] [PASSED] clr-one-set-other
[21:18:36] [PASSED] set-field
[21:18:36] [PASSED] conflict-duplicate
[21:18:36] [PASSED] conflict-not-disjoint
[21:18:36] [PASSED] conflict-reg-type
[21:18:36] ============== [PASSED] xe_rtp_process_tests ===============
[21:18:36] ===================== [PASSED] xe_rtp ======================
[21:18:36] ==================== xe_wa (1 subtest) =====================
[21:18:36] ======================== xe_wa_gt  =========================
[21:18:36] [PASSED] TIGERLAKE (B0)
[21:18:36] [PASSED] DG1 (A0)
[21:18:36] [PASSED] DG1 (B0)
[21:18:36] # xe_wa_gt: ASSERTION FAILED at drivers/gpu/drm/xe/tests/xe_wa_test.c:91
[21:18:36] Expected ret == 0, but
[21:18:36]     ret == -19 (0xffffffffffffffed)
[21:18:36] [FAILED] ALDERLAKE_S (A0)
[21:18:36] # xe_wa_gt: ASSERTION FAILED at drivers/gpu/drm/xe/tests/xe_wa_test.c:91
[21:18:36] Expected ret == 0, but
[21:18:36]     ret == -19 (0xffffffffffffffed)
[21:18:36] [FAILED] ALDERLAKE_S (B0)
[21:18:36] # xe_wa_gt: ASSERTION FAILED at drivers/gpu/drm/xe/tests/xe_wa_test.c:91
[21:18:36] Expected ret == 0, but
[21:18:36]     ret == -19 (0xffffffffffffffed)
[21:18:36] [FAILED] ALDERLAKE_S (C0)
[21:18:36] # xe_wa_gt: ASSERTION FAILED at drivers/gpu/drm/xe/tests/xe_wa_test.c:91
[21:18:36] Expected ret == 0, but
[21:18:36]     ret == -19 (0xffffffffffffffed)
[21:18:36] [FAILED] ALDERLAKE_S (D0)
[21:18:36] # xe_wa_gt: ASSERTION FAILED at drivers/gpu/drm/xe/tests/xe_wa_test.c:91
[21:18:36] Expected ret == 0, but
[21:18:36]     ret == -19 (0xffffffffffffffed)
[21:18:36] [FAILED] ALDERLAKE_P (A0)
[21:18:36] # xe_wa_gt: ASSERTION FAILED at drivers/gpu/drm/xe/tests/xe_wa_test.c:91
[21:18:36] Expected ret == 0, but
[21:18:36]     ret == -19 (0xffffffffffffffed)
[21:18:36] [FAILED] ALDERLAKE_P (B0)
[21:18:36] # xe_wa_gt: ASSERTION FAILED at drivers/gpu/drm/xe/tests/xe_wa_test.c:91
[21:18:36] Expected ret == 0, but
[21:18:36]     ret == -19 (0xffffffffffffffed)
[21:18:36] [FAILED] ALDERLAKE_P (C0)
[21:18:36] [PASSED] ALDERLAKE_S_RPLS (D0)
[21:18:36] [PASSED] ALDERLAKE_P_RPLU (E0)
[21:18:36] [PASSED] DG2_G10 (A0)
[21:18:36] [PASSED] DG2_G10 (A1)
[21:18:36] [PASSED] DG2_G10 (B0)
[21:18:36] [PASSED] DG2_G10 (C0)
[21:18:36] [PASSED] DG2_G11 (A0)
[21:18:36] [PASSED] DG2_G11 (B0)
[21:18:36] [PASSED] DG2_G11 (B1)
[21:18:36] [PASSED] DG2_G12 (A0)
[21:18:36] [PASSED] DG2_G12 (A1)
[21:18:36] [PASSED] PVC (B0)
[21:18:36] [PASSED] PVC (B1)
[21:18:36] [PASSED] PVC (C0)
[21:18:36] # xe_wa_gt: pass:17 fail:7 skip:0 total:24
[21:18:36] ==================== [FAILED] xe_wa_gt =====================
[21:18:36] # Totals: pass:17 fail:7 skip:0 total:24
[21:18:36] ====================== [FAILED] xe_wa ======================
[21:18:36] ============================================================
[21:18:36] Testing complete. Ran 39 tests: passed: 28, failed: 7, skipped: 4
[21:18:36] Elapsed time: 26.496s total, 4.246s configuring, 22.130s building, 0.099s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [Intel-xe] [PATCH 1/5] drm/xe/adlp: s/ADLP/ALDERLAKE_P
  2023-05-26 21:17 ` [Intel-xe] [PATCH 1/5] drm/xe/adlp: s/ADLP/ALDERLAKE_P Anusha Srivatsa
@ 2023-05-29  8:00   ` Jani Nikula
  0 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2023-05-29  8:00 UTC (permalink / raw)
  To: Anusha Srivatsa, intel-xe; +Cc: Anusha Srivatsa, Lucas De Marchi

On Fri, 26 May 2023, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> Inconsistent usage of platform names across the driver.
> Changing to use the name convention throughout - ALDERLAKE_P.
> This will make it easier for macro magic usages.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 2 +-

Changes to this file needs to be split up as fixup to xe display
enabling.

>  drivers/gpu/drm/xe/xe_pci.c                       | 2 +-
>  drivers/gpu/drm/xe/xe_platform_types.h            | 2 +-
>  drivers/gpu/drm/xe/xe_step.c                      | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> index 74e6f063f741..9d212fbbce26 100644
> --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> @@ -160,7 +160,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
>  #define IS_DG2_G10(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G10)
>  #define IS_DG2_G11(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G11)
>  #define IS_DG2_G12(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G12)
> -#define IS_ADLP_RPLU(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_ADLP_RPLU)
> +#define IS_ALDERLAKE_P_RPLU(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU)
>  #define IS_ICL_WITH_PORT_F(xe) (xe && 0)
>  #define HAS_LSPCON(xe) (xe && 0)
>  #define HAS_MSO(xe) (xe || 1)
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index d8f1213ae1d6..33027091cc30 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -213,7 +213,7 @@ static const struct xe_device_desc adl_p_desc = {
>  	.has_llc = true,
>  	.require_force_probe = true,
>  	.subplatforms = (const struct xe_subplatform_desc[]) {
> -		{ XE_SUBPLATFORM_ADLP_RPLU, "RPLU", adlp_rplu_ids },
> +		{ XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
>  		{},
>  	},
>  };
> diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
> index abbb8a1f29a8..cb50e9b77816 100644
> --- a/drivers/gpu/drm/xe/xe_platform_types.h
> +++ b/drivers/gpu/drm/xe/xe_platform_types.h
> @@ -26,7 +26,7 @@ enum xe_platform {
>  enum xe_subplatform {
>  	XE_SUBPLATFORM_UNINITIALIZED = 0,
>  	XE_SUBPLATFORM_NONE,
> -	XE_SUBPLATFORM_ADLP_RPLU,
> +	XE_SUBPLATFORM_ALDERLAKE_P_RPLU,
>  	XE_SUBPLATFORM_DG2_G10,
>  	XE_SUBPLATFORM_DG2_G11,
>  	XE_SUBPLATFORM_DG2_G12,
> diff --git a/drivers/gpu/drm/xe/xe_step.c b/drivers/gpu/drm/xe/xe_step.c
> index 1baf79ba02ad..cb0811c8bf22 100644
> --- a/drivers/gpu/drm/xe/xe_step.c
> +++ b/drivers/gpu/drm/xe/xe_step.c
> @@ -143,7 +143,7 @@ struct xe_step_info xe_step_pre_gmdid_get(struct xe_device *xe)
>  	} else if (xe->info.platform == XE_ALDERLAKE_N) {
>  		revids = adln_revids;
>  		size = ARRAY_SIZE(adln_revids);
> -	} else if (xe->info.subplatform == XE_SUBPLATFORM_ADLP_RPLU) {
> +	} else if (xe->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU) {
>  		revids = adlp_rpl_revids;
>  		size = ARRAY_SIZE(adlp_rpl_revids);
>  	} else if (xe->info.platform == XE_ALDERLAKE_P) {

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [Intel-xe] [PATCH 2/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P
  2023-05-26 21:17 ` [Intel-xe] [PATCH 2/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P Anusha Srivatsa
@ 2023-05-29  8:01   ` Jani Nikula
  0 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2023-05-29  8:01 UTC (permalink / raw)
  To: Anusha Srivatsa, intel-xe; +Cc: Anusha Srivatsa, Lucas De Marchi

On Fri, 26 May 2023, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> Refer to platform with the same consistent name.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

Send this first to intel-gfx, get it merged to i915, and then
cherry-pick -x backport it to xe.

Otherwise, please avoid i915 changes in the xe branch.

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
>  drivers/gpu/drm/i915/i915_drv.h            | 2 +-
>  drivers/gpu/drm/i915/intel_step.c          | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f6223d8f13b8..bb0d8cd7034e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3409,7 +3409,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  		/* Wa_22011320316:adl-p[a0] */
>  		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  			dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
> -		else if (IS_ADLP_RPLU(dev_priv))
> +		else if (IS_ALDERLAKE_P_RPLU(dev_priv))
>  			dev_priv->display.cdclk.table = rplu_cdclk_table;
>  		else
>  			dev_priv->display.cdclk.table = adlp_cdclk_table;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 14c5338c96a6..e870dd412a75 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -578,7 +578,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
>  #define IS_ADLP_N(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
> -#define IS_ADLP_RPLP(i915) \
> +#define IS_ALDERLAKE_P_RPLU(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
>  #define IS_ADLP_RPLU(i915) \
>  	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
> diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
> index 84a6fe736a3b..6a8816fbc15a 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -191,7 +191,7 @@ void intel_step_init(struct drm_i915_private *i915)
>  	} else if (IS_ADLP_N(i915)) {
>  		revids = adlp_n_revids;
>  		size = ARRAY_SIZE(adlp_n_revids);
> -	} else if (IS_ADLP_RPLP(i915)) {
> +	} else if (IS_ALDERLAKE_P_RPLU(i915)) {
>  		revids = adlp_rplp_revids;
>  		size = ARRAY_SIZE(adlp_rplp_revids);
>  	} else if (IS_ALDERLAKE_P(i915)) {

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-05-29  8:01 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-26 21:17 [Intel-xe] [PATCH 0/5] RPLS and other minor support Anusha Srivatsa
2023-05-26 21:17 ` [Intel-xe] [PATCH 1/5] drm/xe/adlp: s/ADLP/ALDERLAKE_P Anusha Srivatsa
2023-05-29  8:00   ` Jani Nikula
2023-05-26 21:17 ` [Intel-xe] [PATCH 2/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P Anusha Srivatsa
2023-05-29  8:01   ` Jani Nikula
2023-05-26 21:17 ` [Intel-xe] [PATCH 3/5] drm/xe/rpls: Add RPLS Support Anusha Srivatsa
2023-05-26 21:17 ` [Intel-xe] [PATCH 4/5] drm/xe/rpls: Add Stepping info for RPLS Anusha Srivatsa
2023-05-26 21:17 ` [Intel-xe] [PATCH 5/5] drm/xe: Add missing ADL entries to xe_test_wa Anusha Srivatsa
2023-05-26 21:17 ` [Intel-xe] ✓ CI.Patch_applied: success for RPLS and other minor support (rev2) Patchwork
2023-05-26 21:18 ` [Intel-xe] ✗ CI.KUnit: failure " Patchwork

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