[PATCH 0/2] spapr: Fix support of POWER5+ processors

[PATCH 0/2] spapr: Fix support of POWER5+ processors

[Cédric Le Goater]

Hello,

Grab the images under : 

  https://github.com/legoater/qemu-ppc-boot/tree/main/buildroot/qemu_ppc64_pseries_p5p-2021.11-730-g4f325ce788-20220104

and run with :

  qemu-system-ppc64 -M pseries -cpu POWER5+ -m 1G -smp 2 -kernel ./vmlinux -append "root=/dev/sda" -drive file=./rootfs.ext2,if=scsi,index=0,format=raw  -device spapr-vlan,netdev=net0 -netdev user,id=net0 -serial mon:stdio -nographic -nodefaults

CPU 970, 970MP are also well supported. 

Virtio devices and USB should be avoided because SLOF would use a
'stdbrx' instruction (cpu_to_le64 helper) which is invalid under
POWER5+ and 970 CPUs. SLOF needs to be compiled with -mcpu=power5 to
fix this issue.

Thanks,

C. 

Cédric Le Goater (2):
  target/ppc: Add popcntb instruction to POWER5+ processors
  spapr: Fix support of POWER5+ processors

 hw/ppc/spapr.c        | 10 ++++++----
 target/ppc/cpu_init.c |  1 +
 2 files changed, 7 insertions(+), 4 deletions(-)

-- 
2.31.1

[PATCH 1/2] target/ppc: Add popcntb instruction to POWER5+ processors

[Cédric Le Goater]

popcntb instruction was added in ISA v2.02. Add support for POWER5+
processors since they implement ISA v2.03.

PPC970 CPUs implement v2.01 and do not support popcntb.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 target/ppc/cpu_init.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index cc93bff3fac4..f15a52259c90 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6957,6 +6957,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
                        PPC_64B |
+                       PPC_POPCNTB |
                        PPC_SEGMENT_64B | PPC_SLBI;
     pcc->insns_flags2 = PPC2_FP_CVT_S64;
     pcc->msr_mask = (1ull << MSR_SF) |
-- 
2.31.1

[PATCH 2/2] spapr: Fix support of POWER5+ processors

[Cédric Le Goater]

POWER5+ (ISA v2.03) processors are supported by the pseries machine
but they do not have Altivec instructions. Do not advertise support
for it in the DT.

To be noted that this test is in contradiction with the assert in
cap_vsx_apply().

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/spapr.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 3b5fd749be89..69c9e1c59f5e 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -723,10 +723,12 @@ static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset,
      *
      * Only CPUs for which we create core types in spapr_cpu_core.c
      * are possible, and all of those have VMX */
-    if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
-        _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
-    } else {
-        _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
+    if (env->insns_flags & PPC_ALTIVEC) {
+        if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
+            _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
+        } else {
+            _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
+        }
     }
 
     /* Advertise DFP (Decimal Floating Point) if available
-- 
2.31.1

Re: [PATCH 1/2] target/ppc: Add popcntb instruction to POWER5+ processors

[Fabiano Rosas]

Cédric Le Goater <clg@kaod.org> writes:

> popcntb instruction was added in ISA v2.02. Add support for POWER5+
> processors since they implement ISA v2.03.
>
> PPC970 CPUs implement v2.01 and do not support popcntb.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>

Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>

Re: [PATCH 2/2] spapr: Fix support of POWER5+ processors

[Fabiano Rosas]

Cédric Le Goater <clg@kaod.org> writes:

> POWER5+ (ISA v2.03) processors are supported by the pseries machine
> but they do not have Altivec instructions. Do not advertise support
> for it in the DT.
>
> To be noted that this test is in contradiction with the assert in
> cap_vsx_apply().
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>

Tested-by: Fabiano Rosas <farosas@linux.ibm.com>

Re: [PATCH 0/2] spapr: Fix support of POWER5+ processors

[Cédric Le Goater]

On 1/5/22 10:51, Cédric Le Goater wrote:
> Hello,
> 
> Grab the images under :
> 
>    https://github.com/legoater/qemu-ppc-boot/tree/main/buildroot/qemu_ppc64_pseries_p5p-2021.11-730-g4f325ce788-20220104
> 
> and run with :
> 
>    qemu-system-ppc64 -M pseries -cpu POWER5+ -m 1G -smp 2 -kernel ./vmlinux -append "root=/dev/sda" -drive file=./rootfs.ext2,if=scsi,index=0,format=raw  -device spapr-vlan,netdev=net0 -netdev user,id=net0 -serial mon:stdio -nographic -nodefaults
> 
> CPU 970, 970MP are also well supported.
> 
> Virtio devices and USB should be avoided because SLOF would use a
> 'stdbrx' instruction (cpu_to_le64 helper) which is invalid under
> POWER5+ and 970 CPUs. SLOF needs to be compiled with -mcpu=power5 to
> fix this issue.
> 
> Thanks,
> 
> C.
> 
> Cédric Le Goater (2):
>    target/ppc: Add popcntb instruction to POWER5+ processors
>    spapr: Fix support of POWER5+ processors
> 
>   hw/ppc/spapr.c        | 10 ++++++----
>   target/ppc/cpu_init.c |  1 +
>   2 files changed, 7 insertions(+), 4 deletions(-)
> 



Applied to ppc7.0.

Thanks,

C.