* [PATCH] drm/i915/dp: fall back to 18 bpp when sink capability is unknown
@ 2016-01-13 14:35 Jani Nikula
2016-01-13 15:05 ` Ville Syrjälä
2016-01-13 15:13 ` ✗ failure: Fi.CI.BAT Patchwork
0 siblings, 2 replies; 6+ messages in thread
From: Jani Nikula @ 2016-01-13 14:35 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Per DP spec, the source device should fall back to 18 bpp, VESA range
RGB when the sink capability is unknown. Fix the color depth
clamping. 18 bpp color depth should ensure full color range in automatic
mode.
The clamping has been HDMI specific since its introduction in
commit 996a2239f93b03c5972923f04b097f65565c5bed
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Fri Apr 19 11:24:34 2013 +0200
drm/i915: Disable high-bpc on pre-1.4 EDID screens
Cc: stable@vger.kernel.org
Reported-by: Dihan Wickremasuriya <nayomal@gmail.com>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=105331
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 07ca19b0ec17..6eaecd9385ab 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12171,11 +12171,21 @@ connected_sink_compute_bpp(struct intel_connector *connector,
pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
}
- /* Clamp bpp to 8 on screens without EDID 1.4 */
- if (connector->base.display_info.bpc == 0 && bpp > 24) {
- DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
- bpp);
- pipe_config->pipe_bpp = 24;
+ /* Clamp bpp to default limit on screens without EDID 1.4 */
+ if (connector->base.display_info.bpc == 0) {
+ int type = connector->base.connector_type;
+ int clamp_bpp = 24;
+
+ /* Fall back to 18 bpp when DP sink capability is unknown. */
+ if (type == DRM_MODE_CONNECTOR_DisplayPort ||
+ type == DRM_MODE_CONNECTOR_eDP)
+ clamp_bpp = 18;
+
+ if (bpp > clamp_bpp) {
+ DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
+ bpp, clamp_bpp);
+ pipe_config->pipe_bpp = clamp_bpp;
+ }
}
}
--
2.1.4
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/dp: fall back to 18 bpp when sink capability is unknown
2016-01-13 14:35 [PATCH] drm/i915/dp: fall back to 18 bpp when sink capability is unknown Jani Nikula
@ 2016-01-13 15:05 ` Ville Syrjälä
2016-01-15 9:44 ` Jani Nikula
2016-01-13 15:13 ` ✗ failure: Fi.CI.BAT Patchwork
1 sibling, 1 reply; 6+ messages in thread
From: Ville Syrjälä @ 2016-01-13 15:05 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Jan 13, 2016 at 04:35:20PM +0200, Jani Nikula wrote:
> Per DP spec, the source device should fall back to 18 bpp, VESA range
> RGB when the sink capability is unknown. Fix the color depth
> clamping. 18 bpp color depth should ensure full color range in automatic
> mode.
>
> The clamping has been HDMI specific since its introduction in
>
> commit 996a2239f93b03c5972923f04b097f65565c5bed
> Author: Daniel Vetter <daniel.vetter@ffwll.ch>
> Date: Fri Apr 19 11:24:34 2013 +0200
>
> drm/i915: Disable high-bpc on pre-1.4 EDID screens
>
> Cc: stable@vger.kernel.org
> Reported-by: Dihan Wickremasuriya <nayomal@gmail.com>
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=105331
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Makes sense to me as far as the spec is concerned.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++-----
> 1 file changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 07ca19b0ec17..6eaecd9385ab 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12171,11 +12171,21 @@ connected_sink_compute_bpp(struct intel_connector *connector,
> pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
> }
>
> - /* Clamp bpp to 8 on screens without EDID 1.4 */
> - if (connector->base.display_info.bpc == 0 && bpp > 24) {
> - DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
> - bpp);
> - pipe_config->pipe_bpp = 24;
> + /* Clamp bpp to default limit on screens without EDID 1.4 */
> + if (connector->base.display_info.bpc == 0) {
> + int type = connector->base.connector_type;
> + int clamp_bpp = 24;
> +
> + /* Fall back to 18 bpp when DP sink capability is unknown. */
> + if (type == DRM_MODE_CONNECTOR_DisplayPort ||
> + type == DRM_MODE_CONNECTOR_eDP)
> + clamp_bpp = 18;
> +
> + if (bpp > clamp_bpp) {
> + DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
> + bpp, clamp_bpp);
> + pipe_config->pipe_bpp = clamp_bpp;
> + }
> }
> }
>
> --
> 2.1.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ failure: Fi.CI.BAT
2016-01-13 14:35 [PATCH] drm/i915/dp: fall back to 18 bpp when sink capability is unknown Jani Nikula
2016-01-13 15:05 ` Ville Syrjälä
@ 2016-01-13 15:13 ` Patchwork
2016-01-13 16:17 ` Daniel Vetter
1 sibling, 1 reply; 6+ messages in thread
From: Patchwork @ 2016-01-13 15:13 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Summary ==
Built on 4d09810b01441f9124c072a866f608b748f92f6c drm-intel-nightly: 2016y-01m-13d-12h-32m-08s UTC integration manifest
Test gem_ctx_basic:
pass -> FAIL (hsw-gt2)
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (skl-i7k-2) UNSTABLE
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c:
pass -> DMESG-WARN (bdw-ultra)
bdw-nuci7 total:138 pass:129 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:131 dwarn:1 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:136 dwarn:0 dfail:0 fail:1 skip:4
hsw-xps12 total:138 pass:133 dwarn:1 dfail:0 fail:0 skip:4
ilk-hp8440p total:141 pass:100 dwarn:4 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:132 dwarn:1 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:132 dwarn:1 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1170/
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: ✗ failure: Fi.CI.BAT
2016-01-13 15:13 ` ✗ failure: Fi.CI.BAT Patchwork
@ 2016-01-13 16:17 ` Daniel Vetter
2016-01-13 18:03 ` Chris Wilson
0 siblings, 1 reply; 6+ messages in thread
From: Daniel Vetter @ 2016-01-13 16:17 UTC (permalink / raw)
To: Patchwork; +Cc: Jani Nikula, intel-gfx
On Wed, Jan 13, 2016 at 03:13:40PM -0000, Patchwork wrote:
> == Summary ==
>
> Built on 4d09810b01441f9124c072a866f608b748f92f6c drm-intel-nightly: 2016y-01m-13d-12h-32m-08s UTC integration manifest
>
> Test gem_ctx_basic:
> pass -> FAIL (hsw-gt2)
This seems to be a complete fluke. I looked at detailed results and
there's simply no output. Long-term history doesn't show a failure either.
I think we can shrug this one off (for now at least).
> Test gem_storedw_loop:
> Subgroup basic-render:
> dmesg-warn -> PASS (skl-i7k-2) UNSTABLE
> Test kms_pipe_crc_basic:
> Subgroup read-crc-pipe-c:
> pass -> DMESG-WARN (bdw-ultra)
https://bugs.freedesktop.org/show_bug.cgi?id=93699
So looks good, I'll apply the patch.
-Daniel
>
> bdw-nuci7 total:138 pass:129 dwarn:0 dfail:0 fail:0 skip:9
> bdw-ultra total:138 pass:131 dwarn:1 dfail:0 fail:0 skip:6
> bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
> hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
> hsw-gt2 total:141 pass:136 dwarn:0 dfail:0 fail:1 skip:4
> hsw-xps12 total:138 pass:133 dwarn:1 dfail:0 fail:0 skip:4
> ilk-hp8440p total:141 pass:100 dwarn:4 dfail:0 fail:0 skip:37
> ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
> skl-i5k-2 total:141 pass:132 dwarn:1 dfail:0 fail:0 skip:8
> skl-i7k-2 total:141 pass:132 dwarn:1 dfail:0 fail:0 skip:8
> snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
> snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
>
> Results at /archive/results/CI_IGT_test/Patchwork_1170/
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: ✗ failure: Fi.CI.BAT
2016-01-13 16:17 ` Daniel Vetter
@ 2016-01-13 18:03 ` Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2016-01-13 18:03 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Jani Nikula, intel-gfx
On Wed, Jan 13, 2016 at 05:17:03PM +0100, Daniel Vetter wrote:
> On Wed, Jan 13, 2016 at 03:13:40PM -0000, Patchwork wrote:
> > == Summary ==
> >
> > Built on 4d09810b01441f9124c072a866f608b748f92f6c drm-intel-nightly: 2016y-01m-13d-12h-32m-08s UTC integration manifest
> >
> > Test gem_ctx_basic:
> > pass -> FAIL (hsw-gt2)
>
> This seems to be a complete fluke. I looked at detailed results and
> there's simply no output. Long-term history doesn't show a failure either.
>
> I think we can shrug this one off (for now at least).
>
> > Test gem_storedw_loop:
> > Subgroup basic-render:
> > dmesg-warn -> PASS (skl-i7k-2) UNSTABLE
> > Test kms_pipe_crc_basic:
> > Subgroup read-crc-pipe-c:
> > pass -> DMESG-WARN (bdw-ultra)
>
> https://bugs.freedesktop.org/show_bug.cgi?id=93699
>
> So looks good, I'll apply the patch.
It still does a blocking context-close when all it need do is keep the
last-context pinned until replaced.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/dp: fall back to 18 bpp when sink capability is unknown
2016-01-13 15:05 ` Ville Syrjälä
@ 2016-01-15 9:44 ` Jani Nikula
0 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2016-01-15 9:44 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, 13 Jan 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Jan 13, 2016 at 04:35:20PM +0200, Jani Nikula wrote:
>> Per DP spec, the source device should fall back to 18 bpp, VESA range
>> RGB when the sink capability is unknown. Fix the color depth
>> clamping. 18 bpp color depth should ensure full color range in automatic
>> mode.
>>
>> The clamping has been HDMI specific since its introduction in
>>
>> commit 996a2239f93b03c5972923f04b097f65565c5bed
>> Author: Daniel Vetter <daniel.vetter@ffwll.ch>
>> Date: Fri Apr 19 11:24:34 2013 +0200
>>
>> drm/i915: Disable high-bpc on pre-1.4 EDID screens
>>
>> Cc: stable@vger.kernel.org
>> Reported-by: Dihan Wickremasuriya <nayomal@gmail.com>
>> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=105331
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Makes sense to me as far as the spec is concerned.
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Also got Tested-by in the bug. Pushed to drm-intel-next-queued, thanks
for the review.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++-----
>> 1 file changed, 15 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 07ca19b0ec17..6eaecd9385ab 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -12171,11 +12171,21 @@ connected_sink_compute_bpp(struct intel_connector *connector,
>> pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
>> }
>>
>> - /* Clamp bpp to 8 on screens without EDID 1.4 */
>> - if (connector->base.display_info.bpc == 0 && bpp > 24) {
>> - DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
>> - bpp);
>> - pipe_config->pipe_bpp = 24;
>> + /* Clamp bpp to default limit on screens without EDID 1.4 */
>> + if (connector->base.display_info.bpc == 0) {
>> + int type = connector->base.connector_type;
>> + int clamp_bpp = 24;
>> +
>> + /* Fall back to 18 bpp when DP sink capability is unknown. */
>> + if (type == DRM_MODE_CONNECTOR_DisplayPort ||
>> + type == DRM_MODE_CONNECTOR_eDP)
>> + clamp_bpp = 18;
>> +
>> + if (bpp > clamp_bpp) {
>> + DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
>> + bpp, clamp_bpp);
>> + pipe_config->pipe_bpp = clamp_bpp;
>> + }
>> }
>> }
>>
>> --
>> 2.1.4
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-01-15 9:44 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-01-13 14:35 [PATCH] drm/i915/dp: fall back to 18 bpp when sink capability is unknown Jani Nikula
2016-01-13 15:05 ` Ville Syrjälä
2016-01-15 9:44 ` Jani Nikula
2016-01-13 15:13 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-13 16:17 ` Daniel Vetter
2016-01-13 18:03 ` Chris Wilson
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