From: ebiederm@xmission.com (Eric W. Biederman)
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: HATAYAMA Daisuke <d.hatayama@jp.fujitsu.com>,
linux-kernel@vger.kernel.org, kexec@lists.infradead.org,
x86@kernel.org, mingo@elte.hu, tglx@linutronix.de,
len.brown@intel.com, fenghua.yu@intel.com, vgoyal@redhat.com,
grant.likely@secretlab.ca, rob.herring@calxeda.com
Subject: Re: [PATCH v1 2/2] x86, apic: Disable BSP if boot cpu is AP
Date: Mon, 22 Oct 2012 13:43:21 -0700 [thread overview]
Message-ID: <87a9vedyqe.fsf@xmission.com> (raw)
In-Reply-To: <5085AD7D.106@zytor.com> (H. Peter Anvin's message of "Mon, 22 Oct 2012 13:33:01 -0700")
"H. Peter Anvin" <hpa@zytor.com> writes:
> On 10/22/2012 01:31 PM, Eric W. Biederman wrote:
>>>
>>> IIRC Fenghua experimented with that and it didn't work. Not all BIOSes
>>> use that bit to determine BSP-ness.
>>
>> What does a BIOS have to do with anything?
>>
>> The practical issue here is does an INIT IPI cause the cpu to go into
>> startup-ipi-wait or to start booting at 4G-16 bytes.
>>
>> For dealing with BIOSen we may still need to use the bootstrap processor
>> for firmware calls, cpu suspend, and other firmware weirdness, but that
>> should all be completely orthogonal to the behavior to what happens
>> when an INIT IPI is sent to the cpu.
>>
>> The only firmware problem I can imagine having is cpu virtualization
>> bug.
>>
>
> The whole problem is that some BIOSes go wonky after receiving an INIT
> (as in INIT-SIPI-SIPI) to the BSP.
The reason the BIOSen go wonky is the INIT cause the cpu to go to the
reset vector at 4G-16 bytes. So it is very much expected that the
BIOSen start acting like you just came out of reset.
If you can clear bit 8 of IA32_APIC_BASE_MSR and inform the cpu to not
send the cpu to 4G-16 bytes and instead send the cpu into it's magic
startup-ipi-wait mode then the BIOSen will not be involved on that path.
It is a simple question of does the cpu support clearing bit 8
meaningfully.
If the cpu allows bit 8 to be cleared and sends the cpu to the reset
vector on receipt of the INIT IPI I would call that a deviation from the
x86 cpu specification.
So clearing bit 8 is not a question about BIOSen it is a question of can
we avoid the BIOSen, by using an obscure under-documented cpu feature.
Eric
WARNING: multiple messages have this Message-ID (diff)
From: ebiederm@xmission.com (Eric W. Biederman)
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: len.brown@intel.com, fenghua.yu@intel.com, x86@kernel.org,
kexec@lists.infradead.org, linux-kernel@vger.kernel.org,
rob.herring@calxeda.com, grant.likely@secretlab.ca,
HATAYAMA Daisuke <d.hatayama@jp.fujitsu.com>,
tglx@linutronix.de, mingo@elte.hu, vgoyal@redhat.com
Subject: Re: [PATCH v1 2/2] x86, apic: Disable BSP if boot cpu is AP
Date: Mon, 22 Oct 2012 13:43:21 -0700 [thread overview]
Message-ID: <87a9vedyqe.fsf@xmission.com> (raw)
In-Reply-To: <5085AD7D.106@zytor.com> (H. Peter Anvin's message of "Mon, 22 Oct 2012 13:33:01 -0700")
"H. Peter Anvin" <hpa@zytor.com> writes:
> On 10/22/2012 01:31 PM, Eric W. Biederman wrote:
>>>
>>> IIRC Fenghua experimented with that and it didn't work. Not all BIOSes
>>> use that bit to determine BSP-ness.
>>
>> What does a BIOS have to do with anything?
>>
>> The practical issue here is does an INIT IPI cause the cpu to go into
>> startup-ipi-wait or to start booting at 4G-16 bytes.
>>
>> For dealing with BIOSen we may still need to use the bootstrap processor
>> for firmware calls, cpu suspend, and other firmware weirdness, but that
>> should all be completely orthogonal to the behavior to what happens
>> when an INIT IPI is sent to the cpu.
>>
>> The only firmware problem I can imagine having is cpu virtualization
>> bug.
>>
>
> The whole problem is that some BIOSes go wonky after receiving an INIT
> (as in INIT-SIPI-SIPI) to the BSP.
The reason the BIOSen go wonky is the INIT cause the cpu to go to the
reset vector at 4G-16 bytes. So it is very much expected that the
BIOSen start acting like you just came out of reset.
If you can clear bit 8 of IA32_APIC_BASE_MSR and inform the cpu to not
send the cpu to 4G-16 bytes and instead send the cpu into it's magic
startup-ipi-wait mode then the BIOSen will not be involved on that path.
It is a simple question of does the cpu support clearing bit 8
meaningfully.
If the cpu allows bit 8 to be cleared and sends the cpu to the reset
vector on receipt of the INIT IPI I would call that a deviation from the
x86 cpu specification.
So clearing bit 8 is not a question about BIOSen it is a question of can
we avoid the BIOSen, by using an obscure under-documented cpu feature.
Eric
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next prev parent reply other threads:[~2012-10-22 20:43 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-16 4:35 [PATCH v1 0/2] x86, apic: Disable BSP if boot cpu is AP HATAYAMA Daisuke
2012-10-16 4:35 ` HATAYAMA Daisuke
2012-10-16 4:35 ` [PATCH v1 1/2] x86, apic: Introduce boot_cpu_is_bsp indicating whether boot cpu is BSP or not HATAYAMA Daisuke
2012-10-16 4:35 ` HATAYAMA Daisuke
2012-10-16 4:35 ` [PATCH v1 2/2] x86, apic: Disable BSP if boot cpu is AP HATAYAMA Daisuke
2012-10-16 4:35 ` HATAYAMA Daisuke
2012-10-22 20:04 ` Eric W. Biederman
2012-10-22 20:04 ` Eric W. Biederman
2012-10-22 20:16 ` H. Peter Anvin
2012-10-22 20:16 ` H. Peter Anvin
2012-10-22 20:31 ` Eric W. Biederman
2012-10-22 20:31 ` Eric W. Biederman
2012-10-22 20:33 ` H. Peter Anvin
2012-10-22 20:33 ` H. Peter Anvin
2012-10-22 20:38 ` H. Peter Anvin
2012-10-22 20:38 ` H. Peter Anvin
2012-10-22 20:43 ` Eric W. Biederman [this message]
2012-10-22 20:43 ` Eric W. Biederman
2012-10-22 20:47 ` H. Peter Anvin
2012-10-22 20:47 ` H. Peter Anvin
2012-10-22 21:29 ` Eric W. Biederman
2012-10-22 21:29 ` Eric W. Biederman
2012-10-23 0:35 ` H. Peter Anvin
2012-10-23 0:35 ` H. Peter Anvin
2012-10-26 3:24 ` HATAYAMA Daisuke
2012-10-26 3:24 ` HATAYAMA Daisuke
2012-10-26 4:13 ` Eric W. Biederman
2012-10-26 4:13 ` Eric W. Biederman
2013-03-11 1:07 ` HATAYAMA Daisuke
2013-03-11 1:07 ` HATAYAMA Daisuke
2013-03-11 2:13 ` HATAYAMA Daisuke
2013-03-11 2:13 ` HATAYAMA Daisuke
2013-03-11 4:11 ` H. Peter Anvin
2013-03-11 4:11 ` H. Peter Anvin
2012-10-16 4:51 ` [PATCH v1 0/2] " Yu, Fenghua
2012-10-16 4:51 ` Yu, Fenghua
2012-10-16 5:03 ` HATAYAMA Daisuke
2012-10-16 5:03 ` HATAYAMA Daisuke
2012-10-16 5:14 ` Yu, Fenghua
2012-10-16 5:14 ` Yu, Fenghua
2012-10-16 6:38 ` HATAYAMA Daisuke
2012-10-16 6:38 ` HATAYAMA Daisuke
2012-10-22 16:02 ` H. Peter Anvin
2012-10-22 16:02 ` H. Peter Anvin
2012-10-16 5:15 ` HATAYAMA Daisuke
2012-10-16 5:15 ` HATAYAMA Daisuke
2012-10-17 14:12 ` Vivek Goyal
2012-10-17 14:12 ` Vivek Goyal
2012-10-18 3:08 ` HATAYAMA Daisuke
2012-10-18 3:08 ` HATAYAMA Daisuke
2012-10-18 14:14 ` Vivek Goyal
2012-10-18 14:14 ` Vivek Goyal
2012-10-19 3:20 ` HATAYAMA Daisuke
2012-10-19 3:20 ` HATAYAMA Daisuke
2012-10-19 15:17 ` Vivek Goyal
2012-10-19 15:17 ` Vivek Goyal
2012-10-22 6:32 ` HATAYAMA Daisuke
2012-10-22 6:32 ` HATAYAMA Daisuke
2012-10-22 18:37 ` Vivek Goyal
2012-10-22 18:37 ` Vivek Goyal
2012-10-22 17:10 ` Michael Holzheu
2012-10-22 17:10 ` Michael Holzheu
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