From: Michael Walle <michael@walle.cc> To: Tudor Ambarus <tudor.ambarus@microchip.com> Cc: p.yadav@ti.com, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, nicolas.ferre@microchip.com Subject: Re: [PATCH v3 7/9] mtd: spi-nor: micron-st: Rework spi_nor_micron_octal_dtr_enable() Date: Tue, 19 Apr 2022 13:43:39 +0200 [thread overview] Message-ID: <87be34dac82aaeaf7c72c0c606b91723@walle.cc> (raw) In-Reply-To: <20220411091033.98754-8-tudor.ambarus@microchip.com> Am 2022-04-11 11:10, schrieb Tudor Ambarus: > Introduce template operation to remove code duplication. > Split spi_nor_micron_octal_dtr_enable() in > spi_nor_micron_octal_dtr_en() > and spi_nor_micron_octal_dtr_dis() as it no longer made sense to try to > keep everything alltogether: too many "if (enable)" throughout the > code, > which made the code difficult to follow. Add dev_dbg messages in case > spi_nor_read_id() fails. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> > Reviewed-by: Pratyush Yadav <p.yadav@ti.com> There is now micron_st_nor_octal_dtr_en() micron_st_nor_octal_dtr_dis() and micron_st_nor_octal_dtr_enable() Now what does what? :) Maybe we should rename that octal_dtr_enable op. (Or use two?) Reviewed-by: Michael Walle <michael@walle.cc> > --- > v3: collect R-b, update commit message, add dev_dbg message in case > spi_nor_read_id() fails. > > drivers/mtd/spi-nor/micron-st.c | 111 +++++++++++++++++--------------- > 1 file changed, 60 insertions(+), 51 deletions(-) > > diff --git a/drivers/mtd/spi-nor/micron-st.c > b/drivers/mtd/spi-nor/micron-st.c > index 41b87868ecf9..a447762c0d78 100644 > --- a/drivers/mtd/spi-nor/micron-st.c > +++ b/drivers/mtd/spi-nor/micron-st.c > @@ -28,75 +28,78 @@ > #define FSR_P_ERR BIT(4) /* Program operation status */ > #define FSR_PT_ERR BIT(1) /* Protection error bit */ > > -static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool > enable) > +/* Micron ST SPI NOR flash operations. */ > +#define MICRON_ST_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ > + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0), \ > + SPI_MEM_OP_ADDR(naddr, addr, 0), \ > + SPI_MEM_OP_NO_DUMMY, \ > + SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) > + > +static int micron_st_nor_octal_dtr_en(struct spi_nor *nor) > { > struct spi_mem_op op; > u8 *buf = nor->bouncebuf; > int ret; > > - if (enable) { > - /* Use 20 dummy cycles for memory array reads. */ > - ret = spi_nor_write_enable(nor); > - if (ret) > - return ret; > - > - *buf = 20; > - op = (struct spi_mem_op) > - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), > - SPI_MEM_OP_ADDR(3, SPINOR_REG_MT_CFR1V, 1), > - SPI_MEM_OP_NO_DUMMY, > - SPI_MEM_OP_DATA_OUT(1, buf, 1)); > - > - ret = spi_mem_exec_op(nor->spimem, &op); > - if (ret) > - return ret; > - > - ret = spi_nor_wait_till_ready(nor); > - if (ret) > - return ret; > - } > + /* Use 20 dummy cycles for memory array reads. */ > + *buf = 20; > + op = (struct spi_mem_op) > + MICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR1V, 1, buf); > + ret = spi_nor_write_reg(nor, &op, nor->reg_proto); > + if (ret) > + return ret; > + ret = spi_nor_wait_till_ready(nor); > + if (ret) > + return ret; > > - ret = spi_nor_write_enable(nor); > + buf[0] = SPINOR_MT_OCT_DTR; > + op = (struct spi_mem_op) > + MICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR0V, 1, buf); > + ret = spi_nor_write_reg(nor, &op, nor->reg_proto); > if (ret) > return ret; > > - if (enable) { > - buf[0] = SPINOR_MT_OCT_DTR; > - } else { > - /* > - * The register is 1-byte wide, but 1-byte transactions are not > - * allowed in 8D-8D-8D mode. The next register is the dummy > - * cycle configuration register. Since the transaction needs to > - * be at least 2 bytes wide, set the next register to its > - * default value. This also makes sense because the value was > - * changed when enabling 8D-8D-8D mode, it should be reset when > - * disabling. > - */ > - buf[0] = SPINOR_MT_EXSPI; > - buf[1] = SPINOR_REG_MT_CFR1V_DEF; > + /* Read flash ID to make sure the switch was successful. */ > + ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); > + if (ret) { > + dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling > 8D-8D-8D mode\n", ret); > + return ret; > } > > - op = (struct spi_mem_op) > - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), > - SPI_MEM_OP_ADDR(enable ? 3 : 4, > - SPINOR_REG_MT_CFR0V, 1), > - SPI_MEM_OP_NO_DUMMY, > - SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1)); > + if (memcmp(buf, nor->info->id, nor->info->id_len)) > + return -EINVAL; > > - if (!enable) > - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); > + return 0; > +} > + > +static int micron_st_nor_octal_dtr_dis(struct spi_nor *nor) > +{ > + struct spi_mem_op op; > + u8 *buf = nor->bouncebuf; > + int ret; > > - ret = spi_mem_exec_op(nor->spimem, &op); > + /* > + * The register is 1-byte wide, but 1-byte transactions are not > allowed > + * in 8D-8D-8D mode. The next register is the dummy cycle > configuration > + * register. Since the transaction needs to be at least 2 bytes wide, > + * set the next register to its default value. This also makes sense > + * because the value was changed when enabling 8D-8D-8D mode, it > should > + * be reset when disabling. > + */ > + buf[0] = SPINOR_MT_EXSPI; > + buf[1] = SPINOR_REG_MT_CFR1V_DEF; > + op = (struct spi_mem_op) > + MICRON_ST_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 2, buf); > + ret = spi_nor_write_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); > if (ret) > return ret; > > /* Read flash ID to make sure the switch was successful. */ > - if (enable) > - ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); > - else > - ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); > - if (ret) > + ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); > + if (ret) { > + dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling > 8D-8D-8D mode\n", ret); > return ret; > + } > > if (memcmp(buf, nor->info->id, nor->info->id_len)) > return -EINVAL; > @@ -104,6 +107,12 @@ static int micron_st_nor_octal_dtr_enable(struct > spi_nor *nor, bool enable) > return 0; > } > > +static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool > enable) > +{ > + return enable ? micron_st_nor_octal_dtr_en(nor) : > + micron_st_nor_octal_dtr_dis(nor); > +} > + > static void mt35xu512aba_default_init(struct spi_nor *nor) > { > nor->params->octal_dtr_enable = micron_st_nor_octal_dtr_enable;
WARNING: multiple messages have this Message-ID (diff)
From: Michael Walle <michael@walle.cc> To: Tudor Ambarus <tudor.ambarus@microchip.com> Cc: p.yadav@ti.com, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, nicolas.ferre@microchip.com Subject: Re: [PATCH v3 7/9] mtd: spi-nor: micron-st: Rework spi_nor_micron_octal_dtr_enable() Date: Tue, 19 Apr 2022 13:43:39 +0200 [thread overview] Message-ID: <87be34dac82aaeaf7c72c0c606b91723@walle.cc> (raw) In-Reply-To: <20220411091033.98754-8-tudor.ambarus@microchip.com> Am 2022-04-11 11:10, schrieb Tudor Ambarus: > Introduce template operation to remove code duplication. > Split spi_nor_micron_octal_dtr_enable() in > spi_nor_micron_octal_dtr_en() > and spi_nor_micron_octal_dtr_dis() as it no longer made sense to try to > keep everything alltogether: too many "if (enable)" throughout the > code, > which made the code difficult to follow. Add dev_dbg messages in case > spi_nor_read_id() fails. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> > Reviewed-by: Pratyush Yadav <p.yadav@ti.com> There is now micron_st_nor_octal_dtr_en() micron_st_nor_octal_dtr_dis() and micron_st_nor_octal_dtr_enable() Now what does what? :) Maybe we should rename that octal_dtr_enable op. (Or use two?) Reviewed-by: Michael Walle <michael@walle.cc> > --- > v3: collect R-b, update commit message, add dev_dbg message in case > spi_nor_read_id() fails. > > drivers/mtd/spi-nor/micron-st.c | 111 +++++++++++++++++--------------- > 1 file changed, 60 insertions(+), 51 deletions(-) > > diff --git a/drivers/mtd/spi-nor/micron-st.c > b/drivers/mtd/spi-nor/micron-st.c > index 41b87868ecf9..a447762c0d78 100644 > --- a/drivers/mtd/spi-nor/micron-st.c > +++ b/drivers/mtd/spi-nor/micron-st.c > @@ -28,75 +28,78 @@ > #define FSR_P_ERR BIT(4) /* Program operation status */ > #define FSR_PT_ERR BIT(1) /* Protection error bit */ > > -static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool > enable) > +/* Micron ST SPI NOR flash operations. */ > +#define MICRON_ST_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ > + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0), \ > + SPI_MEM_OP_ADDR(naddr, addr, 0), \ > + SPI_MEM_OP_NO_DUMMY, \ > + SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) > + > +static int micron_st_nor_octal_dtr_en(struct spi_nor *nor) > { > struct spi_mem_op op; > u8 *buf = nor->bouncebuf; > int ret; > > - if (enable) { > - /* Use 20 dummy cycles for memory array reads. */ > - ret = spi_nor_write_enable(nor); > - if (ret) > - return ret; > - > - *buf = 20; > - op = (struct spi_mem_op) > - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), > - SPI_MEM_OP_ADDR(3, SPINOR_REG_MT_CFR1V, 1), > - SPI_MEM_OP_NO_DUMMY, > - SPI_MEM_OP_DATA_OUT(1, buf, 1)); > - > - ret = spi_mem_exec_op(nor->spimem, &op); > - if (ret) > - return ret; > - > - ret = spi_nor_wait_till_ready(nor); > - if (ret) > - return ret; > - } > + /* Use 20 dummy cycles for memory array reads. */ > + *buf = 20; > + op = (struct spi_mem_op) > + MICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR1V, 1, buf); > + ret = spi_nor_write_reg(nor, &op, nor->reg_proto); > + if (ret) > + return ret; > + ret = spi_nor_wait_till_ready(nor); > + if (ret) > + return ret; > > - ret = spi_nor_write_enable(nor); > + buf[0] = SPINOR_MT_OCT_DTR; > + op = (struct spi_mem_op) > + MICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR0V, 1, buf); > + ret = spi_nor_write_reg(nor, &op, nor->reg_proto); > if (ret) > return ret; > > - if (enable) { > - buf[0] = SPINOR_MT_OCT_DTR; > - } else { > - /* > - * The register is 1-byte wide, but 1-byte transactions are not > - * allowed in 8D-8D-8D mode. The next register is the dummy > - * cycle configuration register. Since the transaction needs to > - * be at least 2 bytes wide, set the next register to its > - * default value. This also makes sense because the value was > - * changed when enabling 8D-8D-8D mode, it should be reset when > - * disabling. > - */ > - buf[0] = SPINOR_MT_EXSPI; > - buf[1] = SPINOR_REG_MT_CFR1V_DEF; > + /* Read flash ID to make sure the switch was successful. */ > + ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); > + if (ret) { > + dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling > 8D-8D-8D mode\n", ret); > + return ret; > } > > - op = (struct spi_mem_op) > - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), > - SPI_MEM_OP_ADDR(enable ? 3 : 4, > - SPINOR_REG_MT_CFR0V, 1), > - SPI_MEM_OP_NO_DUMMY, > - SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1)); > + if (memcmp(buf, nor->info->id, nor->info->id_len)) > + return -EINVAL; > > - if (!enable) > - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); > + return 0; > +} > + > +static int micron_st_nor_octal_dtr_dis(struct spi_nor *nor) > +{ > + struct spi_mem_op op; > + u8 *buf = nor->bouncebuf; > + int ret; > > - ret = spi_mem_exec_op(nor->spimem, &op); > + /* > + * The register is 1-byte wide, but 1-byte transactions are not > allowed > + * in 8D-8D-8D mode. The next register is the dummy cycle > configuration > + * register. Since the transaction needs to be at least 2 bytes wide, > + * set the next register to its default value. This also makes sense > + * because the value was changed when enabling 8D-8D-8D mode, it > should > + * be reset when disabling. > + */ > + buf[0] = SPINOR_MT_EXSPI; > + buf[1] = SPINOR_REG_MT_CFR1V_DEF; > + op = (struct spi_mem_op) > + MICRON_ST_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 2, buf); > + ret = spi_nor_write_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); > if (ret) > return ret; > > /* Read flash ID to make sure the switch was successful. */ > - if (enable) > - ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); > - else > - ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); > - if (ret) > + ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); > + if (ret) { > + dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling > 8D-8D-8D mode\n", ret); > return ret; > + } > > if (memcmp(buf, nor->info->id, nor->info->id_len)) > return -EINVAL; > @@ -104,6 +107,12 @@ static int micron_st_nor_octal_dtr_enable(struct > spi_nor *nor, bool enable) > return 0; > } > > +static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool > enable) > +{ > + return enable ? micron_st_nor_octal_dtr_en(nor) : > + micron_st_nor_octal_dtr_dis(nor); > +} > + > static void mt35xu512aba_default_init(struct spi_nor *nor) > { > nor->params->octal_dtr_enable = micron_st_nor_octal_dtr_enable; ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2022-04-19 11:43 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-04-11 9:10 [PATCH v3 0/9] mtd: spi-nor: Rework Octal DTR methods Tudor Ambarus 2022-04-11 9:10 ` Tudor Ambarus 2022-04-11 9:10 ` [PATCH v3 1/9] mtd: spi-nor: Rename method, s/spi_nor_match_id/spi_nor_match_name Tudor Ambarus 2022-04-11 9:10 ` Tudor Ambarus 2022-04-11 9:10 ` [PATCH v3 2/9] mtd: spi-nor: Introduce spi_nor_match_id() Tudor Ambarus 2022-04-11 9:10 ` Tudor Ambarus 2022-04-11 9:10 ` [PATCH v3 3/9] mtd: spi-nor: core: Use auto-detection only once Tudor Ambarus 2022-04-11 9:10 ` Tudor Ambarus 2022-04-19 10:18 ` Michael Walle 2022-04-19 10:18 ` Michael Walle 2022-04-11 9:10 ` [PATCH v3 4/9] mtd: spi-nor: core: Introduce method for RDID op Tudor Ambarus 2022-04-11 9:10 ` Tudor Ambarus 2022-04-19 11:10 ` Michael Walle 2022-04-19 11:10 ` Michael Walle 2022-04-11 9:10 ` [PATCH v3 5/9] mtd: spi-nor: manufacturers: Use spi_nor_read_id() core method Tudor Ambarus 2022-04-11 9:10 ` Tudor Ambarus 2022-04-19 11:14 ` Michael Walle 2022-04-19 11:14 ` Michael Walle 2022-04-11 9:10 ` [PATCH v3 6/9] mtd: spi-nor: core: Add helpers to read/write any register Tudor Ambarus 2022-04-11 9:10 ` Tudor Ambarus 2022-04-19 11:19 ` Michael Walle 2022-04-19 11:19 ` Michael Walle 2022-04-19 11:46 ` Michael Walle 2022-04-19 11:46 ` Michael Walle 2022-04-19 12:08 ` Tudor.Ambarus 2022-04-19 12:08 ` Tudor.Ambarus 2022-04-19 12:32 ` Pratyush Yadav 2022-04-19 12:32 ` Pratyush Yadav 2022-04-19 12:46 ` Michael Walle 2022-04-19 12:46 ` Michael Walle 2022-04-19 12:56 ` Tudor.Ambarus 2022-04-19 12:56 ` Tudor.Ambarus 2022-04-20 4:34 ` Pratyush Yadav 2022-04-20 4:34 ` Pratyush Yadav 2022-04-20 5:20 ` Takahiro Kuwano 2022-04-20 5:20 ` Takahiro Kuwano 2022-04-20 5:25 ` Tudor.Ambarus 2022-04-20 5:25 ` Tudor.Ambarus 2022-04-19 13:02 ` Tudor.Ambarus 2022-04-19 13:02 ` Tudor.Ambarus 2022-04-19 12:59 ` Tudor.Ambarus 2022-04-19 12:59 ` Tudor.Ambarus 2022-04-11 9:10 ` [PATCH v3 7/9] mtd: spi-nor: micron-st: Rework spi_nor_micron_octal_dtr_enable() Tudor Ambarus 2022-04-11 9:10 ` Tudor Ambarus 2022-04-19 11:43 ` Michael Walle [this message] 2022-04-19 11:43 ` Michael Walle 2022-04-11 9:10 ` [PATCH v3 8/9] mtd: spi-nor: spansion: Rework spi_nor_cypress_octal_dtr_enable() Tudor Ambarus 2022-04-11 9:10 ` Tudor Ambarus 2022-04-19 11:44 ` Michael Walle 2022-04-19 11:44 ` Michael Walle 2022-04-11 9:10 ` [PATCH v3 9/9] mtd: spi-nor: Introduce templates for SPI NOR operations Tudor Ambarus 2022-04-11 9:10 ` Tudor Ambarus 2022-04-19 11:45 ` Michael Walle 2022-04-19 11:45 ` Michael Walle 2022-04-20 7:49 ` Pratyush Yadav 2022-04-20 7:49 ` Pratyush Yadav
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