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From: Marc Zyngier <maz@kernel.org>
To: Oliver Upton <oupton@google.com>
Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
	Paolo Bonzini <pbonzini@redhat.com>,
	Sean Christopherson <seanjc@google.com>,
	Peter Shier <pshier@google.com>,
	Jim Mattson <jmattson@google.com>,
	David Matlack <dmatlack@google.com>,
	Ricardo Koller <ricarkol@google.com>,
	Jing Zhang <jingzhangos@google.com>,
	Raghavendra Rao Anata <rananta@google.com>,
	James Morse <james.morse@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	Andrew Jones <drjones@redhat.com>, Will Deacon <will@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>
Subject: Re: [PATCH v6 16/21] arm64: cpufeature: Enumerate support for Enhanced Counter Virtualization
Date: Tue, 10 Aug 2021 10:38:10 +0100	[thread overview]
Message-ID: <87bl65bpx9.wl-maz@kernel.org> (raw)
In-Reply-To: <20210804085819.846610-17-oupton@google.com>

On Wed, 04 Aug 2021 09:58:14 +0100,
Oliver Upton <oupton@google.com> wrote:
> 
> Introduce a new cpucap to indicate if the system supports full enhanced
> counter virtualization (i.e. ID_AA64MMFR0_EL1.ECV==0x2).
> 
> Signed-off-by: Oliver Upton <oupton@google.com>
> ---
>  arch/arm64/include/asm/sysreg.h |  2 ++
>  arch/arm64/kernel/cpufeature.c  | 10 ++++++++++
>  arch/arm64/tools/cpucaps        |  1 +
>  3 files changed, 13 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 7b9c3acba684..4dfc44066dfb 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -847,6 +847,8 @@
>  #define ID_AA64MMFR0_ASID_SHIFT		4
>  #define ID_AA64MMFR0_PARANGE_SHIFT	0
>  
> +#define ID_AA64MMFR0_ECV_VIRT		0x1
> +#define ID_AA64MMFR0_ECV_PHYS		0x2
>  #define ID_AA64MMFR0_TGRAN4_NI		0xf
>  #define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0
>  #define ID_AA64MMFR0_TGRAN64_NI		0xf
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 0ead8bfedf20..94c349e179d3 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -2301,6 +2301,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>  		.matches = has_cpuid_feature,
>  		.min_field_value = 1,
>  	},
> +	{
> +		.desc = "Enhanced Counter Virtualization (Physical)",
> +		.capability = ARM64_ECV,
> +		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
> +		.sys_reg = SYS_ID_AA64MMFR0_EL1,
> +		.sign = FTR_UNSIGNED,
> +		.field_pos = ID_AA64MMFR0_ECV_SHIFT,
> +		.matches = has_cpuid_feature,
> +		.min_field_value = ID_AA64MMFR0_ECV_PHYS,
> +	},
>  	{},
>  };
>  
> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
> index 49305c2e6dfd..d819ea614da5 100644
> --- a/arch/arm64/tools/cpucaps
> +++ b/arch/arm64/tools/cpucaps
> @@ -3,6 +3,7 @@
>  # Internal CPU capabilities constants, keep this list sorted
>  
>  BTI
> +ECV
>  # Unreliable: use system_supports_32bit_el0() instead.
>  HAS_32BIT_EL0_DO_NOT_USE
>  HAS_32BIT_EL1

As discussed in another context, we probably want both ECV and ECV2 to
distinguish the two feature sets that ECV has so far.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Oliver Upton <oupton@google.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	kvm@vger.kernel.org, Will Deacon <will@kernel.org>,
	Sean Christopherson <seanjc@google.com>,
	Peter Shier <pshier@google.com>,
	Raghavendra Rao Anata <rananta@google.com>,
	David Matlack <dmatlack@google.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org,
	Jim Mattson <jmattson@google.com>
Subject: Re: [PATCH v6 16/21] arm64: cpufeature: Enumerate support for Enhanced Counter Virtualization
Date: Tue, 10 Aug 2021 10:38:10 +0100	[thread overview]
Message-ID: <87bl65bpx9.wl-maz@kernel.org> (raw)
In-Reply-To: <20210804085819.846610-17-oupton@google.com>

On Wed, 04 Aug 2021 09:58:14 +0100,
Oliver Upton <oupton@google.com> wrote:
> 
> Introduce a new cpucap to indicate if the system supports full enhanced
> counter virtualization (i.e. ID_AA64MMFR0_EL1.ECV==0x2).
> 
> Signed-off-by: Oliver Upton <oupton@google.com>
> ---
>  arch/arm64/include/asm/sysreg.h |  2 ++
>  arch/arm64/kernel/cpufeature.c  | 10 ++++++++++
>  arch/arm64/tools/cpucaps        |  1 +
>  3 files changed, 13 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 7b9c3acba684..4dfc44066dfb 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -847,6 +847,8 @@
>  #define ID_AA64MMFR0_ASID_SHIFT		4
>  #define ID_AA64MMFR0_PARANGE_SHIFT	0
>  
> +#define ID_AA64MMFR0_ECV_VIRT		0x1
> +#define ID_AA64MMFR0_ECV_PHYS		0x2
>  #define ID_AA64MMFR0_TGRAN4_NI		0xf
>  #define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0
>  #define ID_AA64MMFR0_TGRAN64_NI		0xf
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 0ead8bfedf20..94c349e179d3 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -2301,6 +2301,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>  		.matches = has_cpuid_feature,
>  		.min_field_value = 1,
>  	},
> +	{
> +		.desc = "Enhanced Counter Virtualization (Physical)",
> +		.capability = ARM64_ECV,
> +		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
> +		.sys_reg = SYS_ID_AA64MMFR0_EL1,
> +		.sign = FTR_UNSIGNED,
> +		.field_pos = ID_AA64MMFR0_ECV_SHIFT,
> +		.matches = has_cpuid_feature,
> +		.min_field_value = ID_AA64MMFR0_ECV_PHYS,
> +	},
>  	{},
>  };
>  
> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
> index 49305c2e6dfd..d819ea614da5 100644
> --- a/arch/arm64/tools/cpucaps
> +++ b/arch/arm64/tools/cpucaps
> @@ -3,6 +3,7 @@
>  # Internal CPU capabilities constants, keep this list sorted
>  
>  BTI
> +ECV
>  # Unreliable: use system_supports_32bit_el0() instead.
>  HAS_32BIT_EL0_DO_NOT_USE
>  HAS_32BIT_EL1

As discussed in another context, we probably want both ECV and ECV2 to
distinguish the two feature sets that ECV has so far.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Oliver Upton <oupton@google.com>
Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
	Paolo Bonzini <pbonzini@redhat.com>,
	Sean Christopherson <seanjc@google.com>,
	Peter Shier <pshier@google.com>,
	Jim Mattson <jmattson@google.com>,
	David Matlack <dmatlack@google.com>,
	Ricardo Koller <ricarkol@google.com>,
	Jing Zhang <jingzhangos@google.com>,
	Raghavendra Rao Anata <rananta@google.com>,
	James Morse <james.morse@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	Andrew Jones <drjones@redhat.com>, Will Deacon <will@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>
Subject: Re: [PATCH v6 16/21] arm64: cpufeature: Enumerate support for Enhanced Counter Virtualization
Date: Tue, 10 Aug 2021 10:38:10 +0100	[thread overview]
Message-ID: <87bl65bpx9.wl-maz@kernel.org> (raw)
In-Reply-To: <20210804085819.846610-17-oupton@google.com>

On Wed, 04 Aug 2021 09:58:14 +0100,
Oliver Upton <oupton@google.com> wrote:
> 
> Introduce a new cpucap to indicate if the system supports full enhanced
> counter virtualization (i.e. ID_AA64MMFR0_EL1.ECV==0x2).
> 
> Signed-off-by: Oliver Upton <oupton@google.com>
> ---
>  arch/arm64/include/asm/sysreg.h |  2 ++
>  arch/arm64/kernel/cpufeature.c  | 10 ++++++++++
>  arch/arm64/tools/cpucaps        |  1 +
>  3 files changed, 13 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 7b9c3acba684..4dfc44066dfb 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -847,6 +847,8 @@
>  #define ID_AA64MMFR0_ASID_SHIFT		4
>  #define ID_AA64MMFR0_PARANGE_SHIFT	0
>  
> +#define ID_AA64MMFR0_ECV_VIRT		0x1
> +#define ID_AA64MMFR0_ECV_PHYS		0x2
>  #define ID_AA64MMFR0_TGRAN4_NI		0xf
>  #define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0
>  #define ID_AA64MMFR0_TGRAN64_NI		0xf
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 0ead8bfedf20..94c349e179d3 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -2301,6 +2301,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>  		.matches = has_cpuid_feature,
>  		.min_field_value = 1,
>  	},
> +	{
> +		.desc = "Enhanced Counter Virtualization (Physical)",
> +		.capability = ARM64_ECV,
> +		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
> +		.sys_reg = SYS_ID_AA64MMFR0_EL1,
> +		.sign = FTR_UNSIGNED,
> +		.field_pos = ID_AA64MMFR0_ECV_SHIFT,
> +		.matches = has_cpuid_feature,
> +		.min_field_value = ID_AA64MMFR0_ECV_PHYS,
> +	},
>  	{},
>  };
>  
> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
> index 49305c2e6dfd..d819ea614da5 100644
> --- a/arch/arm64/tools/cpucaps
> +++ b/arch/arm64/tools/cpucaps
> @@ -3,6 +3,7 @@
>  # Internal CPU capabilities constants, keep this list sorted
>  
>  BTI
> +ECV
>  # Unreliable: use system_supports_32bit_el0() instead.
>  HAS_32BIT_EL0_DO_NOT_USE
>  HAS_32BIT_EL1

As discussed in another context, we probably want both ECV and ECV2 to
distinguish the two feature sets that ECV has so far.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-08-10  9:38 UTC|newest]

Thread overview: 153+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-04  8:57 [PATCH v6 00/21] KVM: Add idempotent controls for migrating system counter state Oliver Upton
2021-08-04  8:57 ` Oliver Upton
2021-08-04  8:57 ` Oliver Upton
2021-08-04  8:57 ` [PATCH v6 01/21] KVM: x86: Fix potential race in KVM_GET_CLOCK Oliver Upton
2021-08-04  8:57   ` Oliver Upton
2021-08-04  8:57   ` Oliver Upton
2021-08-11 12:23   ` Paolo Bonzini
2021-08-11 12:23     ` Paolo Bonzini
2021-08-11 12:23     ` Paolo Bonzini
2021-08-13 10:39     ` Oliver Upton
2021-08-13 10:39       ` Oliver Upton
2021-08-13 10:39       ` Oliver Upton
2021-08-13 10:44       ` Paolo Bonzini
2021-08-13 10:44         ` Paolo Bonzini
2021-08-13 10:44         ` Paolo Bonzini
2021-08-13 17:46         ` Oliver Upton
2021-08-13 17:46           ` Oliver Upton
2021-08-13 17:46           ` Oliver Upton
2021-08-04  8:58 ` [PATCH v6 02/21] KVM: x86: Report host tsc and realtime values " Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58 ` [PATCH v6 03/21] KVM: x86: Take the pvclock sync lock behind the tsc_write_lock Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58 ` [PATCH v6 04/21] KVM: x86: Refactor tsc synchronization code Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58 ` [PATCH v6 05/21] KVM: x86: Expose TSC offset controls to userspace Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58 ` [PATCH v6 06/21] tools: arch: x86: pull in pvclock headers Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58 ` [PATCH v6 07/21] selftests: KVM: Add test for KVM_{GET,SET}_CLOCK Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58 ` [PATCH v6 08/21] selftests: KVM: Fix kvm device helper ioctl assertions Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58 ` [PATCH v6 09/21] selftests: KVM: Add helpers for vCPU device attributes Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58 ` [PATCH v6 10/21] selftests: KVM: Introduce system counter offset test Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58 ` [PATCH v6 11/21] KVM: arm64: Refactor update_vtimer_cntvoff() Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  9:23   ` Andrew Jones
2021-08-04  9:23     ` Andrew Jones
2021-08-04  9:23     ` Andrew Jones
2021-08-04  8:58 ` [PATCH v6 12/21] KVM: arm64: Separate guest/host counter offset values Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04 10:19   ` Andrew Jones
2021-08-04 10:19     ` Andrew Jones
2021-08-04 10:19     ` Andrew Jones
2021-08-04  8:58 ` [PATCH v6 13/21] KVM: arm64: Allow userspace to configure a vCPU's virtual offset Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04 10:20   ` Andrew Jones
2021-08-04 10:20     ` Andrew Jones
2021-08-04 10:20     ` Andrew Jones
2021-08-10  9:35   ` Marc Zyngier
2021-08-10  9:35     ` Marc Zyngier
2021-08-10  9:35     ` Marc Zyngier
2021-08-10  9:44     ` Oliver Upton
2021-08-10  9:44       ` Oliver Upton
2021-08-10  9:44       ` Oliver Upton
2021-08-11 15:22       ` Marc Zyngier
2021-08-11 15:22         ` Marc Zyngier
2021-08-11 15:22         ` Marc Zyngier
2021-08-04  8:58 ` [PATCH v6 14/21] selftests: KVM: Add helper to check for register presence Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  9:14   ` Andrew Jones
2021-08-04  9:14     ` Andrew Jones
2021-08-04  9:14     ` Andrew Jones
2021-08-04  8:58 ` [PATCH v6 15/21] selftests: KVM: Add support for aarch64 to system_counter_offset_test Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58 ` [PATCH v6 16/21] arm64: cpufeature: Enumerate support for Enhanced Counter Virtualization Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-10  9:38   ` Marc Zyngier [this message]
2021-08-10  9:38     ` Marc Zyngier
2021-08-10  9:38     ` Marc Zyngier
2021-08-04  8:58 ` [PATCH v6 17/21] KVM: arm64: Allow userspace to configure a guest's counter-timer offset Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04 10:17   ` Andrew Jones
2021-08-04 10:17     ` Andrew Jones
2021-08-04 10:17     ` Andrew Jones
2021-08-04 10:22     ` Oliver Upton
2021-08-04 10:22       ` Oliver Upton
2021-08-04 10:22       ` Oliver Upton
2021-08-10 10:56   ` Marc Zyngier
2021-08-10 10:56     ` Marc Zyngier
2021-08-10 10:56     ` Marc Zyngier
2021-08-10 17:55     ` Oliver Upton
2021-08-10 17:55       ` Oliver Upton
2021-08-10 17:55       ` Oliver Upton
2021-08-11  9:01       ` Marc Zyngier
2021-08-11  9:01         ` Marc Zyngier
2021-08-11  9:01         ` Marc Zyngier
2021-08-04  8:58 ` [PATCH v6 18/21] KVM: arm64: Configure timer traps in vcpu_load() for VHE Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04 10:25   ` Andrew Jones
2021-08-04 10:25     ` Andrew Jones
2021-08-04 10:25     ` Andrew Jones
2021-08-04  8:58 ` [PATCH v6 19/21] KVM: arm64: Emulate physical counter offsetting on non-ECV systems Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04 11:05   ` Andrew Jones
2021-08-04 11:05     ` Andrew Jones
2021-08-04 11:05     ` Andrew Jones
2021-08-05  6:27     ` Oliver Upton
2021-08-05  6:27       ` Oliver Upton
2021-08-05  6:27       ` Oliver Upton
2021-08-10 11:27   ` Marc Zyngier
2021-08-10 11:27     ` Marc Zyngier
2021-08-10 11:27     ` Marc Zyngier
2021-08-04  8:58 ` [PATCH v6 20/21] selftests: KVM: Test physical counter offsetting Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04 11:03   ` Andrew Jones
2021-08-04 11:03     ` Andrew Jones
2021-08-04 11:03     ` Andrew Jones
2021-08-04  8:58 ` [PATCH v6 21/21] selftests: KVM: Add counter emulation benchmark Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04  8:58   ` Oliver Upton
2021-08-04 11:05 ` [PATCH v6 00/21] KVM: Add idempotent controls for migrating system counter state Oliver Upton
2021-08-04 11:05   ` Oliver Upton
2021-08-04 11:05   ` Oliver Upton
2021-08-04 22:03   ` Oliver Upton
2021-08-04 22:03     ` Oliver Upton
2021-08-04 22:03     ` Oliver Upton
2021-08-10  0:04     ` Oliver Upton
2021-08-10  0:04       ` Oliver Upton
2021-08-10  0:04       ` Oliver Upton
2021-08-10 12:30       ` Marc Zyngier
2021-08-10 12:30         ` Marc Zyngier
2021-08-10 12:30         ` Marc Zyngier
2021-08-11 13:05 ` Paolo Bonzini
2021-08-11 13:05   ` Paolo Bonzini
2021-08-11 13:05   ` Paolo Bonzini
2021-08-11 18:56   ` Oliver Upton
2021-08-11 18:56     ` Oliver Upton
2021-08-11 18:56     ` Oliver Upton
2021-08-11 19:01     ` Marc Zyngier
2021-08-11 19:01       ` Marc Zyngier
2021-08-11 19:01       ` Marc Zyngier

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