* [PATCH v4 1/3] drm/i915: introduce REG_BIT() and REG_GENMASK() to define register contents
2019-03-15 13:56 [PATCH v4 0/3] drm/i915: introduce macros to define register contents Jani Nikula
@ 2019-03-15 13:56 ` Jani Nikula
2019-03-15 13:56 ` [PATCH v4 2/3] drm/i915: deprecate _SHIFT in favor of _MASK passed to accessors Jani Nikula
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2019-03-15 13:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Introduce REG_BIT(n) to define register bits and REG_GENMASK(h, l) to
define register bitfield masks.
We define the above as wrappers to BIT() and GENMASK() respectively to
force u32 type to go with our register size, and to add compile time
checks on the bit numbers.
The intention is that these are easier to get right and review against
the spec than hand rolled masks.
Convert power sequencer registers as an example.
v4:
- rebase
v3:
- rename macros to REG_BIT() and REG_GENMASK() to avoid underscore
prefix and to be in line with kernel macros (Chris)
- add compile time checks (Mika)
v2:
- rename macros to just _BIT() and _MASK() to reduce verbosity
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 94 +++++++++++++++++++++------------
1 file changed, 61 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9b69cec21f7b..4a025e3c49c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -25,6 +25,8 @@
#ifndef _I915_REG_H_
#define _I915_REG_H_
+#include <linux/bits.h>
+
/**
* DOC: The i915 register macro definition style guide
*
@@ -59,15 +61,13 @@
* significant to least significant bit. Indent the register content macros
* using two extra spaces between ``#define`` and the macro name.
*
- * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field
- * contents so that they are already shifted in place, and can be directly
- * OR'd. For convenience, function-like macros may be used to define bit fields,
- * but do note that the macros may be needed to read as well as write the
- * register contents.
+ * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Use
+ * ``REG_GENMASK()`` to define _MASK. Define bit field contents so that they are
+ * already shifted in place, and can be directly OR'd. For convenience,
+ * function-like macros may be used to define bit fields, but do note that the
+ * macros may be needed to read as well as write the register contents.
*
- * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in
- * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix
- * to the name.
+ * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
*
* Group the register and its contents together without blank lines, separate
* from other registers and their contents with one blank line.
@@ -105,8 +105,8 @@
* #define _FOO_A 0xf000
* #define _FOO_B 0xf001
* #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
- * #define FOO_ENABLE (1 << 31)
- * #define FOO_MODE_MASK (0xf << 16)
+ * #define FOO_ENABLE REG_BIT(31)
+ * #define FOO_MODE_MASK REG_GENMASK(19, 16)
* #define FOO_MODE_SHIFT 16
* #define FOO_MODE_BAR (0 << 16)
* #define FOO_MODE_BAZ (1 << 16)
@@ -116,6 +116,34 @@
* #define GEN8_BAR _MMIO(0xb888)
*/
+/**
+ * REG_BIT() - Prepare a u32 bit value
+ * @__n: 0-based bit number
+ *
+ * Local wrapper for BIT() to force u32, with compile time checks.
+ *
+ * @return: Value with bit @__n set.
+ */
+#define REG_BIT(__n) \
+ ((u32)(BIT(__n) + \
+ BUILD_BUG_ON_ZERO(__builtin_constant_p(__n) && \
+ ((__n) < 0 || (__n) > 31))))
+
+/**
+ * REG_GENMASK() - Prepare a continuous u32 bitmask
+ * @__high: 0-based high bit
+ * @__low: 0-based low bit
+ *
+ * Local wrapper for GENMASK() to force u32, with compile time checks.
+ *
+ * @return: Continuous bitmask from @__high to @__low, inclusive.
+ */
+#define REG_GENMASK(__high, __low) \
+ ((u32)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__builtin_constant_p(__high) && \
+ __builtin_constant_p(__low) && \
+ ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
+
typedef struct {
u32 reg;
} i915_reg_t;
@@ -4692,18 +4720,18 @@ enum {
#define _PP_STATUS 0x61200
#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
-#define PP_ON (1 << 31)
+#define PP_ON REG_BIT(31)
#define _PP_CONTROL_1 0xc7204
#define _PP_CONTROL_2 0xc7304
#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
_PP_CONTROL_2)
-#define POWER_CYCLE_DELAY_MASK (0x1f << 4)
+#define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
#define POWER_CYCLE_DELAY_SHIFT 4
-#define VDD_OVERRIDE_FORCE (1 << 3)
-#define BACKLIGHT_ENABLE (1 << 2)
-#define PWR_DOWN_ON_RESET (1 << 1)
-#define PWR_STATE_TARGET (1 << 0)
+#define VDD_OVERRIDE_FORCE REG_BIT(3)
+#define BACKLIGHT_ENABLE REG_BIT(2)
+#define PWR_DOWN_ON_RESET REG_BIT(1)
+#define PWR_STATE_TARGET REG_BIT(0)
/*
* Indicates that all dependencies of the panel are on:
*
@@ -4711,14 +4739,14 @@ enum {
* - pipe enabled
* - LVDS/DVOB/DVOC on
*/
-#define PP_READY (1 << 30)
+#define PP_READY REG_BIT(30)
+#define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
#define PP_SEQUENCE_NONE (0 << 28)
#define PP_SEQUENCE_POWER_UP (1 << 28)
#define PP_SEQUENCE_POWER_DOWN (2 << 28)
-#define PP_SEQUENCE_MASK (3 << 28)
#define PP_SEQUENCE_SHIFT 28
-#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
-#define PP_SEQUENCE_STATE_MASK 0x0000000f
+#define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
+#define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
@@ -4731,41 +4759,41 @@ enum {
#define _PP_CONTROL 0x61204
#define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
+#define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
#define PANEL_UNLOCK_REGS (0xabcd << 16)
-#define PANEL_UNLOCK_MASK (0xffff << 16)
-#define BXT_POWER_CYCLE_DELAY_MASK 0x1f0
+#define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
#define BXT_POWER_CYCLE_DELAY_SHIFT 4
-#define EDP_FORCE_VDD (1 << 3)
-#define EDP_BLC_ENABLE (1 << 2)
-#define PANEL_POWER_RESET (1 << 1)
-#define PANEL_POWER_ON (1 << 0)
+#define EDP_FORCE_VDD REG_BIT(3)
+#define EDP_BLC_ENABLE REG_BIT(2)
+#define PANEL_POWER_RESET REG_BIT(1)
+#define PANEL_POWER_ON REG_BIT(0)
#define _PP_ON_DELAYS 0x61208
#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
#define PANEL_PORT_SELECT_SHIFT 30
-#define PANEL_PORT_SELECT_MASK (3 << 30)
+#define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
#define PANEL_PORT_SELECT_LVDS (0 << 30)
#define PANEL_PORT_SELECT_DPA (1 << 30)
#define PANEL_PORT_SELECT_DPC (2 << 30)
#define PANEL_PORT_SELECT_DPD (3 << 30)
#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
-#define PANEL_POWER_UP_DELAY_MASK 0x1fff0000
+#define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
#define PANEL_POWER_UP_DELAY_SHIFT 16
-#define PANEL_LIGHT_ON_DELAY_MASK 0x1fff
+#define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
#define PANEL_LIGHT_ON_DELAY_SHIFT 0
#define _PP_OFF_DELAYS 0x6120C
#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
-#define PANEL_POWER_DOWN_DELAY_MASK 0x1fff0000
+#define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16)
#define PANEL_POWER_DOWN_DELAY_SHIFT 16
-#define PANEL_LIGHT_OFF_DELAY_MASK 0x1fff
+#define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0)
#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
#define _PP_DIVISOR 0x61210
#define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
-#define PP_REFERENCE_DIVIDER_MASK 0xffffff00
+#define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8)
#define PP_REFERENCE_DIVIDER_SHIFT 8
-#define PANEL_POWER_CYCLE_DELAY_MASK 0x1f
+#define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0)
#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
/* Panel fitting */
--
2.20.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v4 2/3] drm/i915: deprecate _SHIFT in favor of _MASK passed to accessors
2019-03-15 13:56 [PATCH v4 0/3] drm/i915: introduce macros to define register contents Jani Nikula
2019-03-15 13:56 ` [PATCH v4 1/3] drm/i915: introduce REG_BIT() and REG_GENMASK() " Jani Nikula
@ 2019-03-15 13:56 ` Jani Nikula
2019-03-15 13:56 ` [PATCH v4 3/3] drm/i915: use REG_FIELD_PREP() to define register bitfield values Jani Nikula
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2019-03-15 13:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
bitfield.h defines FIELD_GET() and FIELD_PREP() macros to access
bitfields using the mask alone, with no need for separate shift. Indeed,
the shift is redundant.
We define REG_FIELD_GET() and REG_FIELD_PREP() wrappers for the above,
in part to force u32 and for consistency with REG_BIT() and
REG_GENMASK(), but also as we'll need to redefine REG_FIELD_PREP() in
follow-up work to make it produce integer constant expressions.
For the most part, REG_FIELD_GET() is shorter than masking followed by
shift, and arguably has more clarity.
REG_FIELD_PREP() can get more verbose than simply shifting in place, but
it does provide masking to ensure we don't overflow the mask, something
we usually don't bother with currently.
Convert power sequencer registers as an example.
v3:
- temp variable removal (Chris)
- rebase
v2:
- Add the REG_FIELD_GET() and REG_FIELD_PREP() wrappers to use them
consistently from the start.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 45 ++++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_dp.c | 42 ++++++++++-------------------
drivers/gpu/drm/i915/intel_lvds.c | 42 +++++++++++++----------------
3 files changed, 63 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4a025e3c49c4..31a3020e369d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -25,6 +25,7 @@
#ifndef _I915_REG_H_
#define _I915_REG_H_
+#include <linux/bitfield.h>
#include <linux/bits.h>
/**
@@ -61,11 +62,11 @@
* significant to least significant bit. Indent the register content macros
* using two extra spaces between ``#define`` and the macro name.
*
- * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Use
- * ``REG_GENMASK()`` to define _MASK. Define bit field contents so that they are
- * already shifted in place, and can be directly OR'd. For convenience,
- * function-like macros may be used to define bit fields, but do note that the
- * macros may be needed to read as well as write the register contents.
+ * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents so
+ * that they are already shifted in place, and can be directly OR'd. For
+ * convenience, function-like macros may be used to define bit fields, but do
+ * note that the macros may be needed to read as well as write the register
+ * contents.
*
* Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
*
@@ -107,7 +108,6 @@
* #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
* #define FOO_ENABLE REG_BIT(31)
* #define FOO_MODE_MASK REG_GENMASK(19, 16)
- * #define FOO_MODE_SHIFT 16
* #define FOO_MODE_BAR (0 << 16)
* #define FOO_MODE_BAZ (1 << 16)
* #define FOO_MODE_QUX_SNB (2 << 16)
@@ -144,6 +144,30 @@
__builtin_constant_p(__low) && \
((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
+/**
+ * REG_FIELD_PREP() - Prepare a u32 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to put in the field
+
+ * Local wrapper for FIELD_PREP() to force u32 and for consistency with
+ * REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
+ *
+ * @return: @__val masked and shifted into the field defined by @__mask.
+ */
+#define REG_FIELD_PREP(__mask, __val) ((u32)FIELD_PREP(__mask, __val))
+
+/**
+ * REG_FIELD_GET() - Extract a u32 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to extract the bitfield value from
+ *
+ * Local wrapper for FIELD_GET() to force u32 and for consistency with
+ * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
+ *
+ * @return: Masked and shifted value of the field defined by @__mask in @__val.
+ */
+#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
+
typedef struct {
u32 reg;
} i915_reg_t;
@@ -4727,7 +4751,6 @@ enum {
#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
_PP_CONTROL_2)
#define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
-#define POWER_CYCLE_DELAY_SHIFT 4
#define VDD_OVERRIDE_FORCE REG_BIT(3)
#define BACKLIGHT_ENABLE REG_BIT(2)
#define PWR_DOWN_ON_RESET REG_BIT(1)
@@ -4744,7 +4767,6 @@ enum {
#define PP_SEQUENCE_NONE (0 << 28)
#define PP_SEQUENCE_POWER_UP (1 << 28)
#define PP_SEQUENCE_POWER_DOWN (2 << 28)
-#define PP_SEQUENCE_SHIFT 28
#define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
#define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
@@ -4770,7 +4792,6 @@ enum {
#define _PP_ON_DELAYS 0x61208
#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
-#define PANEL_PORT_SELECT_SHIFT 30
#define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
#define PANEL_PORT_SELECT_LVDS (0 << 30)
#define PANEL_PORT_SELECT_DPA (1 << 30)
@@ -4778,23 +4799,17 @@ enum {
#define PANEL_PORT_SELECT_DPD (3 << 30)
#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
#define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
-#define PANEL_POWER_UP_DELAY_SHIFT 16
#define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
-#define PANEL_LIGHT_ON_DELAY_SHIFT 0
#define _PP_OFF_DELAYS 0x6120C
#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
#define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16)
-#define PANEL_POWER_DOWN_DELAY_SHIFT 16
#define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0)
-#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
#define _PP_DIVISOR 0x61210
#define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
#define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8)
-#define PP_REFERENCE_DIVIDER_SHIFT 8
#define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0)
-#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
/* Panel fitting */
#define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 47857f96c3b1..35962a84b910 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6438,29 +6438,19 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
pp_off = I915_READ(regs.pp_off);
/* Pull timing values out of registers */
- seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
- PANEL_POWER_UP_DELAY_SHIFT;
-
- seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
- PANEL_LIGHT_ON_DELAY_SHIFT;
-
- seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
- PANEL_LIGHT_OFF_DELAY_SHIFT;
-
- seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
- PANEL_POWER_DOWN_DELAY_SHIFT;
+ seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
+ seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
+ seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
+ seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
if (i915_mmio_reg_valid(regs.pp_div)) {
u32 pp_div;
pp_div = I915_READ(regs.pp_div);
- seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
- PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
-
+ seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
} else {
- seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
- BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
+ seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
}
}
@@ -6620,10 +6610,10 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
I915_WRITE(regs.pp_ctrl, pp);
}
- pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
- (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
- pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
- (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
+ pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
+ REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
+ pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
+ REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
/* Haswell doesn't have any port selection bits for the panel
* power sequencer any more. */
@@ -6655,19 +6645,15 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
* Compute the divisor for the pp clock, simply match the Bspec formula.
*/
if (i915_mmio_reg_valid(regs.pp_div)) {
- u32 pp_div;
-
- pp_div = ((100 * div) / 2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
- pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) <<
- PANEL_POWER_CYCLE_DELAY_SHIFT);
- I915_WRITE(regs.pp_div, pp_div);
+ I915_WRITE(regs.pp_div,
+ REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) |
+ REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
} else {
u32 pp_ctl;
pp_ctl = I915_READ(regs.pp_ctrl);
pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
- pp_ctl |= (DIV_ROUND_UP(seq->t11_t12, 1000) <<
- BXT_POWER_CYCLE_DELAY_SHIFT);
+ pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
I915_WRITE(regs.pp_ctrl, pp_ctl);
}
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index b4aa49768e90..6e3cf1c4ad00 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -152,24 +152,17 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
val = I915_READ(PP_ON_DELAYS(0));
- pps->port = (val & PANEL_PORT_SELECT_MASK) >>
- PANEL_PORT_SELECT_SHIFT;
- pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
- PANEL_POWER_UP_DELAY_SHIFT;
- pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
- PANEL_LIGHT_ON_DELAY_SHIFT;
+ pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
+ pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
+ pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
val = I915_READ(PP_OFF_DELAYS(0));
- pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
- PANEL_POWER_DOWN_DELAY_SHIFT;
- pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
- PANEL_LIGHT_OFF_DELAY_SHIFT;
+ pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
+ pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
val = I915_READ(PP_DIVISOR(0));
- pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
- PP_REFERENCE_DIVIDER_SHIFT;
- val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
- PANEL_POWER_CYCLE_DELAY_SHIFT;
+ pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
+ val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);
/*
* Remove the BSpec specified +1 (100ms) offset that accounts for a
* too short power-cycle delay due to the asynchronous programming of
@@ -209,16 +202,19 @@ static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
val |= PANEL_POWER_RESET;
I915_WRITE(PP_CONTROL(0), val);
- I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) |
- (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) |
- (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT));
- I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) |
- (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT));
+ I915_WRITE(PP_ON_DELAYS(0),
+ REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |
+ REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) |
+ REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5));
- val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT;
- val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) <<
- PANEL_POWER_CYCLE_DELAY_SHIFT;
- I915_WRITE(PP_DIVISOR(0), val);
+ I915_WRITE(PP_OFF_DELAYS(0),
+ REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) |
+ REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx));
+
+ I915_WRITE(PP_DIVISOR(0),
+ REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
+ REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK,
+ DIV_ROUND_UP(pps->t4, 1000) + 1));
}
static void intel_pre_enable_lvds(struct intel_encoder *encoder,
--
2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v4 3/3] drm/i915: use REG_FIELD_PREP() to define register bitfield values
2019-03-15 13:56 [PATCH v4 0/3] drm/i915: introduce macros to define register contents Jani Nikula
2019-03-15 13:56 ` [PATCH v4 1/3] drm/i915: introduce REG_BIT() and REG_GENMASK() " Jani Nikula
2019-03-15 13:56 ` [PATCH v4 2/3] drm/i915: deprecate _SHIFT in favor of _MASK passed to accessors Jani Nikula
@ 2019-03-15 13:56 ` Jani Nikula
2019-03-15 15:10 ` ✓ Fi.CI.BAT: success for drm/i915: introduce macros to define register contents (rev4) Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2019-03-15 13:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Slightly verbose, but does away with hand rolled shifts. Ties the field
values with the mask defining the field.
Unfortunately we have to make a local copy of FIELD_PREP() to evaluate
to a integer constant expression. But with this, we can ensure the mask
is non-zero, power of 2, fits u32, and the value fits the mask (when the
value is a constant expression).
Convert power sequencer registers as an example.
v4:
- rebase
v3:
- rename the macro to REG_FIELD_PREP to avoid underscore prefix and to
be in line with kernel macros (Chris)
- rename power of 2 check macro (Chris)
v2:
- add build-time checks with BUILD_BUG_ON_ZERO()
- rename to just _FIELD() due to regmap.h REG_FIELD() clash
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 69 +++++++++++++++++++--------------
1 file changed, 39 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 31a3020e369d..477dfda38fc7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -62,11 +62,11 @@
* significant to least significant bit. Indent the register content macros
* using two extra spaces between ``#define`` and the macro name.
*
- * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents so
- * that they are already shifted in place, and can be directly OR'd. For
- * convenience, function-like macros may be used to define bit fields, but do
- * note that the macros may be needed to read as well as write the register
- * contents.
+ * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
+ * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
+ * shifted in place, so they can be directly OR'd together. For convenience,
+ * function-like macros may be used to define bit fields, but do note that the
+ * macros may be needed to read as well as write the register contents.
*
* Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
*
@@ -108,9 +108,9 @@
* #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
* #define FOO_ENABLE REG_BIT(31)
* #define FOO_MODE_MASK REG_GENMASK(19, 16)
- * #define FOO_MODE_BAR (0 << 16)
- * #define FOO_MODE_BAZ (1 << 16)
- * #define FOO_MODE_QUX_SNB (2 << 16)
+ * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
+ * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
+ * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
*
* #define BAR _MMIO(0xb000)
* #define GEN8_BAR _MMIO(0xb888)
@@ -144,17 +144,27 @@
__builtin_constant_p(__low) && \
((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
+/*
+ * Local integer constant expression version of is_power_of_2().
+ */
+#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
+
/**
* REG_FIELD_PREP() - Prepare a u32 bitfield value
* @__mask: shifted mask defining the field's length and position
* @__val: value to put in the field
- * Local wrapper for FIELD_PREP() to force u32 and for consistency with
- * REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
+ * Local copy of FIELD_PREP() to generate an integer constant expression, force
+ * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
*
* @return: @__val masked and shifted into the field defined by @__mask.
*/
-#define REG_FIELD_PREP(__mask, __val) ((u32)FIELD_PREP(__mask, __val))
+#define REG_FIELD_PREP(__mask, __val) \
+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__builtin_constant_p(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
/**
* REG_FIELD_GET() - Extract a u32 bitfield value
@@ -4764,27 +4774,26 @@ enum {
*/
#define PP_READY REG_BIT(30)
#define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
-#define PP_SEQUENCE_NONE (0 << 28)
-#define PP_SEQUENCE_POWER_UP (1 << 28)
-#define PP_SEQUENCE_POWER_DOWN (2 << 28)
+#define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
+#define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
+#define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
#define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
#define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
-#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
-#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
-#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
-#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
-#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
-#define PP_SEQUENCE_STATE_ON_S1_1 (0x9 << 0)
-#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
-#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
-#define PP_SEQUENCE_STATE_RESET (0xf << 0)
+#define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
+#define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
+#define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
+#define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
+#define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
+#define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
+#define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
+#define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
+#define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
#define _PP_CONTROL 0x61204
#define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
#define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
-#define PANEL_UNLOCK_REGS (0xabcd << 16)
+#define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
#define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
-#define BXT_POWER_CYCLE_DELAY_SHIFT 4
#define EDP_FORCE_VDD REG_BIT(3)
#define EDP_BLC_ENABLE REG_BIT(2)
#define PANEL_POWER_RESET REG_BIT(1)
@@ -4793,11 +4802,11 @@ enum {
#define _PP_ON_DELAYS 0x61208
#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
#define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
-#define PANEL_PORT_SELECT_LVDS (0 << 30)
-#define PANEL_PORT_SELECT_DPA (1 << 30)
-#define PANEL_PORT_SELECT_DPC (2 << 30)
-#define PANEL_PORT_SELECT_DPD (3 << 30)
-#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
+#define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
+#define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
+#define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
+#define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
+#define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
#define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
#define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: introduce macros to define register contents (rev4)
2019-03-15 13:56 [PATCH v4 0/3] drm/i915: introduce macros to define register contents Jani Nikula
` (2 preceding siblings ...)
2019-03-15 13:56 ` [PATCH v4 3/3] drm/i915: use REG_FIELD_PREP() to define register bitfield values Jani Nikula
@ 2019-03-15 15:10 ` Patchwork
2019-03-15 17:01 ` ✓ Fi.CI.IGT: " Patchwork
2019-03-15 22:58 ` [PATCH v4 0/3] drm/i915: introduce macros to define register contents Rodrigo Vivi
5 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-03-15 15:10 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: introduce macros to define register contents (rev4)
URL : https://patchwork.freedesktop.org/series/50513/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5753 -> Patchwork_12476
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/50513/revisions/4/mbox/
Known issues
------------
Here are the changes found in Patchwork_12476 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-kbl-7567u: NOTRUN -> SKIP [fdo#109271] +33
* igt@gem_exec_basic@readonly-bsd2:
- fi-pnv-d510: NOTRUN -> SKIP [fdo#109271] +76
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: PASS -> FAIL [fdo#108511]
* igt@kms_busy@basic-flip-c:
- fi-pnv-d510: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-8809g: NOTRUN -> SKIP [fdo#109271] +65
* igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-7560u: NOTRUN -> SKIP [fdo#109271] +33
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- fi-kbl-7560u: INCOMPLETE [fdo#103665] -> PASS
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: FAIL [fdo#103182] -> PASS +1
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (44 -> 42)
------------------------------
Additional (3): fi-kbl-7567u fi-kbl-8809g fi-pnv-d510
Missing (5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
Build changes
-------------
* Linux: CI_DRM_5753 -> Patchwork_12476
CI_DRM_5753: 0eb0838c0c26378949de6816166117c8b2d73caa @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4887: 5a7c7575b5bb9542f722ed6ba095b9d62609cd56 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12476: 054624c06486283fbfdd74444224ea18e881448a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
054624c06486 drm/i915: use REG_FIELD_PREP() to define register bitfield values
a85d9dbaf18f drm/i915: deprecate _SHIFT in favor of _MASK passed to accessors
129656622c9a drm/i915: introduce REG_BIT() and REG_GENMASK() to define register contents
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12476/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: introduce macros to define register contents (rev4)
2019-03-15 13:56 [PATCH v4 0/3] drm/i915: introduce macros to define register contents Jani Nikula
` (3 preceding siblings ...)
2019-03-15 15:10 ` ✓ Fi.CI.BAT: success for drm/i915: introduce macros to define register contents (rev4) Patchwork
@ 2019-03-15 17:01 ` Patchwork
2019-03-15 22:58 ` [PATCH v4 0/3] drm/i915: introduce macros to define register contents Rodrigo Vivi
5 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-03-15 17:01 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: introduce macros to define register contents (rev4)
URL : https://patchwork.freedesktop.org/series/50513/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5753_full -> Patchwork_12476_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12476_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_parallel@bsd1:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +78
* igt@gem_exec_params@no-blt:
- shard-iclb: NOTRUN -> SKIP [fdo#109283]
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-iclb: NOTRUN -> INCOMPLETE [fdo#107713] / [fdo#109766] / [fdo#109801]
* igt@gem_pwrite@huge-gtt-random:
- shard-iclb: NOTRUN -> SKIP [fdo#109290]
* igt@i915_pm_backlight@fade_with_suspend:
- shard-iclb: NOTRUN -> FAIL [fdo#107847]
* igt@i915_pm_rpm@gem-execbuf-stress:
- shard-skl: PASS -> INCOMPLETE [fdo#107803] / [fdo#107807]
* igt@i915_pm_rpm@sysfs-read:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@i915_pm_rps@reset:
- shard-iclb: NOTRUN -> FAIL [fdo#108059] +1
* igt@kms_busy@basic-modeset-e:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-hsw: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-oldfb-render-e:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_busy@extended-pageflip-hang-oldfb-render-d:
- shard-iclb: NOTRUN -> SKIP [fdo#109278] +4
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-iclb: PASS -> DMESG-WARN [fdo#107956]
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-apl: PASS -> FAIL [fdo#107725] / [fdo#108145]
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic:
- shard-iclb: NOTRUN -> FAIL [fdo#107725]
* igt@kms_chamelium@vga-edid-read:
- shard-iclb: NOTRUN -> SKIP [fdo#109284] +1
* igt@kms_color@pipe-b-legacy-gamma:
- shard-iclb: NOTRUN -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-128x128-onscreen:
- shard-skl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-128x128-random:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: PASS -> FAIL [fdo#104873]
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-glk: PASS -> FAIL [fdo#105454] / [fdo#106509]
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-iclb: PASS -> FAIL [fdo#103355]
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: NOTRUN -> SKIP [fdo#109349]
* igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
- shard-iclb: NOTRUN -> SKIP [fdo#109274] +1
* igt@kms_flip@busy-flip:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_flip@flip-vs-suspend:
- shard-hsw: PASS -> INCOMPLETE [fdo#103540]
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: NOTRUN -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-skl: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-glk: PASS -> FAIL [fdo#103167]
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +14
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +44
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-iclb: PASS -> FAIL [fdo#103167] +8
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247] +1
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
- shard-iclb: NOTRUN -> FAIL [fdo#109247] +2
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-iclb: PASS -> FAIL [fdo#109247] +15
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +2
* igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
- shard-iclb: NOTRUN -> FAIL [fdo#109052]
* igt@kms_psr@cursor_plane_onoff:
- shard-iclb: NOTRUN -> FAIL [fdo#107383]
* igt@kms_psr@primary_mmap_cpu:
- shard-iclb: PASS -> FAIL [fdo#107383]
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: PASS -> SKIP [fdo#109441] +3
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: NOTRUN -> SKIP [fdo#109441]
* igt@kms_rotation_crc@bad-pixel-format:
- shard-iclb: NOTRUN -> SKIP [fdo#109289]
* igt@kms_universal_plane@cursor-fb-leak-pipe-d:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-iclb: PASS -> FAIL [fdo#104894]
* igt@prime_nv_api@i915_nv_import_twice_check_flink_name:
- shard-iclb: NOTRUN -> SKIP [fdo#109291] +3
* igt@prime_vgem@coherency-gtt:
- shard-iclb: NOTRUN -> SKIP [fdo#109292]
* igt@prime_vgem@fence-wait-bsd1:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +11
#### Possible fixes ####
* igt@gem_exec_schedule@wide-blt:
- shard-iclb: DMESG-WARN [fdo#109638] -> PASS
* igt@gem_exec_suspend@basic-s3:
- shard-skl: INCOMPLETE [fdo#104108] -> PASS
* igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
- shard-iclb: INCOMPLETE [fdo#107713] -> PASS
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-iclb: INCOMPLETE [fdo#109100] / [fdo#109766] / [fdo#109801] -> PASS
* igt@gem_tiled_fence_blits@normal:
- shard-iclb: TIMEOUT [fdo#109673] -> PASS +1
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-iclb: FAIL [fdo#107725] -> PASS
* igt@kms_color@pipe-b-legacy-gamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-128x128-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-iclb: FAIL [fdo#103167] -> PASS +8
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
- shard-apl: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-glk: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt:
- shard-iclb: FAIL [fdo#109247] -> PASS +12
* {igt@kms_plane@pixel-format-pipe-b-planes-source-clamping}:
- shard-apl: FAIL [fdo#110033] -> PASS
* {igt@kms_plane@plane-position-covered-pipe-b-planes}:
- shard-iclb: FAIL [fdo#110038] -> PASS +1
* {igt@kms_plane_multiple@atomic-pipe-a-tiling-none}:
- shard-iclb: FAIL [fdo#110037] -> PASS +1
* {igt@kms_plane_multiple@atomic-pipe-b-tiling-none}:
- shard-apl: FAIL [fdo#110037] -> PASS
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: SKIP [fdo#109441] -> PASS +1
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: DMESG-FAIL [fdo#105763] -> PASS
* igt@kms_vblank@pipe-c-ts-continuation-modeset-rpm:
- shard-apl: FAIL [fdo#104894] -> PASS
#### Warnings ####
* igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
- shard-glk: FAIL [fdo#110098] -> SKIP [fdo#109271] / [fdo#109278]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105454]: https://bugs.freedesktop.org/show_bug.cgi?id=105454
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
[fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107847]: https://bugs.freedesktop.org/show_bug.cgi?id=107847
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108059]: https://bugs.freedesktop.org/show_bug.cgi?id=108059
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109052]: https://bugs.freedesktop.org/show_bug.cgi?id=109052
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109290]: https://bugs.freedesktop.org/show_bug.cgi?id=109290
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109292]: https://bugs.freedesktop.org/show_bug.cgi?id=109292
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109638]: https://bugs.freedesktop.org/show_bug.cgi?id=109638
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#109766]: https://bugs.freedesktop.org/show_bug.cgi?id=109766
[fdo#109801]: https://bugs.freedesktop.org/show_bug.cgi?id=109801
[fdo#110032]: https://bugs.freedesktop.org/show_bug.cgi?id=110032
[fdo#110033]: https://bugs.freedesktop.org/show_bug.cgi?id=110033
[fdo#110037]: https://bugs.freedesktop.org/show_bug.cgi?id=110037
[fdo#110038]: https://bugs.freedesktop.org/show_bug.cgi?id=110038
[fdo#110098]: https://bugs.freedesktop.org/show_bug.cgi?id=110098
[fdo#110129]: https://bugs.freedesktop.org/show_bug.cgi?id=110129
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5753 -> Patchwork_12476
CI_DRM_5753: 0eb0838c0c26378949de6816166117c8b2d73caa @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4887: 5a7c7575b5bb9542f722ed6ba095b9d62609cd56 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12476: 054624c06486283fbfdd74444224ea18e881448a @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12476/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v4 0/3] drm/i915: introduce macros to define register contents
2019-03-15 13:56 [PATCH v4 0/3] drm/i915: introduce macros to define register contents Jani Nikula
` (4 preceding siblings ...)
2019-03-15 17:01 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-03-15 22:58 ` Rodrigo Vivi
2019-03-18 14:57 ` Jani Nikula
5 siblings, 1 reply; 8+ messages in thread
From: Rodrigo Vivi @ 2019-03-15 22:58 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Fri, Mar 15, 2019 at 03:56:17PM +0200, Jani Nikula wrote:
> v4 of [1], rebased and very mildly tweaked, with the intention to merge.
before it starts conflicting again :)
> I added
> Chris' Reviewed-bys despite the rebase.
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Do you intend to follow-up with a big sed or coccinelle?
and document that we should prefer REG_BIT?
>
> BR,
> Jani.
>
>
> [1] http://mid.mail-archive.com/cover.1551286447.git.jani.nikula@intel.com
>
>
> Jani Nikula (3):
> drm/i915: introduce REG_BIT() and REG_GENMASK() to define register
> contents
> drm/i915: deprecate _SHIFT in favor of _MASK passed to accessors
> drm/i915: use REG_FIELD_PREP() to define register bitfield values
>
> drivers/gpu/drm/i915/i915_reg.h | 182 +++++++++++++++++++-----------
> drivers/gpu/drm/i915/intel_dp.c | 42 +++----
> drivers/gpu/drm/i915/intel_lvds.c | 42 ++++---
> 3 files changed, 150 insertions(+), 116 deletions(-)
>
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v4 0/3] drm/i915: introduce macros to define register contents
2019-03-15 22:58 ` [PATCH v4 0/3] drm/i915: introduce macros to define register contents Rodrigo Vivi
@ 2019-03-18 14:57 ` Jani Nikula
0 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2019-03-18 14:57 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Fri, 15 Mar 2019, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Fri, Mar 15, 2019 at 03:56:17PM +0200, Jani Nikula wrote:
>> v4 of [1], rebased and very mildly tweaked, with the intention to merge.
>
> before it starts conflicting again :)
>
>> I added
>> Chris' Reviewed-bys despite the rebase.
>
> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Thanks, pushed.
> Do you intend to follow-up with a big sed or coccinelle?
> and document that we should prefer REG_BIT?
It's already documented in i915_reg.h. I'm not keen on disrupting
everything with the mass changes.
BR,
Jani.
>
>
>>
>> BR,
>> Jani.
>>
>>
>> [1] http://mid.mail-archive.com/cover.1551286447.git.jani.nikula@intel.com
>>
>>
>> Jani Nikula (3):
>> drm/i915: introduce REG_BIT() and REG_GENMASK() to define register
>> contents
>> drm/i915: deprecate _SHIFT in favor of _MASK passed to accessors
>> drm/i915: use REG_FIELD_PREP() to define register bitfield values
>>
>> drivers/gpu/drm/i915/i915_reg.h | 182 +++++++++++++++++++-----------
>> drivers/gpu/drm/i915/intel_dp.c | 42 +++----
>> drivers/gpu/drm/i915/intel_lvds.c | 42 ++++---
>> 3 files changed, 150 insertions(+), 116 deletions(-)
>>
>> --
>> 2.20.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread