[GLK MIPI DSI V7] GLK MIPI DSI VIDEO MODE PATCHES

[GLK MIPI DSI V7] GLK MIPI DSI VIDEO MODE PATCHES

[Madhav Chauhan]

The patches in this list enable MIPI DSI video mode
support for GLK platform. Tesed locally.
v2: Renamed bitfields macros as per review comments(Jani)
v3: Code alignment/abstraction as per arch (Jani review comments)
v4: Fix MIPI DSI disable sequence. Review comments(Jani)
v5: Review comments addressed for restructuring code (Jani & Ander)
v6: Changes in enable i/o sequence, remove compile warning (Jani review comments)
v7: Patch (GLK MIPI DSI V6 3/7) rebased to Han dsi restructuring series [1]
    [1]: https://patchwork.freedesktop.org/series/20361
    Rest of the GLK dsi video mode patches which published from
    v1 to v6 merged to drm-tip.

Deepak M (1):
  drm/i915/glk: Add MIPIIO Enable/disable sequence

 drivers/gpu/drm/i915/intel_dsi.c | 206 ++++++++++++++++++++++++++++++++++++---
 1 file changed, 195 insertions(+), 11 deletions(-)

-- 
1.9.1

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[GLK MIPI DSI V7] drm/i915/glk: Add MIPIIO Enable/disable sequence

[Madhav Chauhan]

From: Deepak M <m.deepak@intel.com>

v2: Addressed Jani's Review comments(renamed bit field macros)
v3: Jani's Review comment for aligning code to platforms and added
wrapper functions.
v4: Corrected enable/disable seuqence as per BSPEC
v5: Corrected waiting twice for same bit (Review comments: Jani)
v6: Rebased to Han's patches(dsi restructuring code)

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 206 ++++++++++++++++++++++++++++++++++++---
 1 file changed, 195 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 20ed799..8e97bae3 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -357,6 +357,109 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 	return true;
 }
 
+static void glk_dsi_device_ready(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 tmp, val;
+
+	/* Set the MIPI mode
+	 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
+	 * Power ON MIPI IO first and then write into IO reset and LP wake bits
+	 */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(MIPI_CTRL(port));
+		I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
+	}
+
+	/* Put the IO into reset */
+	tmp = I915_READ(MIPI_CTRL(PORT_A));
+	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
+	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
+
+	/* Program LP Wake */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(MIPI_CTRL(port));
+		tmp |= GLK_LP_WAKE;
+		I915_WRITE(MIPI_CTRL(port), tmp);
+	}
+
+	/* Wait for Pwr ACK */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+				MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
+				GLK_MIPIIO_PORT_POWERED, 20))
+			DRM_ERROR("MIPIO port is powergated\n");
+	}
+
+	/* Wait for MIPI PHY status bit to set */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+				MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
+				GLK_PHY_STATUS_PORT_READY, 20))
+			DRM_ERROR("PHY is not ON\n");
+	}
+
+	/* Get IO out of reset */
+	tmp = I915_READ(MIPI_CTRL(PORT_A));
+	I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED);
+
+	/* Get IO out of Low power state*/
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
+			val = I915_READ(MIPI_DEVICE_READY(port));
+			val &= ~ULPS_STATE_MASK;
+			val |= DEVICE_READY;
+			I915_WRITE(MIPI_DEVICE_READY(port), val);
+			usleep_range(10, 15);
+		}
+
+		/* Enter ULPS */
+		val = I915_READ(MIPI_DEVICE_READY(port));
+		val &= ~ULPS_STATE_MASK;
+		val |= (ULPS_STATE_ENTER | DEVICE_READY);
+		I915_WRITE(MIPI_DEVICE_READY(port), val);
+
+		/* Wait for ULPS Not active */
+		if (intel_wait_for_register(dev_priv,
+				MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
+				GLK_ULPS_NOT_ACTIVE, 20))
+
+		/* Exit ULPS */
+		val = I915_READ(MIPI_DEVICE_READY(port));
+		val &= ~ULPS_STATE_MASK;
+		val |= (ULPS_STATE_EXIT | DEVICE_READY);
+		I915_WRITE(MIPI_DEVICE_READY(port), val);
+
+		/* Enter Normal Mode */
+		val = I915_READ(MIPI_DEVICE_READY(port));
+		val &= ~ULPS_STATE_MASK;
+		val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
+		I915_WRITE(MIPI_DEVICE_READY(port), val);
+
+		tmp = I915_READ(MIPI_CTRL(port));
+		tmp &= ~GLK_LP_WAKE;
+		I915_WRITE(MIPI_CTRL(port), tmp);
+	}
+
+	/* Wait for Stop state */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+				MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
+				GLK_DATA_LANE_STOP_STATE, 20))
+			DRM_ERROR("Date lane not in STOP state\n");
+	}
+
+	/* Wait for AFE LATCH */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+				BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
+				AFE_LATCHOUT, 20))
+			DRM_ERROR("D-PHY not entering LP-11 state\n");
+	}
+}
+
 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -429,11 +532,79 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		vlv_dsi_device_ready(encoder);
-	else if (IS_GEN9_LP(dev_priv))
+	else if (IS_BROXTON(dev_priv))
 		bxt_dsi_device_ready(encoder);
+	else if (IS_GEMINILAKE(dev_priv))
+		glk_dsi_device_ready(encoder);
 }
 
-static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
+static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 val;
+
+	/* Enter ULPS */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		val = I915_READ(MIPI_DEVICE_READY(port));
+		val &= ~ULPS_STATE_MASK;
+		val |= (ULPS_STATE_ENTER | DEVICE_READY);
+		I915_WRITE(MIPI_DEVICE_READY(port), val);
+	}
+
+	/* Wait for MIPI PHY status bit to unset */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+					    MIPI_CTRL(port),
+					    GLK_PHY_STATUS_PORT_READY, 0, 20))
+			DRM_ERROR("PHY is not turning OFF\n");
+	}
+
+	/* Wait for Pwr ACK bit to unset */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+					    MIPI_CTRL(port),
+					    GLK_MIPIIO_PORT_POWERED, 0, 20))
+			DRM_ERROR("MIPI IO Port is not powergated\n");
+	}
+}
+
+static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 tmp;
+
+	/* Put the IO into reset */
+	tmp = I915_READ(MIPI_CTRL(PORT_A));
+	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
+	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
+
+	/* Wait for MIPI PHY status bit to unset */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+					    MIPI_CTRL(port),
+					    GLK_PHY_STATUS_PORT_READY, 0, 20))
+			DRM_ERROR("PHY is not turning OFF\n");
+	}
+
+	/* Clear MIPI mode */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(MIPI_CTRL(port));
+		tmp &= ~GLK_MIPIIO_ENABLE;
+		I915_WRITE(MIPI_CTRL(port), tmp);
+	}
+}
+
+static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
+{
+	glk_dsi_enter_low_power_mode(encoder);
+	glk_dsi_disable_mipi_io(encoder);
+}
+
+static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -670,6 +841,17 @@ static void intel_dsi_pre_disable(struct intel_encoder *encoder,
 	}
 }
 
+static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
+	    IS_BROXTON(dev_priv))
+		vlv_dsi_clear_device_ready(encoder);
+	else if (IS_GEMINILAKE(dev_priv))
+		glk_dsi_clear_device_ready(encoder);
+}
+
 static void intel_dsi_post_disable(struct intel_encoder *encoder,
 				   struct intel_crtc_state *pipe_config,
 				   struct drm_connector_state *conn_state)
@@ -1314,18 +1496,20 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder)
 	enum port port;
 	u32 val;
 
-	for_each_dsi_port(port, intel_dsi->ports) {
-		/* Panel commands can be sent when clock is in LP11 */
-		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
+	if (!IS_GEMINILAKE(dev_priv)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			/* Panel commands can be sent when clock is in LP11 */
+			I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 
-		intel_dsi_reset_clocks(encoder, port);
-		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
+			intel_dsi_reset_clocks(encoder, port);
+			I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 
-		val = I915_READ(MIPI_DSI_FUNC_PRG(port));
-		val &= ~VID_MODE_FORMAT_MASK;
-		I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
+			val = I915_READ(MIPI_DSI_FUNC_PRG(port));
+			val &= ~VID_MODE_FORMAT_MASK;
+			I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
 
-		I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
+			I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
+		}
 	}
 }
 
-- 
1.9.1

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✓ Fi.CI.BAT: success for drm/i915/glk: Add MIPIIO Enable/disable sequence

[Patchwork]

== Series Details ==

Series: drm/i915/glk: Add MIPIIO Enable/disable sequence
URL   : https://patchwork.freedesktop.org/series/20436/
State : success

== Summary ==

Series 20436v1 drm/i915/glk: Add MIPIIO Enable/disable sequence
https://patchwork.freedesktop.org/api/1.0/series/20436/revisions/1/mbox/

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050     total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700     total:108  pass:95   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-n2820     total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u     total:278  pass:259  dwarn:1   dfail:0   fail:0   skip:18 
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29 

5d37006b578e38562382215e8782cfced9c992ce drm-tip: 2017y-02m-28d-16h-27m-13s UTC integration manifest
f25326a drm/i915/glk: Add MIPIIO Enable/disable sequence

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4012/
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Re: [GLK MIPI DSI V7] drm/i915/glk: Add MIPIIO Enable/disable sequence

[Jani Nikula]

On Wed, 01 Mar 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> v2: Addressed Jani's Review comments(renamed bit field macros)
> v3: Jani's Review comment for aligning code to platforms and added
> wrapper functions.
> v4: Corrected enable/disable seuqence as per BSPEC
> v5: Corrected waiting twice for same bit (Review comments: Jani)
> v6: Rebased to Han's patches(dsi restructuring code)
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>

Pushed to drm-intel-next-queued, thanks for the patch.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 206 ++++++++++++++++++++++++++++++++++++---
>  1 file changed, 195 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 20ed799..8e97bae3 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -357,6 +357,109 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
>  	return true;
>  }
>  
> +static void glk_dsi_device_ready(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
> +	u32 tmp, val;
> +
> +	/* Set the MIPI mode
> +	 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
> +	 * Power ON MIPI IO first and then write into IO reset and LP wake bits
> +	 */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(MIPI_CTRL(port));
> +		I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
> +	}
> +
> +	/* Put the IO into reset */
> +	tmp = I915_READ(MIPI_CTRL(PORT_A));
> +	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
> +	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
> +
> +	/* Program LP Wake */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(MIPI_CTRL(port));
> +		tmp |= GLK_LP_WAKE;
> +		I915_WRITE(MIPI_CTRL(port), tmp);
> +	}
> +
> +	/* Wait for Pwr ACK */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +				MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
> +				GLK_MIPIIO_PORT_POWERED, 20))
> +			DRM_ERROR("MIPIO port is powergated\n");
> +	}
> +
> +	/* Wait for MIPI PHY status bit to set */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +				MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
> +				GLK_PHY_STATUS_PORT_READY, 20))
> +			DRM_ERROR("PHY is not ON\n");
> +	}
> +
> +	/* Get IO out of reset */
> +	tmp = I915_READ(MIPI_CTRL(PORT_A));
> +	I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED);
> +
> +	/* Get IO out of Low power state*/
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
> +			val = I915_READ(MIPI_DEVICE_READY(port));
> +			val &= ~ULPS_STATE_MASK;
> +			val |= DEVICE_READY;
> +			I915_WRITE(MIPI_DEVICE_READY(port), val);
> +			usleep_range(10, 15);
> +		}
> +
> +		/* Enter ULPS */
> +		val = I915_READ(MIPI_DEVICE_READY(port));
> +		val &= ~ULPS_STATE_MASK;
> +		val |= (ULPS_STATE_ENTER | DEVICE_READY);
> +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +
> +		/* Wait for ULPS Not active */
> +		if (intel_wait_for_register(dev_priv,
> +				MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
> +				GLK_ULPS_NOT_ACTIVE, 20))
> +
> +		/* Exit ULPS */
> +		val = I915_READ(MIPI_DEVICE_READY(port));
> +		val &= ~ULPS_STATE_MASK;
> +		val |= (ULPS_STATE_EXIT | DEVICE_READY);
> +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +
> +		/* Enter Normal Mode */
> +		val = I915_READ(MIPI_DEVICE_READY(port));
> +		val &= ~ULPS_STATE_MASK;
> +		val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
> +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +
> +		tmp = I915_READ(MIPI_CTRL(port));
> +		tmp &= ~GLK_LP_WAKE;
> +		I915_WRITE(MIPI_CTRL(port), tmp);
> +	}
> +
> +	/* Wait for Stop state */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +				MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
> +				GLK_DATA_LANE_STOP_STATE, 20))
> +			DRM_ERROR("Date lane not in STOP state\n");
> +	}
> +
> +	/* Wait for AFE LATCH */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +				BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
> +				AFE_LATCHOUT, 20))
> +			DRM_ERROR("D-PHY not entering LP-11 state\n");
> +	}
> +}
> +
>  static void bxt_dsi_device_ready(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -429,11 +532,79 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
>  
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		vlv_dsi_device_ready(encoder);
> -	else if (IS_GEN9_LP(dev_priv))
> +	else if (IS_BROXTON(dev_priv))
>  		bxt_dsi_device_ready(encoder);
> +	else if (IS_GEMINILAKE(dev_priv))
> +		glk_dsi_device_ready(encoder);
>  }
>  
> -static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> +static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
> +	u32 val;
> +
> +	/* Enter ULPS */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		val = I915_READ(MIPI_DEVICE_READY(port));
> +		val &= ~ULPS_STATE_MASK;
> +		val |= (ULPS_STATE_ENTER | DEVICE_READY);
> +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +	}
> +
> +	/* Wait for MIPI PHY status bit to unset */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +					    MIPI_CTRL(port),
> +					    GLK_PHY_STATUS_PORT_READY, 0, 20))
> +			DRM_ERROR("PHY is not turning OFF\n");
> +	}
> +
> +	/* Wait for Pwr ACK bit to unset */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +					    MIPI_CTRL(port),
> +					    GLK_MIPIIO_PORT_POWERED, 0, 20))
> +			DRM_ERROR("MIPI IO Port is not powergated\n");
> +	}
> +}
> +
> +static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
> +	u32 tmp;
> +
> +	/* Put the IO into reset */
> +	tmp = I915_READ(MIPI_CTRL(PORT_A));
> +	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
> +	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
> +
> +	/* Wait for MIPI PHY status bit to unset */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +					    MIPI_CTRL(port),
> +					    GLK_PHY_STATUS_PORT_READY, 0, 20))
> +			DRM_ERROR("PHY is not turning OFF\n");
> +	}
> +
> +	/* Clear MIPI mode */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(MIPI_CTRL(port));
> +		tmp &= ~GLK_MIPIIO_ENABLE;
> +		I915_WRITE(MIPI_CTRL(port), tmp);
> +	}
> +}
> +
> +static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
> +{
> +	glk_dsi_enter_low_power_mode(encoder);
> +	glk_dsi_disable_mipi_io(encoder);
> +}
> +
> +static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> @@ -670,6 +841,17 @@ static void intel_dsi_pre_disable(struct intel_encoder *encoder,
>  	}
>  }
>  
> +static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> +	    IS_BROXTON(dev_priv))
> +		vlv_dsi_clear_device_ready(encoder);
> +	else if (IS_GEMINILAKE(dev_priv))
> +		glk_dsi_clear_device_ready(encoder);
> +}
> +
>  static void intel_dsi_post_disable(struct intel_encoder *encoder,
>  				   struct intel_crtc_state *pipe_config,
>  				   struct drm_connector_state *conn_state)
> @@ -1314,18 +1496,20 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder)
>  	enum port port;
>  	u32 val;
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		/* Panel commands can be sent when clock is in LP11 */
> -		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
> +	if (!IS_GEMINILAKE(dev_priv)) {
> +		for_each_dsi_port(port, intel_dsi->ports) {
> +			/* Panel commands can be sent when clock is in LP11 */
> +			I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
>  
> -		intel_dsi_reset_clocks(encoder, port);
> -		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> +			intel_dsi_reset_clocks(encoder, port);
> +			I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
>  
> -		val = I915_READ(MIPI_DSI_FUNC_PRG(port));
> -		val &= ~VID_MODE_FORMAT_MASK;
> -		I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
> +			val = I915_READ(MIPI_DSI_FUNC_PRG(port));
> +			val &= ~VID_MODE_FORMAT_MASK;
> +			I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
>  
> -		I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> +			I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> +		}
>  	}
>  }

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [GLK MIPI DSI V7] drm/i915/glk: Add MIPIIO Enable/disable sequence

[Jani Nikula]

On Wed, 01 Mar 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> v2: Addressed Jani's Review comments(renamed bit field macros)
> v3: Jani's Review comment for aligning code to platforms and added
> wrapper functions.
> v4: Corrected enable/disable seuqence as per BSPEC
> v5: Corrected waiting twice for same bit (Review comments: Jani)
> v6: Rebased to Han's patches(dsi restructuring code)
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 206 ++++++++++++++++++++++++++++++++++++---
>  1 file changed, 195 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 20ed799..8e97bae3 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -357,6 +357,109 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
>  	return true;
>  }
>  
> +static void glk_dsi_device_ready(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
> +	u32 tmp, val;
> +
> +	/* Set the MIPI mode
> +	 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
> +	 * Power ON MIPI IO first and then write into IO reset and LP wake bits
> +	 */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(MIPI_CTRL(port));
> +		I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
> +	}
> +
> +	/* Put the IO into reset */
> +	tmp = I915_READ(MIPI_CTRL(PORT_A));
> +	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
> +	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
> +
> +	/* Program LP Wake */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(MIPI_CTRL(port));
> +		tmp |= GLK_LP_WAKE;
> +		I915_WRITE(MIPI_CTRL(port), tmp);
> +	}
> +
> +	/* Wait for Pwr ACK */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +				MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
> +				GLK_MIPIIO_PORT_POWERED, 20))
> +			DRM_ERROR("MIPIO port is powergated\n");
> +	}
> +
> +	/* Wait for MIPI PHY status bit to set */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +				MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
> +				GLK_PHY_STATUS_PORT_READY, 20))
> +			DRM_ERROR("PHY is not ON\n");
> +	}
> +
> +	/* Get IO out of reset */
> +	tmp = I915_READ(MIPI_CTRL(PORT_A));
> +	I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED);
> +
> +	/* Get IO out of Low power state*/
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
> +			val = I915_READ(MIPI_DEVICE_READY(port));
> +			val &= ~ULPS_STATE_MASK;
> +			val |= DEVICE_READY;
> +			I915_WRITE(MIPI_DEVICE_READY(port), val);
> +			usleep_range(10, 15);
> +		}
> +
> +		/* Enter ULPS */
> +		val = I915_READ(MIPI_DEVICE_READY(port));
> +		val &= ~ULPS_STATE_MASK;
> +		val |= (ULPS_STATE_ENTER | DEVICE_READY);
> +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +
> +		/* Wait for ULPS Not active */
> +		if (intel_wait_for_register(dev_priv,
> +				MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
> +				GLK_ULPS_NOT_ACTIVE, 20))


Auch, I missed this. The if statement covers the next line, and my
compiler didn't complain. I already pushed this, so please send a
follow-up fix on top.

BR,
Jani.

> +
> +		/* Exit ULPS */
> +		val = I915_READ(MIPI_DEVICE_READY(port));
> +		val &= ~ULPS_STATE_MASK;
> +		val |= (ULPS_STATE_EXIT | DEVICE_READY);
> +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +
> +		/* Enter Normal Mode */
> +		val = I915_READ(MIPI_DEVICE_READY(port));
> +		val &= ~ULPS_STATE_MASK;
> +		val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
> +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +
> +		tmp = I915_READ(MIPI_CTRL(port));
> +		tmp &= ~GLK_LP_WAKE;
> +		I915_WRITE(MIPI_CTRL(port), tmp);
> +	}
> +
> +	/* Wait for Stop state */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +				MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
> +				GLK_DATA_LANE_STOP_STATE, 20))
> +			DRM_ERROR("Date lane not in STOP state\n");
> +	}
> +
> +	/* Wait for AFE LATCH */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +				BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
> +				AFE_LATCHOUT, 20))
> +			DRM_ERROR("D-PHY not entering LP-11 state\n");
> +	}
> +}
> +
>  static void bxt_dsi_device_ready(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -429,11 +532,79 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
>  
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		vlv_dsi_device_ready(encoder);
> -	else if (IS_GEN9_LP(dev_priv))
> +	else if (IS_BROXTON(dev_priv))
>  		bxt_dsi_device_ready(encoder);
> +	else if (IS_GEMINILAKE(dev_priv))
> +		glk_dsi_device_ready(encoder);
>  }
>  
> -static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> +static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
> +	u32 val;
> +
> +	/* Enter ULPS */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		val = I915_READ(MIPI_DEVICE_READY(port));
> +		val &= ~ULPS_STATE_MASK;
> +		val |= (ULPS_STATE_ENTER | DEVICE_READY);
> +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +	}
> +
> +	/* Wait for MIPI PHY status bit to unset */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +					    MIPI_CTRL(port),
> +					    GLK_PHY_STATUS_PORT_READY, 0, 20))
> +			DRM_ERROR("PHY is not turning OFF\n");
> +	}
> +
> +	/* Wait for Pwr ACK bit to unset */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +					    MIPI_CTRL(port),
> +					    GLK_MIPIIO_PORT_POWERED, 0, 20))
> +			DRM_ERROR("MIPI IO Port is not powergated\n");
> +	}
> +}
> +
> +static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
> +	u32 tmp;
> +
> +	/* Put the IO into reset */
> +	tmp = I915_READ(MIPI_CTRL(PORT_A));
> +	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
> +	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
> +
> +	/* Wait for MIPI PHY status bit to unset */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (intel_wait_for_register(dev_priv,
> +					    MIPI_CTRL(port),
> +					    GLK_PHY_STATUS_PORT_READY, 0, 20))
> +			DRM_ERROR("PHY is not turning OFF\n");
> +	}
> +
> +	/* Clear MIPI mode */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(MIPI_CTRL(port));
> +		tmp &= ~GLK_MIPIIO_ENABLE;
> +		I915_WRITE(MIPI_CTRL(port), tmp);
> +	}
> +}
> +
> +static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
> +{
> +	glk_dsi_enter_low_power_mode(encoder);
> +	glk_dsi_disable_mipi_io(encoder);
> +}
> +
> +static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> @@ -670,6 +841,17 @@ static void intel_dsi_pre_disable(struct intel_encoder *encoder,
>  	}
>  }
>  
> +static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> +	    IS_BROXTON(dev_priv))
> +		vlv_dsi_clear_device_ready(encoder);
> +	else if (IS_GEMINILAKE(dev_priv))
> +		glk_dsi_clear_device_ready(encoder);
> +}
> +
>  static void intel_dsi_post_disable(struct intel_encoder *encoder,
>  				   struct intel_crtc_state *pipe_config,
>  				   struct drm_connector_state *conn_state)
> @@ -1314,18 +1496,20 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder)
>  	enum port port;
>  	u32 val;
>  
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -		/* Panel commands can be sent when clock is in LP11 */
> -		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
> +	if (!IS_GEMINILAKE(dev_priv)) {
> +		for_each_dsi_port(port, intel_dsi->ports) {
> +			/* Panel commands can be sent when clock is in LP11 */
> +			I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
>  
> -		intel_dsi_reset_clocks(encoder, port);
> -		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> +			intel_dsi_reset_clocks(encoder, port);
> +			I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
>  
> -		val = I915_READ(MIPI_DSI_FUNC_PRG(port));
> -		val &= ~VID_MODE_FORMAT_MASK;
> -		I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
> +			val = I915_READ(MIPI_DSI_FUNC_PRG(port));
> +			val &= ~VID_MODE_FORMAT_MASK;
> +			I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
>  
> -		I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> +			I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> +		}
>  	}
>  }

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [GLK MIPI DSI V7] drm/i915/glk: Add MIPIIO Enable/disable sequence

[Chauhan, Madhav]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Wednesday, March 1, 2017 7:44 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Conselvan De Oliveira, Ander <ander.conselvan.de.oliveira@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
> <indranil.mukherjee@intel.com>; Saarinen, Jani <jani.saarinen@intel.com>;
> Kamath, Sunil <sunil.kamath@intel.com>; Deepak M
> <m.deepak@intel.com>; Chauhan, Madhav <madhav.chauhan@intel.com>
> Subject: Re: [GLK MIPI DSI V7] drm/i915/glk: Add MIPIIO Enable/disable
> sequence
> 
> On Wed, 01 Mar 2017, Madhav Chauhan <madhav.chauhan@intel.com>
> wrote:
> > From: Deepak M <m.deepak@intel.com>
> >
> > v2: Addressed Jani's Review comments(renamed bit field macros)
> > v3: Jani's Review comment for aligning code to platforms and added
> > wrapper functions.
> > v4: Corrected enable/disable seuqence as per BSPEC
> > v5: Corrected waiting twice for same bit (Review comments: Jani)
> > v6: Rebased to Han's patches(dsi restructuring code)
> >
> > Signed-off-by: Deepak M <m.deepak@intel.com>
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dsi.c | 206
> > ++++++++++++++++++++++++++++++++++++---
> >  1 file changed, 195 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > b/drivers/gpu/drm/i915/intel_dsi.c
> > index 20ed799..8e97bae3 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -357,6 +357,109 @@ static bool intel_dsi_compute_config(struct
> intel_encoder *encoder,
> >  	return true;
> >  }
> >
> > +static void glk_dsi_device_ready(struct intel_encoder *encoder) {
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> > +	enum port port;
> > +	u32 tmp, val;
> > +
> > +	/* Set the MIPI mode
> > +	 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
> > +	 * Power ON MIPI IO first and then write into IO reset and LP wake
> bits
> > +	 */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		tmp = I915_READ(MIPI_CTRL(port));
> > +		I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
> > +	}
> > +
> > +	/* Put the IO into reset */
> > +	tmp = I915_READ(MIPI_CTRL(PORT_A));
> > +	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
> > +	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
> > +
> > +	/* Program LP Wake */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		tmp = I915_READ(MIPI_CTRL(port));
> > +		tmp |= GLK_LP_WAKE;
> > +		I915_WRITE(MIPI_CTRL(port), tmp);
> > +	}
> > +
> > +	/* Wait for Pwr ACK */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (intel_wait_for_register(dev_priv,
> > +				MIPI_CTRL(port),
> GLK_MIPIIO_PORT_POWERED,
> > +				GLK_MIPIIO_PORT_POWERED, 20))
> > +			DRM_ERROR("MIPIO port is powergated\n");
> > +	}
> > +
> > +	/* Wait for MIPI PHY status bit to set */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (intel_wait_for_register(dev_priv,
> > +				MIPI_CTRL(port),
> GLK_PHY_STATUS_PORT_READY,
> > +				GLK_PHY_STATUS_PORT_READY, 20))
> > +			DRM_ERROR("PHY is not ON\n");
> > +	}
> > +
> > +	/* Get IO out of reset */
> > +	tmp = I915_READ(MIPI_CTRL(PORT_A));
> > +	I915_WRITE(MIPI_CTRL(PORT_A), tmp |
> GLK_MIPIIO_RESET_RELEASED);
> > +
> > +	/* Get IO out of Low power state*/
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (!(I915_READ(MIPI_DEVICE_READY(port)) &
> DEVICE_READY)) {
> > +			val = I915_READ(MIPI_DEVICE_READY(port));
> > +			val &= ~ULPS_STATE_MASK;
> > +			val |= DEVICE_READY;
> > +			I915_WRITE(MIPI_DEVICE_READY(port), val);
> > +			usleep_range(10, 15);
> > +		}
> > +
> > +		/* Enter ULPS */
> > +		val = I915_READ(MIPI_DEVICE_READY(port));
> > +		val &= ~ULPS_STATE_MASK;
> > +		val |= (ULPS_STATE_ENTER | DEVICE_READY);
> > +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> > +
> > +		/* Wait for ULPS Not active */
> > +		if (intel_wait_for_register(dev_priv,
> > +				MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
> > +				GLK_ULPS_NOT_ACTIVE, 20))
> 
> 
> Auch, I missed this. The if statement covers the next line, and my compiler
> didn't complain. I already pushed this, so please send a follow-up fix on top.

Done. Thanks for capturing this.

> 
> BR,
> Jani.
> 
> > +
> > +		/* Exit ULPS */
> > +		val = I915_READ(MIPI_DEVICE_READY(port));
> > +		val &= ~ULPS_STATE_MASK;
> > +		val |= (ULPS_STATE_EXIT | DEVICE_READY);
> > +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> > +
> > +		/* Enter Normal Mode */
> > +		val = I915_READ(MIPI_DEVICE_READY(port));
> > +		val &= ~ULPS_STATE_MASK;
> > +		val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
> > +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> > +
> > +		tmp = I915_READ(MIPI_CTRL(port));
> > +		tmp &= ~GLK_LP_WAKE;
> > +		I915_WRITE(MIPI_CTRL(port), tmp);
> > +	}
> > +
> > +	/* Wait for Stop state */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (intel_wait_for_register(dev_priv,
> > +				MIPI_CTRL(port),
> GLK_DATA_LANE_STOP_STATE,
> > +				GLK_DATA_LANE_STOP_STATE, 20))
> > +			DRM_ERROR("Date lane not in STOP state\n");
> > +	}
> > +
> > +	/* Wait for AFE LATCH */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (intel_wait_for_register(dev_priv,
> > +				BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
> > +				AFE_LATCHOUT, 20))
> > +			DRM_ERROR("D-PHY not entering LP-11 state\n");
> > +	}
> > +}
> > +
> >  static void bxt_dsi_device_ready(struct intel_encoder *encoder)  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@
> > -429,11 +532,79 @@ static void intel_dsi_device_ready(struct
> > intel_encoder *encoder)
> >
> >  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> >  		vlv_dsi_device_ready(encoder);
> > -	else if (IS_GEN9_LP(dev_priv))
> > +	else if (IS_BROXTON(dev_priv))
> >  		bxt_dsi_device_ready(encoder);
> > +	else if (IS_GEMINILAKE(dev_priv))
> > +		glk_dsi_device_ready(encoder);
> >  }
> >
> > -static void intel_dsi_clear_device_ready(struct intel_encoder
> > *encoder)
> > +static void glk_dsi_enter_low_power_mode(struct intel_encoder
> > +*encoder) {
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> > +	enum port port;
> > +	u32 val;
> > +
> > +	/* Enter ULPS */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		val = I915_READ(MIPI_DEVICE_READY(port));
> > +		val &= ~ULPS_STATE_MASK;
> > +		val |= (ULPS_STATE_ENTER | DEVICE_READY);
> > +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> > +	}
> > +
> > +	/* Wait for MIPI PHY status bit to unset */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (intel_wait_for_register(dev_priv,
> > +					    MIPI_CTRL(port),
> > +					    GLK_PHY_STATUS_PORT_READY, 0,
> 20))
> > +			DRM_ERROR("PHY is not turning OFF\n");
> > +	}
> > +
> > +	/* Wait for Pwr ACK bit to unset */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (intel_wait_for_register(dev_priv,
> > +					    MIPI_CTRL(port),
> > +					    GLK_MIPIIO_PORT_POWERED, 0,
> 20))
> > +			DRM_ERROR("MIPI IO Port is not powergated\n");
> > +	}
> > +}
> > +
> > +static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) {
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> > +	enum port port;
> > +	u32 tmp;
> > +
> > +	/* Put the IO into reset */
> > +	tmp = I915_READ(MIPI_CTRL(PORT_A));
> > +	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
> > +	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
> > +
> > +	/* Wait for MIPI PHY status bit to unset */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		if (intel_wait_for_register(dev_priv,
> > +					    MIPI_CTRL(port),
> > +					    GLK_PHY_STATUS_PORT_READY, 0,
> 20))
> > +			DRM_ERROR("PHY is not turning OFF\n");
> > +	}
> > +
> > +	/* Clear MIPI mode */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		tmp = I915_READ(MIPI_CTRL(port));
> > +		tmp &= ~GLK_MIPIIO_ENABLE;
> > +		I915_WRITE(MIPI_CTRL(port), tmp);
> > +	}
> > +}
> > +
> > +static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
> > +{
> > +	glk_dsi_enter_low_power_mode(encoder);
> > +	glk_dsi_disable_mipi_io(encoder);
> > +}
> > +
> > +static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@
> > -670,6 +841,17 @@ static void intel_dsi_pre_disable(struct intel_encoder
> *encoder,
> >  	}
> >  }
> >
> > +static void intel_dsi_clear_device_ready(struct intel_encoder
> > +*encoder) {
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +
> > +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> > +	    IS_BROXTON(dev_priv))
> > +		vlv_dsi_clear_device_ready(encoder);
> > +	else if (IS_GEMINILAKE(dev_priv))
> > +		glk_dsi_clear_device_ready(encoder);
> > +}
> > +
> >  static void intel_dsi_post_disable(struct intel_encoder *encoder,
> >  				   struct intel_crtc_state *pipe_config,
> >  				   struct drm_connector_state *conn_state)
> @@ -1314,18 +1496,20
> > @@ static void intel_dsi_unprepare(struct intel_encoder *encoder)
> >  	enum port port;
> >  	u32 val;
> >
> > -	for_each_dsi_port(port, intel_dsi->ports) {
> > -		/* Panel commands can be sent when clock is in LP11 */
> > -		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
> > +	if (!IS_GEMINILAKE(dev_priv)) {
> > +		for_each_dsi_port(port, intel_dsi->ports) {
> > +			/* Panel commands can be sent when clock is in LP11
> */
> > +			I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
> >
> > -		intel_dsi_reset_clocks(encoder, port);
> > -		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> > +			intel_dsi_reset_clocks(encoder, port);
> > +			I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> >
> > -		val = I915_READ(MIPI_DSI_FUNC_PRG(port));
> > -		val &= ~VID_MODE_FORMAT_MASK;
> > -		I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
> > +			val = I915_READ(MIPI_DSI_FUNC_PRG(port));
> > +			val &= ~VID_MODE_FORMAT_MASK;
> > +			I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
> >
> > -		I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> > +			I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> > +		}
> >  	}
> >  }
> 
> --
> Jani Nikula, Intel Open Source Technology Center
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