[PATCH 0/7] OMAP4: Add 4460 base support

[PATCH 0/7] OMAP4: Add 4460 base support

[Rajendra Nayak]

This series adds base support needed to be able
to boot on a OMAP4460 device.
Patches are based on Benoit's for_3.0.1/7_hwmod_modulemode
branch and boot tested on both 4460sdp as well as 4430sdp.

Aneesh V (2):
  OMAP: ID: introduce chip detection for OMAP4460
  OMAP4: ID: add omap_has_feature for max freq supported

Rajendra Nayak (5):
  OMAP4: PRCM: OMAP4460 specific PRM and CM register bitshifts
  OMAP4: clocks: Update the clock tree with 4460 clock nodes
  OMAP4: powerdomain: Reuse on 4460 using CHIP_IS_44XX
  OMAP4: clockdomain: Reuse on 4460 using CHIP_IS_44XX
  4460sdp/blaze/panda: hwmod: Prevent gpio1 reset during hwmod init

 arch/arm/mach-omap2/board-4430sdp.c           |   14 ++
 arch/arm/mach-omap2/board-omap4panda.c        |   14 ++
 arch/arm/mach-omap2/clock44xx_data.c          |   39 +++++
 arch/arm/mach-omap2/clockdomains44xx_data.c   |  200 ++++++++++++------------
 arch/arm/mach-omap2/cm-regbits-44xx.h         |   36 +++++
 arch/arm/mach-omap2/id.c                      |   44 +++++-
 arch/arm/mach-omap2/powerdomains44xx_data.c   |   30 ++--
 arch/arm/mach-omap2/prm-regbits-44xx.h        |    8 +
 arch/arm/plat-omap/include/plat/clkdev_omap.h |    2 +-
 arch/arm/plat-omap/include/plat/clock.h       |    3 +-
 arch/arm/plat-omap/include/plat/cpu.h         |   32 ++++-
 11 files changed, 301 insertions(+), 121 deletions(-)

-- 
1.7.4.1

[PATCH 1/7] OMAP: ID: introduce chip detection for OMAP4460

[Rajendra Nayak]

From: Aneesh V <aneesh@ti.com>

Add support for detecting the latest in the OMAP4 family: OMAP4460
Among other changes, the new chip also can support 1.5GHz A9s,
1080p stereoscopic 3D and 12 MP stereo (dual camera). In addition,
we have changes to OPPs supported, clock tree etc, hence having a
chip detection is required.

For more details on OMAP4460, see
Highlights:
http://focus.ti.com/general/docs/wtbu/wtbuproductcontent.tsp?contentId=53243&navigationId=12843&templateId=6123
Public TRM is available here as usual:
http://focus.ti.com/general/docs/wtbu/wtbudocumentcenter.tsp?templateId=6123&navigationId=12667

[nm@ti.com: cleanups and introduction of ramp system]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/mach-omap2/id.c              |   15 ++++++++++++---
 arch/arm/plat-omap/include/plat/cpu.h |   13 ++++++++++++-
 2 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 2537090..3d43d64 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -331,8 +331,8 @@ static void __init omap3_check_revision(void)
 static void __init omap4_check_revision(void)
 {
 	u32 idcode;
-	u16 hawkeye;
 	u8 rev;
+	u16 hawkeye;
 
 	/*
 	 * The IC rev detection is done with hawkeye and rev.
@@ -344,10 +344,10 @@ static void __init omap4_check_revision(void)
 	rev = (idcode >> 28) & 0xf;
 
 	/*
-	 * Few initial ES2.0 samples IDCODE is same as ES1.0
+	 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
 	 * Use ARM register to detect the correct ES version
 	 */
-	if (!rev) {
+	if (!rev && (hawkeye != 0xb94e)) {
 		idcode = read_cpuid(CPUID_ID);
 		rev = (idcode & 0xf) - 1;
 	}
@@ -377,6 +377,15 @@ static void __init omap4_check_revision(void)
 			omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
 		}
 		break;
+	case 0xb94e:
+		switch (rev) {
+		case 0:
+		default:
+			omap_revision = OMAP4460_REV_ES1_0;
+			omap_chip.oc |= CHIP_IS_OMAP4460ES1_0;
+			break;
+		}
+		break;
 	default:
 		/* Unknown default to latest silicon rev as default */
 		omap_revision = OMAP4430_REV_ES2_2;
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 96850a6..86b1420 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -88,6 +88,7 @@ unsigned int omap_rev(void);
  * cpu_is_omap243x():	True for OMAP2430
  * cpu_is_omap343x():	True for OMAP3430
  * cpu_is_omap443x():	True for OMAP4430
+ * cpu_is_omap446x():	True for OMAP4460
  */
 #define GET_OMAP_CLASS	(omap_rev() & 0xff)
 
@@ -123,6 +124,7 @@ IS_OMAP_SUBCLASS(243x, 0x243)
 IS_OMAP_SUBCLASS(343x, 0x343)
 IS_OMAP_SUBCLASS(363x, 0x363)
 IS_OMAP_SUBCLASS(443x, 0x443)
+IS_OMAP_SUBCLASS(446x, 0x446)
 
 IS_TI_SUBCLASS(816x, 0x816)
 
@@ -137,6 +139,7 @@ IS_TI_SUBCLASS(816x, 0x816)
 #define cpu_is_ti816x()			0
 #define cpu_is_omap44xx()		0
 #define cpu_is_omap443x()		0
+#define cpu_is_omap446x()		0
 
 #if defined(MULTI_OMAP1)
 # if defined(CONFIG_ARCH_OMAP730)
@@ -361,8 +364,10 @@ IS_OMAP_TYPE(3517, 0x3517)
 # if defined(CONFIG_ARCH_OMAP4)
 # undef cpu_is_omap44xx
 # undef cpu_is_omap443x
+# undef cpu_is_omap446x
 # define cpu_is_omap44xx()		is_omap44xx()
 # define cpu_is_omap443x()		is_omap443x()
+# define cpu_is_omap446x()		is_omap446x()
 # endif
 
 /* Macros to detect if we have OMAP1 or OMAP2 */
@@ -410,6 +415,9 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP4430_REV_ES2_1	(OMAP443X_CLASS | (0x21 << 8))
 #define OMAP4430_REV_ES2_2	(OMAP443X_CLASS | (0x22 << 8))
 
+#define OMAP446X_CLASS		0x44600044
+#define OMAP4460_REV_ES1_0	(OMAP446X_CLASS | (0x10 << 8))
+
 /*
  * omap_chip bits
  *
@@ -439,6 +447,7 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define CHIP_IS_OMAP4430ES2_1		(1 << 12)
 #define CHIP_IS_OMAP4430ES2_2		(1 << 13)
 #define CHIP_IS_TI816X			(1 << 14)
+#define CHIP_IS_OMAP4460ES1_0		(1 << 15)
 
 #define CHIP_IS_OMAP24XX		(CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
 
@@ -447,7 +456,9 @@ IS_OMAP_TYPE(3517, 0x3517)
 					 CHIP_IS_OMAP4430ES2_1 |	\
 					 CHIP_IS_OMAP4430ES2_2)
 
-#define CHIP_IS_OMAP44XX		(CHIP_IS_OMAP4430)
+#define CHIP_IS_OMAP446X		CHIP_IS_OMAP4460ES1_0
+
+#define CHIP_IS_OMAP44XX		(CHIP_IS_OMAP4430 | CHIP_IS_OMAP446X)
 
 /*
  * "GE" here represents "greater than or equal to" in terms of ES
-- 
1.7.4.1

[PATCH 2/7] OMAP4: ID: add omap_has_feature for max freq supported

[Rajendra Nayak]

From: Aneesh V <aneesh@ti.com>

Macros for identifying the max frequency supported by various
OMAP4 variants - Expanding along the lines of OMAP3's feature
handling.

[nm@ti.com: minor fixes for checks that should only for 443x|446x]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/mach-omap2/id.c              |   29 +++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/cpu.h |   19 +++++++++++++++++++
 2 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 3d43d64..a86d0f9 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -32,6 +32,7 @@ static struct omap_chip_id omap_chip;
 static unsigned int omap_revision;
 
 u32 omap3_features;
+u32 omap4_features;
 
 unsigned int omap_rev(void)
 {
@@ -212,6 +213,33 @@ static void __init omap3_check_features(void)
 	 */
 }
 
+static void __init omap4_check_features(void)
+{
+	u32 si_type;
+
+	omap4_features = 0;
+
+	if (cpu_is_omap443x())
+		omap4_features |= OMAP4_HAS_MPU_1GHZ;
+
+
+	if (cpu_is_omap446x()) {
+		si_type =
+			read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
+		switch ((si_type & (3 << 16)) >> 16) {
+		case 2:
+			/* High performance device */
+			omap4_features |= OMAP4_HAS_MPU_1_5GHZ;
+			break;
+		case 1:
+		default:
+			/* Standard device */
+			omap4_features |= OMAP4_HAS_MPU_1_2GHZ;
+			break;
+		}
+	}
+}
+
 static void __init ti816x_check_features(void)
 {
 	omap3_features = OMAP3_HAS_NEON;
@@ -527,6 +555,7 @@ void __init omap2_check_revision(void)
 		return;
 	} else if (cpu_is_omap44xx()) {
 		omap4_check_revision();
+		omap4_check_features();
 		return;
 	} else {
 		pr_err("OMAP revision unknown, please fix!\n");
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 86b1420..7e1ba5c 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -507,4 +507,23 @@ OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
 OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
 OMAP3_HAS_FEATURE(sdrc, SDRC)
 
+/*
+ * Runtime detection of OMAP4 features
+ */
+extern u32 omap4_features;
+
+#define OMAP4_HAS_MPU_1GHZ		BIT(0)
+#define OMAP4_HAS_MPU_1_2GHZ		BIT(1)
+#define OMAP4_HAS_MPU_1_5GHZ		BIT(2)
+
+#define OMAP4_HAS_FEATURE(feat, flag)			\
+static inline unsigned int omap4_has_ ##feat(void)	\
+{							\
+	return omap4_features & OMAP4_HAS_ ##flag;	\
+}							\
+
+OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
+OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
+OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
+
 #endif
-- 
1.7.4.1

[PATCH 3/7] OMAP4: PRCM: OMAP4460 specific PRM and CM register bitshifts

[Rajendra Nayak]

This patch adds additional register bitshifts for
registers added in OMAP4460 platform.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
---
 arch/arm/mach-omap2/cm-regbits-44xx.h  |   36 ++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm-regbits-44xx.h |    8 +++++++
 2 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 5e96e7b..43a7c0f 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -101,6 +101,10 @@
 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT		9
 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK		(1 << 9)
 
+/* Used by CM_L4CFG_CLKSTCTRL */
+#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT		9
+#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK			(1 << 9)
+
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT		9
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK		(1 << 9)
@@ -401,6 +405,10 @@
 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT		11
 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK		(1 << 11)
 
+/* Used by CM_WKUP_CLKSTCTRL */
+#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT		13
+#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK			(1 << 13)
+
 /*
  * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
  * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
@@ -431,6 +439,10 @@
 #define OMAP4430_CLKSEL_60M_SHIFT				24
 #define OMAP4430_CLKSEL_60M_MASK				(1 << 24)
 
+/* Used by CM_MPU_MPU_CLKCTRL */
+#define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT			25
+#define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK			(1 << 25)
+
 /* Used by CM1_ABE_AESS_CLKCTRL */
 #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT				24
 #define OMAP4430_CLKSEL_AESS_FCLK_MASK				(1 << 24)
@@ -447,6 +459,10 @@
 #define OMAP4430_CLKSEL_DIV_SHIFT				24
 #define OMAP4430_CLKSEL_DIV_MASK				(1 << 24)
 
+/* Used by CM_MPU_MPU_CLKCTRL */
+#define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT			24
+#define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK			(1 << 24)
+
 /* Used by CM_CAM_FDIF_CLKCTRL */
 #define OMAP4430_CLKSEL_FCLK_SHIFT				24
 #define OMAP4430_CLKSEL_FCLK_MASK				(0x3 << 24)
@@ -542,6 +558,14 @@
 #define OMAP4430_D2D_STATDEP_SHIFT				18
 #define OMAP4430_D2D_STATDEP_MASK				(1 << 18)
 
+/* Used by CM_CLKSEL_DPLL_MPU */
+#define OMAP4460_DCC_COUNT_MAX_SHIFT				24
+#define OMAP4460_DCC_COUNT_MAX_MASK				(0xff << 24)
+
+/* Used by CM_CLKSEL_DPLL_MPU */
+#define OMAP4460_DCC_EN_SHIFT					22
+#define OMAP4460_DCC_EN_MASK					(1 << 22)
+
 /*
  * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
  * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
@@ -551,6 +575,10 @@
 #define OMAP4430_DELTAMSTEP_SHIFT				0
 #define OMAP4430_DELTAMSTEP_MASK				(0xfffff << 0)
 
+/* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
+#define OMAP4460_DELTAMSTEP_0_20_SHIFT				0
+#define OMAP4460_DELTAMSTEP_0_20_MASK				(0x1fffff << 0)
+
 /* Used by CM_DLL_CTRL */
 #define OMAP4430_DLL_OVERRIDE_SHIFT				0
 #define OMAP4430_DLL_OVERRIDE_MASK				(1 << 0)
@@ -1079,6 +1107,10 @@
 #define OMAP4430_MODULEMODE_SHIFT				0
 #define OMAP4430_MODULEMODE_MASK				(0x3 << 0)
 
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP4460_MPU_DYNDEP_SHIFT				19
+#define OMAP4460_MPU_DYNDEP_MASK				(1 << 19)
+
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT			9
 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK			(1 << 9)
@@ -1171,6 +1203,10 @@
 #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT			10
 #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK				(1 << 10)
 
+/* Used by CM_WKUP_BANDGAP_CLKCTRL */
+#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT			8
+#define OMAP4460_OPTFCLKEN_TS_FCLK_MASK				(1 << 8)
+
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT				11
 #define OMAP4430_OPTFCLKEN_TV_CLK_MASK				(1 << 11)
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index 9fd91d6..0b750cf 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -282,6 +282,14 @@
 #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT				10
 #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK				(0x3 << 10)
 
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT				8
+#define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK				(1 << 8)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT				9
+#define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK				(1 << 9)
+
 /* Used by RM_MPU_RSTST */
 #define OMAP4430_EMULATION_RST_SHIFT					0
 #define OMAP4430_EMULATION_RST_MASK					(1 << 0)
-- 
1.7.4.1

[PATCH 4/7] OMAP4: clocks: Update the clock tree with 4460 clock nodes

[Rajendra Nayak]

Add the new clock nodes (bandgap_ts_fclk, div_ts_ck) for omap4460.
Handle these nodes using the clock flags (CK_*).

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
---
 arch/arm/mach-omap2/clock44xx_data.c          |   39 +++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/clkdev_omap.h |    2 +-
 arch/arm/plat-omap/include/plat/clock.h       |    3 +-
 3 files changed, 42 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index f1cfa3c..be016ee 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1277,6 +1277,40 @@ static struct clk bandgap_fclk = {
 	.clkdm_name	= "l4_wkup_clkdm",
 };
 
+static const struct clksel_rate div3_8to32_rates[] = {
+	{ .div = 8, .val = 0, .flags = RATE_IN_44XX },
+	{ .div = 16, .val = 1, .flags = RATE_IN_44XX },
+	{ .div = 32, .val = 2, .flags = RATE_IN_44XX },
+	{ .div = 0 },
+};
+
+static const struct clksel div_ts_div[] = {
+	{ .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
+	{ .parent = NULL },
+};
+
+static struct clk div_ts_ck = {
+	.name		= "div_ts_ck",
+	.parent		= &l4_wkup_clk_mux_ck,
+	.clksel		= div_ts_div,
+	.clksel_reg	= OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_24_25_MASK,
+	.ops		= &clkops_null,
+	.recalc		= &omap2_clksel_recalc,
+	.round_rate	= &omap2_clksel_round_rate,
+	.set_rate	= &omap2_clksel_set_rate,
+};
+
+static struct clk bandgap_ts_fclk = {
+	.name		= "bandgap_ts_fclk",
+	.ops		= &clkops_omap2_dflt,
+	.enable_reg	= OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+	.enable_bit	= OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
+	.clkdm_name	= "l4_wkup_clkdm",
+	.parent		= &div_ts_ck,
+	.recalc		= &followparent_recalc,
+};
+
 static struct clk dss_48mhz_clk = {
 	.name		= "dss_48mhz_clk",
 	.parent		= &func_48mc_fclk,
@@ -2487,6 +2521,7 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"pmd_trace_clk_mux_ck",		&pmd_trace_clk_mux_ck,	CK_44XX),
 	CLK(NULL,	"syc_clk_div_ck",		&syc_clk_div_ck,	CK_44XX),
 	CLK(NULL,	"bandgap_fclk",			&bandgap_fclk,	CK_44XX),
+	CLK(NULL,	"bandgap_ts_fclk",		&bandgap_ts_fclk,	CK_446X),
 	CLK("omapdss_dss",	"video_clk",		&dss_48mhz_clk,	CK_44XX),
 	CLK("omapdss_dss",	"fck",			&dss_dss_clk,	CK_44XX),
 	CLK("omapdss_dss",	"sys_clk",		&dss_sys_clk,	CK_44XX),
@@ -2530,6 +2565,7 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"cm2_dm3_mux_ck",		&cm2_dm3_mux_ck,	CK_44XX),
 	CLK(NULL,	"cm2_dm4_mux_ck",		&cm2_dm4_mux_ck,	CK_44XX),
 	CLK(NULL,	"cm2_dm9_mux_ck",		&cm2_dm9_mux_ck,	CK_44XX),
+	CLK(NULL,	"div_ts_ck",			&div_ts_ck,	CK_446X),
 	CLK(NULL,	"dmic_sync_mux_ck",		&dmic_sync_mux_ck,	CK_44XX),
 	CLK(NULL,	"gpt1_fck",			&timer1_fck,	CK_44XX),
 	CLK(NULL,	"fdif_fclk",			&fdif_fclk,	CK_44XX),
@@ -2619,6 +2655,9 @@ int __init omap4xxx_clk_init(void)
 	if (cpu_is_omap443x()) {
 		cpu_mask = RATE_IN_4430;
 		cpu_clkflg = CK_443X;
+	} else if (cpu_is_omap446x()) {
+		cpu_mask = RATE_IN_4460;
+		cpu_clkflg = CK_446X;
 	}
 
 	clk_init(&omap2_clk_functions);
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index 4609a3f..324446b 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -45,7 +45,7 @@ struct omap_clk {
 #define CK_34XX		(CK_3430ES1 | CK_3430ES2PLUS)
 #define CK_AM35XX	(CK_3505 | CK_3517)	/* all Sitara AM35xx */
 #define CK_3XXX		(CK_34XX | CK_AM35XX | CK_36XX)
-#define CK_44XX		(CK_443X)
+#define CK_44XX		(CK_443X | CK_446X)
 
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 10349fe..df4b968 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -58,11 +58,12 @@ struct clkops {
 #define RATE_IN_36XX		(1 << 4)
 #define RATE_IN_4430		(1 << 5)
 #define RATE_IN_TI816X		(1 << 6)
+#define RATE_IN_4460		(1 << 7)
 
 #define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)
 #define RATE_IN_34XX		(RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
 #define RATE_IN_3XXX		(RATE_IN_34XX | RATE_IN_36XX)
-#define RATE_IN_44XX		(RATE_IN_4430)
+#define RATE_IN_44XX		(RATE_IN_4430 | RATE_IN_4460)
 
 /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
 #define RATE_IN_3430ES2PLUS_36XX	(RATE_IN_3430ES2PLUS | RATE_IN_36XX)
-- 
1.7.4.1

[PATCH 5/7] OMAP4: powerdomain: Reuse on 4460 using CHIP_IS_44XX

[Rajendra Nayak]

The 4460 platform has no difference in the powerdomains as compared
to the 4430 platform. Hence just update the .omap_chip field to make
sure the same powerdomain data can be reused on the 4460 platform.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
---
 arch/arm/mach-omap2/powerdomains44xx_data.c |   32 +++++++++++++-------------
 1 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index 8f46e7d..29d2e2e 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -35,7 +35,7 @@ static struct powerdomain core_44xx_pwrdm = {
 	.name		  = "core_pwrdm",
 	.prcm_offs	  = OMAP4430_PRM_CORE_INST,
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_RET_ON,
 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
 	.banks		  = 5,
@@ -61,7 +61,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
 	.name		  = "gfx_pwrdm",
 	.prcm_offs	  = OMAP4430_PRM_GFX_INST,
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 1,
 	.pwrsts_mem_ret	= {
@@ -78,7 +78,7 @@ static struct powerdomain abe_44xx_pwrdm = {
 	.name		  = "abe_pwrdm",
 	.prcm_offs	  = OMAP4430_PRM_ABE_INST,
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_OFF_RET_ON,
 	.pwrsts_logic_ret = PWRSTS_OFF,
 	.banks		  = 2,
@@ -98,7 +98,7 @@ static struct powerdomain dss_44xx_pwrdm = {
 	.name		  = "dss_pwrdm",
 	.prcm_offs	  = OMAP4430_PRM_DSS_INST,
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_OFF_RET_ON,
 	.pwrsts_logic_ret = PWRSTS_OFF,
 	.banks		  = 1,
@@ -116,7 +116,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
 	.name		  = "tesla_pwrdm",
 	.prcm_offs	  = OMAP4430_PRM_TESLA_INST,
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_OFF_RET_ON,
 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
 	.banks		  = 3,
@@ -138,7 +138,7 @@ static struct powerdomain wkup_44xx_pwrdm = {
 	.name		  = "wkup_pwrdm",
 	.prcm_offs	  = OMAP4430_PRM_WKUP_INST,
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_ON,
 	.banks		  = 1,
 	.pwrsts_mem_ret	= {
@@ -154,7 +154,7 @@ static struct powerdomain cpu0_44xx_pwrdm = {
 	.name		  = "cpu0_pwrdm",
 	.prcm_offs	  = OMAP4430_PRCM_MPU_CPU0_INST,
 	.prcm_partition	  = OMAP4430_PRCM_MPU_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_OFF_RET_ON,
 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
 	.banks		  = 1,
@@ -171,7 +171,7 @@ static struct powerdomain cpu1_44xx_pwrdm = {
 	.name		  = "cpu1_pwrdm",
 	.prcm_offs	  = OMAP4430_PRCM_MPU_CPU1_INST,
 	.prcm_partition	  = OMAP4430_PRCM_MPU_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_OFF_RET_ON,
 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
 	.banks		  = 1,
@@ -188,7 +188,7 @@ static struct powerdomain emu_44xx_pwrdm = {
 	.name		  = "emu_pwrdm",
 	.prcm_offs	  = OMAP4430_PRM_EMU_INST,
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 1,
 	.pwrsts_mem_ret	= {
@@ -204,7 +204,7 @@ static struct powerdomain mpu_44xx_pwrdm = {
 	.name		  = "mpu_pwrdm",
 	.prcm_offs	  = OMAP4430_PRM_MPU_INST,
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_OFF_RET_ON,
 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
 	.banks		  = 3,
@@ -225,7 +225,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
 	.name		  = "ivahd_pwrdm",
 	.prcm_offs	  = OMAP4430_PRM_IVAHD_INST,
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_OFF_RET_ON,
 	.pwrsts_logic_ret = PWRSTS_OFF,
 	.banks		  = 4,
@@ -249,7 +249,7 @@ static struct powerdomain cam_44xx_pwrdm = {
 	.name		  = "cam_pwrdm",
 	.prcm_offs	  = OMAP4430_PRM_CAM_INST,
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 1,
 	.pwrsts_mem_ret	= {
@@ -266,7 +266,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
 	.name		  = "l3init_pwrdm",
 	.prcm_offs	  = OMAP4430_PRM_L3INIT_INST,
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_RET_ON,
 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
 	.banks		  = 1,
@@ -284,7 +284,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
 	.name		  = "l4per_pwrdm",
 	.prcm_offs	  = OMAP4430_PRM_L4PER_INST,
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_RET_ON,
 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
 	.banks		  = 2,
@@ -307,7 +307,7 @@ static struct powerdomain always_on_core_44xx_pwrdm = {
 	.name		  = "always_on_core_pwrdm",
 	.prcm_offs	  = OMAP4430_PRM_ALWAYS_ON_INST,
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_ON,
 };
 
@@ -316,7 +316,7 @@ static struct powerdomain cefuse_44xx_pwrdm = {
 	.name		  = "cefuse_pwrdm",
 	.prcm_offs	  = OMAP4430_PRM_CEFUSE_INST,
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
-- 
1.7.4.1

[PATCH 6/7] OMAP4: clockdomain: Reuse on 4460 using CHIP_IS_44XX

[Rajendra Nayak]

The 4460 platform has no difference in the clockdomains as compared
to the 4430 platform. Hence just update the .omap_chip field to make
sure the same clockdomain data can be reused on the 4460 platform.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
---
 arch/arm/mach-omap2/clockdomains44xx_data.c |  200 +++++++++++++-------------
 1 files changed, 100 insertions(+), 100 deletions(-)

diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index 863006a..1659813 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -36,35 +36,35 @@
 static struct clkdm_dep d2d_wkup_sleep_deps[] = {
 	{
 		.clkdm_name	 = "abe_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "ivahd_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_1_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_2_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_emif_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_init_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_cfg_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_per_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{ NULL },
 };
@@ -72,55 +72,55 @@ static struct clkdm_dep d2d_wkup_sleep_deps[] = {
 static struct clkdm_dep ducati_wkup_sleep_deps[] = {
 	{
 		.clkdm_name	 = "abe_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "ivahd_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_1_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_2_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_dss_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_emif_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_gfx_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_init_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_cfg_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_per_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_secure_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_wkup_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "tesla_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{ NULL },
 };
@@ -128,15 +128,15 @@ static struct clkdm_dep ducati_wkup_sleep_deps[] = {
 static struct clkdm_dep iss_wkup_sleep_deps[] = {
 	{
 		.clkdm_name	 = "ivahd_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_1_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_emif_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{ NULL },
 };
@@ -144,11 +144,11 @@ static struct clkdm_dep iss_wkup_sleep_deps[] = {
 static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
 	{
 		.clkdm_name	 = "l3_1_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_emif_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{ NULL },
 };
@@ -156,47 +156,47 @@ static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
 static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
 	{
 		.clkdm_name	 = "abe_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "ducati_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "ivahd_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_1_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_dss_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_emif_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_init_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_cfg_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_per_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_secure_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_wkup_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{ NULL },
 };
@@ -204,15 +204,15 @@ static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
 static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
 	{
 		.clkdm_name	 = "ivahd_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_2_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_emif_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{ NULL },
 };
@@ -220,15 +220,15 @@ static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
 static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
 	{
 		.clkdm_name	 = "ivahd_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_1_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_emif_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{ NULL },
 };
@@ -236,31 +236,31 @@ static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
 static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
 	{
 		.clkdm_name	 = "abe_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "ivahd_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_emif_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_cfg_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_per_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_secure_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_wkup_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{ NULL },
 };
@@ -268,15 +268,15 @@ static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
 static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
 	{
 		.clkdm_name	 = "l3_1_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_emif_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_per_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{ NULL },
 };
@@ -284,59 +284,59 @@ static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
 static struct clkdm_dep mpu_wkup_sleep_deps[] = {
 	{
 		.clkdm_name	 = "abe_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "ducati_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "ivahd_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_1_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_2_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_dss_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_emif_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_gfx_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_init_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_cfg_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_per_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_secure_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_wkup_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "tesla_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{ NULL },
 };
@@ -344,39 +344,39 @@ static struct clkdm_dep mpu_wkup_sleep_deps[] = {
 static struct clkdm_dep tesla_wkup_sleep_deps[] = {
 	{
 		.clkdm_name	 = "abe_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "ivahd_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_1_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_2_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_emif_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l3_init_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_cfg_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_per_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{
 		.clkdm_name	 = "l4_wkup_clkdm",
-		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
+		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX)
 	},
 	{ NULL },
 };
@@ -388,7 +388,7 @@ static struct clockdomain l4_cefuse_44xx_clkdm = {
 	.cm_inst	  = OMAP4430_CM2_CEFUSE_INST,
 	.clkdm_offs	  = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain l4_cfg_44xx_clkdm = {
@@ -399,7 +399,7 @@ static struct clockdomain l4_cfg_44xx_clkdm = {
 	.clkdm_offs	  = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
 	.dep_bit	  = OMAP4430_L4CFG_STATDEP_SHIFT,
 	.flags		  = CLKDM_CAN_HWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain tesla_44xx_clkdm = {
@@ -412,7 +412,7 @@ static struct clockdomain tesla_44xx_clkdm = {
 	.wkdep_srcs	  = tesla_wkup_sleep_deps,
 	.sleepdep_srcs	  = tesla_wkup_sleep_deps,
 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain l3_gfx_44xx_clkdm = {
@@ -425,7 +425,7 @@ static struct clockdomain l3_gfx_44xx_clkdm = {
 	.wkdep_srcs	  = l3_gfx_wkup_sleep_deps,
 	.sleepdep_srcs	  = l3_gfx_wkup_sleep_deps,
 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain ivahd_44xx_clkdm = {
@@ -438,7 +438,7 @@ static struct clockdomain ivahd_44xx_clkdm = {
 	.wkdep_srcs	  = ivahd_wkup_sleep_deps,
 	.sleepdep_srcs	  = ivahd_wkup_sleep_deps,
 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain l4_secure_44xx_clkdm = {
@@ -451,7 +451,7 @@ static struct clockdomain l4_secure_44xx_clkdm = {
 	.wkdep_srcs	  = l4_secure_wkup_sleep_deps,
 	.sleepdep_srcs	  = l4_secure_wkup_sleep_deps,
 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain l4_per_44xx_clkdm = {
@@ -462,7 +462,7 @@ static struct clockdomain l4_per_44xx_clkdm = {
 	.clkdm_offs	  = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
 	.dep_bit	  = OMAP4430_L4PER_STATDEP_SHIFT,
 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain abe_44xx_clkdm = {
@@ -473,7 +473,7 @@ static struct clockdomain abe_44xx_clkdm = {
 	.clkdm_offs	  = OMAP4430_CM1_ABE_ABE_CDOFFS,
 	.dep_bit	  = OMAP4430_ABE_STATDEP_SHIFT,
 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain l3_instr_44xx_clkdm = {
@@ -482,7 +482,7 @@ static struct clockdomain l3_instr_44xx_clkdm = {
 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
 	.cm_inst	  = OMAP4430_CM2_CORE_INST,
 	.clkdm_offs	  = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain l3_init_44xx_clkdm = {
@@ -495,7 +495,7 @@ static struct clockdomain l3_init_44xx_clkdm = {
 	.wkdep_srcs	  = l3_init_wkup_sleep_deps,
 	.sleepdep_srcs	  = l3_init_wkup_sleep_deps,
 	.flags		  = CLKDM_CAN_FORCE_WAKEUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain d2d_44xx_clkdm = {
@@ -507,7 +507,7 @@ static struct clockdomain d2d_44xx_clkdm = {
 	.wkdep_srcs	  = d2d_wkup_sleep_deps,
 	.sleepdep_srcs	  = d2d_wkup_sleep_deps,
 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain mpu0_44xx_clkdm = {
@@ -517,7 +517,7 @@ static struct clockdomain mpu0_44xx_clkdm = {
 	.cm_inst	  = OMAP4430_PRCM_MPU_CPU0_INST,
 	.clkdm_offs	  = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain mpu1_44xx_clkdm = {
@@ -527,7 +527,7 @@ static struct clockdomain mpu1_44xx_clkdm = {
 	.cm_inst	  = OMAP4430_PRCM_MPU_CPU1_INST,
 	.clkdm_offs	  = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain l3_emif_44xx_clkdm = {
@@ -538,7 +538,7 @@ static struct clockdomain l3_emif_44xx_clkdm = {
 	.clkdm_offs	  = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
 	.dep_bit	  = OMAP4430_MEMIF_STATDEP_SHIFT,
 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain l4_ao_44xx_clkdm = {
@@ -548,7 +548,7 @@ static struct clockdomain l4_ao_44xx_clkdm = {
 	.cm_inst	  = OMAP4430_CM2_ALWAYS_ON_INST,
 	.clkdm_offs	  = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain ducati_44xx_clkdm = {
@@ -561,7 +561,7 @@ static struct clockdomain ducati_44xx_clkdm = {
 	.wkdep_srcs	  = ducati_wkup_sleep_deps,
 	.sleepdep_srcs	  = ducati_wkup_sleep_deps,
 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain mpu_44xx_clkdm = {
@@ -573,7 +573,7 @@ static struct clockdomain mpu_44xx_clkdm = {
 	.wkdep_srcs	  = mpu_wkup_sleep_deps,
 	.sleepdep_srcs	  = mpu_wkup_sleep_deps,
 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain l3_2_44xx_clkdm = {
@@ -584,7 +584,7 @@ static struct clockdomain l3_2_44xx_clkdm = {
 	.clkdm_offs	  = OMAP4430_CM2_CORE_L3_2_CDOFFS,
 	.dep_bit	  = OMAP4430_L3_2_STATDEP_SHIFT,
 	.flags		  = CLKDM_CAN_HWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain l3_1_44xx_clkdm = {
@@ -595,7 +595,7 @@ static struct clockdomain l3_1_44xx_clkdm = {
 	.clkdm_offs	  = OMAP4430_CM2_CORE_L3_1_CDOFFS,
 	.dep_bit	  = OMAP4430_L3_1_STATDEP_SHIFT,
 	.flags		  = CLKDM_CAN_HWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain iss_44xx_clkdm = {
@@ -607,7 +607,7 @@ static struct clockdomain iss_44xx_clkdm = {
 	.wkdep_srcs	  = iss_wkup_sleep_deps,
 	.sleepdep_srcs	  = iss_wkup_sleep_deps,
 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain l3_dss_44xx_clkdm = {
@@ -620,7 +620,7 @@ static struct clockdomain l3_dss_44xx_clkdm = {
 	.wkdep_srcs	  = l3_dss_wkup_sleep_deps,
 	.sleepdep_srcs	  = l3_dss_wkup_sleep_deps,
 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain l4_wkup_44xx_clkdm = {
@@ -631,7 +631,7 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
 	.clkdm_offs	  = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
 	.dep_bit	  = OMAP4430_L4WKUP_STATDEP_SHIFT,
 	.flags		  = CLKDM_CAN_HWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain emu_sys_44xx_clkdm = {
@@ -641,7 +641,7 @@ static struct clockdomain emu_sys_44xx_clkdm = {
 	.cm_inst	  = OMAP4430_PRM_EMU_CM_INST,
 	.clkdm_offs	  = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
 	.flags		  = CLKDM_CAN_HWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 static struct clockdomain l3_dma_44xx_clkdm = {
@@ -653,7 +653,7 @@ static struct clockdomain l3_dma_44xx_clkdm = {
 	.wkdep_srcs	  = l3_dma_wkup_sleep_deps,
 	.sleepdep_srcs	  = l3_dma_wkup_sleep_deps,
 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
 };
 
 /* As clockdomains are added or removed above, this list must also be changed */
-- 
1.7.4.1

[PATCH 7/7] 4460sdp/blaze/panda: hwmod: Prevent gpio1 reset during hwmod init

[Rajendra Nayak]

For 4460sdp/blaze/panda, GPIO-7 of bank1 is used for controlling
the TPS modes, hence GPIO1 should not be reset
during init as reset will cause the TPS voltage to
drop to 0.9 V preventing the system from continuing the boot.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Moiz Sonasath <m-sonasath@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/board-4430sdp.c    |   14 ++++++++++++++
 arch/arm/mach-omap2/board-omap4panda.c |   14 ++++++++++++++
 2 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 63de2d3..7343209 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -36,6 +36,7 @@
 #include <plat/usb.h>
 #include <plat/mmc.h>
 #include <plat/omap4-keypad.h>
+#include <plat/omap_hwmod.h>
 #include <video/omapdss.h>
 
 #include "mux.h"
@@ -298,6 +299,19 @@ static void __init omap_4430sdp_init_early(void)
 #ifdef CONFIG_OMAP_32K_TIMER
 	omap2_gp_clockevent_set_gptimer(1);
 #endif
+	/*
+	 * For 4460sdp/blaze, GPIO-7 of bank1 is used for controlling
+	 * the TPS modes, hence GPIO1 should not be reset
+	 * during init as reset will cause the TPS voltage to
+	 * drop to 0.9 V  preventing the system from continuing the boot.
+	 */
+	if (cpu_is_omap446x()) {
+		struct omap_hwmod *gpio1 = omap_hwmod_lookup("gpio1");
+		if (gpio1)
+			omap_hwmod_no_setup_reset(gpio1);
+		else
+			pr_err("%s: gpio1 hwmod lookup failed\n", __func__);
+	}
 }
 
 static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 0cfe200..75a847c 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -40,6 +40,7 @@
 #include <plat/common.h>
 #include <plat/usb.h>
 #include <plat/mmc.h>
+#include <plat/omap_hwmod.h>
 #include <video/omap-panel-generic-dpi.h>
 #include "timer-gp.h"
 
@@ -100,6 +101,19 @@ static void __init omap4_panda_init_early(void)
 {
 	omap2_init_common_infrastructure();
 	omap2_init_common_devices(NULL, NULL);
+	/*
+	 * For 4460panda, GPIO-7 of bank1 is used for controling
+	 * the TPS modes, hence GPIO1 should not be reset
+	 * during init as reset will cause the TPS voltage to
+	 * drop to 0.9 V preventing the system from continuing the boot.
+	 */
+	if (cpu_is_omap446x()) {
+		struct omap_hwmod *gpio1 = omap_hwmod_lookup("gpio1");
+		if (gpio1)
+			omap_hwmod_no_setup_reset(gpio1);
+		else
+			pr_err("%s: gpio1 hwmod lookup failed\n", __func__);
+	}
 }
 
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
-- 
1.7.4.1

Re: [PATCH 7/7] 4460sdp/blaze/panda: hwmod: Prevent gpio1 reset during hwmod init

[Tony Lindgren]

* Rajendra Nayak <rnayak@ti.com> [110630 19:03]:
> For 4460sdp/blaze/panda, GPIO-7 of bank1 is used for controlling
> the TPS modes, hence GPIO1 should not be reset
> during init as reset will cause the TPS voltage to
> drop to 0.9 V preventing the system from continuing the boot.

NAK for this patch. We don't want any of this in init_early.

The problem is with hwmod core code that wrongly assumes it
can just reset all devices.

We should fix the hwmod code to lazily only reset devices as they
are enabled, and only reset unused devices with late_initcall
when we have decent debug output. And the reset of unused devices
should be possible to turn off with some kernel cmdline option.

Regards,

Tony


> --- a/arch/arm/mach-omap2/board-4430sdp.c
> +++ b/arch/arm/mach-omap2/board-4430sdp.c
> @@ -36,6 +36,7 @@
>  #include <plat/usb.h>
>  #include <plat/mmc.h>
>  #include <plat/omap4-keypad.h>
> +#include <plat/omap_hwmod.h>
>  #include <video/omapdss.h>
>  
>  #include "mux.h"
> @@ -298,6 +299,19 @@ static void __init omap_4430sdp_init_early(void)
>  #ifdef CONFIG_OMAP_32K_TIMER
>  	omap2_gp_clockevent_set_gptimer(1);
>  #endif
> +	/*
> +	 * For 4460sdp/blaze, GPIO-7 of bank1 is used for controlling
> +	 * the TPS modes, hence GPIO1 should not be reset
> +	 * during init as reset will cause the TPS voltage to
> +	 * drop to 0.9 V  preventing the system from continuing the boot.
> +	 */
> +	if (cpu_is_omap446x()) {
> +		struct omap_hwmod *gpio1 = omap_hwmod_lookup("gpio1");
> +		if (gpio1)
> +			omap_hwmod_no_setup_reset(gpio1);
> +		else
> +			pr_err("%s: gpio1 hwmod lookup failed\n", __func__);
> +	}
>  }
>  
>  static struct omap_musb_board_data musb_board_data = {
> diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
> index 0cfe200..75a847c 100644
> --- a/arch/arm/mach-omap2/board-omap4panda.c
> +++ b/arch/arm/mach-omap2/board-omap4panda.c
> @@ -40,6 +40,7 @@
>  #include <plat/common.h>
>  #include <plat/usb.h>
>  #include <plat/mmc.h>
> +#include <plat/omap_hwmod.h>
>  #include <video/omap-panel-generic-dpi.h>
>  #include "timer-gp.h"
>  
> @@ -100,6 +101,19 @@ static void __init omap4_panda_init_early(void)
>  {
>  	omap2_init_common_infrastructure();
>  	omap2_init_common_devices(NULL, NULL);
> +	/*
> +	 * For 4460panda, GPIO-7 of bank1 is used for controling
> +	 * the TPS modes, hence GPIO1 should not be reset
> +	 * during init as reset will cause the TPS voltage to
> +	 * drop to 0.9 V preventing the system from continuing the boot.
> +	 */
> +	if (cpu_is_omap446x()) {
> +		struct omap_hwmod *gpio1 = omap_hwmod_lookup("gpio1");
> +		if (gpio1)
> +			omap_hwmod_no_setup_reset(gpio1);
> +		else
> +			pr_err("%s: gpio1 hwmod lookup failed\n", __func__);
> +	}
>  }
>  
>  static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
> -- 
> 1.7.4.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 7/7] 4460sdp/blaze/panda: hwmod: Prevent gpio1 reset during hwmod init

[Paul Walmsley]

Hi Tony

On Thu, 30 Jun 2011, Tony Lindgren wrote:

> NAK for this patch. We don't want any of this in init_early.
> 
> The problem is with hwmod core code that wrongly assumes it
> can just reset all devices.

I don't think the hwmod core code has any way of knowing which devices 
shouldn't be reset unless the board file specifically tells it.  Even if 
the reset happens right before the hwmod enable (as called by the device 
driver), the 4460 boards would still crash when the GPIO driver starts.

What you suggested below should allow those omap_hwmod_no_setup_reset() 
calls to live in init_machine, rather than init_early.  Hopefully that is 
acceptable?  So I did a test implementation of your idea, and learned some 
good news and bad news.

The good news is that it seems to work for the PM runtime-converted 
drivers.  omap_hwmod_no_setup_reset() calls can go into init_machine code.  
We should also be able to get rid of the postsetup code in 
mach-omap2/io.c.

The bad news is that the unused IP block reset code will reset IP blocks 
used by drivers that haven't been converted to use runtime PM.  The hwmod 
core code doesn't know that those IP blocks are in use, since 
omap_hwmod_enable() is never called for them.  The unused IP block reset 
code will then reset those blocks after the drivers have already probed, 
and the drivers are not expecting this :-)

GPTIMER and HSMMC drivers are the obvious problems in terms of getting a 
successful boot, but DSS is another one that may cause some problems here.  
There are HSMMC and DSS driver PM runtime conversion patches posted, 
hopefully they will go into mainline soon, but there are probably some 
other important drivers yet to be converted or yet to be pushed.

Here are some options that come to mind:

1. Wait until the driver runtime PM conversion is finished before doing 
   anything.  In the meantime, boards with IP blocks that can't be reset 
   - N810, TI 4460 boards - will have problems.

2. Merge the lazy/unused hwmod reset code, but prevent IP blocks 
   controlled by non-runtime PM drivers from being reset.  We'd have to
   maintain a list of these somewhere, perhaps in some common code called 
   by board file init_machine code.  Then we'd need to redact that list as 
   new driver runtime PM conversions complete.

3. Merge the lazy/unused hwmod reset code, but disable the unused hwmod 
   reset code until the driver runtime PM conversion is finished.  This
   could cause problems with driverless devices that are left configured
   by bootloaders or ROM code, and that problem would reoccur for each new
   OMAP chip.

Do you have a preference as to which approach to take?

> We should fix the hwmod code to lazily only reset devices as they
> are enabled, and only reset unused devices with late_initcall
> when we have decent debug output. And the reset of unused devices
> should be possible to turn off with some kernel cmdline option.


- Paul

Re: [PATCH 7/7] 4460sdp/blaze/panda: hwmod: Prevent gpio1 reset during hwmod init

[Tony Lindgren]

* Paul Walmsley <paul@pwsan.com> [110702 21:09]:
> Hi Tony
> 
> On Thu, 30 Jun 2011, Tony Lindgren wrote:
> 
> > NAK for this patch. We don't want any of this in init_early.
> > 
> > The problem is with hwmod core code that wrongly assumes it
> > can just reset all devices.
> 
> I don't think the hwmod core code has any way of knowing which devices 
> shouldn't be reset unless the board file specifically tells it.  Even if 
> the reset happens right before the hwmod enable (as called by the device 
> driver), the 4460 boards would still crash when the GPIO driver starts.
> 
> What you suggested below should allow those omap_hwmod_no_setup_reset() 
> calls to live in init_machine, rather than init_early.  Hopefully that is 
> acceptable?  So I did a test implementation of your idea, and learned some 
> good news and bad news.

Yes later on that should be fine, but preferrably not until late_initcall
so we have decent debug output even without DEBUG_LL being enabled.
 
> The good news is that it seems to work for the PM runtime-converted 
> drivers.  omap_hwmod_no_setup_reset() calls can go into init_machine code.  
> We should also be able to get rid of the postsetup code in 
> mach-omap2/io.c.
> 
> The bad news is that the unused IP block reset code will reset IP blocks 
> used by drivers that haven't been converted to use runtime PM.  The hwmod 
> core code doesn't know that those IP blocks are in use, since 
> omap_hwmod_enable() is never called for them.  The unused IP block reset 
> code will then reset those blocks after the drivers have already probed, 
> and the drivers are not expecting this :-)

I guess we should keep it disabled for now :)
 
> GPTIMER and HSMMC drivers are the obvious problems in terms of getting a 
> successful boot, but DSS is another one that may cause some problems here.  
> There are HSMMC and DSS driver PM runtime conversion patches posted, 
> hopefully they will go into mainline soon, but there are probably some 
> other important drivers yet to be converted or yet to be pushed.
> 
> Here are some options that come to mind:
> 
> 1. Wait until the driver runtime PM conversion is finished before doing 
>    anything.  In the meantime, boards with IP blocks that can't be reset 
>    - N810, TI 4460 boards - will have problems.
> 
> 2. Merge the lazy/unused hwmod reset code, but prevent IP blocks 
>    controlled by non-runtime PM drivers from being reset.  We'd have to
>    maintain a list of these somewhere, perhaps in some common code called 
>    by board file init_machine code.  Then we'd need to redact that list as 
>    new driver runtime PM conversions complete.
> 
> 3. Merge the lazy/unused hwmod reset code, but disable the unused hwmod 
>    reset code until the driver runtime PM conversion is finished.  This
>    could cause problems with driverless devices that are left configured
>    by bootloaders or ROM code, and that problem would reoccur for each new
>    OMAP chip.
> 
> Do you have a preference as to which approach to take?

I think #3 above is the safest option. How about make it only happen with
hwmod_reset=1 cmdline with 0 being the default value?

Regards,

Tony 

Re: [PATCH 7/7] 4460sdp/blaze/panda: hwmod: Prevent gpio1 reset during hwmod init

[Paul Walmsley]

Hi Tony

On Mon, 4 Jul 2011, Tony Lindgren wrote:

> * Paul Walmsley <paul@pwsan.com> [110702 21:09]:
> 
> > Here are some options that come to mind:
> > 
> > 1. Wait until the driver runtime PM conversion is finished before doing 
> >    anything.  In the meantime, boards with IP blocks that can't be reset 
> >    - N810, TI 4460 boards - will have problems.
> > 
> > 2. Merge the lazy/unused hwmod reset code, but prevent IP blocks 
> >    controlled by non-runtime PM drivers from being reset.  We'd have to
> >    maintain a list of these somewhere, perhaps in some common code called 
> >    by board file init_machine code.  Then we'd need to redact that list as 
> >    new driver runtime PM conversions complete.
> > 
> > 3. Merge the lazy/unused hwmod reset code, but disable the unused hwmod 
> >    reset code until the driver runtime PM conversion is finished.  This
> >    could cause problems with driverless devices that are left configured
> >    by bootloaders or ROM code, and that problem would reoccur for each new
> >    OMAP chip.
> > 
> > Do you have a preference as to which approach to take?
> 
> I think #3 above is the safest option. How about make it only happen with
> hwmod_reset=1 cmdline with 0 being the default value?

With the patch that was posted, that would disable all reset.  Probably we 
want to reset devices that have drivers with PM runtime support?  That 
would allow drivers to assume that they are starting from consistent 
device state.  It also should prevent some power management problems 
that are dependent on particular bootloaders.   How about if we add a 
second parameter, hwmod_reset_unused?  The default could be 'no' and then 
only devices with PM runtime-enabled drivers would be reset first.


- Paul

Re: [PATCH 7/7] 4460sdp/blaze/panda: hwmod: Prevent gpio1 reset during hwmod init

[Tony Lindgren]

* Paul Walmsley <paul@pwsan.com> [110705 00:35]:
> Hi Tony
> 
> On Mon, 4 Jul 2011, Tony Lindgren wrote:
> 
> > * Paul Walmsley <paul@pwsan.com> [110702 21:09]:
> > 
> > > Here are some options that come to mind:
> > > 
> > > 1. Wait until the driver runtime PM conversion is finished before doing 
> > >    anything.  In the meantime, boards with IP blocks that can't be reset 
> > >    - N810, TI 4460 boards - will have problems.
> > > 
> > > 2. Merge the lazy/unused hwmod reset code, but prevent IP blocks 
> > >    controlled by non-runtime PM drivers from being reset.  We'd have to
> > >    maintain a list of these somewhere, perhaps in some common code called 
> > >    by board file init_machine code.  Then we'd need to redact that list as 
> > >    new driver runtime PM conversions complete.
> > > 
> > > 3. Merge the lazy/unused hwmod reset code, but disable the unused hwmod 
> > >    reset code until the driver runtime PM conversion is finished.  This
> > >    could cause problems with driverless devices that are left configured
> > >    by bootloaders or ROM code, and that problem would reoccur for each new
> > >    OMAP chip.
> > > 
> > > Do you have a preference as to which approach to take?
> > 
> > I think #3 above is the safest option. How about make it only happen with
> > hwmod_reset=1 cmdline with 0 being the default value?
> 
> With the patch that was posted, that would disable all reset.  Probably we 
> want to reset devices that have drivers with PM runtime support?

Can't we always reset the registered hwmods automatically one at a time when
omap_device_build is called?

> That would allow drivers to assume that they are starting from consistent 
> device state.  It also should prevent some power management problems 
> that are dependent on particular bootloaders.   How about if we add a 
> second parameter, hwmod_reset_unused?  The default could be 'no' and then 
> only devices with PM runtime-enabled drivers would be reset first.

Yes I think hwmod_reset_unsed would be a better name, but do we actually
need any other reset option in addition to that?

TOny

Re: [PATCH 7/7] 4460sdp/blaze/panda: hwmod: Prevent gpio1 reset during hwmod init

[Paul Walmsley]

Hi Tony

On Tue, 5 Jul 2011, Tony Lindgren wrote:

> * Paul Walmsley <paul@pwsan.com> [110705 00:35]:
> > On Mon, 4 Jul 2011, Tony Lindgren wrote:
> > > * Paul Walmsley <paul@pwsan.com> [110702 21:09]:
> > > 
> > > > 3. Merge the lazy/unused hwmod reset code, but disable the unused hwmod 
> > > >    reset code until the driver runtime PM conversion is finished.  This
> > > >    could cause problems with driverless devices that are left configured
> > > >    by bootloaders or ROM code, and that problem would reoccur for each new
> > > >    OMAP chip.
> > >
> > > I think #3 above is the safest option. How about make it only happen with
> > > hwmod_reset=1 cmdline with 0 being the default value?
> > 
> > With the patch that was posted, that would disable all reset.  Probably we 
> > want to reset devices that have drivers with PM runtime support?
> 
> Can't we always reset the registered hwmods automatically one at a time when
> omap_device_build is called?

The experimental series that I wrote, but haven't posted yet, resets each 
IP block during the first time it's enabled -- which is probably going to 
be when omap_device_build() is called.

> > That would allow drivers to assume that they are starting from consistent 
> > device state.  It also should prevent some power management problems 
> > that are dependent on particular bootloaders.   How about if we add a 
> > second parameter, hwmod_reset_unused?  The default could be 'no' and then 
> > only devices with PM runtime-enabled drivers would be reset first.
> 
> Yes I think hwmod_reset_unsed would be a better name, but do we actually
> need any other reset option in addition to that?

If a driver doesn't reset its device(s) when it starts, then disabling all 
reset might allow the kernel to boot when the board file is missing some 
omap_hwmod_no_setup_reset() calls.

Consider the 4460 GPIO case.  If someone hasn't added in the 
omap_hwmod_no_setup_reset(gpioX_hwmod) call into the 4460 board file's 
init_machine(), then these boards would still crash on boot.

This would definitely be considered a bug in the board file, that it's 
missing that omap_hwmod_no_setup_reset() call.  But having a general 
'hwmod_no_reset' might make it easier during initial board bring-up to 
determine whether a problem is caused by reset.

In any case, it doesn't matter too much to me whether a 'hwmod_no_reset' 
option is preserved or not; this is just based on our discussion of the 
issue a few months ago.

regards

- Paul

Re: [PATCH 7/7] 4460sdp/blaze/panda: hwmod: Prevent gpio1 reset during hwmod init

[Tony Lindgren]

* Paul Walmsley <paul@pwsan.com> [110705 14:42]:
> On Tue, 5 Jul 2011, Tony Lindgren wrote:
> > 
> > Can't we always reset the registered hwmods automatically one at a time when
> > omap_device_build is called?
> 
> The experimental series that I wrote, but haven't posted yet, resets each 
> IP block during the first time it's enabled -- which is probably going to 
> be when omap_device_build() is called.

OK
 
> > > That would allow drivers to assume that they are starting from consistent 
> > > device state.  It also should prevent some power management problems 
> > > that are dependent on particular bootloaders.   How about if we add a 
> > > second parameter, hwmod_reset_unused?  The default could be 'no' and then 
> > > only devices with PM runtime-enabled drivers would be reset first.
> > 
> > Yes I think hwmod_reset_unsed would be a better name, but do we actually
> > need any other reset option in addition to that?
> 
> If a driver doesn't reset its device(s) when it starts, then disabling all 
> reset might allow the kernel to boot when the board file is missing some 
> omap_hwmod_no_setup_reset() calls.
> 
> Consider the 4460 GPIO case.  If someone hasn't added in the 
> omap_hwmod_no_setup_reset(gpioX_hwmod) call into the 4460 board file's 
> init_machine(), then these boards would still crash on boot.
> 
> This would definitely be considered a bug in the board file, that it's 
> missing that omap_hwmod_no_setup_reset() call.  But having a general 
> 'hwmod_no_reset' might make it easier during initial board bring-up to 
> determine whether a problem is caused by reset.
> 
> In any case, it doesn't matter too much to me whether a 'hwmod_no_reset' 
> option is preserved or not; this is just based on our discussion of the 
> issue a few months ago.

Yeah. Sounds like for passing the board specific flags for special case
devices is best done with omap2_init_devices() like you suggested.

Tony

Re: [PATCH 2/7] OMAP4: ID: add omap_has_feature for max freq supported

[Todd Poynor]

On Fri, Jul 01, 2011 at 07:37:56AM +0530, Rajendra Nayak wrote:
> From: Aneesh V <aneesh@ti.com>
> 
> Macros for identifying the max frequency supported by various
> OMAP4 variants - Expanding along the lines of OMAP3's feature
> handling.
> 
> [nm@ti.com: minor fixes for checks that should only for 443x|446x]
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---
>  arch/arm/mach-omap2/id.c              |   29 +++++++++++++++++++++++++++++
>  arch/arm/plat-omap/include/plat/cpu.h |   19 +++++++++++++++++++
>  2 files changed, 48 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
> index 3d43d64..a86d0f9 100644
> --- a/arch/arm/mach-omap2/id.c
> +++ b/arch/arm/mach-omap2/id.c
> @@ -32,6 +32,7 @@ static struct omap_chip_id omap_chip;
>  static unsigned int omap_revision;
>  
>  u32 omap3_features;
> +u32 omap4_features;

Since the features are enabled by cpu_is*, need to have separate masks
for OMAP3 vs. OMAP4 in same kernel?

>  
>  unsigned int omap_rev(void)
>  {
> @@ -212,6 +213,33 @@ static void __init omap3_check_features(void)
>  	 */
>  }
>  
> +static void __init omap4_check_features(void)
> +{
> +	u32 si_type;
> +
> +	omap4_features = 0;

Already guaranteed to be zero, could skip this.

> +
> +	if (cpu_is_omap443x())
> +		omap4_features |= OMAP4_HAS_MPU_1GHZ;
> +
> +
> +	if (cpu_is_omap446x()) {
> +		si_type =
> +			read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
> +		switch ((si_type & (3 << 16)) >> 16) {
> +		case 2:
> +			/* High performance device */
> +			omap4_features |= OMAP4_HAS_MPU_1_5GHZ;
> +			break;

Should this fall through to also add OMAP4_HAS_MPU_1_2GHZ?  (Or are
they mutually exclusive, or 1.5 implies 1.2 also present by
convention)?


Todd

Re: [PATCH 2/7] OMAP4: ID: add omap_has_feature for max freq supported

[Aneesh V]

On Friday 01 July 2011 08:11 AM, Todd Poynor wrote:
> On Fri, Jul 01, 2011 at 07:37:56AM +0530, Rajendra Nayak wrote:
>> From: Aneesh V<aneesh@ti.com>
>>
>> Macros for identifying the max frequency supported by various
>> OMAP4 variants - Expanding along the lines of OMAP3's feature
>> handling.
>>
>> [nm@ti.com: minor fixes for checks that should only for 443x|446x]
>> Signed-off-by: Nishanth Menon<nm@ti.com>
>> Signed-off-by: Aneesh V<aneesh@ti.com>
>> ---
>>   arch/arm/mach-omap2/id.c              |   29 +++++++++++++++++++++++++++++
>>   arch/arm/plat-omap/include/plat/cpu.h |   19 +++++++++++++++++++
>>   2 files changed, 48 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
>> index 3d43d64..a86d0f9 100644
>> --- a/arch/arm/mach-omap2/id.c
>> +++ b/arch/arm/mach-omap2/id.c
>> @@ -32,6 +32,7 @@ static struct omap_chip_id omap_chip;
>>   static unsigned int omap_revision;
>>
>>   u32 omap3_features;
>> +u32 omap4_features;
>
> Since the features are enabled by cpu_is*, need to have separate masks
> for OMAP3 vs. OMAP4 in same kernel?

No. I think they can be same. How about changing both to omap_features?
I would not like to use omap3_features for OMAP4.

>
>>
>>   unsigned int omap_rev(void)
>>   {
>> @@ -212,6 +213,33 @@ static void __init omap3_check_features(void)
>>   	 */
>>   }
>>
>> +static void __init omap4_check_features(void)
>> +{
>> +	u32 si_type;
>> +
>> +	omap4_features = 0;
>
> Already guaranteed to be zero, could skip this.

ok.

>
>> +
>> +	if (cpu_is_omap443x())
>> +		omap4_features |= OMAP4_HAS_MPU_1GHZ;
>> +
>> +
>> +	if (cpu_is_omap446x()) {
>> +		si_type =
>> +			read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
>> +		switch ((si_type&  (3<<  16))>>  16) {
>> +		case 2:
>> +			/* High performance device */
>> +			omap4_features |= OMAP4_HAS_MPU_1_5GHZ;
>> +			break;
>
> Should this fall through to also add OMAP4_HAS_MPU_1_2GHZ?  (Or are
> they mutually exclusive, or 1.5 implies 1.2 also present by
> convention)?

This is the max frequency supported by the device. So, 1.5GHz implies
availability of 1.2GHz

Re: [PATCH 1/7] OMAP: ID: introduce chip detection for OMAP4460

[Tony Lindgren]

* Rajendra Nayak <rnayak@ti.com> [110630 19:03]:
> --- a/arch/arm/mach-omap2/id.c
> +++ b/arch/arm/mach-omap2/id.c
> @@ -331,8 +331,8 @@ static void __init omap3_check_revision(void)
>  static void __init omap4_check_revision(void)
>  {
>  	u32 idcode;
> -	u16 hawkeye;
>  	u8 rev;
> +	u16 hawkeye;
>  
>  	/*
>  	 * The IC rev detection is done with hawkeye and rev.

Please leave out this change, there's no need for it.

Tony

Re: [PATCH 1/7] OMAP: ID: introduce chip detection for OMAP4460

[Aneesh V]

On Friday 01 July 2011 11:55 AM, Tony Lindgren wrote:
> * Rajendra Nayak<rnayak@ti.com>  [110630 19:03]:
>> --- a/arch/arm/mach-omap2/id.c
>> +++ b/arch/arm/mach-omap2/id.c
>> @@ -331,8 +331,8 @@ static void __init omap3_check_revision(void)
>>   static void __init omap4_check_revision(void)
>>   {
>>   	u32 idcode;
>> -	u16 hawkeye;
>>   	u8 rev;
>> +	u16 hawkeye;
>>
>>   	/*
>>   	 * The IC rev detection is done with hawkeye and rev.
>
> Please leave out this change, there's no need for it.

Ok. I will fix this.

br,
Aneesh

Re: [PATCH 0/7] OMAP4: Add 4460 base support

[Kevin Hilman]

Hi Rajendra,

Rajendra Nayak <rnayak@ti.com> writes:

> This series adds base support needed to be able
> to boot on a OMAP4460 device.
> Patches are based on Benoit's for_3.0.1/7_hwmod_modulemode
> branch and boot tested on both 4460sdp as well as 4430sdp.

Since you're on the delivery path of these patches, they  need your
signoff as well.  Several are missing your signoff.

Also, please Cc linux-arm-kernel.

Thanks,

Kevin

Re: [PATCH 0/7] OMAP4: Add 4460 base support

[Kevin Hilman]

Rajendra Nayak <rnayak@ti.com> writes:

> This series adds base support needed to be able
> to boot on a OMAP4460 device.
> Patches are based on Benoit's for_3.0.1/7_hwmod_modulemode
> branch and boot tested on both 4460sdp as well as 4430sdp.

Can you also briefly summarize the dependencies between this series an
Benoit's?   I'm assuming it is mainly because of the s/4430/44XX/
changes, and also avoiding conflicts in clockdomain and powerdomain data
files.

With that, you can add

Reviewed-by: Kevin Hilman <khilman@ti.com>

for the whole series.

Kevin

Re: [PATCH 0/7] OMAP4: Add 4460 base support

[Kevin Hilman]

On Fri, 2011-07-01 at 09:36 -0700, Kevin Hilman wrote:
> Rajendra Nayak <rnayak@ti.com> writes:
> 
> > This series adds base support needed to be able
> > to boot on a OMAP4460 device.
> > Patches are based on Benoit's for_3.0.1/7_hwmod_modulemode
> > branch and boot tested on both 4460sdp as well as 4430sdp.
> 
> Can you also briefly summarize the dependencies between this series an
> Benoit's?   I'm assuming it is mainly because of the s/4430/44XX/
> changes, and also avoiding conflicts in clockdomain and powerdomain data
> files.
> 
> With that, you can add
> 
> Reviewed-by: Kevin Hilman <khilman@ti.com>
> 
> for the whole series.

oops, except for [7/7], where I agree with Tony.

As discussed off-list, lets just drop this patch all together and state
in [0/7] that there is a limitation that until we fix the hwmod fwk to
do lazy disable as Tony suggested, 4460 can only reliably boot at OPP50.

Kevin

Re: [PATCH 0/7] OMAP4: Add 4460 base support

[Rajendra Nayak]

On 7/1/2011 9:40 AM, Kevin Hilman wrote:
> On Fri, 2011-07-01 at 09:36 -0700, Kevin Hilman wrote:
>> Rajendra Nayak<rnayak@ti.com>  writes:
>>
>>> This series adds base support needed to be able
>>> to boot on a OMAP4460 device.
>>> Patches are based on Benoit's for_3.0.1/7_hwmod_modulemode
>>> branch and boot tested on both 4460sdp as well as 4430sdp.
>>
>> Can you also briefly summarize the dependencies between this series an
>> Benoit's?   I'm assuming it is mainly because of the s/4430/44XX/
>> changes, and also avoiding conflicts in clockdomain and powerdomain data
>> files.
>>
>> With that, you can add
>>
>> Reviewed-by: Kevin Hilman<khilman@ti.com>
>>
>> for the whole series.
>
> oops, except for [7/7], where I agree with Tony.
>
> As discussed off-list, lets just drop this patch all together and state
> in [0/7] that there is a limitation that until we fix the hwmod fwk to
> do lazy disable as Tony suggested, 4460 can only reliably boot at OPP50.

Sure, I'll re-post the series once I have Benoit's updated one's
to base on.

Thanks Kevin.

>
> Kevin
>
>