* [PATCH 1/2] drm/i915: enable pnv gpu reset @ 2013-07-26 6:35 Daniel Vetter 2013-07-26 6:35 ` [PATCH 2/2] drm/i915: fix pnv display core clock readout out Daniel Vetter 2013-07-26 7:28 ` [PATCH 1/2] drm/i915: enable pnv gpu reset Chris Wilson 0 siblings, 2 replies; 6+ messages in thread From: Daniel Vetter @ 2013-07-26 6:35 UTC (permalink / raw) To: Intel Graphics Development; +Cc: Daniel Vetter According to configdb the same register as for gen4 also exists on pnv. Try to use it. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/intel_uncore.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 8f5bc86..859c84d 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -566,11 +566,21 @@ int intel_gpu_reset(struct drm_device *dev) { switch (INTEL_INFO(dev)->gen) { case 7: - case 6: return gen6_do_reset(dev); - case 5: return ironlake_do_reset(dev); - case 4: return i965_do_reset(dev); - case 2: return i8xx_do_reset(dev); - default: return -ENODEV; + case 6: + return gen6_do_reset(dev); + case 5: + return ironlake_do_reset(dev); + case 4: + return i965_do_reset(dev); + case 3: + if (IS_PINEVIEW(dev)) + return i965_do_reset(dev); + else + return -ENODEV; + case 2: + return i8xx_do_reset(dev); + default: + return -ENODEV; } } -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/i915: fix pnv display core clock readout out 2013-07-26 6:35 [PATCH 1/2] drm/i915: enable pnv gpu reset Daniel Vetter @ 2013-07-26 6:35 ` Daniel Vetter 2013-07-26 7:19 ` Chris Wilson 2013-07-26 8:18 ` Jani Nikula 2013-07-26 7:28 ` [PATCH 1/2] drm/i915: enable pnv gpu reset Chris Wilson 1 sibling, 2 replies; 6+ messages in thread From: Daniel Vetter @ 2013-07-26 6:35 UTC (permalink / raw) To: Intel Graphics Development; +Cc: Daniel Vetter, Stuart Abercrombie We need the correct clock to accurately assess whether we need to enable the double wide pipe mode or not. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Stéphane Marchesin <marcheu@chromium.org> Cc: Stuart Abercrombie <sabercrombie@google.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6caa748..3aebe5d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -61,6 +61,12 @@ #define GC_LOW_FREQUENCY_ENABLE (1 << 7) #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) +#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) +#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) +#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) +#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) +#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) +#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) #define GC_DISPLAY_CLOCK_MASK (7 << 4) #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b3389d7..3e66f05 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4163,6 +4163,30 @@ static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) return 200000; } +static int pnv_get_display_clock_speed(struct drm_device *dev) +{ + u16 gcfgc = 0; + + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); + + switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { + case GC_DISPLAY_CLOCK_267_MHZ_PNV: + return 267000; + case GC_DISPLAY_CLOCK_333_MHZ_PNV: + return 333000; + case GC_DISPLAY_CLOCK_444_MHZ_PNV: + return 444000; + case GC_DISPLAY_CLOCK_200_MHZ_PNV: + return 200000; + default: + DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); + case GC_DISPLAY_CLOCK_133_MHZ_PNV: + return 133000; + case GC_DISPLAY_CLOCK_167_MHZ_PNV: + return 167000; + } +} + static int i915gm_get_display_clock_speed(struct drm_device *dev) { u16 gcfgc = 0; @@ -9605,9 +9629,12 @@ static void intel_init_display(struct drm_device *dev) else if (IS_I915G(dev)) dev_priv->display.get_display_clock_speed = i915_get_display_clock_speed; - else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) + else if (IS_I945GM(dev) || IS_845G(dev)) dev_priv->display.get_display_clock_speed = i9xx_misc_get_display_clock_speed; + else if (IS_PINEVIEW(dev)) + dev_priv->display.get_display_clock_speed = + pnv_get_display_clock_speed; else if (IS_I915GM(dev)) dev_priv->display.get_display_clock_speed = i915gm_get_display_clock_speed; -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: fix pnv display core clock readout out 2013-07-26 6:35 ` [PATCH 2/2] drm/i915: fix pnv display core clock readout out Daniel Vetter @ 2013-07-26 7:19 ` Chris Wilson 2013-07-26 8:18 ` Jani Nikula 1 sibling, 0 replies; 6+ messages in thread From: Chris Wilson @ 2013-07-26 7:19 UTC (permalink / raw) To: Daniel Vetter; +Cc: Intel Graphics Development, Stuart Abercrombie On Fri, Jul 26, 2013 at 08:35:42AM +0200, Daniel Vetter wrote: > We need the correct clock to accurately assess whether we need to > enable the double wide pipe mode or not. > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Stéphane Marchesin <marcheu@chromium.org> > Cc: Stuart Abercrombie <sabercrombie@google.com> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> I have not found a definition of GCFGC for NM10. Mind including a reference? -Chris -- Chris Wilson, Intel Open Source Technology Centre ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: fix pnv display core clock readout out 2013-07-26 6:35 ` [PATCH 2/2] drm/i915: fix pnv display core clock readout out Daniel Vetter 2013-07-26 7:19 ` Chris Wilson @ 2013-07-26 8:18 ` Jani Nikula 2013-07-26 17:55 ` Daniel Vetter 1 sibling, 1 reply; 6+ messages in thread From: Jani Nikula @ 2013-07-26 8:18 UTC (permalink / raw) To: Intel Graphics Development; +Cc: Daniel Vetter, Stuart Abercrombie On Fri, 26 Jul 2013, Daniel Vetter <daniel.vetter@ffwll.ch> wrote: > We need the correct clock to accurately assess whether we need to > enable the double wide pipe mode or not. > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Stéphane Marchesin <marcheu@chromium.org> > Cc: Stuart Abercrombie <sabercrombie@google.com> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> > --- > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++++++++++++++++++++- > 2 files changed, 34 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 6caa748..3aebe5d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -61,6 +61,12 @@ > #define GC_LOW_FREQUENCY_ENABLE (1 << 7) > #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) > #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) > +#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) > +#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) > +#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) > +#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) > +#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) > +#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) > #define GC_DISPLAY_CLOCK_MASK (7 << 4) > #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) > #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index b3389d7..3e66f05 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4163,6 +4163,30 @@ static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) > return 200000; > } > > +static int pnv_get_display_clock_speed(struct drm_device *dev) > +{ > + u16 gcfgc = 0; > + > + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); > + > + switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { > + case GC_DISPLAY_CLOCK_267_MHZ_PNV: > + return 267000; > + case GC_DISPLAY_CLOCK_333_MHZ_PNV: > + return 333000; > + case GC_DISPLAY_CLOCK_444_MHZ_PNV: > + return 444000; > + case GC_DISPLAY_CLOCK_200_MHZ_PNV: > + return 200000; > + default: > + DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); Reading the spec, should the default/fallback be 333 MHz for desktop? Otherwise, Reviewed-by: Jani Nikula <jani.nikula@intel.com> > + case GC_DISPLAY_CLOCK_133_MHZ_PNV: > + return 133000; > + case GC_DISPLAY_CLOCK_167_MHZ_PNV: > + return 167000; > + } > +} > + > static int i915gm_get_display_clock_speed(struct drm_device *dev) > { > u16 gcfgc = 0; > @@ -9605,9 +9629,12 @@ static void intel_init_display(struct drm_device *dev) > else if (IS_I915G(dev)) > dev_priv->display.get_display_clock_speed = > i915_get_display_clock_speed; > - else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) > + else if (IS_I945GM(dev) || IS_845G(dev)) > dev_priv->display.get_display_clock_speed = > i9xx_misc_get_display_clock_speed; > + else if (IS_PINEVIEW(dev)) > + dev_priv->display.get_display_clock_speed = > + pnv_get_display_clock_speed; > else if (IS_I915GM(dev)) > dev_priv->display.get_display_clock_speed = > i915gm_get_display_clock_speed; > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: fix pnv display core clock readout out 2013-07-26 8:18 ` Jani Nikula @ 2013-07-26 17:55 ` Daniel Vetter 0 siblings, 0 replies; 6+ messages in thread From: Daniel Vetter @ 2013-07-26 17:55 UTC (permalink / raw) To: Jani Nikula; +Cc: Daniel Vetter, Intel Graphics Development, Stuart Abercrombie On Fri, Jul 26, 2013 at 11:18:21AM +0300, Jani Nikula wrote: > On Fri, 26 Jul 2013, Daniel Vetter <daniel.vetter@ffwll.ch> wrote: > > We need the correct clock to accurately assess whether we need to > > enable the double wide pipe mode or not. > > > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Stéphane Marchesin <marcheu@chromium.org> > > Cc: Stuart Abercrombie <sabercrombie@google.com> > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > > drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++++++++++++++++++++- > > 2 files changed, 34 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 6caa748..3aebe5d 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -61,6 +61,12 @@ > > #define GC_LOW_FREQUENCY_ENABLE (1 << 7) > > #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) > > #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) > > +#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) > > +#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) > > +#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) > > +#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) > > +#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) > > +#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) > > #define GC_DISPLAY_CLOCK_MASK (7 << 4) > > #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) > > #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index b3389d7..3e66f05 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -4163,6 +4163,30 @@ static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) > > return 200000; > > } > > > > +static int pnv_get_display_clock_speed(struct drm_device *dev) > > +{ > > + u16 gcfgc = 0; > > + > > + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); > > + > > + switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { > > + case GC_DISPLAY_CLOCK_267_MHZ_PNV: > > + return 267000; > > + case GC_DISPLAY_CLOCK_333_MHZ_PNV: > > + return 333000; > > + case GC_DISPLAY_CLOCK_444_MHZ_PNV: > > + return 444000; > > + case GC_DISPLAY_CLOCK_200_MHZ_PNV: > > + return 200000; > > + default: > > + DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); > > Reading the spec, should the default/fallback be 333 MHz for desktop? > Otherwise, As discussed on irc the default case should never happen, but I've simply picked the slowest frequency to be on the safe side and hopefully show something on the screen. > Reviewed-by: Jani Nikula <jani.nikula@intel.com> Queued for -next, thanks for the review. -Daniel > > > + case GC_DISPLAY_CLOCK_133_MHZ_PNV: > > + return 133000; > > + case GC_DISPLAY_CLOCK_167_MHZ_PNV: > > + return 167000; > > + } > > +} > > + > > static int i915gm_get_display_clock_speed(struct drm_device *dev) > > { > > u16 gcfgc = 0; > > @@ -9605,9 +9629,12 @@ static void intel_init_display(struct drm_device *dev) > > else if (IS_I915G(dev)) > > dev_priv->display.get_display_clock_speed = > > i915_get_display_clock_speed; > > - else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) > > + else if (IS_I945GM(dev) || IS_845G(dev)) > > dev_priv->display.get_display_clock_speed = > > i9xx_misc_get_display_clock_speed; > > + else if (IS_PINEVIEW(dev)) > > + dev_priv->display.get_display_clock_speed = > > + pnv_get_display_clock_speed; > > else if (IS_I915GM(dev)) > > dev_priv->display.get_display_clock_speed = > > i915gm_get_display_clock_speed; > > -- > > 1.8.3.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Jani Nikula, Intel Open Source Technology Center -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/i915: enable pnv gpu reset 2013-07-26 6:35 [PATCH 1/2] drm/i915: enable pnv gpu reset Daniel Vetter 2013-07-26 6:35 ` [PATCH 2/2] drm/i915: fix pnv display core clock readout out Daniel Vetter @ 2013-07-26 7:28 ` Chris Wilson 1 sibling, 0 replies; 6+ messages in thread From: Chris Wilson @ 2013-07-26 7:28 UTC (permalink / raw) To: Daniel Vetter; +Cc: Intel Graphics Development On Fri, Jul 26, 2013 at 08:35:41AM +0200, Daniel Vetter wrote: > According to configdb the same register as for gen4 also exists on > pnv. Try to use it. > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> I think I also remember it dying terminally afterwards (some missing reinit), but it's been long enough that we may fare better today. I'll poke around the next time I boot into a pnv. -Chris -- Chris Wilson, Intel Open Source Technology Centre ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2013-07-26 17:55 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2013-07-26 6:35 [PATCH 1/2] drm/i915: enable pnv gpu reset Daniel Vetter 2013-07-26 6:35 ` [PATCH 2/2] drm/i915: fix pnv display core clock readout out Daniel Vetter 2013-07-26 7:19 ` Chris Wilson 2013-07-26 8:18 ` Jani Nikula 2013-07-26 17:55 ` Daniel Vetter 2013-07-26 7:28 ` [PATCH 1/2] drm/i915: enable pnv gpu reset Chris Wilson
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.