[PATCH 0/3] OMAP3: PM: OMAP3630 support for smartreflex driver

[PATCH 0/3] OMAP3: PM: OMAP3630 support for smartreflex driver

[Thara Gopinath]

This patch series adds support for the updated 45nm smrtrelfex IP
supported in OMAP3630 and OMAP4 in the smartreflex driver and
adds support to enable smartreflex autocompensation for OMAP3630
using test nvalues.

This patch series is based on the following patch series/patches
for proper functionality.
	http://marc.info/?l=linux-omap&m=126700378625593&w=2
	http://patchwork.kernel.org/patch/77739/

This patch series has been tested on OMAP3630 SDP board with
CONFIG_OMAP_SMARTREFLEX_TESTING option enabled in the menuconfig.

This patch series has been based on Kevin's PM tree
origin/pm-wip-opp branch and on
adea81232e8fc82334bca3707efa23dc854f29fc commit id.

Thara Gopinath (3):
  OMAP3: PM: Bug fix in Smartreflex driver.
  OMAP3: PM: Smartreflex IP update changes for OMAP3630
  OMAP3: PM: Adding OMAP3630 support in smartreflex driver

 arch/arm/mach-omap2/omap_hwmod_34xx.h     |   49 ++++-
 arch/arm/mach-omap2/smartreflex.c         |  354 +++++++++++++++++++++++-----
 arch/arm/mach-omap2/smartreflex.h         |   51 ++++-
 arch/arm/mach-omap2/voltage.c             |  167 +++++++++++---
 arch/arm/mach-omap2/voltage.h             |   32 ++-
 arch/arm/plat-omap/include/plat/control.h |    8 +
 6 files changed, 542 insertions(+), 119 deletions(-)

[PATCH 1/3] OMAP3: PM: Bug fix in Smartreflex driver.

[Thara Gopinath]

This patch sets and unsets is_sr_reset is appropriate places so that
trying to enable smart reflex in a non-supported OMAP chip does not
lead to unnecessary crash

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/smartreflex.c |   31 +++++++++++++++++++++----------
 1 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index ca2223d..7aa84ab 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -108,9 +108,14 @@ static int sr_clk_enable(struct omap_sr *sr)
 {
 	struct omap_smartreflex_data *pdata = sr->pdev->dev.platform_data;
 
+	if (!sr->is_sr_reset)
+		return 0;
+
 	if (pdata->device_enable)
 		pdata->device_enable(sr->pdev);
 
+	sr->is_sr_reset = 0;
+
 	return 0;
 }
 
@@ -118,6 +123,9 @@ static void sr_clk_disable(struct omap_sr *sr)
 {
 	struct omap_smartreflex_data *pdata = sr->pdev->dev.platform_data;
 
+	if (sr->is_sr_reset)
+		return;
+
 	if (pdata->device_idle)
 		pdata->device_idle(sr->pdev);
 
@@ -262,7 +270,6 @@ static void sr_configure(struct omap_sr *sr)
 			 ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
 			 ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
 	}
-	sr->is_sr_reset = 0;
 }
 
 static void sr_start_vddautocomap(int srid)
@@ -283,8 +290,7 @@ static void sr_start_vddautocomap(int srid)
 	sr->is_autocomp_active = 1;
 	if (!sr_class->enable(srid)) {
 		sr->is_autocomp_active = 0;
-		if (sr->is_sr_reset == 1)
-			sr_clk_disable(sr);
+		sr_clk_disable(sr);
 	}
 }
 
@@ -303,8 +309,10 @@ static void sr_stop_vddautocomap(int srid)
 	}
 
 	if (sr->is_autocomp_active == 1) {
-		sr_class->disable(srid);
-		sr_clk_disable(sr);
+		if (!sr->is_sr_reset) {
+			sr_class->disable(srid);
+			sr_clk_disable(sr);
+		}
 		sr->is_autocomp_active = 0;
 	}
 
@@ -357,6 +365,11 @@ int sr_enable(int srid, u32 target_opp_no)
 
 	/* Enable the clocks and configure SR */
 	sr_clk_enable(sr);
+
+	/* Check if SR is already enabled. If yes do nothing */
+	if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE)
+		return true;
+
 	sr_configure(sr);
 
 	nvalue_reciprocal = pdata->sr_nvalue[target_opp_no - 1];
@@ -447,10 +460,8 @@ void omap_smartreflex_enable(int srid)
 	}
 
 	if (sr->is_autocomp_active == 1) {
-		if (sr->is_sr_reset == 1) {
-			if (!sr_class->enable(srid))
-				sr_clk_disable(sr);
-		}
+		if (!sr_class->enable(srid))
+			sr_clk_disable(sr);
 	}
 }
 
@@ -478,7 +489,7 @@ void omap_smartreflex_disable(int srid)
 	}
 
 	if (sr->is_autocomp_active == 1) {
-		if (sr->is_sr_reset == 0) {
+		if (!sr->is_sr_reset) {
 			sr_class->disable(srid);
 			/* Disable SR clk */
 			sr_clk_disable(sr);
-- 
1.7.0.rc1.33.g07cf0f

[PATCH 2/3] OMAP3: PM: Smartreflex IP update changes for OMAP3630

[Thara Gopinath]

OMAP3430 uses the 65nm version of the smartreflex IP where as
OMAP3630 and OMAP4430 uses the 45nm updated IP.

This patch adds support for the updated smartreflex IP used
in OMAP3630 and OMAP4 in the smartreflex driver.

Major changes between the two versions of IP involve:
1. Change in offset position for ERRCONFIG and SENERROR registers
2. Change in bit positions for VP bound interrupt enable and status
   in ERRCONFIG register.
3. Change in bit positions and width of SENNENABLE and SENPENABLE
   bits in SRCONFIG registers.
4. Introduction of separate irq registers for MCU bound interrupts.
5. Removal of clockactivity bits in ERRCONFIG and introduction of
  idlemode and wakeupenable bits in ERRCONFIG.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/smartreflex.c |  218 ++++++++++++++++++++++++++++---------
 arch/arm/mach-omap2/smartreflex.h |   51 +++++++--
 2 files changed, 208 insertions(+), 61 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 7aa84ab..2b1c529 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -58,6 +58,18 @@ static struct omap_smartreflex_class_data *sr_class;
 
 #define SR_REGADDR(offs)	(sr->srbase_addr + offset)
 
+static inline int sr_type(void)
+{
+	if (cpu_is_omap3630())
+		return SR_TYPE_V2;
+	else if (cpu_is_omap343x())
+		return SR_TYPE_V1;
+	else {
+		pr_err("Trying to enable SR for Chip not support SR! \n");
+		return 0;
+	}
+}
+
 static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
 {
 	__raw_writel(value, SR_REGADDR(offset));
@@ -67,9 +79,11 @@ static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
 					u32 value)
 {
 	u32 reg_val;
+	u32 errconfig_offs, errconfig_mask;
 
 	reg_val = __raw_readl(SR_REGADDR(offset));
 	reg_val &= ~mask;
+
 	/*
 	 * Smartreflex error config register is special as it contains
 	 * certain status bits which if written a 1 into means a clear
@@ -78,8 +92,16 @@ static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
 	 * value. Now if there is an actual reguest to write to these bits
 	 * they will be set in the nex step.
 	 */
-	if (offset == ERRCONFIG)
-		reg_val &= ~ERRCONFIG_STATUS_MASK;
+	if (sr_type() == SR_TYPE_V1) {
+		errconfig_offs = ERRCONFIG_V1;
+		errconfig_mask = ERRCONFIG_STATUS_V1_MASK;
+	} else if (sr_type() == SR_TYPE_V2) {
+		errconfig_offs = ERRCONFIG_V2;
+		errconfig_mask = ERRCONFIG_VPBOUNDINTST_V2;
+	}
+
+	if (offset == errconfig_offs)
+		reg_val &= ~errconfig_mask;
 
 	reg_val |= value;
 	__raw_writel(reg_val, SR_REGADDR(offset));
@@ -135,13 +157,21 @@ static void sr_clk_disable(struct omap_sr *sr)
 static irqreturn_t sr_omap_isr(int irq, void *data)
 {
 	struct omap_sr *sr_info = (struct omap_sr *)data;
-	u32 status;
+	u32 status = 0;
 
-	/* Read the status bits */
-	status = sr_read_reg(sr_info, ERRCONFIG);
+	if (sr_type() == SR_TYPE_V1) {
+		/* Read the status bits */
+		status = sr_read_reg(sr_info, ERRCONFIG_V1);
 
-	/* Clear them by writing back */
-	sr_write_reg(sr_info, ERRCONFIG, status);
+		/* Clear them by writing back */
+		sr_write_reg(sr_info, ERRCONFIG_V1, status);
+	} else if (sr_type() == SR_TYPE_V2) {
+		/* Read the status bits */
+		sr_read_reg(sr_info, IRQSTATUS);
+
+		/* Clear them by writing back */
+		sr_write_reg(sr_info, IRQSTATUS, status);
+	}
 
 	/* Call the class driver notify function if registered*/
 	if (sr_class->class_type == SR_CLASS2 && sr_class->notify)
@@ -208,6 +238,7 @@ static void sr_configure(struct omap_sr *sr)
 {
 	u32 sr_config;
 	u32 senp_en , senn_en;
+	u8 senp_shift, senn_shift;
 	struct omap_smartreflex_data *pdata = sr->pdev->dev.platform_data;
 
 	/* Common settings for SR Class3 and SR Class2 */
@@ -218,8 +249,16 @@ static void sr_configure(struct omap_sr *sr)
 	senn_en = pdata->senn_mod;
 
 	sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
-		SRCONFIG_SENENABLE | (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
-		(senp_en << SRCONFIG_SENPENABLE_SHIFT) | SRCONFIG_DELAYCTRL;
+		SRCONFIG_SENENABLE;
+	if (sr_type() == SR_TYPE_V1) {
+		sr_config |= SRCONFIG_DELAYCTRL;
+		senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
+		senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
+	} else if (sr_type() == SR_TYPE_V2) {
+		senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
+		senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
+	}
+	sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
 	sr_write_reg(sr, SRCONFIG, sr_config);
 
 	if ((sr_class->class_type == SR_CLASS3) || (sr_class->class_type ==
@@ -230,20 +269,30 @@ static void sr_configure(struct omap_sr *sr)
 		 * SR CLASS 2 can choose between ERROR module and MINMAXAVG
 		 * module.
 		 */
-		u32 sr_errconfig;
+		u32 sr_errconfig, errconfig_offs;
+		u32 vpboundint_en, vpboundint_st;
+
+		if (sr_type() == SR_TYPE_V1) {
+			errconfig_offs = ERRCONFIG_V1;
+			vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
+			vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
+		} else if (sr_type() == SR_TYPE_V2) {
+			errconfig_offs = ERRCONFIG_V2;
+			vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
+			vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
+		}
 
 		sr_modify_reg(sr, SRCONFIG, SRCONFIG_ERRGEN_EN,
 			SRCONFIG_ERRGEN_EN);
 		sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) |
 			(sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) |
 			(sr->err_minlimit <<  ERRCONFIG_ERRMiNLIMIT_SHIFT);
-		sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
+		sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK |
 			SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
 			sr_errconfig);
 		/* Enabling the interrupts if the ERROR module is used */
-		sr_modify_reg(sr, ERRCONFIG,
-			(ERRCONFIG_VPBOUNDINTEN),
-			(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
+		sr_modify_reg(sr, errconfig_offs,
+			vpboundint_en, (vpboundint_en | vpboundint_st));
 	} else if ((sr_class->class_type == SR_CLASS2) &&
 			(sr_class->mod_use == SR_USE_ERROR_MOD)) {
 		/*
@@ -263,12 +312,27 @@ static void sr_configure(struct omap_sr *sr)
 		 * Enabling the interrupts if MINMAXAVG module is used.
 		 * TODO: check if all the interrupts are mandatory
 		 */
-		sr_modify_reg(sr, ERRCONFIG,
-			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
-			ERRCONFIG_MCUBOUNDINTEN),
-			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
-			 ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
-			 ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
+		if (sr_type() == SR_TYPE_V1) {
+			sr_modify_reg(sr, ERRCONFIG_V1,
+				(ERRCONFIG_MCUACCUMINTEN |
+				 ERRCONFIG_MCUVALIDINTEN |
+				 ERRCONFIG_MCUBOUNDINTEN),
+				(ERRCONFIG_MCUACCUMINTEN |
+				 ERRCONFIG_MCUACCUMINTST |
+				 ERRCONFIG_MCUVALIDINTEN |
+				 ERRCONFIG_MCUVALIDINTST |
+				 ERRCONFIG_MCUBOUNDINTEN |
+				 ERRCONFIG_MCUBOUNDINTST));
+		} else if (sr_type() == SR_TYPE_V2) {
+			sr_write_reg(sr, IRQSTATUS,
+				IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
+				IRQSTATUS_MCBOUNDSINT |
+				IRQSTATUS_MCUDISABLEACKINT);
+			sr_write_reg(sr, IRQENABLE_SET,
+				IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
+				IRQENABLE_MCUBOUNDSINT |
+				IRQENABLE_MCUDISABLEACKINT);
+		}
 	}
 }
 
@@ -318,6 +382,81 @@ static void sr_stop_vddautocomap(int srid)
 
 }
 
+static void sr_v1_disable(struct omap_sr *sr)
+{
+	int timeout = 0;
+
+	/* Enable MCUDisableAcknowledge interrupt */
+	sr_modify_reg(sr, ERRCONFIG_V1,
+			ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
+
+	/* SRCONFIG - disable SR */
+	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+
+	/* Disable all other SR interrupts and clear the status */
+	sr_modify_reg(sr, ERRCONFIG_V1,
+			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
+			ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
+			(ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
+			ERRCONFIG_MCUBOUNDINTST |
+			ERRCONFIG_VPBOUNDINTST_V1));
+
+	/* Wait for SR to be disabled.
+	 * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
+	 */
+	while ((timeout < SR_DISABLE_TIMEOUT) &&
+		(!(sr_read_reg(sr, ERRCONFIG_V1) &
+		ERRCONFIG_MCUDISACKINTST))) {
+		udelay(1);
+		timeout++;
+	}
+
+	if (timeout == SR_DISABLE_TIMEOUT)
+		pr_warning("SR%d disable timedout\n", sr->srid);
+
+	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+	sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN,
+			ERRCONFIG_MCUDISACKINTST);
+}
+
+static void sr_v2_disable(struct omap_sr *sr)
+{
+	int timeout = 0;
+
+	/* Enable MCUDisableAcknowledge interrupt */
+	sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT);
+
+	/* SRCONFIG - disable SR */
+	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+
+	/* Disable all other SR interrupts and clear the status */
+	sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
+			ERRCONFIG_VPBOUNDINTST_V2);
+	sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
+			IRQENABLE_MCUVALIDINT |
+			IRQENABLE_MCUBOUNDSINT));
+	sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT |
+			IRQSTATUS_MCVALIDINT |
+			IRQSTATUS_MCBOUNDSINT));
+
+	/* Wait for SR to be disabled.
+	 * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
+	 */
+	while ((timeout < SR_DISABLE_TIMEOUT) &&
+		(!(sr_read_reg(sr, IRQSTATUS) &
+		IRQSTATUS_MCUDISABLEACKINT))) {
+		udelay(1);
+		timeout++;
+	}
+
+	if (timeout == SR_DISABLE_TIMEOUT)
+		pr_warning("SR%d disable timedout\n", sr->srid);
+
+	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+	sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT);
+	sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
+}
+
 /* Public Functions */
 
 /**
@@ -373,6 +512,7 @@ int sr_enable(int srid, u32 target_opp_no)
 	sr_configure(sr);
 
 	nvalue_reciprocal = pdata->sr_nvalue[target_opp_no - 1];
+
 	if (nvalue_reciprocal == 0) {
 		pr_notice("OPP%d doesn't support SmartReflex\n",
 								target_opp_no);
@@ -395,44 +535,18 @@ int sr_enable(int srid, u32 target_opp_no)
 void sr_disable(int srid)
 {
 	struct omap_sr *sr = _sr_lookup(srid);
-	int timeout = 0;
 
 	/* Check if SR is already disabled. If yes do nothing */
 	if (!(sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE))
 		return;
 
-	/* Enable MCUDisableAcknowledge interrupt */
-	sr_modify_reg(sr, ERRCONFIG,
-			ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
+	if (sr_type() == SR_TYPE_V1)
+		sr_v1_disable(sr);
 
-	/* SRCONFIG - disable SR */
-	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
-
-	/* Disable all other SR interrupts and clear the status */
-	sr_modify_reg(sr, ERRCONFIG,
-			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
-			ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN),
-			(ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
-			ERRCONFIG_MCUBOUNDINTST | ERRCONFIG_VPBOUNDINTST));
-
-	/* Wait for SR to be disabled.
-	 * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
-	 */
-	while ((timeout < SR_DISABLE_TIMEOUT) &&
-		(!(sr_read_reg(sr, ERRCONFIG) & ERRCONFIG_MCUDISACKINTST))) {
-
-		udelay(1);
-		timeout++;
-	}
-
-	if (timeout == SR_DISABLE_TIMEOUT)
-		pr_warning("SR%d disable timedout\n", srid);
-
-	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt
-	 * Also enable VPBOUND interrrupt
-	 */
-	sr_modify_reg(sr, ERRCONFIG, ERRCONFIG_MCUDISACKINTEN,
-			ERRCONFIG_MCUDISACKINTST);
+	else if (sr_type() == SR_TYPE_V2)
+		sr_v2_disable(sr);
+	else
+		return;
 }
 
 /**
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index ae8d5db..4373cfb 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -22,6 +22,14 @@ extern struct dentry *pm_dbg_main_dir;
 #define SR1		1
 #define SR2		2
 
+/*
+ * Different Smartreflex IPs version. The v1 is the 65nm version used in
+ * OMAP3430. The v2 is the update for the 45nm version of the IP
+ * used in OMAP3630 and OMAP4430
+ */
+#define SR_TYPE_V1	1
+#define SR_TYPE_V2	2
+
 #define GAIN_MAXLIMIT	16
 #define R_MAXLIMIT	256
 
@@ -34,16 +42,25 @@ extern struct dentry *pm_dbg_main_dir;
 #define SENAVG			0x14
 #define AVGWEIGHT		0x18
 #define NVALUERECIPROCAL	0x1C
-#define SENERROR		0x20
-#define ERRCONFIG		0x24
+#define SENERROR_V1		0x20
+#define ERRCONFIG_V1		0x24
+#define IRQ_EOI			0x20
+#define IRQSTATUS_RAW		0x24
+#define IRQSTATUS		0x28
+#define IRQENABLE_SET		0x2C
+#define IRQENABLE_CLR		0x30
+#define SENERROR_V2		0x34
+#define ERRCONFIG_V2		0x38
 
 /* Bit/Shift Positions */
 
 /* SRCONFIG */
 #define SRCONFIG_ACCUMDATA_SHIFT	22
 #define SRCONFIG_SRCLKLENGTH_SHIFT	12
-#define SRCONFIG_SENNENABLE_SHIFT	5
-#define SRCONFIG_SENPENABLE_SHIFT	3
+#define SRCONFIG_SENNENABLE_V1_SHIFT	5
+#define SRCONFIG_SENPENABLE_V1_SHIFT	3
+#define SRCONFIG_SENNENABLE_V2_SHIFT	1
+#define SRCONFIG_SENPENABLE_V2_SHIFT	0
 #define SRCONFIG_CLKCTRL_SHIFT		0
 
 #define SRCONFIG_ACCUMDATA_MASK		(0x3FF << 22)
@@ -73,8 +90,8 @@ extern struct dentry *pm_dbg_main_dir;
 #define SR_ERRMAXLIMIT_MASK		(0xFF << 8)
 #define SR_ERRMINLIMIT_MASK		(0xFF << 0)
 
-#define ERRCONFIG_VPBOUNDINTEN		BIT(31)
-#define ERRCONFIG_VPBOUNDINTST		BIT(30)
+#define ERRCONFIG_VPBOUNDINTEN_V1	BIT(31)
+#define ERRCONFIG_VPBOUNDINTST_V1	BIT(30)
 #define	ERRCONFIG_MCUACCUMINTEN		BIT(29)
 #define ERRCONFIG_MCUACCUMINTST		BIT(28)
 #define	ERRCONFIG_MCUVALIDINTEN		BIT(27)
@@ -82,13 +99,26 @@ extern struct dentry *pm_dbg_main_dir;
 #define ERRCONFIG_MCUBOUNDINTEN		BIT(25)
 #define	ERRCONFIG_MCUBOUNDINTST		BIT(24)
 #define	ERRCONFIG_MCUDISACKINTEN	BIT(23)
+#define ERRCONFIG_VPBOUNDINTST_V2	BIT(23)
 #define ERRCONFIG_MCUDISACKINTST	BIT(22)
+#define ERRCONFIG_VPBOUNDINTEN_V2	BIT(22)
 
-#define ERRCONFIG_STATUS_MASK		(ERRCONFIG_VPBOUNDINTST | \
+#define ERRCONFIG_STATUS_V1_MASK	(ERRCONFIG_VPBOUNDINTST_V1 | \
 					ERRCONFIG_MCUACCUMINTST | \
 					ERRCONFIG_MCUVALIDINTST | \
 					ERRCONFIG_MCUBOUNDINTST | \
 					ERRCONFIG_MCUDISACKINTST)
+/* IRQSTATUS */
+#define IRQSTATUS_MCUACCUMINT		BIT(3)
+#define IRQSTATUS_MCVALIDINT		BIT(2)
+#define IRQSTATUS_MCBOUNDSINT		BIT(1)
+#define IRQSTATUS_MCUDISABLEACKINT	BIT(0)
+
+/* IRQENABLE_SET and IRQENABLE_CLEAR */
+#define IRQENABLE_MCUACCUMINT		BIT(3)
+#define IRQENABLE_MCUVALIDINT		BIT(2)
+#define IRQENABLE_MCUBOUNDSINT		BIT(1)
+#define IRQENABLE_MCUDISABLEACKINT	BIT(0)
 
 /* Common Bit values */
 
@@ -99,7 +129,7 @@ extern struct dentry *pm_dbg_main_dir;
 #define SRCLKLENGTH_38MHZ_SYSCLK	0xC0
 
 /*
- * 3430 specific values. Maybe these should be passed from board file or
+ * OMAP3 specific values. Maybe these should be passed from board file or
  * pmic structures.
  */
 #define OMAP3430_SR_ACCUMDATA		0x1F4
@@ -115,7 +145,10 @@ extern struct dentry *pm_dbg_main_dir;
 #define OMAP3430_SR_ERRMINLIMIT_HIGHOPP	0xF9
 #define OMAP3430_SR_ERRMINLIMIT_LOWOPP	0xF4
 
-/* TODO:3630/OMAP4 values if it has to come from this file */
+/* OMAP3630 specific values */
+#define OMAP3630_SR_ERRMINLIMIT_OPPTM	0xFA
+
+/* TODO:OMAP4 values */
 
 /* Info for enabling SR in T2/gaia. ToDo: Move it to twl4030_power.c */
 #define PHY_TO_OFF_PM_RECIEVER(p)	(p - 0x5b)
-- 
1.7.0.rc1.33.g07cf0f

[PATCH 3/3] OMAP3: PM: Adding OMAP3630 support in smartreflex driver

[Thara Gopinath]

This patch adapts smartreflex driver to support OMAP3630 also.
Changes involve:
1. Separate hwmod structures for OMAP3630 distinguished from
   3430 structures using omap_chip attribute.
2. Introducing new test nvalues for OMAP3630.
3. OMAP3630 specific changes for srconfig err_minlimit field,
   vpx_config errorgain field and vpx_vlimitto vddmax and vddmin
   fields.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_34xx.h     |   49 ++++++++-
 arch/arm/mach-omap2/smartreflex.c         |  105 ++++++++++++++++++-
 arch/arm/mach-omap2/voltage.c             |  167 ++++++++++++++++++++++-------
 arch/arm/mach-omap2/voltage.h             |   32 +++++--
 arch/arm/plat-omap/include/plat/control.h |    8 ++
 5 files changed, 313 insertions(+), 48 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_34xx.h b/arch/arm/mach-omap2/omap_hwmod_34xx.h
index dccb4a4..eb2233b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_34xx.h
+++ b/arch/arm/mach-omap2/omap_hwmod_34xx.h
@@ -204,6 +204,19 @@ static struct omap_hwmod_sysconfig sr_if_ctrl = {
 	.sysc_fields	= &sr_sysc_fields,
 };
 
+static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
+	.sidle_shift	= 24,
+	.enwkup_shift	= 26
+};
+
+static struct omap_hwmod_sysconfig omap36xx_sr_if_ctrl = {
+	.sysc_offs	= 0x38,
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+			SYSC_NO_CACHE),
+	.sysc_fields	= &omap36xx_sr_sysc_fields,
+};
+
 /* SR1 */
 static struct omap_hwmod_ocp_if *omap34xx_sr1_slaves[] = {
 	&omap3_l4_core__sr1,
@@ -218,10 +231,24 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
 	.slaves		= omap34xx_sr1_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap34xx_sr1_slaves),
 	.sysconfig	= &sr_if_ctrl,
-	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
+					CHIP_IS_OMAP3430ES3_0 |
+					CHIP_IS_OMAP3430ES3_1),
 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
+static struct omap_hwmod omap36xx_sr1_hwmod = {
+	.name		= "sr1_hwmod",
+	.mpu_irqs	= NULL,
+	.sdma_chs	= NULL,
+	.clkdev_dev_id	= NULL,
+	.clkdev_con_id	= "sr1_fck",
+	.slaves		= omap34xx_sr1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap34xx_sr1_slaves),
+	.sysconfig	= &omap36xx_sr_if_ctrl,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+};
+
 /* SR2 */
 static struct omap_hwmod_ocp_if *omap34xx_sr2_slaves[] = {
 	&omap3_l4_core__sr2,
@@ -236,10 +263,26 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
 	.slaves		= omap34xx_sr2_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap34xx_sr2_slaves),
 	.sysconfig	= &sr_if_ctrl,
-	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
+					CHIP_IS_OMAP3430ES3_0 |
+					CHIP_IS_OMAP3430ES3_1),
 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
+
+static struct omap_hwmod omap36xx_sr2_hwmod = {
+	.name		= "sr2_hwmod",
+	.mpu_irqs	= NULL,
+	.sdma_chs	= NULL,
+	.clkdev_dev_id	= NULL,
+	.clkdev_con_id	= "sr2_fck",
+	.slaves		= omap34xx_sr2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap34xx_sr2_slaves),
+	.sysconfig	= &omap36xx_sr_if_ctrl,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+};
+
+
 static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
 	&omap34xx_l3_hwmod,
 	&omap34xx_l4_core_hwmod,
@@ -248,6 +291,8 @@ static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
 	&omap34xx_mpu_hwmod,
 	&omap34xx_sr1_hwmod,
 	&omap34xx_sr2_hwmod,
+	&omap36xx_sr1_hwmod,
+	&omap36xx_sr2_hwmod,
 	NULL,
 };
 
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 2b1c529..1f13fab 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -497,7 +497,18 @@ int sr_enable(int srid, u32 target_opp_no)
 	 * For OMAP3430 errminlimit is dependent on opp. So choose
 	 * it appropriately
 	 */
-	if (cpu_is_omap343x())
+	if (cpu_is_omap3630()) {
+		switch (target_opp_no) {
+		case 1:
+			sr->err_minlimit = OMAP3430_SR_ERRMINLIMIT_LOWOPP;
+			break;
+		case 2:
+			sr->err_minlimit = OMAP3430_SR_ERRMINLIMIT_HIGHOPP;
+			break;
+		default:
+			sr->err_minlimit = OMAP3630_SR_ERRMINLIMIT_OPPTM;
+		}
+	} else if (cpu_is_omap343x())
 		sr->err_minlimit = (target_opp_no > 2) ?
 			OMAP3430_SR_ERRMINLIMIT_HIGHOPP :
 			OMAP3430_SR_ERRMINLIMIT_LOWOPP;
@@ -936,10 +947,100 @@ static void __init omap3_sr_set_testing_nvalues(
 	}
 }
 
+static void __init omap3630_sr_read_efuse(
+			struct omap_smartreflex_data *sr_data, int sr_id)
+{
+	if (sr_id == SR1) {
+		/*
+		 * TODO: When opp framework come into picture use appropriate
+		 * API's to find out number of opp's.
+		 */
+		sr_data->no_opp = 4;
+		sr_data->sr_nvalue = kzalloc(sizeof(sr_data->sr_nvalue) *
+					sr_data->no_opp , GFP_KERNEL);
+		if (WARN_ON(!sr_data->sr_nvalue))
+			return;
+
+		sr_data->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+					OMAP343X_SR1_SENNENABLE_MASK) >>
+					OMAP343X_SR1_SENNENABLE_SHIFT;
+		sr_data->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+					OMAP343X_SR1_SENPENABLE_MASK) >>
+					OMAP343X_SR1_SENPENABLE_SHIFT;
+		sr_data->sr_nvalue[3] = omap_ctrl_readl(
+					OMAP3630_CONTROL_FUSE_OPPTM_VDD1);
+		sr_data->sr_nvalue[2] = omap_ctrl_readl(
+					OMAP3630_CONTROL_FUSE_OPP120_VDD1);
+		sr_data->sr_nvalue[1] = omap_ctrl_readl(
+					OMAP3630_CONTROL_FUSE_OPP100_VDD1);
+		sr_data->sr_nvalue[0] = omap_ctrl_readl(
+					OMAP3630_CONTROL_FUSE_OPP50_VDD1);
+	} else if (sr_id == SR2) {
+		/*
+		 * TODO: When opp framework come into picture use appropriate
+		 * API's to find out number of opp's.
+		 */
+		sr_data->no_opp = 2;
+		sr_data->sr_nvalue = kzalloc(sizeof(sr_data->sr_nvalue) *
+					sr_data->no_opp , GFP_KERNEL);
+		if (WARN_ON(!sr_data->sr_nvalue))
+			return;
+
+		sr_data->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+					OMAP343X_SR2_SENNENABLE_MASK) >>
+					OMAP343X_SR2_SENNENABLE_SHIFT;
+		sr_data->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+					OMAP343X_SR2_SENPENABLE_MASK) >>
+					OMAP343X_SR2_SENPENABLE_SHIFT;
+		sr_data->sr_nvalue[1] = omap_ctrl_readl(
+					OMAP3630_CONTROL_FUSE_OPP100_VDD2);
+		sr_data->sr_nvalue[0] = omap_ctrl_readl(
+					OMAP3630_CONTROL_FUSE_OPP50_VDD2);
+	}
+}
+
+/* OMAP3630 Hard coded nvalues for testing purposes.*/
+static void __init omap3630_sr_set_testing_nvalues(
+			struct omap_smartreflex_data *sr_data, int srid)
+{
+	if (srid == SR1) {
+		sr_data->no_opp = 4;
+		sr_data->sr_nvalue = kzalloc(sizeof(sr_data->sr_nvalue) *
+				sr_data->no_opp , GFP_KERNEL);
+		if (WARN_ON(!sr_data->sr_nvalue))
+			return;
+
+		sr_data->senp_mod = 0x1;
+		sr_data->senn_mod = 0x1;
+		/* OMAP3630 nvalues for each VDD1 opp */
+		sr_data->sr_nvalue[3] = 0xaab197;
+		sr_data->sr_nvalue[2] = 0xaac5a8;
+		sr_data->sr_nvalue[1] = 0x999b83;
+		sr_data->sr_nvalue[0] = 0x898beb;
+	} else if (srid == SR2) {
+		sr_data->no_opp = 2;
+		sr_data->sr_nvalue = kzalloc(sizeof(sr_data->sr_nvalue) *
+				sr_data->no_opp , GFP_KERNEL);
+		if (WARN_ON(!sr_data->sr_nvalue))
+			return;
+
+		sr_data->senp_mod = 0x1;
+		sr_data->senn_mod = 0x1;
+		/* OMAP3630 nvalues for each VDD2 opp */
+		sr_data->sr_nvalue[1] = 0x9a8cee;
+		sr_data->sr_nvalue[0] = 0x898beb;
+	}
+}
+
 static void __init sr_set_nvalues(struct omap_smartreflex_data *sr_data,
 						int srid)
 {
-	if (cpu_is_omap343x()) {
+	if (cpu_is_omap3630()) {
+		if (SR_TESTING_NVALUES)
+			omap3630_sr_set_testing_nvalues(sr_data, srid);
+		else
+			omap3630_sr_read_efuse(sr_data, srid);
+	} else if (cpu_is_omap343x()) {
 		if (SR_TESTING_NVALUES)
 			omap3_sr_set_testing_nvalues(sr_data, srid);
 		else
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 4f325af..b723927 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -80,6 +80,9 @@ static struct vp_reg_info *vp_reg;
  */
 static int no_scalable_vdd;
 
+/* Structure containing error gain values */
+static u8 *omap_errorgain;
+
 /* OMAP3 VP register offsets and other definitions */
 struct __init vp_reg_offs omap3_vp_offs[] = {
 	/* VP1 */
@@ -104,6 +107,25 @@ struct __init vp_reg_offs omap3_vp_offs[] = {
 #define OMAP3_NO_SCALABLE_VDD ARRAY_SIZE(omap3_vp_offs)
 static struct vp_reg_info omap3_vp_reg[OMAP3_NO_SCALABLE_VDD];
 
+/*
+ * OMAP3430 Error Gain values. OMAP3430 has two errorgain
+ * values - one for OPP2 and below and one for above.
+ */
+static u8 omap3430_errorgain[2] = {
+	OMAP3430_VP_CONFIG_ERRORGAIN_LOWOPP,
+	OMAP3430_VP_CONFIG_ERRORGAIN_HIGHOPP
+};
+
+/*
+ * OMAP3630 Error Gain values. OMAP3630 has four errorgain
+ * values - one for each OPP
+ */
+static u8 omap3630_errorgain[4] = {
+	OMAP3630_VP_CONFIG_ERRORGAIN_OPP50,
+	OMAP3630_VP_CONFIG_ERRORGAIN_OPP100,
+	OMAP3630_VP_CONFIG_ERRORGAIN_OPP120,
+	OMAP3630_VP_CONFIG_ERRORGAIN_OPPTM
+};
 
 /* TODO: OMAP4 register offsets */
 
@@ -289,32 +311,66 @@ static void __init vp_reg_configure(int vp_id)
 
 		vp_reg[vp_id].vp_offs = omap3_vp_offs[vp_id];
 		if (vp_id == VP1) {
-			/*
-			 * OMAP3430 has error gain varying btw higher and
-			 * lower opp's
-			 */
-			vp_reg[vp_id].vp_errorgain = (((get_vdd1_opp() > 2) ?
-					(OMAP3_VP_CONFIG_ERRORGAIN_HIGHOPP) :
-					(OMAP3_VP_CONFIG_ERRORGAIN_LOWOPP)) <<
+			u8 vlimitto_vddmin, vlimitto_vddmax;
+
+			if (cpu_is_omap3630()) {
+				vlimitto_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
+				vlimitto_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
+				/*
+				 * OMAP3630 has error gain varying btw
+				 * all opp's
+				 */
+				vp_reg[vp_id].vp_errorgain =
+					(omap_errorgain[get_vdd1_opp() - 1] <<
+					OMAP3430_ERRORGAIN_SHIFT);
+			} else {
+				vlimitto_vddmin = OMAP3430_VP1_VLIMITTO_VDDMIN;
+				vlimitto_vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX;
+				/*
+				 * OMAP3430 has error gain varying btw higher
+				 * and lower opp's
+				 */
+				vp_reg[vp_id].vp_errorgain =
+					(((get_vdd1_opp() > 2) ?
+					(omap_errorgain[1]) :
+					(omap_errorgain[0])) <<
 					OMAP3430_ERRORGAIN_SHIFT);
-			vp_reg[vp_id].vp_vddmin = (OMAP3_VP1_VLIMITTO_VDDMIN <<
+			}
+			vp_reg[vp_id].vp_vddmin = (vlimitto_vddmin <<
 					OMAP3430_VDDMIN_SHIFT);
-			vp_reg[vp_id].vp_vddmax = (OMAP3_VP1_VLIMITTO_VDDMAX <<
+			vp_reg[vp_id].vp_vddmax = (vlimitto_vddmax <<
 					OMAP3430_VDDMAX_SHIFT);
 			vp_reg[vp_id].vp_tranxdone_status =
 					OMAP3430_VP1_TRANXDONE_ST;
 		} else if (vp_id == VP2) {
-			/*
-			 * OMAP3430 has error gain varying btw higher and
-			 * lower opp's
-			 */
-			vp_reg[vp_id].vp_errorgain = (((get_vdd2_opp() > 2) ?
-					(OMAP3_VP_CONFIG_ERRORGAIN_HIGHOPP) :
-					(OMAP3_VP_CONFIG_ERRORGAIN_LOWOPP)) <<
+			u8 vlimitto_vddmin, vlimitto_vddmax;
+
+			if (cpu_is_omap3630()) {
+				vlimitto_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
+				vlimitto_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
+				/*
+				 * OMAP3630 has error gain varying btw
+				 * all opp's
+				 */
+				vp_reg[vp_id].vp_errorgain =
+					(omap_errorgain[get_vdd2_opp() - 1] <<
+					 OMAP3430_ERRORGAIN_SHIFT);
+			} else {
+				vlimitto_vddmin = OMAP3430_VP2_VLIMITTO_VDDMIN;
+				vlimitto_vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX;
+				/*
+				 * OMAP3430 has error gain varying btw higher
+				 * and lower opp's
+				 */
+				vp_reg[vp_id].vp_errorgain =
+					(((get_vdd2_opp() > 2) ?
+					(omap_errorgain[1]) :
+					(omap_errorgain[0])) <<
 					OMAP3430_ERRORGAIN_SHIFT);
-			vp_reg[vp_id].vp_vddmin = (OMAP3_VP2_VLIMITTO_VDDMIN <<
+			}
+			vp_reg[vp_id].vp_vddmin = (vlimitto_vddmin <<
 					OMAP3430_VDDMIN_SHIFT);
-			vp_reg[vp_id].vp_vddmax = (OMAP3_VP2_VLIMITTO_VDDMAX <<
+			vp_reg[vp_id].vp_vddmax = (vlimitto_vddmax <<
 					OMAP3430_VDDMAX_SHIFT);
 			vp_reg[vp_id].vp_tranxdone_status =
 					OMAP3430_VP2_TRANXDONE_ST;
@@ -369,7 +425,6 @@ static int vp_forceupdate_scale_voltage(u32 vdd, u8 target_vsel,
 
 	smps_steps = abs(target_vsel - current_vsel);
 
-	/* OMAP3430 has errorgain varying btw higher and lower opp's */
 	if (cpu_is_omap34xx()) {
 		if (vdd == VDD1_OPP) {
 			u32 vc_cmdval0;
@@ -378,9 +433,20 @@ static int vp_forceupdate_scale_voltage(u32 vdd, u8 target_vsel,
 			vc_cmdval0 &= ~VC_CMD_ON_MASK;
 			vc_cmdval0 |= (target_vsel << VC_CMD_ON_SHIFT);
 			voltage_write_reg(vc_reg.vc_cmdval0_reg, vc_cmdval0);
-			vp_reg[vp_id].vp_errorgain = (((get_vdd1_opp() > 2) ?
-					(OMAP3_VP_CONFIG_ERRORGAIN_HIGHOPP) :
-					(OMAP3_VP_CONFIG_ERRORGAIN_LOWOPP)) <<
+			/*
+			 * OMAP3630 has error gain varying btw
+			 * all opp's where are 3430 has it varying between
+			 * higher and lower opp's
+			 */
+			if (cpu_is_omap3630())
+				vp_reg[vp_id].vp_errorgain =
+					(omap_errorgain[get_vdd1_opp() - 1] <<
+					OMAP3430_ERRORGAIN_SHIFT);
+			else
+				vp_reg[vp_id].vp_errorgain =
+					(((get_vdd1_opp() > 2) ?
+					(omap_errorgain[1]) :
+					(omap_errorgain[0])) <<
 					OMAP3430_ERRORGAIN_SHIFT);
 		} else if (vdd == VDD2_OPP) {
 			u32 vc_cmdval1;
@@ -389,9 +455,20 @@ static int vp_forceupdate_scale_voltage(u32 vdd, u8 target_vsel,
 			vc_cmdval1 &= ~VC_CMD_ON_MASK;
 			vc_cmdval1 |= (target_vsel << VC_CMD_ON_SHIFT);
 			voltage_write_reg(vc_reg.vc_cmdval1_reg, vc_cmdval1);
-			vp_reg[vp_id].vp_errorgain = (((get_vdd2_opp() > 2) ?
-					(OMAP3_VP_CONFIG_ERRORGAIN_HIGHOPP) :
-					(OMAP3_VP_CONFIG_ERRORGAIN_LOWOPP)) <<
+			/*
+			 * OMAP3630 has error gain varying btw
+			 * all opp's where are 3430 has it varying between
+			 * higher and lower opp's
+			 */
+			if (cpu_is_omap3630())
+				vp_reg[vp_id].vp_errorgain =
+					(omap_errorgain[get_vdd2_opp() - 1] <<
+					OMAP3430_ERRORGAIN_SHIFT);
+			else
+				vp_reg[vp_id].vp_errorgain =
+					(((get_vdd2_opp() > 2) ?
+					(omap_errorgain[1]) :
+					(omap_errorgain[0])) <<
 					OMAP3430_ERRORGAIN_SHIFT);
 		}
 	}
@@ -498,12 +575,18 @@ static int vc_bypass_scale_voltage(u32 vdd, u8 target_vsel, u8 current_vsel)
 		vc_cmdval0 |= (target_vsel << VC_CMD_ON_SHIFT);
 		voltage_write_reg(vc_reg.vc_cmdval0_reg, vc_cmdval0);
 		reg_addr = R_VDD1_SR_CONTROL;
-		/* OMAP3430 has errorgain varying btw higher and lower opp's */
-		if (cpu_is_omap34xx())
-			vp_reg[vdd].vp_errorgain = (((get_vdd1_opp() > 2) ?
-					(OMAP3_VP_CONFIG_ERRORGAIN_HIGHOPP) :
-					(OMAP3_VP_CONFIG_ERRORGAIN_LOWOPP)) <<
-					OMAP3430_ERRORGAIN_SHIFT);
+		/*
+		 * OMAP3630 has error gain varying btw all opp's where
+		 * are 3430 has it varying between higher and lower opp's
+		 */
+		if (cpu_is_omap3630())
+			vp_reg[vp_id].vp_errorgain =
+				(omap_errorgain[get_vdd1_opp() - 1] <<
+				OMAP3430_ERRORGAIN_SHIFT);
+		else
+			vp_reg[vp_id].vp_errorgain = (((get_vdd1_opp() > 2) ?
+				(omap_errorgain[1]) : (omap_errorgain[0])) <<
+				OMAP3430_ERRORGAIN_SHIFT);
 	} else if (vdd == VDD2_OPP) {
 		u32 vc_cmdval1;
 
@@ -512,12 +595,18 @@ static int vc_bypass_scale_voltage(u32 vdd, u8 target_vsel, u8 current_vsel)
 		vc_cmdval1 |= (target_vsel << VC_CMD_ON_SHIFT);
 		voltage_write_reg(vc_reg.vc_cmdval1_reg, vc_cmdval1);
 		reg_addr = R_VDD2_SR_CONTROL;
-		/* OMAP3430 has errorgain varying btw higher and lower opp's */
-		if (cpu_is_omap34xx())
-			vp_reg[vdd].vp_errorgain = (((get_vdd2_opp() > 2) ?
-					(OMAP3_VP_CONFIG_ERRORGAIN_HIGHOPP) :
-					(OMAP3_VP_CONFIG_ERRORGAIN_LOWOPP)) <<
-					OMAP3430_ERRORGAIN_SHIFT);
+		/*
+		 * OMAP3630 has error gain varying btw all opp's where
+		 * are 3430 has it varying between higher and lower opp's
+		 */
+		if (cpu_is_omap3630())
+			vp_reg[vp_id].vp_errorgain =
+				(omap_errorgain[get_vdd2_opp() - 1] <<
+				OMAP3430_ERRORGAIN_SHIFT);
+		else
+			vp_reg[vp_id].vp_errorgain = (((get_vdd2_opp() > 2) ?
+				(omap_errorgain[1]) : (omap_errorgain[0])) <<
+				OMAP3430_ERRORGAIN_SHIFT);
 	} else {
 		pr_warning("Wrong VDD passed in vc_bypass_scale_voltage %d\n",
 				vdd);
@@ -577,6 +666,10 @@ static void __init init_voltageprocessors(void)
 	if (cpu_is_omap34xx()) {
 		vp_reg = omap3_vp_reg;
 		no_scalable_vdd = OMAP3_NO_SCALABLE_VDD;
+		if (cpu_is_omap3630())
+			omap_errorgain = omap3630_errorgain;
+		else
+			omap_errorgain = omap3430_errorgain;
 	} else {
 		/* TODO: Add support for OMAP4 */
 		pr_warning("Voltage processor support not yet added \n");
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 615bde6..8135b91 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -50,23 +50,41 @@ extern int get_vdd2_opp(void);
 
 
 /*
- * Omap 3430 VP registerspecific values. Maybe these need to come from
+ * Omap3 generic VP register values. Maybe these need to come from
  * board file or PMIC data structure
  */
 #define OMAP3_VP_CONFIG_ERROROFFSET		0x00
-#define OMAP3_VP_CONFIG_ERRORGAIN_LOWOPP	0x0C
-#define OMAP3_VP_CONFIG_ERRORGAIN_HIGHOPP	0x18
 #define	OMAP3_VP_VSTEPMIN_SMPSWAITTIMEMIN	0x3C
 #define OMAP3_VP_VSTEPMIN_VSTEPMIN		0x1
 #define OMAP3_VP_VSTEPMAX_SMPSWAITTIMEMAX	0x3C
 #define OMAP3_VP_VSTEPMAX_VSTEPMAX		0x04
-#define OMAP3_VP1_VLIMITTO_VDDMIN		0x14
-#define OMAP3_VP1_VLIMITTO_VDDMAX		0x42
-#define OMAP3_VP2_VLIMITTO_VDDMAX		0x2C
-#define OMAP3_VP2_VLIMITTO_VDDMIN		0x18
 #define OMAP3_VP_VLIMITTO_TIMEOUT_US		0x200
 
 #define VOLTAGE_MOD	OMAP3430_GR_MOD
+
+
+/* Omap3430 specific VP register values. Maybe these need to come from
+ * board file or PMIC data structure
+ */
+#define OMAP3430_VP_CONFIG_ERRORGAIN_LOWOPP	0x0C
+#define OMAP3430_VP_CONFIG_ERRORGAIN_HIGHOPP	0x18
+#define OMAP3430_VP1_VLIMITTO_VDDMIN		0x14
+#define OMAP3430_VP1_VLIMITTO_VDDMAX		0x42
+#define OMAP3430_VP2_VLIMITTO_VDDMAX		0x2C
+#define OMAP3430_VP2_VLIMITTO_VDDMIN		0x18
+
+/* Omap3430 specific VP register values. Maybe these need to come from
+ * board file or PMIC data structure
+ */
+#define OMAP3630_VP_CONFIG_ERRORGAIN_OPP50	0x0C
+#define OMAP3630_VP_CONFIG_ERRORGAIN_OPP100	0x16
+#define OMAP3630_VP_CONFIG_ERRORGAIN_OPP120	0x23
+#define OMAP3630_VP_CONFIG_ERRORGAIN_OPPTM	0x27
+#define OMAP3630_VP1_VLIMITTO_VDDMIN		0x18
+#define OMAP3630_VP1_VLIMITTO_VDDMAX		0x3C
+#define OMAP3630_VP2_VLIMITTO_VDDMIN		0x18
+#define OMAP3630_VP2_VLIMITTO_VDDMAX		0x30
+
 /* TODO OMAP4 VP register values if the same file is used for OMAP4*/
 
 void omap_voltageprocessor_enable(int vp_id);
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index 804ed50..9b5e87b 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -169,6 +169,14 @@
 #define OMAP343X_CONTROL_SRAMLDO5	(OMAP2_CONTROL_GENERAL + 0x02C0)
 #define OMAP343X_CONTROL_CSI		(OMAP2_CONTROL_GENERAL + 0x02C4)
 
+/* OMAP3630 only CONTROL_GENERAL register offsets */
+#define OMAP3630_CONTROL_FUSE_OPP50_VDD1	(OMAP2_CONTROL_GENERAL + 0x0114)
+#define OMAP3630_CONTROL_FUSE_OPP100_VDD1	(OMAP2_CONTROL_GENERAL + 0x0118)
+#define OMAP3630_CONTROL_FUSE_OPP120_VDD1	(OMAP2_CONTROL_GENERAL + 0x011C)
+#define OMAP3630_CONTROL_FUSE_OPPTM_VDD1	(OMAP2_CONTROL_GENERAL + 0x0120)
+#define OMAP3630_CONTROL_FUSE_OPP50_VDD2	(OMAP2_CONTROL_GENERAL + 0x0128)
+#define OMAP3630_CONTROL_FUSE_OPP100_VDD2	(OMAP2_CONTROL_GENERAL + 0x012C)
+
 /* AM35XX only CONTROL_GENERAL register offsets */
 #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
 #define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
-- 
1.7.0.rc1.33.g07cf0f

Re: [PATCH 3/3] OMAP3: PM: Adding OMAP3630 support in smartreflex driver

[Felipe Balbi]

hi,

On Mon, Mar 08, 2010 at 10:50:51PM +0530, Thara Gopinath wrote:
> @@ -289,32 +311,66 @@ static void __init vp_reg_configure(int vp_id)
>  
>  		vp_reg[vp_id].vp_offs = omap3_vp_offs[vp_id];
>  		if (vp_id == VP1) {
> -			/*
> -			 * OMAP3430 has error gain varying btw higher and
> -			 * lower opp's
> -			 */
> -			vp_reg[vp_id].vp_errorgain = (((get_vdd1_opp() > 2) ?
> -					(OMAP3_VP_CONFIG_ERRORGAIN_HIGHOPP) :
> -					(OMAP3_VP_CONFIG_ERRORGAIN_LOWOPP)) <<
> +			u8 vlimitto_vddmin, vlimitto_vddmax;
> +
> +			if (cpu_is_omap3630()) {
> +				vlimitto_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
> +				vlimitto_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
> +				/*
> +				 * OMAP3630 has error gain varying btw
> +				 * all opp's
> +				 */
> +				vp_reg[vp_id].vp_errorgain =
> +					(omap_errorgain[get_vdd1_opp() - 1] <<
> +					OMAP3430_ERRORGAIN_SHIFT);

this error gain hunk repeats itself over and over again. How about
adding an inline function for handling that ? Also, why not using
SR version you added instead of cpu_is_xxx() check ?

-- 
balbi

RE: [PATCH 3/3] OMAP3: PM: Adding OMAP3630 support in smartreflex driver

[Gopinath, Thara]

>>-----Original Message-----
>>From: Felipe Balbi [mailto:me@felipebalbi.com]
>>Sent: Monday, March 08, 2010 11:49 PM
>>To: Gopinath, Thara
>>Cc: linux-omap@vger.kernel.org; khilman@deeprootsystems.com; paul@pwsan.com; Menon, Nishanth;
>>Sripathy, Vishwanath; Sawant, Anand; Cousson, Benoit
>>Subject: Re: [PATCH 3/3] OMAP3: PM: Adding OMAP3630 support in smartreflex driver
>>
>>hi,
>>
>>On Mon, Mar 08, 2010 at 10:50:51PM +0530, Thara Gopinath wrote:
>>> @@ -289,32 +311,66 @@ static void __init vp_reg_configure(int vp_id)
>>>
>>>  		vp_reg[vp_id].vp_offs = omap3_vp_offs[vp_id];
>>>  		if (vp_id == VP1) {
>>> -			/*
>>> -			 * OMAP3430 has error gain varying btw higher and
>>> -			 * lower opp's
>>> -			 */
>>> -			vp_reg[vp_id].vp_errorgain = (((get_vdd1_opp() > 2) ?
>>> -					(OMAP3_VP_CONFIG_ERRORGAIN_HIGHOPP) :
>>> -					(OMAP3_VP_CONFIG_ERRORGAIN_LOWOPP)) <<
>>> +			u8 vlimitto_vddmin, vlimitto_vddmax;
>>> +
>>> +			if (cpu_is_omap3630()) {
>>> +				vlimitto_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
>>> +				vlimitto_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
>>> +				/*
>>> +				 * OMAP3630 has error gain varying btw
>>> +				 * all opp's
>>> +				 */
>>> +				vp_reg[vp_id].vp_errorgain =
>>> +					(omap_errorgain[get_vdd1_opp() - 1] <<
>>> +					OMAP3430_ERRORGAIN_SHIFT);
>>
>>this error gain hunk repeats itself over and over again. How about
>>adding an inline function for handling that ? Also, why not using
>>SR version you added instead of cpu_is_xxx() check ?
Hello Felipe 

I could try adding a separate inline function. But I cannot use SR version to check this. This is because the error gain values vary between OMAP3430 OMAP3630 and OMAP4 and is independent of the smartreflex ip in use.

Regards
Thara

Re: [PATCH 2/3] OMAP3: PM: Smartreflex IP update changes for OMAP3630

[Kevin Hilman]

Thara Gopinath <thara@ti.com> writes:

> OMAP3430 uses the 65nm version of the smartreflex IP where as
> OMAP3630 and OMAP4430 uses the 45nm updated IP.
>
> This patch adds support for the updated smartreflex IP used
> in OMAP3630 and OMAP4 in the smartreflex driver.
>
> Major changes between the two versions of IP involve:
> 1. Change in offset position for ERRCONFIG and SENERROR registers
> 2. Change in bit positions for VP bound interrupt enable and status
>    in ERRCONFIG register.
> 3. Change in bit positions and width of SENNENABLE and SENPENABLE
>    bits in SRCONFIG registers.
> 4. Introduction of separate irq registers for MCU bound interrupts.
> 5. Removal of clockactivity bits in ERRCONFIG and introduction of
>   idlemode and wakeupenable bits in ERRCONFIG.
>
> Signed-off-by: Thara Gopinath <thara@ti.com>
> ---
>  arch/arm/mach-omap2/smartreflex.c |  218 ++++++++++++++++++++++++++++---------
>  arch/arm/mach-omap2/smartreflex.h |   51 +++++++--
>  2 files changed, 208 insertions(+), 61 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
> index 7aa84ab..2b1c529 100644
> --- a/arch/arm/mach-omap2/smartreflex.c
> +++ b/arch/arm/mach-omap2/smartreflex.c
> @@ -58,6 +58,18 @@ static struct omap_smartreflex_class_data *sr_class;
>  
>  #define SR_REGADDR(offs)	(sr->srbase_addr + offset)
>  
> +static inline int sr_type(void)
> +{
> +	if (cpu_is_omap3630())

what about OMAP4?

> +		return SR_TYPE_V2;
> +	else if (cpu_is_omap343x())
> +		return SR_TYPE_V1;
> +	else {
> +		pr_err("Trying to enable SR for Chip not support SR! \n");
> +		return 0;
> +	}
> +}

Instead of calling a function to check the type each time.  How about
adding a 'type' field to sr_info, setting the type once at init and
checking the flag at runtime.

>  static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
>  {
>  	__raw_writel(value, SR_REGADDR(offset));
> @@ -67,9 +79,11 @@ static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
>  					u32 value)
>  {
>  	u32 reg_val;
> +	u32 errconfig_offs, errconfig_mask;
>  
>  	reg_val = __raw_readl(SR_REGADDR(offset));
>  	reg_val &= ~mask;
> +
>  	/*
>  	 * Smartreflex error config register is special as it contains
>  	 * certain status bits which if written a 1 into means a clear
> @@ -78,8 +92,16 @@ static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
>  	 * value. Now if there is an actual reguest to write to these bits
>  	 * they will be set in the nex step.
>  	 */
> -	if (offset == ERRCONFIG)
> -		reg_val &= ~ERRCONFIG_STATUS_MASK;
> +	if (sr_type() == SR_TYPE_V1) {
> +		errconfig_offs = ERRCONFIG_V1;
> +		errconfig_mask = ERRCONFIG_STATUS_V1_MASK;
> +	} else if (sr_type() == SR_TYPE_V2) {
> +		errconfig_offs = ERRCONFIG_V2;
> +		errconfig_mask = ERRCONFIG_VPBOUNDINTST_V2;
> +	}
> +
> +	if (offset == errconfig_offs)
> +		reg_val &= ~errconfig_mask;
>  
>  	reg_val |= value;
>  	__raw_writel(reg_val, SR_REGADDR(offset));
> @@ -135,13 +157,21 @@ static void sr_clk_disable(struct omap_sr *sr)
>  static irqreturn_t sr_omap_isr(int irq, void *data)
>  {
>  	struct omap_sr *sr_info = (struct omap_sr *)data;
> -	u32 status;
> +	u32 status = 0;
>  
> -	/* Read the status bits */
> -	status = sr_read_reg(sr_info, ERRCONFIG);
> +	if (sr_type() == SR_TYPE_V1) {
> +		/* Read the status bits */
> +		status = sr_read_reg(sr_info, ERRCONFIG_V1);
>  
> -	/* Clear them by writing back */
> -	sr_write_reg(sr_info, ERRCONFIG, status);
> +		/* Clear them by writing back */
> +		sr_write_reg(sr_info, ERRCONFIG_V1, status);
> +	} else if (sr_type() == SR_TYPE_V2) {
> +		/* Read the status bits */
> +		sr_read_reg(sr_info, IRQSTATUS);
> +
> +		/* Clear them by writing back */
> +		sr_write_reg(sr_info, IRQSTATUS, status);
> +	}
>  
>  	/* Call the class driver notify function if registered*/
>  	if (sr_class->class_type == SR_CLASS2 && sr_class->notify)
> @@ -208,6 +238,7 @@ static void sr_configure(struct omap_sr *sr)
>  {
>  	u32 sr_config;
>  	u32 senp_en , senn_en;
> +	u8 senp_shift, senn_shift;
>  	struct omap_smartreflex_data *pdata = sr->pdev->dev.platform_data;
>  
>  	/* Common settings for SR Class3 and SR Class2 */
> @@ -218,8 +249,16 @@ static void sr_configure(struct omap_sr *sr)
>  	senn_en = pdata->senn_mod;
>  
>  	sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
> -		SRCONFIG_SENENABLE | (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
> -		(senp_en << SRCONFIG_SENPENABLE_SHIFT) | SRCONFIG_DELAYCTRL;
> +		SRCONFIG_SENENABLE;
> +	if (sr_type() == SR_TYPE_V1) {
> +		sr_config |= SRCONFIG_DELAYCTRL;
> +		senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
> +		senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
> +	} else if (sr_type() == SR_TYPE_V2) {
> +		senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
> +		senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
> +	}
> +	sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
>  	sr_write_reg(sr, SRCONFIG, sr_config);
>  
>  	if ((sr_class->class_type == SR_CLASS3) || (sr_class->class_type ==
> @@ -230,20 +269,30 @@ static void sr_configure(struct omap_sr *sr)
>  		 * SR CLASS 2 can choose between ERROR module and MINMAXAVG
>  		 * module.
>  		 */
> -		u32 sr_errconfig;
> +		u32 sr_errconfig, errconfig_offs;
> +		u32 vpboundint_en, vpboundint_st;
> +
> +		if (sr_type() == SR_TYPE_V1) {
> +			errconfig_offs = ERRCONFIG_V1;
> +			vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
> +			vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
> +		} else if (sr_type() == SR_TYPE_V2) {
> +			errconfig_offs = ERRCONFIG_V2;
> +			vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
> +			vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
> +		}
>  
>  		sr_modify_reg(sr, SRCONFIG, SRCONFIG_ERRGEN_EN,
>  			SRCONFIG_ERRGEN_EN);
>  		sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) |
>  			(sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) |
>  			(sr->err_minlimit <<  ERRCONFIG_ERRMiNLIMIT_SHIFT);
> -		sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
> +		sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK |
>  			SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
>  			sr_errconfig);
>  		/* Enabling the interrupts if the ERROR module is used */
> -		sr_modify_reg(sr, ERRCONFIG,
> -			(ERRCONFIG_VPBOUNDINTEN),
> -			(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
> +		sr_modify_reg(sr, errconfig_offs,
> +			vpboundint_en, (vpboundint_en | vpboundint_st));
>  	} else if ((sr_class->class_type == SR_CLASS2) &&
>  			(sr_class->mod_use == SR_USE_ERROR_MOD)) {
>  		/*
> @@ -263,12 +312,27 @@ static void sr_configure(struct omap_sr *sr)
>  		 * Enabling the interrupts if MINMAXAVG module is used.
>  		 * TODO: check if all the interrupts are mandatory
>  		 */
> -		sr_modify_reg(sr, ERRCONFIG,
> -			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
> -			ERRCONFIG_MCUBOUNDINTEN),
> -			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
> -			 ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
> -			 ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
> +		if (sr_type() == SR_TYPE_V1) {
> +			sr_modify_reg(sr, ERRCONFIG_V1,
> +				(ERRCONFIG_MCUACCUMINTEN |
> +				 ERRCONFIG_MCUVALIDINTEN |
> +				 ERRCONFIG_MCUBOUNDINTEN),
> +				(ERRCONFIG_MCUACCUMINTEN |
> +				 ERRCONFIG_MCUACCUMINTST |
> +				 ERRCONFIG_MCUVALIDINTEN |
> +				 ERRCONFIG_MCUVALIDINTST |
> +				 ERRCONFIG_MCUBOUNDINTEN |
> +				 ERRCONFIG_MCUBOUNDINTST));
> +		} else if (sr_type() == SR_TYPE_V2) {
> +			sr_write_reg(sr, IRQSTATUS,
> +				IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
> +				IRQSTATUS_MCBOUNDSINT |
> +				IRQSTATUS_MCUDISABLEACKINT);
> +			sr_write_reg(sr, IRQENABLE_SET,
> +				IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
> +				IRQENABLE_MCUBOUNDSINT |
> +				IRQENABLE_MCUDISABLEACKINT);
> +		}
>  	}
>  }
>  
> @@ -318,6 +382,81 @@ static void sr_stop_vddautocomap(int srid)
>  
>  }
>  
> +static void sr_v1_disable(struct omap_sr *sr)
> +{
> +	int timeout = 0;
> +
> +	/* Enable MCUDisableAcknowledge interrupt */
> +	sr_modify_reg(sr, ERRCONFIG_V1,
> +			ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
> +
> +	/* SRCONFIG - disable SR */
> +	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
> +
> +	/* Disable all other SR interrupts and clear the status */
> +	sr_modify_reg(sr, ERRCONFIG_V1,
> +			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
> +			ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
> +			(ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
> +			ERRCONFIG_MCUBOUNDINTST |
> +			ERRCONFIG_VPBOUNDINTST_V1));
> +
> +	/* Wait for SR to be disabled.
> +	 * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
> +	 */
> +	while ((timeout < SR_DISABLE_TIMEOUT) &&
> +		(!(sr_read_reg(sr, ERRCONFIG_V1) &
> +		ERRCONFIG_MCUDISACKINTST))) {
> +		udelay(1);
> +		timeout++;
> +	}
> +
> +	if (timeout == SR_DISABLE_TIMEOUT)
> +		pr_warning("SR%d disable timedout\n", sr->srid);
> +
> +	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
> +	sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN,
> +			ERRCONFIG_MCUDISACKINTST);
> +}
> +
> +static void sr_v2_disable(struct omap_sr *sr)
> +{
> +	int timeout = 0;
> +
> +	/* Enable MCUDisableAcknowledge interrupt */
> +	sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT);
> +
> +	/* SRCONFIG - disable SR */
> +	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
> +
> +	/* Disable all other SR interrupts and clear the status */
> +	sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
> +			ERRCONFIG_VPBOUNDINTST_V2);
> +	sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
> +			IRQENABLE_MCUVALIDINT |
> +			IRQENABLE_MCUBOUNDSINT));
> +	sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT |
> +			IRQSTATUS_MCVALIDINT |
> +			IRQSTATUS_MCBOUNDSINT));
> +
> +	/* Wait for SR to be disabled.
> +	 * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
> +	 */

multi-line comment style

> +	while ((timeout < SR_DISABLE_TIMEOUT) &&
> +		(!(sr_read_reg(sr, IRQSTATUS) &
> +		IRQSTATUS_MCUDISABLEACKINT))) {
> +		udelay(1);
> +		timeout++;
> +	}

use omap_test_timeout()

> +	if (timeout == SR_DISABLE_TIMEOUT)
> +		pr_warning("SR%d disable timedout\n", sr->srid);
> +
> +	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
> +	sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT);
> +	sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
> +}
> +
>  /* Public Functions */
>  
>  /**
> @@ -373,6 +512,7 @@ int sr_enable(int srid, u32 target_opp_no)
>  	sr_configure(sr);
>  
>  	nvalue_reciprocal = pdata->sr_nvalue[target_opp_no - 1];
> +

stray whitespace change

>  	if (nvalue_reciprocal == 0) {
>  		pr_notice("OPP%d doesn't support SmartReflex\n",
>  								target_opp_no);
> @@ -395,44 +535,18 @@ int sr_enable(int srid, u32 target_opp_no)
>  void sr_disable(int srid)
>  {
>  	struct omap_sr *sr = _sr_lookup(srid);
> -	int timeout = 0;
>  
>  	/* Check if SR is already disabled. If yes do nothing */
>  	if (!(sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE))
>  		return;
>  
> -	/* Enable MCUDisableAcknowledge interrupt */
> -	sr_modify_reg(sr, ERRCONFIG,
> -			ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
> +	if (sr_type() == SR_TYPE_V1)
> +		sr_v1_disable(sr);
>  
> -	/* SRCONFIG - disable SR */
> -	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
> -
> -	/* Disable all other SR interrupts and clear the status */
> -	sr_modify_reg(sr, ERRCONFIG,
> -			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
> -			ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN),
> -			(ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
> -			ERRCONFIG_MCUBOUNDINTST | ERRCONFIG_VPBOUNDINTST));
> -
> -	/* Wait for SR to be disabled.
> -	 * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
> -	 */
> -	while ((timeout < SR_DISABLE_TIMEOUT) &&
> -		(!(sr_read_reg(sr, ERRCONFIG) & ERRCONFIG_MCUDISACKINTST))) {
> -
> -		udelay(1);
> -		timeout++;
> -	}
> -
> -	if (timeout == SR_DISABLE_TIMEOUT)
> -		pr_warning("SR%d disable timedout\n", srid);
> -
> -	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt
> -	 * Also enable VPBOUND interrrupt
> -	 */
> -	sr_modify_reg(sr, ERRCONFIG, ERRCONFIG_MCUDISACKINTEN,
> -			ERRCONFIG_MCUDISACKINTST);
> +	else if (sr_type() == SR_TYPE_V2)
> +		sr_v2_disable(sr);
> +	else
> +		return;

Rather than the if-else, how about adding a ->disable hook to sr_info
set at init time and called here.

Kevin

RE: [PATCH 2/3] OMAP3: PM: Smartreflex IP update changes for OMAP3630

[Gopinath, Thara]

>>-----Original Message-----
>>From: Kevin Hilman [mailto:khilman@deeprootsystems.com]
>>Sent: Monday, March 08, 2010 11:16 PM
>>To: Gopinath, Thara
>>Cc: linux-omap@vger.kernel.org; paul@pwsan.com; Menon, Nishanth; Sripathy, Vishwanath; Sawant, Anand;
>>Cousson, Benoit
>>Subject: Re: [PATCH 2/3] OMAP3: PM: Smartreflex IP update changes for OMAP3630
>>
>>Thara Gopinath <thara@ti.com> writes:
>>
>>> OMAP3430 uses the 65nm version of the smartreflex IP where as
>>> OMAP3630 and OMAP4430 uses the 45nm updated IP.
>>>
>>> This patch adds support for the updated smartreflex IP used
>>> in OMAP3630 and OMAP4 in the smartreflex driver.
>>>
>>> Major changes between the two versions of IP involve:
>>> 1. Change in offset position for ERRCONFIG and SENERROR registers
>>> 2. Change in bit positions for VP bound interrupt enable and status
>>>    in ERRCONFIG register.
>>> 3. Change in bit positions and width of SENNENABLE and SENPENABLE
>>>    bits in SRCONFIG registers.
>>> 4. Introduction of separate irq registers for MCU bound interrupts.
>>> 5. Removal of clockactivity bits in ERRCONFIG and introduction of
>>>   idlemode and wakeupenable bits in ERRCONFIG.
>>>
>>> Signed-off-by: Thara Gopinath <thara@ti.com>
>>> ---
>>>  arch/arm/mach-omap2/smartreflex.c |  218 ++++++++++++++++++++++++++++---------
>>>  arch/arm/mach-omap2/smartreflex.h |   51 +++++++--
>>>  2 files changed, 208 insertions(+), 61 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
>>> index 7aa84ab..2b1c529 100644
>>> --- a/arch/arm/mach-omap2/smartreflex.c
>>> +++ b/arch/arm/mach-omap2/smartreflex.c
>>> @@ -58,6 +58,18 @@ static struct omap_smartreflex_class_data *sr_class;
>>>
>>>  #define SR_REGADDR(offs)	(sr->srbase_addr + offset)
>>>
>>> +static inline int sr_type(void)
>>> +{
>>> +	if (cpu_is_omap3630())
>>
>>what about OMAP4?

Hi Kevin,

OMAP4 support will be added as a different patch once these preliminary patches get accepted.

Regards
Thara

Re: [PATCH 2/3] OMAP3: PM: Smartreflex IP update changes for OMAP3630

[Felipe Balbi]

On Mon, Mar 08, 2010 at 10:50:50PM +0530, Thara Gopinath wrote:
> +static inline int sr_type(void)
> +{
> +	if (cpu_is_omap3630())
> +		return SR_TYPE_V2;
> +	else if (cpu_is_omap343x())
> +		return SR_TYPE_V1;
> +	else {
> +		pr_err("Trying to enable SR for Chip not support SR! \n");
> +		return 0;
> +	}

if one branch has curly braces, all of them should have. Check
Documentation/CodingStyle.

-- 
balbi

Re: [PATCH 1/3] OMAP3: PM: Bug fix in Smartreflex driver.

[Kevin Hilman]

Thara Gopinath <thara@ti.com> writes:

> This patch sets and unsets is_sr_reset is appropriate places so that
> trying to enable smart reflex in a non-supported OMAP chip does not
> lead to unnecessary crash

$SUBJECT needs to be more desciptive.   Patch content looks fine.

Kevin


> Signed-off-by: Thara Gopinath <thara@ti.com>
> ---
>  arch/arm/mach-omap2/smartreflex.c |   31 +++++++++++++++++++++----------
>  1 files changed, 21 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
> index ca2223d..7aa84ab 100644
> --- a/arch/arm/mach-omap2/smartreflex.c
> +++ b/arch/arm/mach-omap2/smartreflex.c
> @@ -108,9 +108,14 @@ static int sr_clk_enable(struct omap_sr *sr)
>  {
>  	struct omap_smartreflex_data *pdata = sr->pdev->dev.platform_data;
>  
> +	if (!sr->is_sr_reset)
> +		return 0;
> +
>  	if (pdata->device_enable)
>  		pdata->device_enable(sr->pdev);
>  
> +	sr->is_sr_reset = 0;
> +
>  	return 0;
>  }
>  
> @@ -118,6 +123,9 @@ static void sr_clk_disable(struct omap_sr *sr)
>  {
>  	struct omap_smartreflex_data *pdata = sr->pdev->dev.platform_data;
>  
> +	if (sr->is_sr_reset)
> +		return;
> +
>  	if (pdata->device_idle)
>  		pdata->device_idle(sr->pdev);
>  
> @@ -262,7 +270,6 @@ static void sr_configure(struct omap_sr *sr)
>  			 ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
>  			 ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
>  	}
> -	sr->is_sr_reset = 0;
>  }
>  
>  static void sr_start_vddautocomap(int srid)
> @@ -283,8 +290,7 @@ static void sr_start_vddautocomap(int srid)
>  	sr->is_autocomp_active = 1;
>  	if (!sr_class->enable(srid)) {
>  		sr->is_autocomp_active = 0;
> -		if (sr->is_sr_reset == 1)
> -			sr_clk_disable(sr);
> +		sr_clk_disable(sr);
>  	}
>  }
>  
> @@ -303,8 +309,10 @@ static void sr_stop_vddautocomap(int srid)
>  	}
>  
>  	if (sr->is_autocomp_active == 1) {
> -		sr_class->disable(srid);
> -		sr_clk_disable(sr);
> +		if (!sr->is_sr_reset) {
> +			sr_class->disable(srid);
> +			sr_clk_disable(sr);
> +		}
>  		sr->is_autocomp_active = 0;
>  	}
>  
> @@ -357,6 +365,11 @@ int sr_enable(int srid, u32 target_opp_no)
>  
>  	/* Enable the clocks and configure SR */
>  	sr_clk_enable(sr);
> +
> +	/* Check if SR is already enabled. If yes do nothing */
> +	if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE)
> +		return true;
> +
>  	sr_configure(sr);
>  
>  	nvalue_reciprocal = pdata->sr_nvalue[target_opp_no - 1];
> @@ -447,10 +460,8 @@ void omap_smartreflex_enable(int srid)
>  	}
>  
>  	if (sr->is_autocomp_active == 1) {
> -		if (sr->is_sr_reset == 1) {
> -			if (!sr_class->enable(srid))
> -				sr_clk_disable(sr);
> -		}
> +		if (!sr_class->enable(srid))
> +			sr_clk_disable(sr);
>  	}
>  }
>  
> @@ -478,7 +489,7 @@ void omap_smartreflex_disable(int srid)
>  	}
>  
>  	if (sr->is_autocomp_active == 1) {
> -		if (sr->is_sr_reset == 0) {
> +		if (!sr->is_sr_reset) {
>  			sr_class->disable(srid);
>  			/* Disable SR clk */
>  			sr_clk_disable(sr);
> -- 
> 1.7.0.rc1.33.g07cf0f

Re: [PATCH 1/3] OMAP3: PM: Bug fix in Smartreflex driver.

[Felipe Balbi]

On Mon, Mar 08, 2010 at 10:50:49PM +0530, Thara Gopinath wrote:
> This patch sets and unsets is_sr_reset is appropriate places so that
> trying to enable smart reflex in a non-supported OMAP chip does not
> lead to unnecessary crash
> 
> Signed-off-by: Thara Gopinath <thara@ti.com>

$SUBJECT is not really useful. You could describe the problem slightly
by saying something like:

fix crash when enabling SmartReflex on non-supported OMAPs

-- 
balbi

Re: [PATCH 0/3] OMAP3: PM: OMAP3630 support for smartreflex driver

[Kevin Hilman]

Thara Gopinath <thara@ti.com> writes:

> This patch series adds support for the updated 45nm smrtrelfex IP
> supported in OMAP3630 and OMAP4 in the smartreflex driver and
> adds support to enable smartreflex autocompensation for OMAP3630
> using test nvalues.
>
> This patch series is based on the following patch series/patches
> for proper functionality.
> 	http://marc.info/?l=linux-omap&m=126700378625593&w=2
> 	http://patchwork.kernel.org/patch/77739/
>
> This patch series has been tested on OMAP3630 SDP board with
> CONFIG_OMAP_SMARTREFLEX_TESTING option enabled in the menuconfig.
>
> This patch series has been based on Kevin's PM tree
> origin/pm-wip-opp branch 

It appears to also depend on the previous SR rework series.  It
doesn't apply directly to pm-wip-opp.

> and on adea81232e8fc82334bca3707efa23dc854f29fc commit id.

This commit is a rather old version of pm-wip-opp, please refresh
against current.

Kevin




> Thara Gopinath (3):
>   OMAP3: PM: Bug fix in Smartreflex driver.
>   OMAP3: PM: Smartreflex IP update changes for OMAP3630
>   OMAP3: PM: Adding OMAP3630 support in smartreflex driver
>
>  arch/arm/mach-omap2/omap_hwmod_34xx.h     |   49 ++++-
>  arch/arm/mach-omap2/smartreflex.c         |  354 +++++++++++++++++++++++-----
>  arch/arm/mach-omap2/smartreflex.h         |   51 ++++-
>  arch/arm/mach-omap2/voltage.c             |  167 +++++++++++---
>  arch/arm/mach-omap2/voltage.h             |   32 ++-
>  arch/arm/plat-omap/include/plat/control.h |    8 +
>  6 files changed, 542 insertions(+), 119 deletions(-)

RE: [PATCH 0/3] OMAP3: PM: OMAP3630 support for smartreflex driver

[Gopinath, Thara]

>>-----Original Message-----
>>From: Kevin Hilman [mailto:khilman@deeprootsystems.com]
>>Sent: Monday, March 08, 2010 11:06 PM
>>To: Gopinath, Thara
>>Cc: linux-omap@vger.kernel.org; paul@pwsan.com; Menon, Nishanth; Sripathy, Vishwanath; Sawant, Anand;
>>Cousson, Benoit
>>Subject: Re: [PATCH 0/3] OMAP3: PM: OMAP3630 support for smartreflex driver
>>
>>Thara Gopinath <thara@ti.com> writes:
>>
>>> This patch series adds support for the updated 45nm smrtrelfex IP
>>> supported in OMAP3630 and OMAP4 in the smartreflex driver and
>>> adds support to enable smartreflex autocompensation for OMAP3630
>>> using test nvalues.
>>>
>>> This patch series is based on the following patch series/patches
>>> for proper functionality.
>>> 	http://marc.info/?l=linux-omap&m=126700378625593&w=2
>>> 	http://patchwork.kernel.org/patch/77739/
>>>
>>> This patch series has been tested on OMAP3630 SDP board with
>>> CONFIG_OMAP_SMARTREFLEX_TESTING option enabled in the menuconfig.
>>>
>>> This patch series has been based on Kevin's PM tree
>>> origin/pm-wip-opp branch
>>
>>It appears to also depend on the previous SR rework series.  It
>>doesn't apply directly to pm-wip-opp.

Hi Kevin,

The patch/series dependency mentions the previous SR rework patch series in the above line.

>>
>>> and on adea81232e8fc82334bca3707efa23dc854f29fc commit id.
>>
>>This commit is a rather old version of pm-wip-opp, please refresh
>>against current.

I will do this. I will send out a V2 for both this series and the earlier smartreflex rework series.

Regards
Thara

Re: [PATCH 0/3] OMAP3: PM: OMAP3630 support for smartreflex driver

[Kevin Hilman]

"Gopinath, Thara" <thara@ti.com> writes:

>>>-----Original Message-----
>>>From: Kevin Hilman [mailto:khilman@deeprootsystems.com]
>>>Sent: Monday, March 08, 2010 11:06 PM
>>>To: Gopinath, Thara
>>>Cc: linux-omap@vger.kernel.org; paul@pwsan.com; Menon, Nishanth; Sripathy, Vishwanath; Sawant, Anand;
>>>Cousson, Benoit
>>>Subject: Re: [PATCH 0/3] OMAP3: PM: OMAP3630 support for smartreflex driver
>>>
>>>Thara Gopinath <thara@ti.com> writes:
>>>
>>>> This patch series adds support for the updated 45nm smrtrelfex IP
>>>> supported in OMAP3630 and OMAP4 in the smartreflex driver and
>>>> adds support to enable smartreflex autocompensation for OMAP3630
>>>> using test nvalues.
>>>>
>>>> This patch series is based on the following patch series/patches
>>>> for proper functionality.
>>>> 	http://marc.info/?l=linux-omap&m=126700378625593&w=2
>>>> 	http://patchwork.kernel.org/patch/77739/
>>>>
>>>> This patch series has been tested on OMAP3630 SDP board with
>>>> CONFIG_OMAP_SMARTREFLEX_TESTING option enabled in the menuconfig.
>>>>
>>>> This patch series has been based on Kevin's PM tree
>>>> origin/pm-wip-opp branch
>>>
>>>It appears to also depend on the previous SR rework series.  It
>>>doesn't apply directly to pm-wip-opp.
>
> Hi Kevin,
>
> The patch/series dependency mentions the previous SR rework patch series in the above line.
>

No, it only mentions the PM branch + pm-wip-opp branch.  I saw mention
of the previous SR rework series in description.

>>>
>>>> and on adea81232e8fc82334bca3707efa23dc854f29fc commit id.
>>>
>>>This commit is a rather old version of pm-wip-opp, please refresh
>>>against current.
>
> I will do this. I will send out a V2 for both this series and the earlier smartreflex rework series.
>

Thanks,

Kevin