[Intel-gfx] [PATCH 0/9] drm/i915: Register define cleanups

[Intel-gfx] [PATCH 0/9] drm/i915: Register define cleanups

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

A bunch of REG_BIT() stuff a random collection of registers.
Some of these are related to areas where I plan to do a bit of
additional work on the code itself, and a few are just some easy
ones I spotted in the vicinity.

Ville Syrjälä (9):
  drm/i915: Bump DSL linemask to 20 bits
  drm/i915: Clean up PIPEMISC register defines
  drm/i915: Clean up SKL_BOTTOM_COLOR defines
  drm/i915: Clean up PIPECONF bit defines
  drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit defines
  drm/i915: Clean up PIPESRC defines
  drm/i915: Clean up CRC register defines
  drm/i915: Clean up DPINVGTT/VLV_DPFLIPSTAT bits
  drm/i915: Clean up FPGA_DBG/CLAIM_ER bits

 drivers/gpu/drm/i915/display/i9xx_plane.c     |   4 +-
 drivers/gpu/drm/i915/display/icl_dsi.c        |   4 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  95 ++---
 .../gpu/drm/i915/display/intel_pch_display.c  |  20 +-
 drivers/gpu/drm/i915/gvt/display.c            |   4 +-
 drivers/gpu/drm/i915/gvt/handlers.c           |   4 +-
 drivers/gpu/drm/i915/i915_irq.c               |   9 +-
 drivers/gpu/drm/i915/i915_reg.h               | 392 +++++++++---------
 8 files changed, 261 insertions(+), 271 deletions(-)

-- 
2.32.0

[Intel-gfx] [PATCH 1/9] drm/i915: Bump DSL linemask to 20 bits

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Since tgl PIPE_DSL has 20 bits for the scanline. Let's bump our
definition to match. And while at it let's also add the define
for the current field readback.

We can also get rid of the gen2 vs. gen3+ nonsense since none
of the extra bits ever did anything and just always read
as zero.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 10 ++--------
 drivers/gpu/drm/i915/i915_irq.c              |  7 ++-----
 drivers/gpu/drm/i915/i915_reg.h              |  4 ++--
 3 files changed, 6 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0ceee8ac6671..6073f94632ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -348,16 +348,10 @@ static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
 {
 	i915_reg_t reg = PIPEDSL(pipe);
 	u32 line1, line2;
-	u32 line_mask;
 
-	if (DISPLAY_VER(dev_priv) == 2)
-		line_mask = DSL_LINEMASK_GEN2;
-	else
-		line_mask = DSL_LINEMASK_GEN3;
-
-	line1 = intel_de_read(dev_priv, reg) & line_mask;
+	line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
 	msleep(5);
-	line2 = intel_de_read(dev_priv, reg) & line_mask;
+	line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
 
 	return line1 != line2;
 }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 038a9ec563c1..eb8c92324aee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -836,10 +836,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 		vtotal /= 2;
 
-	if (DISPLAY_VER(dev_priv) == 2)
-		position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
-	else
-		position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
+	position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
 
 	/*
 	 * On HSW, the DSL reg (0x70000) appears to return 0 if we
@@ -858,7 +855,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 
 		for (i = 0; i < 100; i++) {
 			udelay(1);
-			temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
+			temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
 			if (temp != position) {
 				position = temp;
 				break;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 686f0a1b7860..f5d54ed2efc1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6165,8 +6165,8 @@ enum {
 
 /* Pipe A */
 #define _PIPEADSL		0x70000
-#define   DSL_LINEMASK_GEN2	0x00000fff
-#define   DSL_LINEMASK_GEN3	0x00001fff
+#define   PIPEDSL_CURR_FIELD	REG_BIT(31) /* ctg+ */
+#define   PIPEDSL_LINE_MASK	REG_GENMASK(19, 0)
 #define _PIPEACONF		0x70008
 #define   PIPECONF_ENABLE	(1 << 31)
 #define   PIPECONF_DISABLE	0
-- 
2.32.0

[Intel-gfx] [PATCH 2/9] drm/i915: Clean up PIPEMISC register defines

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use REG_BIT() & co. for PIPEMISC* bits, and while at it
fill in the missing dithering bits since we already had some
of them defined.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 18 +++++-----
 drivers/gpu/drm/i915/i915_reg.h              | 35 +++++++++++---------
 2 files changed, 28 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6073f94632ab..e293241450b1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3724,18 +3724,18 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
 
 	switch (crtc_state->pipe_bpp) {
 	case 18:
-		val |= PIPEMISC_6_BPC;
+		val |= PIPEMISC_BPC_6;
 		break;
 	case 24:
-		val |= PIPEMISC_8_BPC;
+		val |= PIPEMISC_BPC_8;
 		break;
 	case 30:
-		val |= PIPEMISC_10_BPC;
+		val |= PIPEMISC_BPC_10;
 		break;
 	case 36:
 		/* Port output 12BPC defined for ADLP+ */
 		if (DISPLAY_VER(dev_priv) > 12)
-			val |= PIPEMISC_12_BPC_ADLP;
+			val |= PIPEMISC_BPC_12_ADLP;
 		break;
 	default:
 		MISSING_CASE(crtc_state->pipe_bpp);
@@ -3771,7 +3771,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
 		}
 
 		intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
-			     PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
+			     PIPE_MISC2_BUBBLE_COUNTER_MASK,
 			     scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
 			     PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
 	}
@@ -3787,11 +3787,11 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
 	tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
 
 	switch (tmp & PIPEMISC_BPC_MASK) {
-	case PIPEMISC_6_BPC:
+	case PIPEMISC_BPC_6:
 		return 18;
-	case PIPEMISC_8_BPC:
+	case PIPEMISC_BPC_8:
 		return 24;
-	case PIPEMISC_10_BPC:
+	case PIPEMISC_BPC_10:
 		return 30;
 	/*
 	 * PORT OUTPUT 12 BPC defined for ADLP+.
@@ -3803,7 +3803,7 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
 	 * on older platforms, need to find a workaround for 12 BPC
 	 * MIPI DSI HW readout.
 	 */
-	case PIPEMISC_12_BPC_ADLP:
+	case PIPEMISC_BPC_12_ADLP:
 		if (DISPLAY_VER(dev_priv) > 12)
 			return 36;
 		fallthrough;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f5d54ed2efc1..e300a202ce2d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6308,32 +6308,35 @@ enum {
 
 #define _PIPE_MISC_A			0x70030
 #define _PIPE_MISC_B			0x71030
-#define   PIPEMISC_YUV420_ENABLE	(1 << 27) /* glk+ */
-#define   PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
-#define   PIPEMISC_HDR_MODE_PRECISION	(1 << 23) /* icl+ */
-#define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1 << 11)
-#define   PIPEMISC_PIXEL_ROUNDING_TRUNC	REG_BIT(8) /* tgl+ */
+#define   PIPEMISC_YUV420_ENABLE		REG_BIT(27) /* glk+ */
+#define   PIPEMISC_YUV420_MODE_FULL_BLEND	REG_BIT(26) /* glk+ */
+#define   PIPEMISC_HDR_MODE_PRECISION		REG_BIT(23) /* icl+ */
+#define   PIPEMISC_OUTPUT_COLORSPACE_YUV	REG_BIT(11)
+#define   PIPEMISC_PIXEL_ROUNDING_TRUNC		REG_BIT(8) /* tgl+ */
 /*
  * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
  * valid values of: 6, 8, 10 BPC.
  * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
  * 6, 8, 10, 12 BPC.
  */
-#define   PIPEMISC_BPC_MASK		(7 << 5)
-#define   PIPEMISC_8_BPC		(0 << 5)
-#define   PIPEMISC_10_BPC		(1 << 5)
-#define   PIPEMISC_6_BPC		(2 << 5)
-#define   PIPEMISC_12_BPC_ADLP		(4 << 5) /* adlp+ */
-#define   PIPEMISC_DITHER_ENABLE	(1 << 4)
-#define   PIPEMISC_DITHER_TYPE_MASK	(3 << 2)
-#define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
+#define   PIPEMISC_BPC_MASK			REG_GENMASK(7, 5)
+#define   PIPEMISC_BPC_8			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)
+#define   PIPEMISC_BPC_10			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1)
+#define   PIPEMISC_BPC_6			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2)
+#define   PIPEMISC_BPC_12_ADLP			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */
+#define   PIPEMISC_DITHER_ENABLE		REG_BIT(4)
+#define   PIPEMISC_DITHER_TYPE_MASK		REG_GENMASK(3, 2)
+#define   PIPEMISC_DITHER_TYPE_SP		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0)
+#define   PIPEMISC_DITHER_TYPE_ST1		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1)
+#define   PIPEMISC_DITHER_TYPE_ST2		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2)
+#define   PIPEMISC_DITHER_TYPE_TEMP		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3)
 #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)
 
 #define _PIPE_MISC2_A					0x7002C
 #define _PIPE_MISC2_B					0x7102C
-#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN		(0x50 << 24)
-#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS		(0x14 << 24)
-#define   PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK	(0xff << 24)
+#define   PIPE_MISC2_BUBBLE_COUNTER_MASK	REG_GENMASK(31, 24)
+#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
+#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
 #define PIPE_MISC2(pipe)					_MMIO_PIPE2(pipe, _PIPE_MISC2_A)
 
 /* Skylake+ pipe bottom (background) color */
-- 
2.32.0

[Intel-gfx] [PATCH 3/9] drm/i915: Clean up SKL_BOTTOM_COLOR defines

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use REG_BIT() for SKL_BOTTOM_COLOR.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e300a202ce2d..8b227dabb10c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6341,8 +6341,8 @@ enum {
 
 /* Skylake+ pipe bottom (background) color */
 #define _SKL_BOTTOM_COLOR_A		0x70034
-#define   SKL_BOTTOM_COLOR_GAMMA_ENABLE	(1 << 31)
-#define   SKL_BOTTOM_COLOR_CSC_ENABLE	(1 << 30)
+#define   SKL_BOTTOM_COLOR_GAMMA_ENABLE		REG_BIT(31)
+#define   SKL_BOTTOM_COLOR_CSC_ENABLE		REG_BIT(30)
 #define SKL_BOTTOM_COLOR(pipe)		_MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
 
 #define _ICL_PIPE_A_STATUS			0x70058
-- 
2.32.0

[Intel-gfx] [PATCH 4/9] drm/i915: Clean up PIPECONF bit defines

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use REG_BIT() & co. for PIPECONF bits, and adjust the
naming of various bits to be more consistent.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        |   4 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  60 +++++-----
 .../gpu/drm/i915/display/intel_pch_display.c  |   7 +-
 drivers/gpu/drm/i915/gvt/display.c            |   4 +-
 drivers/gpu/drm/i915/gvt/handlers.c           |   4 +-
 drivers/gpu/drm/i915/i915_reg.h               | 108 +++++++++---------
 6 files changed, 89 insertions(+), 98 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index c05fb861f10c..0f6587bef106 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1048,7 +1048,7 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
 
 		/* wait for transcoder to be enabled */
 		if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
-					  I965_PIPECONF_ACTIVE, 10))
+					  PIPECONF_STATE_ENABLE, 10))
 			drm_err(&dev_priv->drm,
 				"DSI transcoder not enabled\n");
 	}
@@ -1317,7 +1317,7 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
 
 		/* wait for transcoder to be disabled */
 		if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
-					    I965_PIPECONF_ACTIVE, 50))
+					    PIPECONF_STATE_ENABLE, 50))
 			drm_err(&dev_priv->drm,
 				"DSI trancoder not disabled\n");
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e293241450b1..4e29032b29d6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -386,13 +386,11 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 
 	if (DISPLAY_VER(dev_priv) >= 4) {
 		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
-		i915_reg_t reg = PIPECONF(cpu_transcoder);
 
 		/* Wait for the Pipe State to go off */
-		if (intel_de_wait_for_clear(dev_priv, reg,
-					    I965_PIPECONF_ACTIVE, 100))
-			drm_WARN(&dev_priv->drm, 1,
-				 "pipe_off wait timed out\n");
+		if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder),
+					    PIPECONF_STATE_ENABLE, 100))
+			drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
 	} else {
 		intel_wait_for_pipe_scanline_stopped(crtc);
 	}
@@ -3338,13 +3336,13 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
 
 		switch (crtc_state->pipe_bpp) {
 		case 18:
-			pipeconf |= PIPECONF_6BPC;
+			pipeconf |= PIPECONF_BPC_6;
 			break;
 		case 24:
-			pipeconf |= PIPECONF_8BPC;
+			pipeconf |= PIPECONF_BPC_8;
 			break;
 		case 30:
-			pipeconf |= PIPECONF_10BPC;
+			pipeconf |= PIPECONF_BPC_10;
 			break;
 		default:
 			/* Case prevented by intel_choose_pipe_bpp_dither. */
@@ -3359,7 +3357,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
 		else
 			pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
 	} else {
-		pipeconf |= PIPECONF_PROGRESSIVE;
+		pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE;
 	}
 
 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
@@ -3537,16 +3535,17 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 	if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
 	    IS_CHERRYVIEW(dev_priv)) {
 		switch (tmp & PIPECONF_BPC_MASK) {
-		case PIPECONF_6BPC:
+		case PIPECONF_BPC_6:
 			pipe_config->pipe_bpp = 18;
 			break;
-		case PIPECONF_8BPC:
+		case PIPECONF_BPC_8:
 			pipe_config->pipe_bpp = 24;
 			break;
-		case PIPECONF_10BPC:
+		case PIPECONF_BPC_10:
 			pipe_config->pipe_bpp = 30;
 			break;
 		default:
+			MISSING_CASE(tmp);
 			break;
 		}
 	}
@@ -3555,8 +3554,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
 		pipe_config->limited_color_range = true;
 
-	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
-		PIPECONF_GAMMA_MODE_SHIFT;
+	pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp);
 
 	if (IS_CHERRYVIEW(dev_priv))
 		pipe_config->cgm_mode = intel_de_read(dev_priv,
@@ -3643,16 +3641,16 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
 
 	switch (crtc_state->pipe_bpp) {
 	case 18:
-		val |= PIPECONF_6BPC;
+		val |= PIPECONF_BPC_6;
 		break;
 	case 24:
-		val |= PIPECONF_8BPC;
+		val |= PIPECONF_BPC_8;
 		break;
 	case 30:
-		val |= PIPECONF_10BPC;
+		val |= PIPECONF_BPC_10;
 		break;
 	case 36:
-		val |= PIPECONF_12BPC;
+		val |= PIPECONF_BPC_12;
 		break;
 	default:
 		/* Case prevented by intel_choose_pipe_bpp_dither. */
@@ -3660,12 +3658,12 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
 	}
 
 	if (crtc_state->dither)
-		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
+		val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
 
 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
-		val |= PIPECONF_INTERLACED_ILK;
+		val |= PIPECONF_INTERLACE_IF_ID_ILK;
 	else
-		val |= PIPECONF_PROGRESSIVE;
+		val |= PIPECONF_INTERLACE_PF_PD_ILK;
 
 	/*
 	 * This would end up with an odd purple hue over
@@ -3697,12 +3695,12 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
 	u32 val = 0;
 
 	if (IS_HASWELL(dev_priv) && crtc_state->dither)
-		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
+		val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
 
 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
-		val |= PIPECONF_INTERLACED_ILK;
+		val |= PIPECONF_INTERLACE_IF_ID_ILK;
 	else
-		val |= PIPECONF_PROGRESSIVE;
+		val |= PIPECONF_INTERLACE_PF_PD_ILK;
 
 	if (IS_HASWELL(dev_priv) &&
 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
@@ -3996,16 +3994,16 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
 		goto out;
 
 	switch (tmp & PIPECONF_BPC_MASK) {
-	case PIPECONF_6BPC:
+	case PIPECONF_BPC_6:
 		pipe_config->pipe_bpp = 18;
 		break;
-	case PIPECONF_8BPC:
+	case PIPECONF_BPC_8:
 		pipe_config->pipe_bpp = 24;
 		break;
-	case PIPECONF_10BPC:
+	case PIPECONF_BPC_10:
 		pipe_config->pipe_bpp = 30;
 		break;
-	case PIPECONF_12BPC:
+	case PIPECONF_BPC_12:
 		pipe_config->pipe_bpp = 36;
 		break;
 	default:
@@ -4025,8 +4023,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
 		break;
 	}
 
-	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
-		PIPECONF_GAMMA_MODE_SHIFT;
+	pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);
 
 	pipe_config->csc_mode = intel_de_read(dev_priv,
 					      PIPE_CSC_MODE(crtc->pipe));
@@ -9990,8 +9987,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 		udelay(150); /* wait for warmup */
 	}
 
-	intel_de_write(dev_priv, PIPECONF(pipe),
-		       PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
+	intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE);
 	intel_de_posting_read(dev_priv, PIPECONF(pipe));
 
 	intel_wait_for_pipe_scanline_moving(crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index a55c4bfacd0d..81ab761251ae 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -157,13 +157,13 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 		 */
 		val &= ~PIPECONF_BPC_MASK;
 		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
-			val |= PIPECONF_8BPC;
+			val |= PIPECONF_BPC_8;
 		else
 			val |= pipeconf_val & PIPECONF_BPC_MASK;
 	}
 
 	val &= ~TRANS_INTERLACE_MASK;
-	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
+	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) {
 		if (HAS_PCH_IBX(dev_priv) &&
 		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
 			val |= TRANS_LEGACY_INTERLACED_ILK;
@@ -422,8 +422,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	val = TRANS_ENABLE;
 	pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
 
-	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
-	    PIPECONF_INTERLACED_ILK)
+	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK)
 		val |= TRANS_INTERLACED;
 	else
 		val |= TRANS_PROGRESSIVE;
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 034c060f89d4..b3f47b9944d6 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -184,7 +184,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 
 		for_each_pipe(dev_priv, pipe) {
 			vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
-				~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);
+				~(PIPECONF_ENABLE | PIPECONF_STATE_ENABLE);
 			vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
 			vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
 			vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
@@ -245,7 +245,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		 *   setup_virtual_dp_monitor.
 		 */
 		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
-		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE;
+		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_STATE_ENABLE;
 
 		/*
 		 * Golden M/N are calculated based on:
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index cde0a477fb49..a224158303b6 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -701,11 +701,11 @@ static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 	data = vgpu_vreg(vgpu, offset);
 
 	if (data & PIPECONF_ENABLE) {
-		vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
+		vgpu_vreg(vgpu, offset) |= PIPECONF_STATE_ENABLE;
 		vgpu_update_refresh_rate(vgpu);
 		vgpu_update_vblank_emulation(vgpu, true);
 	} else {
-		vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
+		vgpu_vreg(vgpu, offset) &= ~PIPECONF_STATE_ENABLE;
 		vgpu_update_vblank_emulation(vgpu, false);
 	}
 	return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b227dabb10c..d2d5b2fa2a4a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6168,62 +6168,58 @@ enum {
 #define   PIPEDSL_CURR_FIELD	REG_BIT(31) /* ctg+ */
 #define   PIPEDSL_LINE_MASK	REG_GENMASK(19, 0)
 #define _PIPEACONF		0x70008
-#define   PIPECONF_ENABLE	(1 << 31)
-#define   PIPECONF_DISABLE	0
-#define   PIPECONF_DOUBLE_WIDE	(1 << 30)
-#define   I965_PIPECONF_ACTIVE	(1 << 30)
-#define   PIPECONF_DSI_PLL_LOCKED	(1 << 29) /* vlv & pipe A only */
-#define   PIPECONF_FRAME_START_DELAY_MASK	(3 << 27) /* pre-hsw */
-#define   PIPECONF_FRAME_START_DELAY(x)		((x) << 27) /* pre-hsw: 0-3 */
-#define   PIPECONF_SINGLE_WIDE	0
-#define   PIPECONF_PIPE_UNLOCKED 0
-#define   PIPECONF_PIPE_LOCKED	(1 << 25)
-#define   PIPECONF_FORCE_BORDER	(1 << 25)
-#define   PIPECONF_GAMMA_MODE_MASK_I9XX	(1 << 24) /* gmch */
-#define   PIPECONF_GAMMA_MODE_MASK_ILK	(3 << 24) /* ilk-ivb */
-#define   PIPECONF_GAMMA_MODE_8BIT	(0 << 24) /* gmch,ilk-ivb */
-#define   PIPECONF_GAMMA_MODE_10BIT	(1 << 24) /* gmch,ilk-ivb */
-#define   PIPECONF_GAMMA_MODE_12BIT	(2 << 24) /* ilk-ivb */
-#define   PIPECONF_GAMMA_MODE_SPLIT	(3 << 24) /* ivb */
-#define   PIPECONF_GAMMA_MODE(x)	((x) << 24) /* pass in GAMMA_MODE_MODE_* */
-#define   PIPECONF_GAMMA_MODE_SHIFT	24
-#define   PIPECONF_INTERLACE_MASK	(7 << 21)
-#define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
-/* Note that pre-gen3 does not support interlaced display directly. Panel
- * fitting must be disabled on pre-ilk for interlaced. */
-#define   PIPECONF_PROGRESSIVE			(0 << 21)
-#define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
-#define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
-#define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
-#define   PIPECONF_INTERLACE_FIELD_0_ONLY	(7 << 21) /* gen3 only */
-/* Ironlake and later have a complete new set of values for interlaced. PFIT
- * means panel fitter required, PF means progressive fetch, DBL means power
- * saving pixel doubling. */
-#define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
-#define   PIPECONF_INTERLACED_ILK		(3 << 21)
-#define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
-#define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
-#define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)
-#define   PIPECONF_EDP_RR_MODE_SWITCH		(1 << 20)
-#define   PIPECONF_CXSR_DOWNCLOCK	(1 << 16)
-#define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
-#define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
-#define   PIPECONF_OUTPUT_COLORSPACE_MASK	(3 << 11) /* ilk-ivb */
-#define   PIPECONF_OUTPUT_COLORSPACE_RGB	(0 << 11) /* ilk-ivb */
-#define   PIPECONF_OUTPUT_COLORSPACE_YUV601	(1 << 11) /* ilk-ivb */
-#define   PIPECONF_OUTPUT_COLORSPACE_YUV709	(2 << 11) /* ilk-ivb */
-#define   PIPECONF_OUTPUT_COLORSPACE_YUV_HSW	(1 << 11) /* hsw only */
-#define   PIPECONF_BPC_MASK	(0x7 << 5)
-#define   PIPECONF_8BPC		(0 << 5)
-#define   PIPECONF_10BPC	(1 << 5)
-#define   PIPECONF_6BPC		(2 << 5)
-#define   PIPECONF_12BPC	(3 << 5)
-#define   PIPECONF_DITHER_EN	(1 << 4)
-#define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
-#define   PIPECONF_DITHER_TYPE_SP (0 << 2)
-#define   PIPECONF_DITHER_TYPE_ST1 (1 << 2)
-#define   PIPECONF_DITHER_TYPE_ST2 (2 << 2)
-#define   PIPECONF_DITHER_TYPE_TEMP (3 << 2)
+#define   PIPECONF_ENABLE			REG_BIT(31)
+#define   PIPECONF_DOUBLE_WIDE			REG_BIT(30) /* pre-i965 */
+#define   PIPECONF_STATE_ENABLE			REG_BIT(30) /* i965+ */
+#define   PIPECONF_DSI_PLL_LOCKED		REG_BIT(29) /* vlv & pipe A only */
+#define   PIPECONF_FRAME_START_DELAY_MASK	REG_GENMASK(28, 27) /* pre-hsw */
+#define   PIPECONF_FRAME_START_DELAY(x)		REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
+#define   PIPECONF_PIPE_LOCKED			REG_BIT(25)
+#define   PIPECONF_FORCE_BORDER			REG_BIT(25)
+#define   PIPECONF_GAMMA_MODE_MASK_I9XX		REG_BIT(24) /* gmch */
+#define   PIPECONF_GAMMA_MODE_MASK_ILK		REG_GENMASK(25, 24) /* ilk-ivb */
+#define   PIPECONF_GAMMA_MODE_8BIT		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0)
+#define   PIPECONF_GAMMA_MODE_10BIT		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1)
+#define   PIPECONF_GAMMA_MODE_12BIT		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
+#define   PIPECONF_GAMMA_MODE_SPLIT		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
+#define   PIPECONF_GAMMA_MODE(x)		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
+#define   PIPECONF_INTERLACE_MASK		REG_GENMASK(23, 21) /* gen3+ */
+#define   PIPECONF_INTERLACE_PROGRESSIVE	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0)
+#define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */
+#define   PIPECONF_INTERLACE_W_SYNC_SHIFT	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */
+#define   PIPECONF_INTERLACE_W_FIELD_INDICATION	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6)
+#define   PIPECONF_INTERLACE_FIELD_0_ONLY	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */
+/*
+ * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
+ * DBL=power saving pixel doubling, PF-ID* requires panel fitter
+ */
+#define   PIPECONF_INTERLACE_MASK_ILK		REG_GENMASK(23, 21) /* ilk+ */
+#define   PIPECONF_INTERLACE_MASK_HSW		REG_GENMASK(22, 21) /* hsw+ */
+#define   PIPECONF_INTERLACE_PF_PD_ILK		REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0)
+#define   PIPECONF_INTERLACE_PF_ID_ILK		REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1)
+#define   PIPECONF_INTERLACE_IF_ID_ILK		REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3)
+#define   PIPECONF_INTERLACE_IF_ID_DBL_ILK	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
+#define   PIPECONF_INTERLACE_PF_ID_DBL_ILK	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
+#define   PIPECONF_EDP_RR_MODE_SWITCH		REG_BIT(20)
+#define   PIPECONF_CXSR_DOWNCLOCK		REG_BIT(16)
+#define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	REG_BIT(14)
+#define   PIPECONF_COLOR_RANGE_SELECT		REG_BIT(13)
+#define   PIPECONF_OUTPUT_COLORSPACE_MASK	REG_GENMASK(12, 11) /* ilk-ivb */
+#define   PIPECONF_OUTPUT_COLORSPACE_RGB	REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
+#define   PIPECONF_OUTPUT_COLORSPACE_YUV601	REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
+#define   PIPECONF_OUTPUT_COLORSPACE_YUV709	REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
+#define   PIPECONF_OUTPUT_COLORSPACE_YUV_HSW	REG_BIT(11) /* hsw only */
+#define   PIPECONF_BPC_MASK			REG_GENMASK(7, 5) /* ctg-ivb */
+#define   PIPECONF_BPC_8			REG_FIELD_PREP(PIPECONF_BPC_MASK, 0)
+#define   PIPECONF_BPC_10			REG_FIELD_PREP(PIPECONF_BPC_MASK, 1)
+#define   PIPECONF_BPC_6			REG_FIELD_PREP(PIPECONF_BPC_MASK, 2)
+#define   PIPECONF_BPC_12			REG_FIELD_PREP(PIPECONF_BPC_MASK, 3)
+#define   PIPECONF_DITHER_EN			REG_BIT(4)
+#define   PIPECONF_DITHER_TYPE_MASK		REG_GENMASK(3, 2)
+#define   PIPECONF_DITHER_TYPE_SP		REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0)
+#define   PIPECONF_DITHER_TYPE_ST1		REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1)
+#define   PIPECONF_DITHER_TYPE_ST2		REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2)
+#define   PIPECONF_DITHER_TYPE_TEMP		REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3)
 #define _PIPEASTAT		0x70024
 #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL << 31)
 #define   SPRITE1_FLIP_DONE_INT_EN_VLV		(1UL << 30)
-- 
2.32.0

[Intel-gfx] [PATCH 5/9] drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit defines

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use REG_BIT & co. for PCH_TRANSCONF/TRANS_DP_CTL bits, and
adjust the naming a some bits to be more consistent.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../gpu/drm/i915/display/intel_pch_display.c  | 13 +++--
 drivers/gpu/drm/i915/i915_reg.h               | 58 +++++++++----------
 2 files changed, 33 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 81ab761251ae..155c2d19a6bb 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -166,11 +166,11 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) {
 		if (HAS_PCH_IBX(dev_priv) &&
 		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
-			val |= TRANS_LEGACY_INTERLACED_ILK;
+			val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
 		else
-			val |= TRANS_INTERLACED;
+			val |= TRANS_INTERLACE_INTERLACED;
 	} else {
-		val |= TRANS_PROGRESSIVE;
+		val |= TRANS_INTERLACE_PROGRESSIVE;
 	}
 
 	intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
@@ -279,7 +279,8 @@ void ilk_pch_enable(struct intel_atomic_state *state,
 
 		temp = intel_de_read(dev_priv, reg);
 		temp &= ~(TRANS_DP_PORT_SEL_MASK |
-			  TRANS_DP_SYNC_MASK |
+			  TRANS_DP_VSYNC_ACTIVE_HIGH |
+			  TRANS_DP_HSYNC_ACTIVE_HIGH |
 			  TRANS_DP_BPC_MASK);
 		temp |= TRANS_DP_OUTPUT_ENABLE;
 		temp |= bpc << 9; /* same format but at 11:9 */
@@ -423,9 +424,9 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
 
 	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK)
-		val |= TRANS_INTERLACED;
+		val |= TRANS_INTERLACE_INTERLACED;
 	else
-		val |= TRANS_PROGRESSIVE;
+		val |= TRANS_INTERLACE_PROGRESSIVE;
 
 	intel_de_write(dev_priv, LPT_TRANSCONF, val);
 	if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d2d5b2fa2a4a..eea009e76e15 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8994,22 +8994,19 @@ enum {
 #define _PCH_TRANSBCONF              0xf1008
 #define PCH_TRANSCONF(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
 #define LPT_TRANSCONF		PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
-#define  TRANS_DISABLE          (0 << 31)
-#define  TRANS_ENABLE           (1 << 31)
-#define  TRANS_STATE_MASK       (1 << 30)
-#define  TRANS_STATE_DISABLE    (0 << 30)
-#define  TRANS_STATE_ENABLE     (1 << 30)
-#define  TRANS_FRAME_START_DELAY_MASK	(3 << 27) /* ibx */
-#define  TRANS_FRAME_START_DELAY(x)	((x) << 27) /* ibx: 0-3 */
-#define  TRANS_INTERLACE_MASK   (7 << 21)
-#define  TRANS_PROGRESSIVE      (0 << 21)
-#define  TRANS_INTERLACED       (3 << 21)
-#define  TRANS_LEGACY_INTERLACED_ILK (2 << 21)
-#define  TRANS_8BPC             (0 << 5)
-#define  TRANS_10BPC            (1 << 5)
-#define  TRANS_6BPC             (2 << 5)
-#define  TRANS_12BPC            (3 << 5)
-
+#define  TRANS_ENABLE			REG_BIT(31)
+#define  TRANS_STATE_ENABLE		REG_BIT(30)
+#define  TRANS_FRAME_START_DELAY_MASK	REG_GENMASK(28, 27) /* ibx */
+#define  TRANS_FRAME_START_DELAY(x)	REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
+#define  TRANS_INTERLACE_MASK		REG_GENMASK(23, 21)
+#define  TRANS_INTERLACE_PROGRESSIVE	REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
+#define  TRANS_INTERLACE_LEGACY_VSYNC_IBX	REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
+#define  TRANS_INTERLACE_INTERLACED	REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
+#define  TRANS_BPC_MASK			REG_GENMASK(7, 5) /* ibx */
+#define  TRANS_BPC_8			REG_FIELD_PREP(TRANS_BPC_MASK, 0)
+#define  TRANS_BPC_10			REG_FIELD_PREP(TRANS_BPC_MASK, 1)
+#define  TRANS_BPC_6			REG_FIELD_PREP(TRANS_BPC_MASK, 2)
+#define  TRANS_BPC_12			REG_FIELD_PREP(TRANS_BPC_MASK, 3)
 #define _TRANSA_CHICKEN1	 0xf0060
 #define _TRANSB_CHICKEN1	 0xf1060
 #define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
@@ -9219,22 +9216,19 @@ enum {
 #define _TRANS_DP_CTL_B		0xe1300
 #define _TRANS_DP_CTL_C		0xe2300
 #define TRANS_DP_CTL(pipe)	_MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
-#define  TRANS_DP_OUTPUT_ENABLE	(1 << 31)
-#define  TRANS_DP_PORT_SEL_MASK		(3 << 29)
-#define  TRANS_DP_PORT_SEL_NONE		(3 << 29)
-#define  TRANS_DP_PORT_SEL(port)	(((port) - PORT_B) << 29)
-#define  TRANS_DP_AUDIO_ONLY	(1 << 26)
-#define  TRANS_DP_ENH_FRAMING	(1 << 18)
-#define  TRANS_DP_8BPC		(0 << 9)
-#define  TRANS_DP_10BPC		(1 << 9)
-#define  TRANS_DP_6BPC		(2 << 9)
-#define  TRANS_DP_12BPC		(3 << 9)
-#define  TRANS_DP_BPC_MASK	(3 << 9)
-#define  TRANS_DP_VSYNC_ACTIVE_HIGH	(1 << 4)
-#define  TRANS_DP_VSYNC_ACTIVE_LOW	0
-#define  TRANS_DP_HSYNC_ACTIVE_HIGH	(1 << 3)
-#define  TRANS_DP_HSYNC_ACTIVE_LOW	0
-#define  TRANS_DP_SYNC_MASK	(3 << 3)
+#define  TRANS_DP_OUTPUT_ENABLE		REG_BIT(31)
+#define  TRANS_DP_PORT_SEL_MASK		REG_GENMASK(30, 29)
+#define  TRANS_DP_PORT_SEL_NONE		REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
+#define  TRANS_DP_PORT_SEL(port)	REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
+#define  TRANS_DP_AUDIO_ONLY		REG_BIT(26)
+#define  TRANS_DP_ENH_FRAMING		REG_BIT(18)
+#define  TRANS_DP_BPC_MASK		REG_GENMASK(10, 9)
+#define  TRANS_DP_BPC_8			REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
+#define  TRANS_DP_BPC_10		REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
+#define  TRANS_DP_BPC_6			REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
+#define  TRANS_DP_BPC_12		REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
+#define  TRANS_DP_VSYNC_ACTIVE_HIGH	REG_BIT(4)
+#define  TRANS_DP_HSYNC_ACTIVE_HIGH	REG_BIT(3)
 
 #define _TRANS_DP2_CTL_A			0x600a0
 #define _TRANS_DP2_CTL_B			0x610a0
-- 
2.32.0

[Intel-gfx] [PATCH 6/9] drm/i915: Clean up PIPESRC defines

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use REG_GENMASK() & co. when dealing with PIPESRC.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_plane.c    | 4 ++--
 drivers/gpu/drm/i915/display/intel_display.c | 7 ++++---
 drivers/gpu/drm/i915/i915_reg.h              | 4 ++++
 3 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 2194f74101ae..f586e39cb378 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -1048,8 +1048,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 	plane_config->base = base;
 
 	val = intel_de_read(dev_priv, PIPESRC(pipe));
-	fb->width = ((val >> 16) & 0xfff) + 1;
-	fb->height = ((val >> 0) & 0xfff) + 1;
+	fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
+	fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
 
 	val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
 	fb->pitches[0] = val & 0xffffffc0;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4e29032b29d6..e1959a17805c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3236,7 +3236,8 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
 	 * always be the user's requested size.
 	 */
 	intel_de_write(dev_priv, PIPESRC(pipe),
-		       ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
+		       PIPESRC_WIDTH(crtc_state->pipe_src_w - 1) |
+		       PIPESRC_HEIGHT(crtc_state->pipe_src_h - 1));
 }
 
 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
@@ -3307,8 +3308,8 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
 	u32 tmp;
 
 	tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
-	pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
-	pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
+	pipe_config->pipe_src_w = REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1;
+	pipe_config->pipe_src_h = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1;
 }
 
 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eea009e76e15..211e2b415e50 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4476,6 +4476,10 @@ enum {
 #define _VSYNC_A	0x60014
 #define _EXITLINE_A	0x60018
 #define _PIPEASRC	0x6001c
+#define   PIPESRC_WIDTH_MASK	REG_GENMASK(31, 16)
+#define   PIPESRC_WIDTH(w)	REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
+#define   PIPESRC_HEIGHT_MASK	REG_GENMASK(15, 0)
+#define   PIPESRC_HEIGHT(h)	REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
 #define _BCLRPAT_A	0x60020
 #define _VSYNCSHIFT_A	0x60028
 #define _PIPE_MULT_A	0x6002c
-- 
2.32.0

[Intel-gfx] [PATCH 7/9] drm/i915: Clean up CRC register defines

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use REG_BIT() & co. for the CRC registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 77 ++++++++++++++++++---------------
 1 file changed, 41 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 211e2b415e50..6ba5ab277675 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4393,47 +4393,52 @@ enum {
 
 /* Pipe A CRC regs */
 #define _PIPE_CRC_CTL_A			0x60050
-#define   PIPE_CRC_ENABLE		(1 << 31)
+#define   PIPE_CRC_ENABLE		REG_BIT(31)
 /* skl+ source selection */
-#define   PIPE_CRC_SOURCE_PLANE_1_SKL	(0 << 28)
-#define   PIPE_CRC_SOURCE_PLANE_2_SKL	(2 << 28)
-#define   PIPE_CRC_SOURCE_DMUX_SKL	(4 << 28)
-#define   PIPE_CRC_SOURCE_PLANE_3_SKL	(6 << 28)
-#define   PIPE_CRC_SOURCE_PLANE_4_SKL	(7 << 28)
-#define   PIPE_CRC_SOURCE_PLANE_5_SKL	(5 << 28)
-#define   PIPE_CRC_SOURCE_PLANE_6_SKL	(3 << 28)
-#define   PIPE_CRC_SOURCE_PLANE_7_SKL	(1 << 28)
+#define   PIPE_CRC_SOURCE_MASK_SKL	REG_GENMASK(30, 28)
+#define   PIPE_CRC_SOURCE_PLANE_1_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)
+#define   PIPE_CRC_SOURCE_PLANE_2_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2)
+#define   PIPE_CRC_SOURCE_DMUX_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4)
+#define   PIPE_CRC_SOURCE_PLANE_3_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6)
+#define   PIPE_CRC_SOURCE_PLANE_4_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7)
+#define   PIPE_CRC_SOURCE_PLANE_5_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5)
+#define   PIPE_CRC_SOURCE_PLANE_6_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3)
+#define   PIPE_CRC_SOURCE_PLANE_7_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1)
 /* ivb+ source selection */
-#define   PIPE_CRC_SOURCE_PRIMARY_IVB	(0 << 29)
-#define   PIPE_CRC_SOURCE_SPRITE_IVB	(1 << 29)
-#define   PIPE_CRC_SOURCE_PF_IVB	(2 << 29)
+#define   PIPE_CRC_SOURCE_MASK_IVB	REG_GENMASK(30, 29)
+#define   PIPE_CRC_SOURCE_PRIMARY_IVB	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)
+#define   PIPE_CRC_SOURCE_SPRITE_IVB	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1)
+#define   PIPE_CRC_SOURCE_PF_IVB	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2)
 /* ilk+ source selection */
-#define   PIPE_CRC_SOURCE_PRIMARY_ILK	(0 << 28)
-#define   PIPE_CRC_SOURCE_SPRITE_ILK	(1 << 28)
-#define   PIPE_CRC_SOURCE_PIPE_ILK	(2 << 28)
-/* embedded DP port on the north display block, reserved on ivb */
-#define   PIPE_CRC_SOURCE_PORT_A_ILK	(4 << 28)
-#define   PIPE_CRC_SOURCE_FDI_ILK	(5 << 28) /* reserved on ivb */
+#define   PIPE_CRC_SOURCE_MASK_ILK	REG_GENMASK(30, 28)
+#define   PIPE_CRC_SOURCE_PRIMARY_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)
+#define   PIPE_CRC_SOURCE_SPRITE_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1)
+#define   PIPE_CRC_SOURCE_PIPE_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2)
+/* embedded DP port on the north display block */
+#define   PIPE_CRC_SOURCE_PORT_A_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4)
+#define   PIPE_CRC_SOURCE_FDI_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5)
 /* vlv source selection */
-#define   PIPE_CRC_SOURCE_PIPE_VLV	(0 << 27)
-#define   PIPE_CRC_SOURCE_HDMIB_VLV	(1 << 27)
-#define   PIPE_CRC_SOURCE_HDMIC_VLV	(2 << 27)
+#define   PIPE_CRC_SOURCE_MASK_VLV	REG_GENMASK(30, 27)
+#define   PIPE_CRC_SOURCE_PIPE_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)
+#define   PIPE_CRC_SOURCE_HDMIB_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1)
+#define   PIPE_CRC_SOURCE_HDMIC_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2)
 /* with DP port the pipe source is invalid */
-#define   PIPE_CRC_SOURCE_DP_D_VLV	(3 << 27)
-#define   PIPE_CRC_SOURCE_DP_B_VLV	(6 << 27)
-#define   PIPE_CRC_SOURCE_DP_C_VLV	(7 << 27)
+#define   PIPE_CRC_SOURCE_DP_D_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3)
+#define   PIPE_CRC_SOURCE_DP_B_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6)
+#define   PIPE_CRC_SOURCE_DP_C_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7)
 /* gen3+ source selection */
-#define   PIPE_CRC_SOURCE_PIPE_I9XX	(0 << 28)
-#define   PIPE_CRC_SOURCE_SDVOB_I9XX	(1 << 28)
-#define   PIPE_CRC_SOURCE_SDVOC_I9XX	(2 << 28)
+#define   PIPE_CRC_SOURCE_MASK_I9XX	REG_GENMASK(30, 28)
+#define   PIPE_CRC_SOURCE_PIPE_I9XX	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)
+#define   PIPE_CRC_SOURCE_SDVOB_I9XX	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1)
+#define   PIPE_CRC_SOURCE_SDVOC_I9XX	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2)
 /* with DP/TV port the pipe source is invalid */
-#define   PIPE_CRC_SOURCE_DP_D_G4X	(3 << 28)
-#define   PIPE_CRC_SOURCE_TV_PRE	(4 << 28)
-#define   PIPE_CRC_SOURCE_TV_POST	(5 << 28)
-#define   PIPE_CRC_SOURCE_DP_B_G4X	(6 << 28)
-#define   PIPE_CRC_SOURCE_DP_C_G4X	(7 << 28)
+#define   PIPE_CRC_SOURCE_DP_D_G4X	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3)
+#define   PIPE_CRC_SOURCE_TV_PRE	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4)
+#define   PIPE_CRC_SOURCE_TV_POST	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5)
+#define   PIPE_CRC_SOURCE_DP_B_G4X	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6)
+#define   PIPE_CRC_SOURCE_DP_C_G4X	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7)
 /* gen2 doesn't have source selection bits */
-#define   PIPE_CRC_INCLUDE_BORDER_I8XX	(1 << 30)
+#define   PIPE_CRC_INCLUDE_BORDER_I8XX	REG_BIT(30)
 
 #define _PIPE_CRC_RES_1_A_IVB		0x60064
 #define _PIPE_CRC_RES_2_A_IVB		0x60068
@@ -5087,9 +5092,9 @@ enum {
 #define PORT_DFT2_G4X		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
 #define   DC_BALANCE_RESET_VLV			(1 << 31)
 #define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
-#define   PIPE_C_SCRAMBLE_RESET			(1 << 14) /* chv */
-#define   PIPE_B_SCRAMBLE_RESET			(1 << 1)
-#define   PIPE_A_SCRAMBLE_RESET			(1 << 0)
+#define   PIPE_C_SCRAMBLE_RESET			REG_BIT(14) /* chv */
+#define   PIPE_B_SCRAMBLE_RESET			REG_BIT(1)
+#define   PIPE_A_SCRAMBLE_RESET			REG_BIT(0)
 
 /* Gen 3 SDVO bits: */
 #define   SDVO_ENABLE				(1 << 31)
-- 
2.32.0

[Intel-gfx] [PATCH 8/9] drm/i915: Clean up DPINVGTT/VLV_DPFLIPSTAT bits

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use REG_BIT() & co. for DPINVTT/VLV_DPFLIPSTAT bits.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c |  2 +-
 drivers/gpu/drm/i915/i915_reg.h | 94 ++++++++++++++++-----------------
 2 files changed, 48 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index eb8c92324aee..1021f7ae0dda 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3013,7 +3013,7 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 	if (IS_CHERRYVIEW(dev_priv))
 		intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
 	else
-		intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
+		intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_VLV);
 
 	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
 	intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6ba5ab277675..0ceb88828d93 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6358,55 +6358,55 @@ enum {
 #define   PIPE_STATUS_PORT_UNDERRUN_XELPD		REG_BIT(26)
 
 #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
-#define   PIPEB_LINE_COMPARE_INT_EN		(1 << 29)
-#define   PIPEB_HLINE_INT_EN			(1 << 28)
-#define   PIPEB_VBLANK_INT_EN			(1 << 27)
-#define   SPRITED_FLIP_DONE_INT_EN		(1 << 26)
-#define   SPRITEC_FLIP_DONE_INT_EN		(1 << 25)
-#define   PLANEB_FLIP_DONE_INT_EN		(1 << 24)
-#define   PIPE_PSR_INT_EN			(1 << 22)
-#define   PIPEA_LINE_COMPARE_INT_EN		(1 << 21)
-#define   PIPEA_HLINE_INT_EN			(1 << 20)
-#define   PIPEA_VBLANK_INT_EN			(1 << 19)
-#define   SPRITEB_FLIP_DONE_INT_EN		(1 << 18)
-#define   SPRITEA_FLIP_DONE_INT_EN		(1 << 17)
-#define   PLANEA_FLIPDONE_INT_EN		(1 << 16)
-#define   PIPEC_LINE_COMPARE_INT_EN		(1 << 13)
-#define   PIPEC_HLINE_INT_EN			(1 << 12)
-#define   PIPEC_VBLANK_INT_EN			(1 << 11)
-#define   SPRITEF_FLIPDONE_INT_EN		(1 << 10)
-#define   SPRITEE_FLIPDONE_INT_EN		(1 << 9)
-#define   PLANEC_FLIPDONE_INT_EN		(1 << 8)
+#define   PIPEB_LINE_COMPARE_INT_EN			REG_BIT(29)
+#define   PIPEB_HLINE_INT_EN			REG_BIT(28)
+#define   PIPEB_VBLANK_INT_EN			REG_BIT(27)
+#define   SPRITED_FLIP_DONE_INT_EN			REG_BIT(26)
+#define   SPRITEC_FLIP_DONE_INT_EN			REG_BIT(25)
+#define   PLANEB_FLIP_DONE_INT_EN			REG_BIT(24)
+#define   PIPE_PSR_INT_EN			REG_BIT(22)
+#define   PIPEA_LINE_COMPARE_INT_EN			REG_BIT(21)
+#define   PIPEA_HLINE_INT_EN			REG_BIT(20)
+#define   PIPEA_VBLANK_INT_EN			REG_BIT(19)
+#define   SPRITEB_FLIP_DONE_INT_EN			REG_BIT(18)
+#define   SPRITEA_FLIP_DONE_INT_EN			REG_BIT(17)
+#define   PLANEA_FLIPDONE_INT_EN			REG_BIT(16)
+#define   PIPEC_LINE_COMPARE_INT_EN			REG_BIT(13)
+#define   PIPEC_HLINE_INT_EN			REG_BIT(12)
+#define   PIPEC_VBLANK_INT_EN			REG_BIT(11)
+#define   SPRITEF_FLIPDONE_INT_EN			REG_BIT(10)
+#define   SPRITEE_FLIPDONE_INT_EN			REG_BIT(9)
+#define   PLANEC_FLIPDONE_INT_EN			REG_BIT(8)
 
 #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
-#define   SPRITEF_INVALID_GTT_INT_EN		(1 << 27)
-#define   SPRITEE_INVALID_GTT_INT_EN		(1 << 26)
-#define   PLANEC_INVALID_GTT_INT_EN		(1 << 25)
-#define   CURSORC_INVALID_GTT_INT_EN		(1 << 24)
-#define   CURSORB_INVALID_GTT_INT_EN		(1 << 23)
-#define   CURSORA_INVALID_GTT_INT_EN		(1 << 22)
-#define   SPRITED_INVALID_GTT_INT_EN		(1 << 21)
-#define   SPRITEC_INVALID_GTT_INT_EN		(1 << 20)
-#define   PLANEB_INVALID_GTT_INT_EN		(1 << 19)
-#define   SPRITEB_INVALID_GTT_INT_EN		(1 << 18)
-#define   SPRITEA_INVALID_GTT_INT_EN		(1 << 17)
-#define   PLANEA_INVALID_GTT_INT_EN		(1 << 16)
-#define   DPINVGTT_EN_MASK			0xff0000
-#define   DPINVGTT_EN_MASK_CHV			0xfff0000
-#define   SPRITEF_INVALID_GTT_STATUS		(1 << 11)
-#define   SPRITEE_INVALID_GTT_STATUS		(1 << 10)
-#define   PLANEC_INVALID_GTT_STATUS		(1 << 9)
-#define   CURSORC_INVALID_GTT_STATUS		(1 << 8)
-#define   CURSORB_INVALID_GTT_STATUS		(1 << 7)
-#define   CURSORA_INVALID_GTT_STATUS		(1 << 6)
-#define   SPRITED_INVALID_GTT_STATUS		(1 << 5)
-#define   SPRITEC_INVALID_GTT_STATUS		(1 << 4)
-#define   PLANEB_INVALID_GTT_STATUS		(1 << 3)
-#define   SPRITEB_INVALID_GTT_STATUS		(1 << 2)
-#define   SPRITEA_INVALID_GTT_STATUS		(1 << 1)
-#define   PLANEA_INVALID_GTT_STATUS		(1 << 0)
-#define   DPINVGTT_STATUS_MASK			0xff
-#define   DPINVGTT_STATUS_MASK_CHV		0xfff
+#define   DPINVGTT_EN_MASK_CHV				REG_GENMASK(27, 16)
+#define   DPINVGTT_EN_MASK_VLV				REG_GENMASK(23, 16)
+#define   SPRITEF_INVALID_GTT_INT_EN			REG_BIT(27)
+#define   SPRITEE_INVALID_GTT_INT_EN			REG_BIT(26)
+#define   PLANEC_INVALID_GTT_INT_EN			REG_BIT(25)
+#define   CURSORC_INVALID_GTT_INT_EN			REG_BIT(24)
+#define   CURSORB_INVALID_GTT_INT_EN			REG_BIT(23)
+#define   CURSORA_INVALID_GTT_INT_EN			REG_BIT(22)
+#define   SPRITED_INVALID_GTT_INT_EN			REG_BIT(21)
+#define   SPRITEC_INVALID_GTT_INT_EN			REG_BIT(20)
+#define   PLANEB_INVALID_GTT_INT_EN			REG_BIT(19)
+#define   SPRITEB_INVALID_GTT_INT_EN			REG_BIT(18)
+#define   SPRITEA_INVALID_GTT_INT_EN			REG_BIT(17)
+#define   PLANEA_INVALID_GTT_INT_EN			REG_BIT(16)
+#define   DPINVGTT_STATUS_MASK_CHV			REG_GENMASK(11, 0)
+#define   DPINVGTT_STATUS_MASK_VLV			REG_GENMASK(7, 0)
+#define   SPRITEF_INVALID_GTT_STATUS			REG_BIT(11)
+#define   SPRITEE_INVALID_GTT_STATUS			REG_BIT(10)
+#define   PLANEC_INVALID_GTT_STATUS			REG_BIT(9)
+#define   CURSORC_INVALID_GTT_STATUS			REG_BIT(8)
+#define   CURSORB_INVALID_GTT_STATUS			REG_BIT(7)
+#define   CURSORA_INVALID_GTT_STATUS			REG_BIT(6)
+#define   SPRITED_INVALID_GTT_STATUS			REG_BIT(5)
+#define   SPRITEC_INVALID_GTT_STATUS			REG_BIT(4)
+#define   PLANEB_INVALID_GTT_STATUS			REG_BIT(3)
+#define   SPRITEB_INVALID_GTT_STATUS			REG_BIT(2)
+#define   SPRITEA_INVALID_GTT_STATUS			REG_BIT(1)
+#define   PLANEA_INVALID_GTT_STATUS			REG_BIT(0)
 
 #define DSPARB			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
 #define   DSPARB_CSTART_MASK	(0x7f << 7)
-- 
2.32.0

[Intel-gfx] [PATCH 9/9] drm/i915: Clean up FPGA_DBG/CLAIM_ER bits

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use REG_BIT() & co. for FPGA_DBG/CLAIM_ER bits.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0ceb88828d93..a4d6bd380012 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2821,12 +2821,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define GEN12_AUX_ERR_DBG		_MMIO(0x43f4)
 
 #define FPGA_DBG		_MMIO(0x42300)
-#define   FPGA_DBG_RM_NOCLAIM	(1 << 31)
+#define   FPGA_DBG_RM_NOCLAIM	REG_BIT(31)
 
 #define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
-#define   CLAIM_ER_CLR		(1 << 31)
-#define   CLAIM_ER_OVERFLOW	(1 << 16)
-#define   CLAIM_ER_CTR_MASK	0xffff
+#define   CLAIM_ER_CLR		REG_BIT(31)
+#define   CLAIM_ER_OVERFLOW	REG_BIT(16)
+#define   CLAIM_ER_CTR_MASK	REG_GENMASK(15, 0)
 
 #define DERRMR		_MMIO(0x44050)
 /* Note that HBLANK events are reserved on bdw+ */
-- 
2.32.0

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Register define cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: Register define cleanups
URL   : https://patchwork.freedesktop.org/series/96868/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
07e09e2bbe21 drm/i915: Bump DSL linemask to 20 bits
d6e456b58dab drm/i915: Clean up PIPEMISC register defines
972a671d657e drm/i915: Clean up SKL_BOTTOM_COLOR defines
0a60b5b4e2d5 drm/i915: Clean up PIPECONF bit defines
-:347: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#347: FILE: drivers/gpu/drm/i915/i915_reg.h:6176:
+#define   PIPECONF_FRAME_START_DELAY(x)		REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */

-:354: WARNING:LONG_LINE_COMMENT: line length of 109 exceeds 100 columns
#354: FILE: drivers/gpu/drm/i915/i915_reg.h:6183:
+#define   PIPECONF_GAMMA_MODE_12BIT		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */

-:355: WARNING:LONG_LINE_COMMENT: line length of 105 exceeds 100 columns
#355: FILE: drivers/gpu/drm/i915/i915_reg.h:6184:
+#define   PIPECONF_GAMMA_MODE_SPLIT		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */

-:356: WARNING:LONG_LINE_COMMENT: line length of 129 exceeds 100 columns
#356: FILE: drivers/gpu/drm/i915/i915_reg.h:6185:
+#define   PIPECONF_GAMMA_MODE(x)		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */

-:359: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns
#359: FILE: drivers/gpu/drm/i915/i915_reg.h:6188:
+#define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */

-:360: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns
#360: FILE: drivers/gpu/drm/i915/i915_reg.h:6189:
+#define   PIPECONF_INTERLACE_W_SYNC_SHIFT	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */

-:362: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns
#362: FILE: drivers/gpu/drm/i915/i915_reg.h:6191:
+#define   PIPECONF_INTERLACE_FIELD_0_ONLY	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */

-:372: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns
#372: FILE: drivers/gpu/drm/i915/i915_reg.h:6201:
+#define   PIPECONF_INTERLACE_IF_ID_DBL_ILK	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */

-:373: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns
#373: FILE: drivers/gpu/drm/i915/i915_reg.h:6202:
+#define   PIPECONF_INTERLACE_PF_ID_DBL_ILK	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */

-:379: WARNING:LONG_LINE_COMMENT: line length of 112 exceeds 100 columns
#379: FILE: drivers/gpu/drm/i915/i915_reg.h:6208:
+#define   PIPECONF_OUTPUT_COLORSPACE_RGB	REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */

-:380: WARNING:LONG_LINE_COMMENT: line length of 112 exceeds 100 columns
#380: FILE: drivers/gpu/drm/i915/i915_reg.h:6209:
+#define   PIPECONF_OUTPUT_COLORSPACE_YUV601	REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */

-:381: WARNING:LONG_LINE_COMMENT: line length of 112 exceeds 100 columns
#381: FILE: drivers/gpu/drm/i915/i915_reg.h:6210:
+#define   PIPECONF_OUTPUT_COLORSPACE_YUV709	REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */

total: 0 errors, 12 warnings, 0 checks, 340 lines checked
0a96d6cd3a6a drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit defines
-:82: WARNING:LONG_LINE_COMMENT: line length of 104 exceeds 100 columns
#82: FILE: drivers/gpu/drm/i915/i915_reg.h:9000:
+#define  TRANS_FRAME_START_DELAY(x)	REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */

total: 0 errors, 1 warnings, 0 checks, 104 lines checked
9f255d46dcb8 drm/i915: Clean up PIPESRC defines
8a7681e19c01 drm/i915: Clean up CRC register defines
1b63beb57cdd drm/i915: Clean up DPINVGTT/VLV_DPFLIPSTAT bits
f89511a6ac52 drm/i915: Clean up FPGA_DBG/CLAIM_ER bits

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Register define cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: Register define cleanups
URL   : https://patchwork.freedesktop.org/series/96868/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active'
./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq'
./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Function parameter or member 'fbc' not described in 'intel_fbc_is_active'
./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active'
./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Function parameter or member 'fbc' not described in 'intel_fbc_handle_fifo_underrun_irq'
./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq'

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Register define cleanups

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3225 bytes --]

== Series Details ==

Series: drm/i915: Register define cleanups
URL   : https://patchwork.freedesktop.org/series/96868/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10877 -> Patchwork_21579
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/index.html

Participating hosts (30 -> 29)
------------------------------

  Additional (2): fi-skl-6700k2 fi-pnv-d510 
  Missing    (3): fi-bsw-cyan bat-dg1-6 bat-dg1-5 

Known issues
------------

  Here are the changes found in Patchwork_21579 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-gfx:
    - fi-skl-6700k2:      NOTRUN -> [SKIP][1] ([fdo#109271]) +28 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/fi-skl-6700k2/igt@amdgpu/amd_basic@cs-gfx.html

  * igt@gem_huc_copy@huc-copy:
    - fi-skl-6700k2:      NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/fi-skl-6700k2/igt@gem_huc_copy@huc-copy.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-skl-6700k2:      NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/fi-skl-6700k2/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-skl-6700k2:      NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#533])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/fi-skl-6700k2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
    - fi-pnv-d510:        NOTRUN -> [SKIP][5] ([fdo#109271]) +53 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/fi-pnv-d510/igt@prime_vgem@basic-userptr.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-------------

  * Linux: CI_DRM_10877 -> Patchwork_21579

  CI-20190529: 20190529
  CI_DRM_10877: 688d3ea17a90b4acf51de31ef08cd2b23799952e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6280: 246bfd31dba6bf184b26b170d91d72c90a54be6b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21579: f89511a6ac520ed572057ab4153692b6c59cb1d7 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f89511a6ac52 drm/i915: Clean up FPGA_DBG/CLAIM_ER bits
1b63beb57cdd drm/i915: Clean up DPINVGTT/VLV_DPFLIPSTAT bits
8a7681e19c01 drm/i915: Clean up CRC register defines
9f255d46dcb8 drm/i915: Clean up PIPESRC defines
0a96d6cd3a6a drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit defines
0a60b5b4e2d5 drm/i915: Clean up PIPECONF bit defines
972a671d657e drm/i915: Clean up SKL_BOTTOM_COLOR defines
d6e456b58dab drm/i915: Clean up PIPEMISC register defines
07e09e2bbe21 drm/i915: Bump DSL linemask to 20 bits

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/index.html

[-- Attachment #2: Type: text/html, Size: 4250 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Register define cleanups

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30256 bytes --]

== Series Details ==

Series: drm/i915: Register define cleanups
URL   : https://patchwork.freedesktop.org/series/96868/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10877_full -> Patchwork_21579_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_21579_full that come from known issues:

### CI changes ###

#### Issues hit ####

  * boot:
    - shard-glk:          ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [FAIL][50]) ([i915#4392])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk1/boot.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk1/boot.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk2/boot.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk2/boot.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk2/boot.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk3/boot.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk3/boot.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk3/boot.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk4/boot.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk4/boot.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk4/boot.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk5/boot.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk5/boot.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk5/boot.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk6/boot.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk6/boot.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk6/boot.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk7/boot.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk7/boot.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk7/boot.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk8/boot.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk8/boot.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk9/boot.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk9/boot.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk9/boot.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk2/boot.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk9/boot.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk9/boot.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk8/boot.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk8/boot.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk7/boot.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk7/boot.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk7/boot.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk6/boot.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk6/boot.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk1/boot.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk1/boot.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk1/boot.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk2/boot.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk2/boot.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk6/boot.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk6/boot.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk5/boot.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk5/boot.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk5/boot.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk4/boot.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk4/boot.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk3/boot.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk3/boot.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk2/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [PASS][51] -> [TIMEOUT][52] ([i915#2369] / [i915#3063] / [i915#3648])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-tglb5/igt@gem_eio@unwedge-stress.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-tglb3/igt@gem_eio@unwedge-stress.html
    - shard-iclb:         [PASS][53] -> [TIMEOUT][54] ([i915#2369] / [i915#2481] / [i915#3070])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-iclb3/igt@gem_eio@unwedge-stress.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-iclb2/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_capture@pi@vcs0:
    - shard-skl:          NOTRUN -> [INCOMPLETE][55] ([i915#2369])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl4/igt@gem_exec_capture@pi@vcs0.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-skl:          NOTRUN -> [FAIL][56] ([i915#2846])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl8/igt@gem_exec_fair@basic-deadline.html
    - shard-apl:          NOTRUN -> [FAIL][57] ([i915#2846])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl3/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-tglb:         [PASS][58] -> [FAIL][59] ([i915#2842]) +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-tglb1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-tglb8/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-kbl:          [PASS][60] -> [FAIL][61] ([i915#2842])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs0.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [PASS][62] -> [FAIL][63] ([i915#2849])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-tglb:         [PASS][64] -> [INCOMPLETE][65] ([i915#456]) +1 similar issue
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-tglb6/igt@gem_exec_suspend@basic-s3.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-tglb7/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_exec_whisper@basic-fds-forked:
    - shard-glk:          [PASS][66] -> [DMESG-WARN][67] ([i915#118])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk2/igt@gem_exec_whisper@basic-fds-forked.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk6/igt@gem_exec_whisper@basic-fds-forked.html

  * igt@gem_huc_copy@huc-copy:
    - shard-apl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2190])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl8/igt@gem_huc_copy@huc-copy.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-kbl:          NOTRUN -> [WARN][69] ([i915#2658])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl4/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_userptr_blits@input-checking:
    - shard-apl:          NOTRUN -> [DMESG-WARN][70] ([i915#3002]) +1 similar issue
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl4/igt@gem_userptr_blits@input-checking.html
    - shard-kbl:          NOTRUN -> [DMESG-WARN][71] ([i915#3002])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl1/igt@gem_userptr_blits@input-checking.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-apl:          NOTRUN -> [FAIL][72] ([i915#3318])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl4/igt@gem_userptr_blits@vma-merge.html
    - shard-kbl:          NOTRUN -> [FAIL][73] ([i915#3318])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl1/igt@gem_userptr_blits@vma-merge.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [PASS][74] -> [DMESG-WARN][75] ([i915#1436] / [i915#716])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk6/igt@gen9_exec_parse@allowed-all.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk2/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_module_load@reload:
    - shard-skl:          [PASS][76] -> [DMESG-WARN][77] ([i915#1982])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-skl9/igt@i915_module_load@reload.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl1/igt@i915_module_load@reload.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][78] ([i915#3743])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-apl:          NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#3777])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
    - shard-kbl:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#3886]) +4 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl4/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#3886]) +9 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl8/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#3886]) +5 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl8/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-edid-change-during-suspend:
    - shard-apl:          NOTRUN -> [SKIP][83] ([fdo#109271] / [fdo#111827]) +12 similar issues
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl3/igt@kms_chamelium@dp-edid-change-during-suspend.html

  * igt@kms_color_chamelium@pipe-d-ctm-green-to-red:
    - shard-kbl:          NOTRUN -> [SKIP][84] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl4/igt@kms_color_chamelium@pipe-d-ctm-green-to-red.html

  * igt@kms_color_chamelium@pipe-d-degamma:
    - shard-skl:          NOTRUN -> [SKIP][85] ([fdo#109271] / [fdo#111827]) +13 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl8/igt@kms_color_chamelium@pipe-d-degamma.html

  * igt@kms_content_protection@atomic:
    - shard-kbl:          NOTRUN -> [TIMEOUT][86] ([i915#1319])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl1/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@lic:
    - shard-apl:          NOTRUN -> [TIMEOUT][87] ([i915#1319]) +2 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl2/igt@kms_content_protection@lic.html

  * igt@kms_content_protection@uevent:
    - shard-kbl:          NOTRUN -> [FAIL][88] ([i915#2105])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl1/igt@kms_content_protection@uevent.html
    - shard-apl:          NOTRUN -> [FAIL][89] ([i915#2105])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl4/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen:
    - shard-glk:          [PASS][90] -> [FAIL][91] ([i915#3444])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk4/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk6/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-apl:          [PASS][92] -> [DMESG-WARN][93] ([i915#180])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-skl:          [PASS][94] -> [FAIL][95] ([i915#2346])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          [PASS][96] -> [FAIL][97] ([i915#2346] / [i915#533])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
    - shard-iclb:         [PASS][98] -> [FAIL][99] ([i915#2346])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-iclb2/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html

  * igt@kms_cursor_legacy@pipe-d-torture-bo:
    - shard-apl:          NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#533]) +1 similar issue
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl8/igt@kms_cursor_legacy@pipe-d-torture-bo.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-skl:          [PASS][101] -> [INCOMPLETE][102] ([i915#198])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-skl1/igt@kms_fbcon_fbt@psr-suspend.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl7/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1:
    - shard-glk:          [PASS][103] -> [FAIL][104] ([i915#2122])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk3/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk7/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
    - shard-skl:          [PASS][105] -> [FAIL][106] ([i915#2122])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl9/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
    - shard-iclb:         [PASS][107] -> [SKIP][108] ([i915#3701])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-iclb5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
    - shard-apl:          NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#2672])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html

  * igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt:
    - shard-skl:          NOTRUN -> [SKIP][110] ([fdo#109271]) +177 similar issues
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl9/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-apl:          NOTRUN -> [SKIP][111] ([fdo#109271]) +146 similar issues
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-kbl:          NOTRUN -> [SKIP][112] ([fdo#109271]) +55 similar issues
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-tglb:         [PASS][113] -> [INCOMPLETE][114] ([i915#2411] / [i915#456])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-tglb6/igt@kms_frontbuffer_tracking@psr-suspend.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-tglb7/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
    - shard-skl:          NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#533])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl9/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-skl:          NOTRUN -> [FAIL][116] ([fdo#108145] / [i915#265]) +1 similar issue
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [PASS][117] -> [FAIL][118] ([fdo#108145] / [i915#265])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
    - shard-kbl:          NOTRUN -> [FAIL][119] ([fdo#108145] / [i915#265])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
    - shard-apl:          NOTRUN -> [SKIP][120] ([fdo#109271] / [i915#658]) +4 similar issues
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
    - shard-kbl:          NOTRUN -> [SKIP][121] ([fdo#109271] / [i915#658])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-skl:          NOTRUN -> [SKIP][122] ([fdo#109271] / [i915#658]) +2 similar issues
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl2/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         [PASS][123] -> [SKIP][124] ([fdo#109441]) +3 similar issues
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-iclb2/igt@kms_psr@psr2_basic.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-iclb8/igt@kms_psr@psr2_basic.html

  * igt@kms_sysfs_edid_timing:
    - shard-skl:          NOTRUN -> [FAIL][125] ([IGT#2])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl8/igt@kms_sysfs_edid_timing.html

  * igt@kms_writeback@writeback-check-output:
    - shard-apl:          NOTRUN -> [SKIP][126] ([fdo#109271] / [i915#2437]) +1 similar issue
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl4/igt@kms_writeback@writeback-check-output.html
    - shard-kbl:          NOTRUN -> [SKIP][127] ([fdo#109271] / [i915#2437])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl1/igt@kms_writeback@writeback-check-output.html

  * igt@perf@polling-parameterized:
    - shard-glk:          [PASS][128] -> [FAIL][129] ([i915#1542])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk9/igt@perf@polling-parameterized.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk9/igt@perf@polling-parameterized.html
    - shard-iclb:         [PASS][130] -> [FAIL][131] ([i915#1542])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-iclb4/igt@perf@polling-parameterized.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-iclb4/igt@perf@polling-parameterized.html
    - shard-skl:          [PASS][132] -> [FAIL][133] ([i915#1542])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-skl6/igt@perf@polling-parameterized.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl7/igt@perf@polling-parameterized.html

  * igt@perf@polling-small-buf:
    - shard-skl:          [PASS][134] -> [FAIL][135] ([i915#1722])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-skl7/igt@perf@polling-small-buf.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl9/igt@perf@polling-small-buf.html

  * igt@sysfs_clients@create:
    - shard-apl:          NOTRUN -> [SKIP][136] ([fdo#109271] / [i915#2994]) +3 similar issues
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl3/igt@sysfs_clients@create.html
    - shard-skl:          NOTRUN -> [SKIP][137] ([fdo#109271] / [i915#2994]) +2 similar issues
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl8/igt@sysfs_clients@create.html

  
#### Possible fixes ####

  * igt@gem_exec_capture@pi@bcs0:
    - shard-skl:          [INCOMPLETE][138] ([i915#2369]) -> [PASS][139]
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-skl10/igt@gem_exec_capture@pi@bcs0.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl4/igt@gem_exec_capture@pi@bcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          [FAIL][140] ([i915#2842]) -> [PASS][141]
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-tglb:         [FAIL][142] ([i915#2842]) -> [PASS][143]
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-tglb5/igt@gem_exec_fair@basic-pace@vcs1.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-tglb6/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-skl:          [DMESG-WARN][144] ([i915#1436] / [i915#716]) -> [PASS][145]
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-skl9/igt@gen9_exec_parse@allowed-single.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl8/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_suspend@debugfs-reader:
    - shard-apl:          [DMESG-WARN][146] ([i915#180]) -> [PASS][147] +5 similar issues
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-apl3/igt@i915_suspend@debugfs-reader.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-apl3/igt@i915_suspend@debugfs-reader.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][148] ([i915#180]) -> [PASS][149]
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-kbl7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
    - shard-skl:          [FAIL][150] ([i915#2346]) -> [PASS][151]
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][152] ([i915#2122]) -> [PASS][153]
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
    - shard-glk:          [FAIL][154] ([i915#79]) -> [PASS][155]
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-skl:          [FAIL][156] ([i915#79]) -> [PASS][157]
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          [INCOMPLETE][158] ([i915#636]) -> [PASS][159]
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-kbl2/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl1/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][160] ([fdo#108145] / [i915#265]) -> [PASS][161]
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][162] ([fdo#109441]) -> [PASS][163] +2 similar issues
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-kbl:          [INCOMPLETE][164] ([i915#2828] / [i915#794]) -> [PASS][165]
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-kbl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-kbl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  
#### Warnings ####

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-iclb:         [FAIL][166] ([i915#2852]) -> [FAIL][167] ([i915#2842])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-iclb6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-iclb6/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][168] ([i915#2684]) -> [WARN][169] ([i915#1804] / [i915#2684])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
    - shard-iclb:         [SKIP][170] ([i915#658]) -> [SKIP][171] ([i915#2920]) +2 similar issues
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
    - shard-iclb:         [SKIP][172] ([i915#2920]) -> [SKIP][173] ([i915#658]) +1 similar

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/index.html

[-- Attachment #2: Type: text/html, Size: 33381 bytes --]

Re: [Intel-gfx] [PATCH 1/9] drm/i915: Bump DSL linemask to 20 bits

[Rodrigo Vivi]

On Fri, Nov 12, 2021 at 09:38:05PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Since tgl PIPE_DSL has 20 bits for the scanline. Let's bump our
> definition to match. And while at it let's also add the define
> for the current field readback.
> 
> We can also get rid of the gen2 vs. gen3+ nonsense since none
> of the extra bits ever did anything and just always read
> as zero.

You are stepping over reserved bits on older platforms here.

I understand that must probably hw is not using this for anything
and the reads are only zero. But I'm always afraid of opening
precedence for this kind of assumptions and end up stepping
over some reserved bit that hw is using for something else
but not documented.

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 10 ++--------
>  drivers/gpu/drm/i915/i915_irq.c              |  7 ++-----
>  drivers/gpu/drm/i915/i915_reg.h              |  4 ++--
>  3 files changed, 6 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0ceee8ac6671..6073f94632ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -348,16 +348,10 @@ static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
>  {
>  	i915_reg_t reg = PIPEDSL(pipe);
>  	u32 line1, line2;
> -	u32 line_mask;
>  
> -	if (DISPLAY_VER(dev_priv) == 2)
> -		line_mask = DSL_LINEMASK_GEN2;
> -	else
> -		line_mask = DSL_LINEMASK_GEN3;
> -
> -	line1 = intel_de_read(dev_priv, reg) & line_mask;
> +	line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
>  	msleep(5);
> -	line2 = intel_de_read(dev_priv, reg) & line_mask;
> +	line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
>  
>  	return line1 != line2;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 038a9ec563c1..eb8c92324aee 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -836,10 +836,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>  	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
>  		vtotal /= 2;
>  
> -	if (DISPLAY_VER(dev_priv) == 2)
> -		position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
> -	else
> -		position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
> +	position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
>  
>  	/*
>  	 * On HSW, the DSL reg (0x70000) appears to return 0 if we
> @@ -858,7 +855,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>  
>  		for (i = 0; i < 100; i++) {
>  			udelay(1);
> -			temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
> +			temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
>  			if (temp != position) {
>  				position = temp;
>  				break;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 686f0a1b7860..f5d54ed2efc1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6165,8 +6165,8 @@ enum {
>  
>  /* Pipe A */
>  #define _PIPEADSL		0x70000
> -#define   DSL_LINEMASK_GEN2	0x00000fff
> -#define   DSL_LINEMASK_GEN3	0x00001fff
> +#define   PIPEDSL_CURR_FIELD	REG_BIT(31) /* ctg+ */
> +#define   PIPEDSL_LINE_MASK	REG_GENMASK(19, 0)
>  #define _PIPEACONF		0x70008
>  #define   PIPECONF_ENABLE	(1 << 31)
>  #define   PIPECONF_DISABLE	0
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 9/9] drm/i915: Clean up FPGA_DBG/CLAIM_ER bits

[Rodrigo Vivi]

On Fri, Nov 12, 2021 at 09:38:13PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Use REG_BIT() & co. for FPGA_DBG/CLAIM_ER bits.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0ceb88828d93..a4d6bd380012 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2821,12 +2821,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define GEN12_AUX_ERR_DBG		_MMIO(0x43f4)
>  
>  #define FPGA_DBG		_MMIO(0x42300)
> -#define   FPGA_DBG_RM_NOCLAIM	(1 << 31)
> +#define   FPGA_DBG_RM_NOCLAIM	REG_BIT(31)
>  
>  #define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
> -#define   CLAIM_ER_CLR		(1 << 31)
> -#define   CLAIM_ER_OVERFLOW	(1 << 16)
> -#define   CLAIM_ER_CTR_MASK	0xffff
> +#define   CLAIM_ER_CLR		REG_BIT(31)
> +#define   CLAIM_ER_OVERFLOW	REG_BIT(16)
> +#define   CLAIM_ER_CTR_MASK	REG_GENMASK(15, 0)
>  
>  #define DERRMR		_MMIO(0x44050)
>  /* Note that HBLANK events are reserved on bdw+ */
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 8/9] drm/i915: Clean up DPINVGTT/VLV_DPFLIPSTAT bits

[Rodrigo Vivi]

On Fri, Nov 12, 2021 at 09:38:12PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Use REG_BIT() & co. for DPINVTT/VLV_DPFLIPSTAT bits.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_irq.c |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h | 94 ++++++++++++++++-----------------
>  2 files changed, 48 insertions(+), 48 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index eb8c92324aee..1021f7ae0dda 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3013,7 +3013,7 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
>  	if (IS_CHERRYVIEW(dev_priv))
>  		intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
>  	else
> -		intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
> +		intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_VLV);
>  
>  	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
>  	intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6ba5ab277675..0ceb88828d93 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6358,55 +6358,55 @@ enum {
>  #define   PIPE_STATUS_PORT_UNDERRUN_XELPD		REG_BIT(26)
>  
>  #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
> -#define   PIPEB_LINE_COMPARE_INT_EN		(1 << 29)
> -#define   PIPEB_HLINE_INT_EN			(1 << 28)
> -#define   PIPEB_VBLANK_INT_EN			(1 << 27)
> -#define   SPRITED_FLIP_DONE_INT_EN		(1 << 26)
> -#define   SPRITEC_FLIP_DONE_INT_EN		(1 << 25)
> -#define   PLANEB_FLIP_DONE_INT_EN		(1 << 24)
> -#define   PIPE_PSR_INT_EN			(1 << 22)
> -#define   PIPEA_LINE_COMPARE_INT_EN		(1 << 21)
> -#define   PIPEA_HLINE_INT_EN			(1 << 20)
> -#define   PIPEA_VBLANK_INT_EN			(1 << 19)
> -#define   SPRITEB_FLIP_DONE_INT_EN		(1 << 18)
> -#define   SPRITEA_FLIP_DONE_INT_EN		(1 << 17)
> -#define   PLANEA_FLIPDONE_INT_EN		(1 << 16)
> -#define   PIPEC_LINE_COMPARE_INT_EN		(1 << 13)
> -#define   PIPEC_HLINE_INT_EN			(1 << 12)
> -#define   PIPEC_VBLANK_INT_EN			(1 << 11)
> -#define   SPRITEF_FLIPDONE_INT_EN		(1 << 10)
> -#define   SPRITEE_FLIPDONE_INT_EN		(1 << 9)
> -#define   PLANEC_FLIPDONE_INT_EN		(1 << 8)
> +#define   PIPEB_LINE_COMPARE_INT_EN			REG_BIT(29)
> +#define   PIPEB_HLINE_INT_EN			REG_BIT(28)
> +#define   PIPEB_VBLANK_INT_EN			REG_BIT(27)
> +#define   SPRITED_FLIP_DONE_INT_EN			REG_BIT(26)
> +#define   SPRITEC_FLIP_DONE_INT_EN			REG_BIT(25)
> +#define   PLANEB_FLIP_DONE_INT_EN			REG_BIT(24)
> +#define   PIPE_PSR_INT_EN			REG_BIT(22)
> +#define   PIPEA_LINE_COMPARE_INT_EN			REG_BIT(21)
> +#define   PIPEA_HLINE_INT_EN			REG_BIT(20)
> +#define   PIPEA_VBLANK_INT_EN			REG_BIT(19)
> +#define   SPRITEB_FLIP_DONE_INT_EN			REG_BIT(18)
> +#define   SPRITEA_FLIP_DONE_INT_EN			REG_BIT(17)
> +#define   PLANEA_FLIPDONE_INT_EN			REG_BIT(16)
> +#define   PIPEC_LINE_COMPARE_INT_EN			REG_BIT(13)
> +#define   PIPEC_HLINE_INT_EN			REG_BIT(12)
> +#define   PIPEC_VBLANK_INT_EN			REG_BIT(11)
> +#define   SPRITEF_FLIPDONE_INT_EN			REG_BIT(10)
> +#define   SPRITEE_FLIPDONE_INT_EN			REG_BIT(9)
> +#define   PLANEC_FLIPDONE_INT_EN			REG_BIT(8)
>  
>  #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
> -#define   SPRITEF_INVALID_GTT_INT_EN		(1 << 27)
> -#define   SPRITEE_INVALID_GTT_INT_EN		(1 << 26)
> -#define   PLANEC_INVALID_GTT_INT_EN		(1 << 25)
> -#define   CURSORC_INVALID_GTT_INT_EN		(1 << 24)
> -#define   CURSORB_INVALID_GTT_INT_EN		(1 << 23)
> -#define   CURSORA_INVALID_GTT_INT_EN		(1 << 22)
> -#define   SPRITED_INVALID_GTT_INT_EN		(1 << 21)
> -#define   SPRITEC_INVALID_GTT_INT_EN		(1 << 20)
> -#define   PLANEB_INVALID_GTT_INT_EN		(1 << 19)
> -#define   SPRITEB_INVALID_GTT_INT_EN		(1 << 18)
> -#define   SPRITEA_INVALID_GTT_INT_EN		(1 << 17)
> -#define   PLANEA_INVALID_GTT_INT_EN		(1 << 16)
> -#define   DPINVGTT_EN_MASK			0xff0000
> -#define   DPINVGTT_EN_MASK_CHV			0xfff0000
> -#define   SPRITEF_INVALID_GTT_STATUS		(1 << 11)
> -#define   SPRITEE_INVALID_GTT_STATUS		(1 << 10)
> -#define   PLANEC_INVALID_GTT_STATUS		(1 << 9)
> -#define   CURSORC_INVALID_GTT_STATUS		(1 << 8)
> -#define   CURSORB_INVALID_GTT_STATUS		(1 << 7)
> -#define   CURSORA_INVALID_GTT_STATUS		(1 << 6)
> -#define   SPRITED_INVALID_GTT_STATUS		(1 << 5)
> -#define   SPRITEC_INVALID_GTT_STATUS		(1 << 4)
> -#define   PLANEB_INVALID_GTT_STATUS		(1 << 3)
> -#define   SPRITEB_INVALID_GTT_STATUS		(1 << 2)
> -#define   SPRITEA_INVALID_GTT_STATUS		(1 << 1)
> -#define   PLANEA_INVALID_GTT_STATUS		(1 << 0)
> -#define   DPINVGTT_STATUS_MASK			0xff
> -#define   DPINVGTT_STATUS_MASK_CHV		0xfff
> +#define   DPINVGTT_EN_MASK_CHV				REG_GENMASK(27, 16)
> +#define   DPINVGTT_EN_MASK_VLV				REG_GENMASK(23, 16)
> +#define   SPRITEF_INVALID_GTT_INT_EN			REG_BIT(27)
> +#define   SPRITEE_INVALID_GTT_INT_EN			REG_BIT(26)
> +#define   PLANEC_INVALID_GTT_INT_EN			REG_BIT(25)
> +#define   CURSORC_INVALID_GTT_INT_EN			REG_BIT(24)
> +#define   CURSORB_INVALID_GTT_INT_EN			REG_BIT(23)
> +#define   CURSORA_INVALID_GTT_INT_EN			REG_BIT(22)
> +#define   SPRITED_INVALID_GTT_INT_EN			REG_BIT(21)
> +#define   SPRITEC_INVALID_GTT_INT_EN			REG_BIT(20)
> +#define   PLANEB_INVALID_GTT_INT_EN			REG_BIT(19)
> +#define   SPRITEB_INVALID_GTT_INT_EN			REG_BIT(18)
> +#define   SPRITEA_INVALID_GTT_INT_EN			REG_BIT(17)
> +#define   PLANEA_INVALID_GTT_INT_EN			REG_BIT(16)
> +#define   DPINVGTT_STATUS_MASK_CHV			REG_GENMASK(11, 0)
> +#define   DPINVGTT_STATUS_MASK_VLV			REG_GENMASK(7, 0)
> +#define   SPRITEF_INVALID_GTT_STATUS			REG_BIT(11)
> +#define   SPRITEE_INVALID_GTT_STATUS			REG_BIT(10)
> +#define   PLANEC_INVALID_GTT_STATUS			REG_BIT(9)
> +#define   CURSORC_INVALID_GTT_STATUS			REG_BIT(8)
> +#define   CURSORB_INVALID_GTT_STATUS			REG_BIT(7)
> +#define   CURSORA_INVALID_GTT_STATUS			REG_BIT(6)
> +#define   SPRITED_INVALID_GTT_STATUS			REG_BIT(5)
> +#define   SPRITEC_INVALID_GTT_STATUS			REG_BIT(4)
> +#define   PLANEB_INVALID_GTT_STATUS			REG_BIT(3)
> +#define   SPRITEB_INVALID_GTT_STATUS			REG_BIT(2)
> +#define   SPRITEA_INVALID_GTT_STATUS			REG_BIT(1)
> +#define   PLANEA_INVALID_GTT_STATUS			REG_BIT(0)
>  
>  #define DSPARB			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
>  #define   DSPARB_CSTART_MASK	(0x7f << 7)
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 7/9] drm/i915: Clean up CRC register defines

[Rodrigo Vivi]

On Fri, Nov 12, 2021 at 09:38:11PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Use REG_BIT() & co. for the CRC registers.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 77 ++++++++++++++++++---------------
>  1 file changed, 41 insertions(+), 36 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 211e2b415e50..6ba5ab277675 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4393,47 +4393,52 @@ enum {
>  
>  /* Pipe A CRC regs */
>  #define _PIPE_CRC_CTL_A			0x60050
> -#define   PIPE_CRC_ENABLE		(1 << 31)
> +#define   PIPE_CRC_ENABLE		REG_BIT(31)
>  /* skl+ source selection */
> -#define   PIPE_CRC_SOURCE_PLANE_1_SKL	(0 << 28)
> -#define   PIPE_CRC_SOURCE_PLANE_2_SKL	(2 << 28)
> -#define   PIPE_CRC_SOURCE_DMUX_SKL	(4 << 28)
> -#define   PIPE_CRC_SOURCE_PLANE_3_SKL	(6 << 28)
> -#define   PIPE_CRC_SOURCE_PLANE_4_SKL	(7 << 28)
> -#define   PIPE_CRC_SOURCE_PLANE_5_SKL	(5 << 28)
> -#define   PIPE_CRC_SOURCE_PLANE_6_SKL	(3 << 28)
> -#define   PIPE_CRC_SOURCE_PLANE_7_SKL	(1 << 28)
> +#define   PIPE_CRC_SOURCE_MASK_SKL	REG_GENMASK(30, 28)
> +#define   PIPE_CRC_SOURCE_PLANE_1_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)
> +#define   PIPE_CRC_SOURCE_PLANE_2_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2)
> +#define   PIPE_CRC_SOURCE_DMUX_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4)
> +#define   PIPE_CRC_SOURCE_PLANE_3_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6)
> +#define   PIPE_CRC_SOURCE_PLANE_4_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7)
> +#define   PIPE_CRC_SOURCE_PLANE_5_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5)
> +#define   PIPE_CRC_SOURCE_PLANE_6_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3)
> +#define   PIPE_CRC_SOURCE_PLANE_7_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1)
>  /* ivb+ source selection */
> -#define   PIPE_CRC_SOURCE_PRIMARY_IVB	(0 << 29)
> -#define   PIPE_CRC_SOURCE_SPRITE_IVB	(1 << 29)
> -#define   PIPE_CRC_SOURCE_PF_IVB	(2 << 29)
> +#define   PIPE_CRC_SOURCE_MASK_IVB	REG_GENMASK(30, 29)
> +#define   PIPE_CRC_SOURCE_PRIMARY_IVB	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)
> +#define   PIPE_CRC_SOURCE_SPRITE_IVB	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1)
> +#define   PIPE_CRC_SOURCE_PF_IVB	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2)
>  /* ilk+ source selection */
> -#define   PIPE_CRC_SOURCE_PRIMARY_ILK	(0 << 28)
> -#define   PIPE_CRC_SOURCE_SPRITE_ILK	(1 << 28)
> -#define   PIPE_CRC_SOURCE_PIPE_ILK	(2 << 28)
> -/* embedded DP port on the north display block, reserved on ivb */
> -#define   PIPE_CRC_SOURCE_PORT_A_ILK	(4 << 28)
> -#define   PIPE_CRC_SOURCE_FDI_ILK	(5 << 28) /* reserved on ivb */
> +#define   PIPE_CRC_SOURCE_MASK_ILK	REG_GENMASK(30, 28)
> +#define   PIPE_CRC_SOURCE_PRIMARY_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)
> +#define   PIPE_CRC_SOURCE_SPRITE_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1)
> +#define   PIPE_CRC_SOURCE_PIPE_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2)
> +/* embedded DP port on the north display block */
> +#define   PIPE_CRC_SOURCE_PORT_A_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4)
> +#define   PIPE_CRC_SOURCE_FDI_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5)
>  /* vlv source selection */
> -#define   PIPE_CRC_SOURCE_PIPE_VLV	(0 << 27)
> -#define   PIPE_CRC_SOURCE_HDMIB_VLV	(1 << 27)
> -#define   PIPE_CRC_SOURCE_HDMIC_VLV	(2 << 27)
> +#define   PIPE_CRC_SOURCE_MASK_VLV	REG_GENMASK(30, 27)
> +#define   PIPE_CRC_SOURCE_PIPE_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)
> +#define   PIPE_CRC_SOURCE_HDMIB_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1)
> +#define   PIPE_CRC_SOURCE_HDMIC_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2)
>  /* with DP port the pipe source is invalid */
> -#define   PIPE_CRC_SOURCE_DP_D_VLV	(3 << 27)
> -#define   PIPE_CRC_SOURCE_DP_B_VLV	(6 << 27)
> -#define   PIPE_CRC_SOURCE_DP_C_VLV	(7 << 27)
> +#define   PIPE_CRC_SOURCE_DP_D_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3)
> +#define   PIPE_CRC_SOURCE_DP_B_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6)
> +#define   PIPE_CRC_SOURCE_DP_C_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7)
>  /* gen3+ source selection */
> -#define   PIPE_CRC_SOURCE_PIPE_I9XX	(0 << 28)
> -#define   PIPE_CRC_SOURCE_SDVOB_I9XX	(1 << 28)
> -#define   PIPE_CRC_SOURCE_SDVOC_I9XX	(2 << 28)
> +#define   PIPE_CRC_SOURCE_MASK_I9XX	REG_GENMASK(30, 28)
> +#define   PIPE_CRC_SOURCE_PIPE_I9XX	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)
> +#define   PIPE_CRC_SOURCE_SDVOB_I9XX	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1)
> +#define   PIPE_CRC_SOURCE_SDVOC_I9XX	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2)
>  /* with DP/TV port the pipe source is invalid */
> -#define   PIPE_CRC_SOURCE_DP_D_G4X	(3 << 28)
> -#define   PIPE_CRC_SOURCE_TV_PRE	(4 << 28)
> -#define   PIPE_CRC_SOURCE_TV_POST	(5 << 28)
> -#define   PIPE_CRC_SOURCE_DP_B_G4X	(6 << 28)
> -#define   PIPE_CRC_SOURCE_DP_C_G4X	(7 << 28)
> +#define   PIPE_CRC_SOURCE_DP_D_G4X	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3)
> +#define   PIPE_CRC_SOURCE_TV_PRE	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4)
> +#define   PIPE_CRC_SOURCE_TV_POST	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5)
> +#define   PIPE_CRC_SOURCE_DP_B_G4X	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6)
> +#define   PIPE_CRC_SOURCE_DP_C_G4X	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7)
>  /* gen2 doesn't have source selection bits */
> -#define   PIPE_CRC_INCLUDE_BORDER_I8XX	(1 << 30)
> +#define   PIPE_CRC_INCLUDE_BORDER_I8XX	REG_BIT(30)
>  
>  #define _PIPE_CRC_RES_1_A_IVB		0x60064
>  #define _PIPE_CRC_RES_2_A_IVB		0x60068
> @@ -5087,9 +5092,9 @@ enum {
>  #define PORT_DFT2_G4X		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
>  #define   DC_BALANCE_RESET_VLV			(1 << 31)
>  #define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
> -#define   PIPE_C_SCRAMBLE_RESET			(1 << 14) /* chv */
> -#define   PIPE_B_SCRAMBLE_RESET			(1 << 1)
> -#define   PIPE_A_SCRAMBLE_RESET			(1 << 0)
> +#define   PIPE_C_SCRAMBLE_RESET			REG_BIT(14) /* chv */
> +#define   PIPE_B_SCRAMBLE_RESET			REG_BIT(1)
> +#define   PIPE_A_SCRAMBLE_RESET			REG_BIT(0)
>  
>  /* Gen 3 SDVO bits: */
>  #define   SDVO_ENABLE				(1 << 31)
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Clean up PIPEMISC register defines

[Rodrigo Vivi]

On Fri, Nov 12, 2021 at 09:38:06PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Use REG_BIT() & co. for PIPEMISC* bits, and while at it
> fill in the missing dithering bits since we already had some
> of them defined.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 18 +++++-----
>  drivers/gpu/drm/i915/i915_reg.h              | 35 +++++++++++---------
>  2 files changed, 28 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6073f94632ab..e293241450b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3724,18 +3724,18 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
>  
>  	switch (crtc_state->pipe_bpp) {
>  	case 18:
> -		val |= PIPEMISC_6_BPC;
> +		val |= PIPEMISC_BPC_6;
>  		break;
>  	case 24:
> -		val |= PIPEMISC_8_BPC;
> +		val |= PIPEMISC_BPC_8;
>  		break;
>  	case 30:
> -		val |= PIPEMISC_10_BPC;
> +		val |= PIPEMISC_BPC_10;
>  		break;
>  	case 36:
>  		/* Port output 12BPC defined for ADLP+ */
>  		if (DISPLAY_VER(dev_priv) > 12)
> -			val |= PIPEMISC_12_BPC_ADLP;
> +			val |= PIPEMISC_BPC_12_ADLP;

while on it, I wonder if we could remove this "ADLP" suffix.

First because prefix seems to be the most used case for the platform.
But also because there's a clear if here and a clear comment in the definition.
(Btw, I'd prefer the ver >= 13 than > 12 to be really clear :/)

>  		break;
>  	default:
>  		MISSING_CASE(crtc_state->pipe_bpp);
> @@ -3771,7 +3771,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
>  		}
>  
>  		intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
> -			     PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
> +			     PIPE_MISC2_BUBBLE_COUNTER_MASK,
>  			     scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
>  			     PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
>  	}
> @@ -3787,11 +3787,11 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
>  	tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
>  
>  	switch (tmp & PIPEMISC_BPC_MASK) {
> -	case PIPEMISC_6_BPC:
> +	case PIPEMISC_BPC_6:
>  		return 18;
> -	case PIPEMISC_8_BPC:
> +	case PIPEMISC_BPC_8:
>  		return 24;
> -	case PIPEMISC_10_BPC:
> +	case PIPEMISC_BPC_10:
>  		return 30;
>  	/*
>  	 * PORT OUTPUT 12 BPC defined for ADLP+.
> @@ -3803,7 +3803,7 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
>  	 * on older platforms, need to find a workaround for 12 BPC
>  	 * MIPI DSI HW readout.
>  	 */
> -	case PIPEMISC_12_BPC_ADLP:
> +	case PIPEMISC_BPC_12_ADLP:
>  		if (DISPLAY_VER(dev_priv) > 12)
>  			return 36;
>  		fallthrough;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f5d54ed2efc1..e300a202ce2d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6308,32 +6308,35 @@ enum {
>  
>  #define _PIPE_MISC_A			0x70030
>  #define _PIPE_MISC_B			0x71030
> -#define   PIPEMISC_YUV420_ENABLE	(1 << 27) /* glk+ */
> -#define   PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
> -#define   PIPEMISC_HDR_MODE_PRECISION	(1 << 23) /* icl+ */
> -#define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1 << 11)
> -#define   PIPEMISC_PIXEL_ROUNDING_TRUNC	REG_BIT(8) /* tgl+ */
> +#define   PIPEMISC_YUV420_ENABLE		REG_BIT(27) /* glk+ */
> +#define   PIPEMISC_YUV420_MODE_FULL_BLEND	REG_BIT(26) /* glk+ */
> +#define   PIPEMISC_HDR_MODE_PRECISION		REG_BIT(23) /* icl+ */
> +#define   PIPEMISC_OUTPUT_COLORSPACE_YUV	REG_BIT(11)
> +#define   PIPEMISC_PIXEL_ROUNDING_TRUNC		REG_BIT(8) /* tgl+ */
>  /*
>   * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
>   * valid values of: 6, 8, 10 BPC.
>   * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
>   * 6, 8, 10, 12 BPC.
>   */
> -#define   PIPEMISC_BPC_MASK		(7 << 5)
> -#define   PIPEMISC_8_BPC		(0 << 5)
> -#define   PIPEMISC_10_BPC		(1 << 5)
> -#define   PIPEMISC_6_BPC		(2 << 5)
> -#define   PIPEMISC_12_BPC_ADLP		(4 << 5) /* adlp+ */
> -#define   PIPEMISC_DITHER_ENABLE	(1 << 4)
> -#define   PIPEMISC_DITHER_TYPE_MASK	(3 << 2)
> -#define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
> +#define   PIPEMISC_BPC_MASK			REG_GENMASK(7, 5)
> +#define   PIPEMISC_BPC_8			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)
> +#define   PIPEMISC_BPC_10			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1)
> +#define   PIPEMISC_BPC_6			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2)
> +#define   PIPEMISC_BPC_12_ADLP			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */
> +#define   PIPEMISC_DITHER_ENABLE		REG_BIT(4)
> +#define   PIPEMISC_DITHER_TYPE_MASK		REG_GENMASK(3, 2)
> +#define   PIPEMISC_DITHER_TYPE_SP		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0)
> +#define   PIPEMISC_DITHER_TYPE_ST1		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1)
> +#define   PIPEMISC_DITHER_TYPE_ST2		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2)
> +#define   PIPEMISC_DITHER_TYPE_TEMP		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3)
>  #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)
>  
>  #define _PIPE_MISC2_A					0x7002C
>  #define _PIPE_MISC2_B					0x7102C
> -#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN		(0x50 << 24)
> -#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS		(0x14 << 24)
> -#define   PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK	(0xff << 24)
> +#define   PIPE_MISC2_BUBBLE_COUNTER_MASK	REG_GENMASK(31, 24)
> +#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
> +#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
>  #define PIPE_MISC2(pipe)					_MMIO_PIPE2(pipe, _PIPE_MISC2_A)
>  
>  /* Skylake+ pipe bottom (background) color */
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Clean up PIPEMISC register defines

[Ville Syrjälä]

On Mon, Nov 15, 2021 at 02:12:47PM -0500, Rodrigo Vivi wrote:
> On Fri, Nov 12, 2021 at 09:38:06PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Use REG_BIT() & co. for PIPEMISC* bits, and while at it
> > fill in the missing dithering bits since we already had some
> > of them defined.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 18 +++++-----
> >  drivers/gpu/drm/i915/i915_reg.h              | 35 +++++++++++---------
> >  2 files changed, 28 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 6073f94632ab..e293241450b1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -3724,18 +3724,18 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
> >  
> >  	switch (crtc_state->pipe_bpp) {
> >  	case 18:
> > -		val |= PIPEMISC_6_BPC;
> > +		val |= PIPEMISC_BPC_6;
> >  		break;
> >  	case 24:
> > -		val |= PIPEMISC_8_BPC;
> > +		val |= PIPEMISC_BPC_8;
> >  		break;
> >  	case 30:
> > -		val |= PIPEMISC_10_BPC;
> > +		val |= PIPEMISC_BPC_10;
> >  		break;
> >  	case 36:
> >  		/* Port output 12BPC defined for ADLP+ */
> >  		if (DISPLAY_VER(dev_priv) > 12)
> > -			val |= PIPEMISC_12_BPC_ADLP;
> > +			val |= PIPEMISC_BPC_12_ADLP;
> 
> while on it, I wonder if we could remove this "ADLP" suffix.
> 
> First because prefix seems to be the most used case for the platform.

I don't like prefix for such things since it screws up the namespace for
the bits of the same register. So suffix is better IMO.

> But also because there's a clear if here and a clear comment in the definition.

Yeah, I've been removing some similar things in other places for that exact
reason. The only case where we might really need platform designators is
when the bit(s) move etc.

Though I was even pondering removing the 'if' since this only controls
dithering on older platforms and we don't enable dithering for anything
but 6bpc output. Although the whole pipe_bpp concept is kinda wrong and
we should perhaps split it up into pipe_bpp vs. port_bpp, or something 
along those lines.

> (Btw, I'd prefer the ver >= 13 than > 12 to be really clear :/)

Yeah, >= is what we should use.

> 
> >  		break;
> >  	default:
> >  		MISSING_CASE(crtc_state->pipe_bpp);
> > @@ -3771,7 +3771,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
> >  		}
> >  
> >  		intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
> > -			     PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
> > +			     PIPE_MISC2_BUBBLE_COUNTER_MASK,
> >  			     scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
> >  			     PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
> >  	}
> > @@ -3787,11 +3787,11 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
> >  	tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
> >  
> >  	switch (tmp & PIPEMISC_BPC_MASK) {
> > -	case PIPEMISC_6_BPC:
> > +	case PIPEMISC_BPC_6:
> >  		return 18;
> > -	case PIPEMISC_8_BPC:
> > +	case PIPEMISC_BPC_8:
> >  		return 24;
> > -	case PIPEMISC_10_BPC:
> > +	case PIPEMISC_BPC_10:
> >  		return 30;
> >  	/*
> >  	 * PORT OUTPUT 12 BPC defined for ADLP+.
> > @@ -3803,7 +3803,7 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
> >  	 * on older platforms, need to find a workaround for 12 BPC
> >  	 * MIPI DSI HW readout.
> >  	 */
> > -	case PIPEMISC_12_BPC_ADLP:
> > +	case PIPEMISC_BPC_12_ADLP:
> >  		if (DISPLAY_VER(dev_priv) > 12)
> >  			return 36;
> >  		fallthrough;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f5d54ed2efc1..e300a202ce2d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6308,32 +6308,35 @@ enum {
> >  
> >  #define _PIPE_MISC_A			0x70030
> >  #define _PIPE_MISC_B			0x71030
> > -#define   PIPEMISC_YUV420_ENABLE	(1 << 27) /* glk+ */
> > -#define   PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
> > -#define   PIPEMISC_HDR_MODE_PRECISION	(1 << 23) /* icl+ */
> > -#define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1 << 11)
> > -#define   PIPEMISC_PIXEL_ROUNDING_TRUNC	REG_BIT(8) /* tgl+ */
> > +#define   PIPEMISC_YUV420_ENABLE		REG_BIT(27) /* glk+ */
> > +#define   PIPEMISC_YUV420_MODE_FULL_BLEND	REG_BIT(26) /* glk+ */
> > +#define   PIPEMISC_HDR_MODE_PRECISION		REG_BIT(23) /* icl+ */
> > +#define   PIPEMISC_OUTPUT_COLORSPACE_YUV	REG_BIT(11)
> > +#define   PIPEMISC_PIXEL_ROUNDING_TRUNC		REG_BIT(8) /* tgl+ */
> >  /*
> >   * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
> >   * valid values of: 6, 8, 10 BPC.
> >   * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
> >   * 6, 8, 10, 12 BPC.
> >   */
> > -#define   PIPEMISC_BPC_MASK		(7 << 5)
> > -#define   PIPEMISC_8_BPC		(0 << 5)
> > -#define   PIPEMISC_10_BPC		(1 << 5)
> > -#define   PIPEMISC_6_BPC		(2 << 5)
> > -#define   PIPEMISC_12_BPC_ADLP		(4 << 5) /* adlp+ */
> > -#define   PIPEMISC_DITHER_ENABLE	(1 << 4)
> > -#define   PIPEMISC_DITHER_TYPE_MASK	(3 << 2)
> > -#define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
> > +#define   PIPEMISC_BPC_MASK			REG_GENMASK(7, 5)
> > +#define   PIPEMISC_BPC_8			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)
> > +#define   PIPEMISC_BPC_10			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1)
> > +#define   PIPEMISC_BPC_6			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2)
> > +#define   PIPEMISC_BPC_12_ADLP			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */
> > +#define   PIPEMISC_DITHER_ENABLE		REG_BIT(4)
> > +#define   PIPEMISC_DITHER_TYPE_MASK		REG_GENMASK(3, 2)
> > +#define   PIPEMISC_DITHER_TYPE_SP		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0)
> > +#define   PIPEMISC_DITHER_TYPE_ST1		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1)
> > +#define   PIPEMISC_DITHER_TYPE_ST2		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2)
> > +#define   PIPEMISC_DITHER_TYPE_TEMP		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3)
> >  #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)
> >  
> >  #define _PIPE_MISC2_A					0x7002C
> >  #define _PIPE_MISC2_B					0x7102C
> > -#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN		(0x50 << 24)
> > -#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS		(0x14 << 24)
> > -#define   PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK	(0xff << 24)
> > +#define   PIPE_MISC2_BUBBLE_COUNTER_MASK	REG_GENMASK(31, 24)
> > +#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
> > +#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
> >  #define PIPE_MISC2(pipe)					_MMIO_PIPE2(pipe, _PIPE_MISC2_A)
> >  
> >  /* Skylake+ pipe bottom (background) color */
> > -- 
> > 2.32.0
> > 

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 1/9] drm/i915: Bump DSL linemask to 20 bits

[Ville Syrjälä]

On Mon, Nov 15, 2021 at 02:05:00PM -0500, Rodrigo Vivi wrote:
> On Fri, Nov 12, 2021 at 09:38:05PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Since tgl PIPE_DSL has 20 bits for the scanline. Let's bump our
> > definition to match. And while at it let's also add the define
> > for the current field readback.
> > 
> > We can also get rid of the gen2 vs. gen3+ nonsense since none
> > of the extra bits ever did anything and just always read
> > as zero.
> 
> You are stepping over reserved bits on older platforms here.
> 
> I understand that must probably hw is not using this for anything
> and the reads are only zero. But I'm always afraid of opening
> precedence for this kind of assumptions and end up stepping
> over some reserved bit that hw is using for something else
> but not documented.

We do this in other places too in order to keep the code
simple. I think it's fine for cases where all old platforms
had a smaller bitfield which is extended in later platforms.
That is, assuming all the bits were unused (and read as zero)
in the old platforms, which is the case here.

The thing we probably shouldn't do is make the bitfield larger
proactively for future platforms since we can't know if some of
the currently unused bits might end up being used for something
else in the future.

I really hope we don't have any undocumented bits anywhere since
those can screw us up in a lot more ways than this. If we do find
any undocuemnted bits we really need to file bspec issues for those.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Clean up PIPEMISC register defines

[Jani Nikula]

On Fri, 19 Nov 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Mon, Nov 15, 2021 at 02:12:47PM -0500, Rodrigo Vivi wrote:
>> On Fri, Nov 12, 2021 at 09:38:06PM +0200, Ville Syrjala wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > 
>> > Use REG_BIT() & co. for PIPEMISC* bits, and while at it
>> > fill in the missing dithering bits since we already had some
>> > of them defined.
>> > 
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_display.c | 18 +++++-----
>> >  drivers/gpu/drm/i915/i915_reg.h              | 35 +++++++++++---------
>> >  2 files changed, 28 insertions(+), 25 deletions(-)
>> > 
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> > index 6073f94632ab..e293241450b1 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> > @@ -3724,18 +3724,18 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
>> >  
>> >  	switch (crtc_state->pipe_bpp) {
>> >  	case 18:
>> > -		val |= PIPEMISC_6_BPC;
>> > +		val |= PIPEMISC_BPC_6;
>> >  		break;
>> >  	case 24:
>> > -		val |= PIPEMISC_8_BPC;
>> > +		val |= PIPEMISC_BPC_8;
>> >  		break;
>> >  	case 30:
>> > -		val |= PIPEMISC_10_BPC;
>> > +		val |= PIPEMISC_BPC_10;
>> >  		break;
>> >  	case 36:
>> >  		/* Port output 12BPC defined for ADLP+ */
>> >  		if (DISPLAY_VER(dev_priv) > 12)
>> > -			val |= PIPEMISC_12_BPC_ADLP;
>> > +			val |= PIPEMISC_BPC_12_ADLP;
>> 
>> while on it, I wonder if we could remove this "ADLP" suffix.
>> 
>> First because prefix seems to be the most used case for the platform.
>
> I don't like prefix for such things since it screws up the namespace for
> the bits of the same register. So suffix is better IMO.

If we want to promote using suffix for platform specific registers or
contents, I guess we should record that in the i915_reg.h top
comment. Not that anyone reads it, but then we can nag it's there. :p

BR,
Jani.




>
>> But also because there's a clear if here and a clear comment in the definition.
>
> Yeah, I've been removing some similar things in other places for that exact
> reason. The only case where we might really need platform designators is
> when the bit(s) move etc.
>
> Though I was even pondering removing the 'if' since this only controls
> dithering on older platforms and we don't enable dithering for anything
> but 6bpc output. Although the whole pipe_bpp concept is kinda wrong and
> we should perhaps split it up into pipe_bpp vs. port_bpp, or something 
> along those lines.
>
>> (Btw, I'd prefer the ver >= 13 than > 12 to be really clear :/)
>
> Yeah, >= is what we should use.
>
>> 
>> >  		break;
>> >  	default:
>> >  		MISSING_CASE(crtc_state->pipe_bpp);
>> > @@ -3771,7 +3771,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
>> >  		}
>> >  
>> >  		intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
>> > -			     PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
>> > +			     PIPE_MISC2_BUBBLE_COUNTER_MASK,
>> >  			     scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
>> >  			     PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
>> >  	}
>> > @@ -3787,11 +3787,11 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
>> >  	tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
>> >  
>> >  	switch (tmp & PIPEMISC_BPC_MASK) {
>> > -	case PIPEMISC_6_BPC:
>> > +	case PIPEMISC_BPC_6:
>> >  		return 18;
>> > -	case PIPEMISC_8_BPC:
>> > +	case PIPEMISC_BPC_8:
>> >  		return 24;
>> > -	case PIPEMISC_10_BPC:
>> > +	case PIPEMISC_BPC_10:
>> >  		return 30;
>> >  	/*
>> >  	 * PORT OUTPUT 12 BPC defined for ADLP+.
>> > @@ -3803,7 +3803,7 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
>> >  	 * on older platforms, need to find a workaround for 12 BPC
>> >  	 * MIPI DSI HW readout.
>> >  	 */
>> > -	case PIPEMISC_12_BPC_ADLP:
>> > +	case PIPEMISC_BPC_12_ADLP:
>> >  		if (DISPLAY_VER(dev_priv) > 12)
>> >  			return 36;
>> >  		fallthrough;
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index f5d54ed2efc1..e300a202ce2d 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -6308,32 +6308,35 @@ enum {
>> >  
>> >  #define _PIPE_MISC_A			0x70030
>> >  #define _PIPE_MISC_B			0x71030
>> > -#define   PIPEMISC_YUV420_ENABLE	(1 << 27) /* glk+ */
>> > -#define   PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
>> > -#define   PIPEMISC_HDR_MODE_PRECISION	(1 << 23) /* icl+ */
>> > -#define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1 << 11)
>> > -#define   PIPEMISC_PIXEL_ROUNDING_TRUNC	REG_BIT(8) /* tgl+ */
>> > +#define   PIPEMISC_YUV420_ENABLE		REG_BIT(27) /* glk+ */
>> > +#define   PIPEMISC_YUV420_MODE_FULL_BLEND	REG_BIT(26) /* glk+ */
>> > +#define   PIPEMISC_HDR_MODE_PRECISION		REG_BIT(23) /* icl+ */
>> > +#define   PIPEMISC_OUTPUT_COLORSPACE_YUV	REG_BIT(11)
>> > +#define   PIPEMISC_PIXEL_ROUNDING_TRUNC		REG_BIT(8) /* tgl+ */
>> >  /*
>> >   * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
>> >   * valid values of: 6, 8, 10 BPC.
>> >   * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
>> >   * 6, 8, 10, 12 BPC.
>> >   */
>> > -#define   PIPEMISC_BPC_MASK		(7 << 5)
>> > -#define   PIPEMISC_8_BPC		(0 << 5)
>> > -#define   PIPEMISC_10_BPC		(1 << 5)
>> > -#define   PIPEMISC_6_BPC		(2 << 5)
>> > -#define   PIPEMISC_12_BPC_ADLP		(4 << 5) /* adlp+ */
>> > -#define   PIPEMISC_DITHER_ENABLE	(1 << 4)
>> > -#define   PIPEMISC_DITHER_TYPE_MASK	(3 << 2)
>> > -#define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
>> > +#define   PIPEMISC_BPC_MASK			REG_GENMASK(7, 5)
>> > +#define   PIPEMISC_BPC_8			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)
>> > +#define   PIPEMISC_BPC_10			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1)
>> > +#define   PIPEMISC_BPC_6			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2)
>> > +#define   PIPEMISC_BPC_12_ADLP			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */
>> > +#define   PIPEMISC_DITHER_ENABLE		REG_BIT(4)
>> > +#define   PIPEMISC_DITHER_TYPE_MASK		REG_GENMASK(3, 2)
>> > +#define   PIPEMISC_DITHER_TYPE_SP		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0)
>> > +#define   PIPEMISC_DITHER_TYPE_ST1		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1)
>> > +#define   PIPEMISC_DITHER_TYPE_ST2		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2)
>> > +#define   PIPEMISC_DITHER_TYPE_TEMP		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3)
>> >  #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)
>> >  
>> >  #define _PIPE_MISC2_A					0x7002C
>> >  #define _PIPE_MISC2_B					0x7102C
>> > -#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN		(0x50 << 24)
>> > -#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS		(0x14 << 24)
>> > -#define   PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK	(0xff << 24)
>> > +#define   PIPE_MISC2_BUBBLE_COUNTER_MASK	REG_GENMASK(31, 24)
>> > +#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
>> > +#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
>> >  #define PIPE_MISC2(pipe)					_MMIO_PIPE2(pipe, _PIPE_MISC2_A)
>> >  
>> >  /* Skylake+ pipe bottom (background) color */
>> > -- 
>> > 2.32.0
>> > 

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 3/9] drm/i915: Clean up SKL_BOTTOM_COLOR defines

[Jani Nikula]

On Fri, 12 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_BIT() for SKL_BOTTOM_COLOR.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e300a202ce2d..8b227dabb10c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6341,8 +6341,8 @@ enum {
>  
>  /* Skylake+ pipe bottom (background) color */
>  #define _SKL_BOTTOM_COLOR_A		0x70034
> -#define   SKL_BOTTOM_COLOR_GAMMA_ENABLE	(1 << 31)
> -#define   SKL_BOTTOM_COLOR_CSC_ENABLE	(1 << 30)
> +#define   SKL_BOTTOM_COLOR_GAMMA_ENABLE		REG_BIT(31)
> +#define   SKL_BOTTOM_COLOR_CSC_ENABLE		REG_BIT(30)
>  #define SKL_BOTTOM_COLOR(pipe)		_MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
>  
>  #define _ICL_PIPE_A_STATUS			0x70058

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 4/9] drm/i915: Clean up PIPECONF bit defines

[Jani Nikula]

On Fri, 12 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_BIT() & co. for PIPECONF bits, and adjust the
> naming of various bits to be more consistent.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c        |   4 +-
>  drivers/gpu/drm/i915/display/intel_display.c  |  60 +++++-----
>  .../gpu/drm/i915/display/intel_pch_display.c  |   7 +-
>  drivers/gpu/drm/i915/gvt/display.c            |   4 +-
>  drivers/gpu/drm/i915/gvt/handlers.c           |   4 +-
>  drivers/gpu/drm/i915/i915_reg.h               | 108 +++++++++---------
>  6 files changed, 89 insertions(+), 98 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index c05fb861f10c..0f6587bef106 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1048,7 +1048,7 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
>  
>  		/* wait for transcoder to be enabled */
>  		if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
> -					  I965_PIPECONF_ACTIVE, 10))
> +					  PIPECONF_STATE_ENABLE, 10))
>  			drm_err(&dev_priv->drm,
>  				"DSI transcoder not enabled\n");
>  	}
> @@ -1317,7 +1317,7 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
>  
>  		/* wait for transcoder to be disabled */
>  		if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
> -					    I965_PIPECONF_ACTIVE, 50))
> +					    PIPECONF_STATE_ENABLE, 50))
>  			drm_err(&dev_priv->drm,
>  				"DSI trancoder not disabled\n");
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e293241450b1..4e29032b29d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -386,13 +386,11 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
>  
>  	if (DISPLAY_VER(dev_priv) >= 4) {
>  		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> -		i915_reg_t reg = PIPECONF(cpu_transcoder);
>  
>  		/* Wait for the Pipe State to go off */
> -		if (intel_de_wait_for_clear(dev_priv, reg,
> -					    I965_PIPECONF_ACTIVE, 100))
> -			drm_WARN(&dev_priv->drm, 1,
> -				 "pipe_off wait timed out\n");
> +		if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder),
> +					    PIPECONF_STATE_ENABLE, 100))
> +			drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
>  	} else {
>  		intel_wait_for_pipe_scanline_stopped(crtc);
>  	}
> @@ -3338,13 +3336,13 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  
>  		switch (crtc_state->pipe_bpp) {
>  		case 18:
> -			pipeconf |= PIPECONF_6BPC;
> +			pipeconf |= PIPECONF_BPC_6;
>  			break;
>  		case 24:
> -			pipeconf |= PIPECONF_8BPC;
> +			pipeconf |= PIPECONF_BPC_8;
>  			break;
>  		case 30:
> -			pipeconf |= PIPECONF_10BPC;
> +			pipeconf |= PIPECONF_BPC_10;
>  			break;
>  		default:
>  			/* Case prevented by intel_choose_pipe_bpp_dither. */
> @@ -3359,7 +3357,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  		else
>  			pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
>  	} else {
> -		pipeconf |= PIPECONF_PROGRESSIVE;
> +		pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE;
>  	}
>  
>  	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> @@ -3537,16 +3535,17 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  	if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
>  	    IS_CHERRYVIEW(dev_priv)) {
>  		switch (tmp & PIPECONF_BPC_MASK) {
> -		case PIPECONF_6BPC:
> +		case PIPECONF_BPC_6:
>  			pipe_config->pipe_bpp = 18;
>  			break;
> -		case PIPECONF_8BPC:
> +		case PIPECONF_BPC_8:
>  			pipe_config->pipe_bpp = 24;
>  			break;
> -		case PIPECONF_10BPC:
> +		case PIPECONF_BPC_10:
>  			pipe_config->pipe_bpp = 30;
>  			break;
>  		default:
> +			MISSING_CASE(tmp);
>  			break;
>  		}
>  	}
> @@ -3555,8 +3554,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
>  		pipe_config->limited_color_range = true;
>  
> -	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
> -		PIPECONF_GAMMA_MODE_SHIFT;
> +	pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp);
>  
>  	if (IS_CHERRYVIEW(dev_priv))
>  		pipe_config->cgm_mode = intel_de_read(dev_priv,
> @@ -3643,16 +3641,16 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  
>  	switch (crtc_state->pipe_bpp) {
>  	case 18:
> -		val |= PIPECONF_6BPC;
> +		val |= PIPECONF_BPC_6;
>  		break;
>  	case 24:
> -		val |= PIPECONF_8BPC;
> +		val |= PIPECONF_BPC_8;
>  		break;
>  	case 30:
> -		val |= PIPECONF_10BPC;
> +		val |= PIPECONF_BPC_10;
>  		break;
>  	case 36:
> -		val |= PIPECONF_12BPC;
> +		val |= PIPECONF_BPC_12;
>  		break;
>  	default:
>  		/* Case prevented by intel_choose_pipe_bpp_dither. */
> @@ -3660,12 +3658,12 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  	}
>  
>  	if (crtc_state->dither)
> -		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
> +		val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
>  
>  	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> -		val |= PIPECONF_INTERLACED_ILK;
> +		val |= PIPECONF_INTERLACE_IF_ID_ILK;
>  	else
> -		val |= PIPECONF_PROGRESSIVE;
> +		val |= PIPECONF_INTERLACE_PF_PD_ILK;
>  
>  	/*
>  	 * This would end up with an odd purple hue over
> @@ -3697,12 +3695,12 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
>  	u32 val = 0;
>  
>  	if (IS_HASWELL(dev_priv) && crtc_state->dither)
> -		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
> +		val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
>  
>  	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> -		val |= PIPECONF_INTERLACED_ILK;
> +		val |= PIPECONF_INTERLACE_IF_ID_ILK;
>  	else
> -		val |= PIPECONF_PROGRESSIVE;
> +		val |= PIPECONF_INTERLACE_PF_PD_ILK;
>  
>  	if (IS_HASWELL(dev_priv) &&
>  	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
> @@ -3996,16 +3994,16 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
>  		goto out;
>  
>  	switch (tmp & PIPECONF_BPC_MASK) {
> -	case PIPECONF_6BPC:
> +	case PIPECONF_BPC_6:
>  		pipe_config->pipe_bpp = 18;
>  		break;
> -	case PIPECONF_8BPC:
> +	case PIPECONF_BPC_8:
>  		pipe_config->pipe_bpp = 24;
>  		break;
> -	case PIPECONF_10BPC:
> +	case PIPECONF_BPC_10:
>  		pipe_config->pipe_bpp = 30;
>  		break;
> -	case PIPECONF_12BPC:
> +	case PIPECONF_BPC_12:
>  		pipe_config->pipe_bpp = 36;
>  		break;
>  	default:
> @@ -4025,8 +4023,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
>  		break;
>  	}
>  
> -	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
> -		PIPECONF_GAMMA_MODE_SHIFT;
> +	pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);
>  
>  	pipe_config->csc_mode = intel_de_read(dev_priv,
>  					      PIPE_CSC_MODE(crtc->pipe));
> @@ -9990,8 +9987,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		udelay(150); /* wait for warmup */
>  	}
>  
> -	intel_de_write(dev_priv, PIPECONF(pipe),
> -		       PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
> +	intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE);
>  	intel_de_posting_read(dev_priv, PIPECONF(pipe));
>  
>  	intel_wait_for_pipe_scanline_moving(crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index a55c4bfacd0d..81ab761251ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -157,13 +157,13 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
>  		 */
>  		val &= ~PIPECONF_BPC_MASK;
>  		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> -			val |= PIPECONF_8BPC;
> +			val |= PIPECONF_BPC_8;
>  		else
>  			val |= pipeconf_val & PIPECONF_BPC_MASK;
>  	}
>  
>  	val &= ~TRANS_INTERLACE_MASK;
> -	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
> +	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) {
>  		if (HAS_PCH_IBX(dev_priv) &&
>  		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
>  			val |= TRANS_LEGACY_INTERLACED_ILK;
> @@ -422,8 +422,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
>  	val = TRANS_ENABLE;
>  	pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
>  
> -	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
> -	    PIPECONF_INTERLACED_ILK)
> +	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK)
>  		val |= TRANS_INTERLACED;
>  	else
>  		val |= TRANS_PROGRESSIVE;
> diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> index 034c060f89d4..b3f47b9944d6 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -184,7 +184,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  
>  		for_each_pipe(dev_priv, pipe) {
>  			vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
> -				~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);
> +				~(PIPECONF_ENABLE | PIPECONF_STATE_ENABLE);
>  			vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
>  			vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
>  			vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
> @@ -245,7 +245,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  		 *   setup_virtual_dp_monitor.
>  		 */
>  		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
> -		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE;
> +		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_STATE_ENABLE;
>  
>  		/*
>  		 * Golden M/N are calculated based on:
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index cde0a477fb49..a224158303b6 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -701,11 +701,11 @@ static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
>  	data = vgpu_vreg(vgpu, offset);
>  
>  	if (data & PIPECONF_ENABLE) {
> -		vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
> +		vgpu_vreg(vgpu, offset) |= PIPECONF_STATE_ENABLE;
>  		vgpu_update_refresh_rate(vgpu);
>  		vgpu_update_vblank_emulation(vgpu, true);
>  	} else {
> -		vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
> +		vgpu_vreg(vgpu, offset) &= ~PIPECONF_STATE_ENABLE;
>  		vgpu_update_vblank_emulation(vgpu, false);
>  	}
>  	return 0;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8b227dabb10c..d2d5b2fa2a4a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6168,62 +6168,58 @@ enum {
>  #define   PIPEDSL_CURR_FIELD	REG_BIT(31) /* ctg+ */
>  #define   PIPEDSL_LINE_MASK	REG_GENMASK(19, 0)
>  #define _PIPEACONF		0x70008
> -#define   PIPECONF_ENABLE	(1 << 31)
> -#define   PIPECONF_DISABLE	0
> -#define   PIPECONF_DOUBLE_WIDE	(1 << 30)
> -#define   I965_PIPECONF_ACTIVE	(1 << 30)
> -#define   PIPECONF_DSI_PLL_LOCKED	(1 << 29) /* vlv & pipe A only */
> -#define   PIPECONF_FRAME_START_DELAY_MASK	(3 << 27) /* pre-hsw */
> -#define   PIPECONF_FRAME_START_DELAY(x)		((x) << 27) /* pre-hsw: 0-3 */
> -#define   PIPECONF_SINGLE_WIDE	0
> -#define   PIPECONF_PIPE_UNLOCKED 0
> -#define   PIPECONF_PIPE_LOCKED	(1 << 25)
> -#define   PIPECONF_FORCE_BORDER	(1 << 25)
> -#define   PIPECONF_GAMMA_MODE_MASK_I9XX	(1 << 24) /* gmch */
> -#define   PIPECONF_GAMMA_MODE_MASK_ILK	(3 << 24) /* ilk-ivb */
> -#define   PIPECONF_GAMMA_MODE_8BIT	(0 << 24) /* gmch,ilk-ivb */
> -#define   PIPECONF_GAMMA_MODE_10BIT	(1 << 24) /* gmch,ilk-ivb */
> -#define   PIPECONF_GAMMA_MODE_12BIT	(2 << 24) /* ilk-ivb */
> -#define   PIPECONF_GAMMA_MODE_SPLIT	(3 << 24) /* ivb */
> -#define   PIPECONF_GAMMA_MODE(x)	((x) << 24) /* pass in GAMMA_MODE_MODE_* */
> -#define   PIPECONF_GAMMA_MODE_SHIFT	24
> -#define   PIPECONF_INTERLACE_MASK	(7 << 21)
> -#define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
> -/* Note that pre-gen3 does not support interlaced display directly. Panel
> - * fitting must be disabled on pre-ilk for interlaced. */
> -#define   PIPECONF_PROGRESSIVE			(0 << 21)
> -#define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
> -#define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
> -#define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
> -#define   PIPECONF_INTERLACE_FIELD_0_ONLY	(7 << 21) /* gen3 only */
> -/* Ironlake and later have a complete new set of values for interlaced. PFIT
> - * means panel fitter required, PF means progressive fetch, DBL means power
> - * saving pixel doubling. */
> -#define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
> -#define   PIPECONF_INTERLACED_ILK		(3 << 21)
> -#define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
> -#define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
> -#define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)
> -#define   PIPECONF_EDP_RR_MODE_SWITCH		(1 << 20)
> -#define   PIPECONF_CXSR_DOWNCLOCK	(1 << 16)
> -#define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
> -#define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
> -#define   PIPECONF_OUTPUT_COLORSPACE_MASK	(3 << 11) /* ilk-ivb */
> -#define   PIPECONF_OUTPUT_COLORSPACE_RGB	(0 << 11) /* ilk-ivb */
> -#define   PIPECONF_OUTPUT_COLORSPACE_YUV601	(1 << 11) /* ilk-ivb */
> -#define   PIPECONF_OUTPUT_COLORSPACE_YUV709	(2 << 11) /* ilk-ivb */
> -#define   PIPECONF_OUTPUT_COLORSPACE_YUV_HSW	(1 << 11) /* hsw only */
> -#define   PIPECONF_BPC_MASK	(0x7 << 5)
> -#define   PIPECONF_8BPC		(0 << 5)
> -#define   PIPECONF_10BPC	(1 << 5)
> -#define   PIPECONF_6BPC		(2 << 5)
> -#define   PIPECONF_12BPC	(3 << 5)
> -#define   PIPECONF_DITHER_EN	(1 << 4)
> -#define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
> -#define   PIPECONF_DITHER_TYPE_SP (0 << 2)
> -#define   PIPECONF_DITHER_TYPE_ST1 (1 << 2)
> -#define   PIPECONF_DITHER_TYPE_ST2 (2 << 2)
> -#define   PIPECONF_DITHER_TYPE_TEMP (3 << 2)
> +#define   PIPECONF_ENABLE			REG_BIT(31)
> +#define   PIPECONF_DOUBLE_WIDE			REG_BIT(30) /* pre-i965 */
> +#define   PIPECONF_STATE_ENABLE			REG_BIT(30) /* i965+ */
> +#define   PIPECONF_DSI_PLL_LOCKED		REG_BIT(29) /* vlv & pipe A only */
> +#define   PIPECONF_FRAME_START_DELAY_MASK	REG_GENMASK(28, 27) /* pre-hsw */
> +#define   PIPECONF_FRAME_START_DELAY(x)		REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
> +#define   PIPECONF_PIPE_LOCKED			REG_BIT(25)
> +#define   PIPECONF_FORCE_BORDER			REG_BIT(25)
> +#define   PIPECONF_GAMMA_MODE_MASK_I9XX		REG_BIT(24) /* gmch */
> +#define   PIPECONF_GAMMA_MODE_MASK_ILK		REG_GENMASK(25, 24) /* ilk-ivb */
> +#define   PIPECONF_GAMMA_MODE_8BIT		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0)
> +#define   PIPECONF_GAMMA_MODE_10BIT		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1)
> +#define   PIPECONF_GAMMA_MODE_12BIT		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
> +#define   PIPECONF_GAMMA_MODE_SPLIT		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
> +#define   PIPECONF_GAMMA_MODE(x)		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
> +#define   PIPECONF_INTERLACE_MASK		REG_GENMASK(23, 21) /* gen3+ */
> +#define   PIPECONF_INTERLACE_PROGRESSIVE	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0)
> +#define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */
> +#define   PIPECONF_INTERLACE_W_SYNC_SHIFT	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */
> +#define   PIPECONF_INTERLACE_W_FIELD_INDICATION	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6)
> +#define   PIPECONF_INTERLACE_FIELD_0_ONLY	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */
> +/*
> + * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
> + * DBL=power saving pixel doubling, PF-ID* requires panel fitter
> + */
> +#define   PIPECONF_INTERLACE_MASK_ILK		REG_GENMASK(23, 21) /* ilk+ */
> +#define   PIPECONF_INTERLACE_MASK_HSW		REG_GENMASK(22, 21) /* hsw+ */
> +#define   PIPECONF_INTERLACE_PF_PD_ILK		REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0)
> +#define   PIPECONF_INTERLACE_PF_ID_ILK		REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1)
> +#define   PIPECONF_INTERLACE_IF_ID_ILK		REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3)
> +#define   PIPECONF_INTERLACE_IF_ID_DBL_ILK	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
> +#define   PIPECONF_INTERLACE_PF_ID_DBL_ILK	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
> +#define   PIPECONF_EDP_RR_MODE_SWITCH		REG_BIT(20)
> +#define   PIPECONF_CXSR_DOWNCLOCK		REG_BIT(16)
> +#define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	REG_BIT(14)
> +#define   PIPECONF_COLOR_RANGE_SELECT		REG_BIT(13)
> +#define   PIPECONF_OUTPUT_COLORSPACE_MASK	REG_GENMASK(12, 11) /* ilk-ivb */
> +#define   PIPECONF_OUTPUT_COLORSPACE_RGB	REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
> +#define   PIPECONF_OUTPUT_COLORSPACE_YUV601	REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
> +#define   PIPECONF_OUTPUT_COLORSPACE_YUV709	REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
> +#define   PIPECONF_OUTPUT_COLORSPACE_YUV_HSW	REG_BIT(11) /* hsw only */
> +#define   PIPECONF_BPC_MASK			REG_GENMASK(7, 5) /* ctg-ivb */
> +#define   PIPECONF_BPC_8			REG_FIELD_PREP(PIPECONF_BPC_MASK, 0)
> +#define   PIPECONF_BPC_10			REG_FIELD_PREP(PIPECONF_BPC_MASK, 1)
> +#define   PIPECONF_BPC_6			REG_FIELD_PREP(PIPECONF_BPC_MASK, 2)
> +#define   PIPECONF_BPC_12			REG_FIELD_PREP(PIPECONF_BPC_MASK, 3)
> +#define   PIPECONF_DITHER_EN			REG_BIT(4)
> +#define   PIPECONF_DITHER_TYPE_MASK		REG_GENMASK(3, 2)
> +#define   PIPECONF_DITHER_TYPE_SP		REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0)
> +#define   PIPECONF_DITHER_TYPE_ST1		REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1)
> +#define   PIPECONF_DITHER_TYPE_ST2		REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2)
> +#define   PIPECONF_DITHER_TYPE_TEMP		REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3)
>  #define _PIPEASTAT		0x70024
>  #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL << 31)
>  #define   SPRITE1_FLIP_DONE_INT_EN_VLV		(1UL << 30)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 1/9] drm/i915: Bump DSL linemask to 20 bits

[Jani Nikula]

On Fri, 19 Nov 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Mon, Nov 15, 2021 at 02:05:00PM -0500, Rodrigo Vivi wrote:
>> On Fri, Nov 12, 2021 at 09:38:05PM +0200, Ville Syrjala wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > 
>> > Since tgl PIPE_DSL has 20 bits for the scanline. Let's bump our
>> > definition to match. And while at it let's also add the define
>> > for the current field readback.
>> > 
>> > We can also get rid of the gen2 vs. gen3+ nonsense since none
>> > of the extra bits ever did anything and just always read
>> > as zero.
>> 
>> You are stepping over reserved bits on older platforms here.
>> 
>> I understand that must probably hw is not using this for anything
>> and the reads are only zero. But I'm always afraid of opening
>> precedence for this kind of assumptions and end up stepping
>> over some reserved bit that hw is using for something else
>> but not documented.
>
> We do this in other places too in order to keep the code
> simple. I think it's fine for cases where all old platforms
> had a smaller bitfield which is extended in later platforms.
> That is, assuming all the bits were unused (and read as zero)
> in the old platforms, which is the case here.
>
> The thing we probably shouldn't do is make the bitfield larger
> proactively for future platforms since we can't know if some of
> the currently unused bits might end up being used for something
> else in the future.
>
> I really hope we don't have any undocumented bits anywhere since
> those can screw us up in a lot more ways than this. If we do find
> any undocuemnted bits we really need to file bspec issues for those.

I guess I'd record some of this in the commit message while applying, in
case this blows up. Other than that,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Clean up PIPEMISC register defines

[Jani Nikula]

On Fri, 12 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_BIT() & co. for PIPEMISC* bits, and while at it
> fill in the missing dithering bits since we already had some
> of them defined.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 18 +++++-----
>  drivers/gpu/drm/i915/i915_reg.h              | 35 +++++++++++---------
>  2 files changed, 28 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6073f94632ab..e293241450b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3724,18 +3724,18 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
>  
>  	switch (crtc_state->pipe_bpp) {
>  	case 18:
> -		val |= PIPEMISC_6_BPC;
> +		val |= PIPEMISC_BPC_6;
>  		break;
>  	case 24:
> -		val |= PIPEMISC_8_BPC;
> +		val |= PIPEMISC_BPC_8;
>  		break;
>  	case 30:
> -		val |= PIPEMISC_10_BPC;
> +		val |= PIPEMISC_BPC_10;
>  		break;
>  	case 36:
>  		/* Port output 12BPC defined for ADLP+ */
>  		if (DISPLAY_VER(dev_priv) > 12)
> -			val |= PIPEMISC_12_BPC_ADLP;
> +			val |= PIPEMISC_BPC_12_ADLP;
>  		break;
>  	default:
>  		MISSING_CASE(crtc_state->pipe_bpp);
> @@ -3771,7 +3771,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
>  		}
>  
>  		intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
> -			     PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
> +			     PIPE_MISC2_BUBBLE_COUNTER_MASK,
>  			     scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
>  			     PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
>  	}
> @@ -3787,11 +3787,11 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
>  	tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
>  
>  	switch (tmp & PIPEMISC_BPC_MASK) {
> -	case PIPEMISC_6_BPC:
> +	case PIPEMISC_BPC_6:
>  		return 18;
> -	case PIPEMISC_8_BPC:
> +	case PIPEMISC_BPC_8:
>  		return 24;
> -	case PIPEMISC_10_BPC:
> +	case PIPEMISC_BPC_10:
>  		return 30;
>  	/*
>  	 * PORT OUTPUT 12 BPC defined for ADLP+.
> @@ -3803,7 +3803,7 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
>  	 * on older platforms, need to find a workaround for 12 BPC
>  	 * MIPI DSI HW readout.
>  	 */
> -	case PIPEMISC_12_BPC_ADLP:
> +	case PIPEMISC_BPC_12_ADLP:
>  		if (DISPLAY_VER(dev_priv) > 12)
>  			return 36;
>  		fallthrough;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f5d54ed2efc1..e300a202ce2d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6308,32 +6308,35 @@ enum {
>  
>  #define _PIPE_MISC_A			0x70030
>  #define _PIPE_MISC_B			0x71030
> -#define   PIPEMISC_YUV420_ENABLE	(1 << 27) /* glk+ */
> -#define   PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
> -#define   PIPEMISC_HDR_MODE_PRECISION	(1 << 23) /* icl+ */
> -#define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1 << 11)
> -#define   PIPEMISC_PIXEL_ROUNDING_TRUNC	REG_BIT(8) /* tgl+ */
> +#define   PIPEMISC_YUV420_ENABLE		REG_BIT(27) /* glk+ */
> +#define   PIPEMISC_YUV420_MODE_FULL_BLEND	REG_BIT(26) /* glk+ */
> +#define   PIPEMISC_HDR_MODE_PRECISION		REG_BIT(23) /* icl+ */
> +#define   PIPEMISC_OUTPUT_COLORSPACE_YUV	REG_BIT(11)
> +#define   PIPEMISC_PIXEL_ROUNDING_TRUNC		REG_BIT(8) /* tgl+ */
>  /*
>   * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
>   * valid values of: 6, 8, 10 BPC.
>   * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
>   * 6, 8, 10, 12 BPC.
>   */
> -#define   PIPEMISC_BPC_MASK		(7 << 5)
> -#define   PIPEMISC_8_BPC		(0 << 5)
> -#define   PIPEMISC_10_BPC		(1 << 5)
> -#define   PIPEMISC_6_BPC		(2 << 5)
> -#define   PIPEMISC_12_BPC_ADLP		(4 << 5) /* adlp+ */
> -#define   PIPEMISC_DITHER_ENABLE	(1 << 4)
> -#define   PIPEMISC_DITHER_TYPE_MASK	(3 << 2)
> -#define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
> +#define   PIPEMISC_BPC_MASK			REG_GENMASK(7, 5)
> +#define   PIPEMISC_BPC_8			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)
> +#define   PIPEMISC_BPC_10			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1)
> +#define   PIPEMISC_BPC_6			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2)
> +#define   PIPEMISC_BPC_12_ADLP			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */
> +#define   PIPEMISC_DITHER_ENABLE		REG_BIT(4)
> +#define   PIPEMISC_DITHER_TYPE_MASK		REG_GENMASK(3, 2)
> +#define   PIPEMISC_DITHER_TYPE_SP		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0)
> +#define   PIPEMISC_DITHER_TYPE_ST1		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1)
> +#define   PIPEMISC_DITHER_TYPE_ST2		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2)
> +#define   PIPEMISC_DITHER_TYPE_TEMP		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3)
>  #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)
>  
>  #define _PIPE_MISC2_A					0x7002C
>  #define _PIPE_MISC2_B					0x7102C
> -#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN		(0x50 << 24)
> -#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS		(0x14 << 24)
> -#define   PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK	(0xff << 24)
> +#define   PIPE_MISC2_BUBBLE_COUNTER_MASK	REG_GENMASK(31, 24)
> +#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
> +#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
>  #define PIPE_MISC2(pipe)					_MMIO_PIPE2(pipe, _PIPE_MISC2_A)
>  
>  /* Skylake+ pipe bottom (background) color */

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 5/9] drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit defines

[Jani Nikula]

On Fri, 12 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_BIT & co. for PCH_TRANSCONF/TRANS_DP_CTL bits, and
> adjust the naming a some bits to be more consistent.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_pch_display.c  | 13 +++--
>  drivers/gpu/drm/i915/i915_reg.h               | 58 +++++++++----------
>  2 files changed, 33 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 81ab761251ae..155c2d19a6bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -166,11 +166,11 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
>  	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) {
>  		if (HAS_PCH_IBX(dev_priv) &&
>  		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
> -			val |= TRANS_LEGACY_INTERLACED_ILK;
> +			val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
>  		else
> -			val |= TRANS_INTERLACED;
> +			val |= TRANS_INTERLACE_INTERLACED;
>  	} else {
> -		val |= TRANS_PROGRESSIVE;
> +		val |= TRANS_INTERLACE_PROGRESSIVE;
>  	}
>  
>  	intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
> @@ -279,7 +279,8 @@ void ilk_pch_enable(struct intel_atomic_state *state,
>  
>  		temp = intel_de_read(dev_priv, reg);
>  		temp &= ~(TRANS_DP_PORT_SEL_MASK |
> -			  TRANS_DP_SYNC_MASK |
> +			  TRANS_DP_VSYNC_ACTIVE_HIGH |
> +			  TRANS_DP_HSYNC_ACTIVE_HIGH |
>  			  TRANS_DP_BPC_MASK);
>  		temp |= TRANS_DP_OUTPUT_ENABLE;
>  		temp |= bpc << 9; /* same format but at 11:9 */
> @@ -423,9 +424,9 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
>  	pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
>  
>  	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK)
> -		val |= TRANS_INTERLACED;
> +		val |= TRANS_INTERLACE_INTERLACED;
>  	else
> -		val |= TRANS_PROGRESSIVE;
> +		val |= TRANS_INTERLACE_PROGRESSIVE;
>  
>  	intel_de_write(dev_priv, LPT_TRANSCONF, val);
>  	if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d2d5b2fa2a4a..eea009e76e15 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8994,22 +8994,19 @@ enum {
>  #define _PCH_TRANSBCONF              0xf1008
>  #define PCH_TRANSCONF(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
>  #define LPT_TRANSCONF		PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
> -#define  TRANS_DISABLE          (0 << 31)
> -#define  TRANS_ENABLE           (1 << 31)
> -#define  TRANS_STATE_MASK       (1 << 30)
> -#define  TRANS_STATE_DISABLE    (0 << 30)
> -#define  TRANS_STATE_ENABLE     (1 << 30)
> -#define  TRANS_FRAME_START_DELAY_MASK	(3 << 27) /* ibx */
> -#define  TRANS_FRAME_START_DELAY(x)	((x) << 27) /* ibx: 0-3 */
> -#define  TRANS_INTERLACE_MASK   (7 << 21)
> -#define  TRANS_PROGRESSIVE      (0 << 21)
> -#define  TRANS_INTERLACED       (3 << 21)
> -#define  TRANS_LEGACY_INTERLACED_ILK (2 << 21)
> -#define  TRANS_8BPC             (0 << 5)
> -#define  TRANS_10BPC            (1 << 5)
> -#define  TRANS_6BPC             (2 << 5)
> -#define  TRANS_12BPC            (3 << 5)
> -
> +#define  TRANS_ENABLE			REG_BIT(31)
> +#define  TRANS_STATE_ENABLE		REG_BIT(30)
> +#define  TRANS_FRAME_START_DELAY_MASK	REG_GENMASK(28, 27) /* ibx */
> +#define  TRANS_FRAME_START_DELAY(x)	REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
> +#define  TRANS_INTERLACE_MASK		REG_GENMASK(23, 21)
> +#define  TRANS_INTERLACE_PROGRESSIVE	REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
> +#define  TRANS_INTERLACE_LEGACY_VSYNC_IBX	REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
> +#define  TRANS_INTERLACE_INTERLACED	REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
> +#define  TRANS_BPC_MASK			REG_GENMASK(7, 5) /* ibx */
> +#define  TRANS_BPC_8			REG_FIELD_PREP(TRANS_BPC_MASK, 0)
> +#define  TRANS_BPC_10			REG_FIELD_PREP(TRANS_BPC_MASK, 1)
> +#define  TRANS_BPC_6			REG_FIELD_PREP(TRANS_BPC_MASK, 2)
> +#define  TRANS_BPC_12			REG_FIELD_PREP(TRANS_BPC_MASK, 3)
>  #define _TRANSA_CHICKEN1	 0xf0060
>  #define _TRANSB_CHICKEN1	 0xf1060
>  #define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
> @@ -9219,22 +9216,19 @@ enum {
>  #define _TRANS_DP_CTL_B		0xe1300
>  #define _TRANS_DP_CTL_C		0xe2300
>  #define TRANS_DP_CTL(pipe)	_MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
> -#define  TRANS_DP_OUTPUT_ENABLE	(1 << 31)
> -#define  TRANS_DP_PORT_SEL_MASK		(3 << 29)
> -#define  TRANS_DP_PORT_SEL_NONE		(3 << 29)
> -#define  TRANS_DP_PORT_SEL(port)	(((port) - PORT_B) << 29)
> -#define  TRANS_DP_AUDIO_ONLY	(1 << 26)
> -#define  TRANS_DP_ENH_FRAMING	(1 << 18)
> -#define  TRANS_DP_8BPC		(0 << 9)
> -#define  TRANS_DP_10BPC		(1 << 9)
> -#define  TRANS_DP_6BPC		(2 << 9)
> -#define  TRANS_DP_12BPC		(3 << 9)
> -#define  TRANS_DP_BPC_MASK	(3 << 9)
> -#define  TRANS_DP_VSYNC_ACTIVE_HIGH	(1 << 4)
> -#define  TRANS_DP_VSYNC_ACTIVE_LOW	0
> -#define  TRANS_DP_HSYNC_ACTIVE_HIGH	(1 << 3)
> -#define  TRANS_DP_HSYNC_ACTIVE_LOW	0
> -#define  TRANS_DP_SYNC_MASK	(3 << 3)
> +#define  TRANS_DP_OUTPUT_ENABLE		REG_BIT(31)
> +#define  TRANS_DP_PORT_SEL_MASK		REG_GENMASK(30, 29)
> +#define  TRANS_DP_PORT_SEL_NONE		REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
> +#define  TRANS_DP_PORT_SEL(port)	REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
> +#define  TRANS_DP_AUDIO_ONLY		REG_BIT(26)
> +#define  TRANS_DP_ENH_FRAMING		REG_BIT(18)
> +#define  TRANS_DP_BPC_MASK		REG_GENMASK(10, 9)
> +#define  TRANS_DP_BPC_8			REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
> +#define  TRANS_DP_BPC_10		REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
> +#define  TRANS_DP_BPC_6			REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
> +#define  TRANS_DP_BPC_12		REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
> +#define  TRANS_DP_VSYNC_ACTIVE_HIGH	REG_BIT(4)
> +#define  TRANS_DP_HSYNC_ACTIVE_HIGH	REG_BIT(3)
>  
>  #define _TRANS_DP2_CTL_A			0x600a0
>  #define _TRANS_DP2_CTL_B			0x610a0

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 6/9] drm/i915: Clean up PIPESRC defines

[Jani Nikula]

On Fri, 12 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_GENMASK() & co. when dealing with PIPESRC.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/i9xx_plane.c    | 4 ++--
>  drivers/gpu/drm/i915/display/intel_display.c | 7 ++++---
>  drivers/gpu/drm/i915/i915_reg.h              | 4 ++++
>  3 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 2194f74101ae..f586e39cb378 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -1048,8 +1048,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
>  	plane_config->base = base;
>  
>  	val = intel_de_read(dev_priv, PIPESRC(pipe));
> -	fb->width = ((val >> 16) & 0xfff) + 1;
> -	fb->height = ((val >> 0) & 0xfff) + 1;

I guess the mask width change is worth noting in the commit message.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +	fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
> +	fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
>  
>  	val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
>  	fb->pitches[0] = val & 0xffffffc0;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4e29032b29d6..e1959a17805c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3236,7 +3236,8 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
>  	 * always be the user's requested size.
>  	 */
>  	intel_de_write(dev_priv, PIPESRC(pipe),
> -		       ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
> +		       PIPESRC_WIDTH(crtc_state->pipe_src_w - 1) |
> +		       PIPESRC_HEIGHT(crtc_state->pipe_src_h - 1));
>  }
>  
>  static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
> @@ -3307,8 +3308,8 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
>  	u32 tmp;
>  
>  	tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
> -	pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
> -	pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
> +	pipe_config->pipe_src_w = REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1;
> +	pipe_config->pipe_src_h = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1;
>  }
>  
>  static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eea009e76e15..211e2b415e50 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4476,6 +4476,10 @@ enum {
>  #define _VSYNC_A	0x60014
>  #define _EXITLINE_A	0x60018
>  #define _PIPEASRC	0x6001c
> +#define   PIPESRC_WIDTH_MASK	REG_GENMASK(31, 16)
> +#define   PIPESRC_WIDTH(w)	REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
> +#define   PIPESRC_HEIGHT_MASK	REG_GENMASK(15, 0)
> +#define   PIPESRC_HEIGHT(h)	REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
>  #define _BCLRPAT_A	0x60020
>  #define _VSYNCSHIFT_A	0x60028
>  #define _PIPE_MULT_A	0x6002c

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 6/9] drm/i915: Clean up PIPESRC defines

[Ville Syrjälä]

On Wed, Jan 26, 2022 at 04:42:52PM +0200, Jani Nikula wrote:
> On Fri, 12 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Use REG_GENMASK() & co. when dealing with PIPESRC.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/i9xx_plane.c    | 4 ++--
> >  drivers/gpu/drm/i915/display/intel_display.c | 7 ++++---
> >  drivers/gpu/drm/i915/i915_reg.h              | 4 ++++
> >  3 files changed, 10 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> > index 2194f74101ae..f586e39cb378 100644
> > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> > @@ -1048,8 +1048,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
> >  	plane_config->base = base;
> >  
> >  	val = intel_de_read(dev_priv, PIPESRC(pipe));
> > -	fb->width = ((val >> 16) & 0xfff) + 1;
> > -	fb->height = ((val >> 0) & 0xfff) + 1;
> 
> I guess the mask width change is worth noting in the commit message.

Aye. I added a few notes about this and the DSL stuff.

> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Thanks. Series pushed to drm-intel-next.

-- 
Ville Syrjälä
Intel