* [Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing
@ 2020-02-06 1:44 Chris Wilson
2020-02-06 1:44 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Set the PP_DIR registers upon enabling ring submission Chris Wilson
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Chris Wilson @ 2020-02-06 1:44 UTC (permalink / raw)
To: intel-gfx
Don't immediately write the seqno into the breadcrumb slot, but wait
until we've attempted to flush the writes; that is we need to ensure the
memory is coherent prior to updating the breadcrumb so that any
observers who see the new seqno can proceed.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 24 ++++++++++++-------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 9537d4912225..42168d7cf5b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -446,31 +446,39 @@ static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
return cs;
}
-#define GEN7_XCS_WA 32
-static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
+#define GEN7_XCS_WA 8
+static u32 *
+__gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 addr, u32 *cs)
{
int i;
- GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
- GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
-
*cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |
MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
- *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
+ *cs++ = addr | MI_FLUSH_DW_USE_GTT;
*cs++ = rq->fence.seqno;
for (i = 0; i < GEN7_XCS_WA; i++) {
*cs++ = MI_STORE_DWORD_INDEX;
- *cs++ = I915_GEM_HWS_SEQNO_ADDR;
+ *cs++ = addr;
*cs++ = rq->fence.seqno;
}
+ return cs;
+}
+
+static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
+{
+ GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
+ GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
+
+ cs = __gen7_xcs_emit_breadcrumb(rq, I915_GEM_HWS_SEQNO_ADDR + 4, cs);
+ cs = __gen7_xcs_emit_breadcrumb(rq, I915_GEM_HWS_SEQNO_ADDR, cs);
+
*cs++ = MI_FLUSH_DW;
*cs++ = 0;
*cs++ = 0;
*cs++ = MI_USER_INTERRUPT;
- *cs++ = MI_NOOP;
rq->tail = intel_ring_offset(rq, cs);
assert_ring_tail_valid(rq->ring, rq->tail);
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/gt: Set the PP_DIR registers upon enabling ring submission
2020-02-06 1:44 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing Chris Wilson
@ 2020-02-06 1:44 ` Chris Wilson
2020-02-06 16:14 ` Mika Kuoppala
2020-02-06 1:44 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: Stop invalidating the PD cachelines for gen7 Chris Wilson
` (4 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Chris Wilson @ 2020-02-06 1:44 UTC (permalink / raw)
To: intel-gfx
Always prime the page table registers before starting the ring. Even
though we will update these to the per-context page tables during
dispatch, it is prudent to ensure that the registers always point to a
valid PD.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 40 ++++++++++++-------
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 42168d7cf5b5..f915a63e1110 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -635,6 +635,27 @@ static bool stop_ring(struct intel_engine_cs *engine)
return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0;
}
+static struct i915_address_space *vm_alias(struct i915_address_space *vm)
+{
+ if (i915_is_ggtt(vm))
+ vm = &i915_vm_to_ggtt(vm)->alias->vm;
+
+ return vm;
+}
+
+static void set_pp_dir(struct intel_engine_cs *engine)
+{
+ struct i915_address_space *vm = vm_alias(engine->gt->vm);
+
+ if (vm) {
+ struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+
+ ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
+ ENGINE_WRITE(engine, RING_PP_DIR_BASE,
+ px_base(ppgtt->pd)->ggtt_offset << 10);
+ }
+}
+
static int xcs_resume(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
@@ -693,6 +714,8 @@ static int xcs_resume(struct intel_engine_cs *engine)
GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
intel_ring_update_space(ring);
+ set_pp_dir(engine);
+
/* First wake the ring up to an empty/idle ring */
ENGINE_WRITE(engine, RING_HEAD, ring->head);
ENGINE_WRITE(engine, RING_TAIL, ring->head);
@@ -1169,23 +1192,12 @@ static void ring_context_destroy(struct kref *ref)
intel_context_free(ce);
}
-static struct i915_address_space *vm_alias(struct intel_context *ce)
-{
- struct i915_address_space *vm;
-
- vm = ce->vm;
- if (i915_is_ggtt(vm))
- vm = &i915_vm_to_ggtt(vm)->alias->vm;
-
- return vm;
-}
-
static int __context_pin_ppgtt(struct intel_context *ce)
{
struct i915_address_space *vm;
int err = 0;
- vm = vm_alias(ce);
+ vm = vm_alias(ce->vm);
if (vm)
err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)));
@@ -1196,7 +1208,7 @@ static void __context_unpin_ppgtt(struct intel_context *ce)
{
struct i915_address_space *vm;
- vm = vm_alias(ce);
+ vm = vm_alias(ce->vm);
if (vm)
gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm));
}
@@ -1553,7 +1565,7 @@ static int switch_context(struct i915_request *rq)
GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
- ret = switch_mm(rq, vm_alias(ce));
+ ret = switch_mm(rq, vm_alias(ce->vm));
if (ret)
return ret;
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/gt: Stop invalidating the PD cachelines for gen7
2020-02-06 1:44 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing Chris Wilson
2020-02-06 1:44 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Set the PP_DIR registers upon enabling ring submission Chris Wilson
@ 2020-02-06 1:44 ` Chris Wilson
2020-02-06 16:32 ` Mika Kuoppala
2020-02-06 4:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing Patchwork
` (3 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Chris Wilson @ 2020-02-06 1:44 UTC (permalink / raw)
To: intel-gfx
Trust that the HW does the right thing after simply updating the
PD_DIR_BASE?
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index f915a63e1110..23f4fc2669d1 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1341,14 +1341,10 @@ static int load_pd_dir(struct i915_request *rq,
const struct intel_engine_cs * const engine = rq->engine;
u32 *cs;
- cs = intel_ring_begin(rq, 12);
+ cs = intel_ring_begin(rq, 6);
if (IS_ERR(cs))
return PTR_ERR(cs);
- *cs++ = MI_LOAD_REGISTER_IMM(1);
- *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
- *cs++ = valid;
-
*cs++ = MI_LOAD_REGISTER_IMM(1);
*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
*cs++ = px_base(ppgtt->pd)->ggtt_offset << 10;
@@ -1359,10 +1355,6 @@ static int load_pd_dir(struct i915_request *rq,
*cs++ = intel_gt_scratch_offset(engine->gt,
INTEL_GT_SCRATCH_FIELD_DEFAULT);
- *cs++ = MI_LOAD_REGISTER_IMM(1);
- *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));
- *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
-
intel_ring_advance(rq, cs);
return rq->engine->emit_flush(rq, EMIT_FLUSH);
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing
2020-02-06 1:44 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing Chris Wilson
2020-02-06 1:44 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Set the PP_DIR registers upon enabling ring submission Chris Wilson
2020-02-06 1:44 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: Stop invalidating the PD cachelines for gen7 Chris Wilson
@ 2020-02-06 4:07 ` Patchwork
2020-02-06 4:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-02-06 4:07 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing
URL : https://patchwork.freedesktop.org/series/73068/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
be0c11af059b drm/i915/gt: Tweak gen7 xcs flushing
-:51: WARNING:LONG_LINE: line over 100 characters
#51: FILE: drivers/gpu/drm/i915/gt/intel_ring_submission.c:472:
+ GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
total: 0 errors, 1 warnings, 0 checks, 47 lines checked
ffb456a12e2a drm/i915/gt: Set the PP_DIR registers upon enabling ring submission
9a7a58a2f90a drm/i915/gt: Stop invalidating the PD cachelines for gen7
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing
2020-02-06 1:44 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing Chris Wilson
` (2 preceding siblings ...)
2020-02-06 4:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing Patchwork
@ 2020-02-06 4:36 ` Patchwork
2020-02-06 16:35 ` [Intel-gfx] [PATCH 1/3] " Mika Kuoppala
2020-02-08 16:35 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] " Patchwork
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-02-06 4:36 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing
URL : https://patchwork.freedesktop.org/series/73068/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7874 -> Patchwork_16450
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/index.html
Known issues
------------
Here are the changes found in Patchwork_16450 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_close_race@basic-threads:
- fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-byt-j1900/igt@gem_close_race@basic-threads.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-byt-j1900/igt@gem_close_race@basic-threads.html
* igt@gem_flink_basic@bad-flink:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([CI#94] / [i915#402])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-tgl-y/igt@gem_flink_basic@bad-flink.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-tgl-y/igt@gem_flink_basic@bad-flink.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770: [PASS][5] -> [DMESG-FAIL][6] ([i915#553] / [i915#725])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-hsw-4770/igt@i915_selftest@live_blt.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-hsw-4770/igt@i915_selftest@live_blt.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-tgl-y: [FAIL][7] ([CI#94]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_selftest@live_gem_contexts:
- fi-byt-n2820: [DMESG-FAIL][9] ([i915#722]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
* igt@kms_addfb_basic@addfb25-bad-modifier:
- fi-tgl-y: [DMESG-WARN][11] ([CI#94] / [i915#402]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-tgl-y/igt@kms_addfb_basic@addfb25-bad-modifier.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-tgl-y/igt@kms_addfb_basic@addfb25-bad-modifier.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [FAIL][13] ([fdo#109635] / [i915#217]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
#### Warnings ####
* igt@gem_exec_parallel@contexts:
- fi-byt-n2820: [TIMEOUT][15] ([fdo#112271] / [i915#1084]) -> [FAIL][16] ([i915#694])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084
[i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
Participating hosts (51 -> 42)
------------------------------
Missing (9): fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-cfl-8109u fi-kbl-7560u fi-byt-clapper fi-bsw-nick fi-bdw-samus fi-kbl-r
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7874 -> Patchwork_16450
CI-20190529: 20190529
CI_DRM_7874: 3f234d1ab91ec2321312150116c1285bcb0a260b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5420: 497e13d2b4c1053bcd01bd15739fef55e7694a03 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16450: 9a7a58a2f90a9615540ad59a219bbfcb92ef66fa @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9a7a58a2f90a drm/i915/gt: Stop invalidating the PD cachelines for gen7
ffb456a12e2a drm/i915/gt: Set the PP_DIR registers upon enabling ring submission
be0c11af059b drm/i915/gt: Tweak gen7 xcs flushing
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Set the PP_DIR registers upon enabling ring submission
2020-02-06 1:44 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Set the PP_DIR registers upon enabling ring submission Chris Wilson
@ 2020-02-06 16:14 ` Mika Kuoppala
0 siblings, 0 replies; 11+ messages in thread
From: Mika Kuoppala @ 2020-02-06 16:14 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Always prime the page table registers before starting the ring. Even
> though we will update these to the per-context page tables during
> dispatch, it is prudent to ensure that the registers always point to a
> valid PD.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> .../gpu/drm/i915/gt/intel_ring_submission.c | 40 ++++++++++++-------
> 1 file changed, 26 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 42168d7cf5b5..f915a63e1110 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -635,6 +635,27 @@ static bool stop_ring(struct intel_engine_cs *engine)
> return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0;
> }
>
> +static struct i915_address_space *vm_alias(struct i915_address_space *vm)
> +{
> + if (i915_is_ggtt(vm))
> + vm = &i915_vm_to_ggtt(vm)->alias->vm;
> +
> + return vm;
> +}
> +
> +static void set_pp_dir(struct intel_engine_cs *engine)
> +{
> + struct i915_address_space *vm = vm_alias(engine->gt->vm);
> +
> + if (vm) {
> + struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> +
> + ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
I did think that for setup we set these zero first. But it seems
pointless. They should be zero after reset anywasy.
> + ENGINE_WRITE(engine, RING_PP_DIR_BASE,
> + px_base(ppgtt->pd)->ggtt_offset << 10);
Shift for 16 and then index by cacheline so 16-6 it seems.
> + }
> +}
> +
> static int xcs_resume(struct intel_engine_cs *engine)
> {
> struct drm_i915_private *dev_priv = engine->i915;
> @@ -693,6 +714,8 @@ static int xcs_resume(struct intel_engine_cs *engine)
> GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
> intel_ring_update_space(ring);
>
> + set_pp_dir(engine);
> +
Then rings are off and we start by setting up the pd.
Can't figure out a better spot.
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> /* First wake the ring up to an empty/idle ring */
> ENGINE_WRITE(engine, RING_HEAD, ring->head);
> ENGINE_WRITE(engine, RING_TAIL, ring->head);
> @@ -1169,23 +1192,12 @@ static void ring_context_destroy(struct kref *ref)
> intel_context_free(ce);
> }
>
> -static struct i915_address_space *vm_alias(struct intel_context *ce)
> -{
> - struct i915_address_space *vm;
> -
> - vm = ce->vm;
> - if (i915_is_ggtt(vm))
> - vm = &i915_vm_to_ggtt(vm)->alias->vm;
> -
> - return vm;
> -}
> -
> static int __context_pin_ppgtt(struct intel_context *ce)
> {
> struct i915_address_space *vm;
> int err = 0;
>
> - vm = vm_alias(ce);
> + vm = vm_alias(ce->vm);
> if (vm)
> err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)));
>
> @@ -1196,7 +1208,7 @@ static void __context_unpin_ppgtt(struct intel_context *ce)
> {
> struct i915_address_space *vm;
>
> - vm = vm_alias(ce);
> + vm = vm_alias(ce->vm);
> if (vm)
> gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm));
> }
> @@ -1553,7 +1565,7 @@ static int switch_context(struct i915_request *rq)
>
> GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
>
> - ret = switch_mm(rq, vm_alias(ce));
> + ret = switch_mm(rq, vm_alias(ce->vm));
> if (ret)
> return ret;
>
> --
> 2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/gt: Stop invalidating the PD cachelines for gen7
2020-02-06 1:44 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: Stop invalidating the PD cachelines for gen7 Chris Wilson
@ 2020-02-06 16:32 ` Mika Kuoppala
2020-02-06 19:26 ` Chris Wilson
0 siblings, 1 reply; 11+ messages in thread
From: Mika Kuoppala @ 2020-02-06 16:32 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Trust that the HW does the right thing after simply updating the
> PD_DIR_BASE?
Bspec offers an invalidate before writing the base.
So, lets assume the DCLV write is superfluous as it will be
the same.
Then the sequence would be TLB_INVLIDATE followed by
PP_DIR_BASE (which will all pds)
-Mika
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_ring_submission.c | 10 +---------
> 1 file changed, 1 insertion(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index f915a63e1110..23f4fc2669d1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -1341,14 +1341,10 @@ static int load_pd_dir(struct i915_request *rq,
> const struct intel_engine_cs * const engine = rq->engine;
> u32 *cs;
>
> - cs = intel_ring_begin(rq, 12);
> + cs = intel_ring_begin(rq, 6);
> if (IS_ERR(cs))
> return PTR_ERR(cs);
>
> - *cs++ = MI_LOAD_REGISTER_IMM(1);
> - *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
> - *cs++ = valid;
> -
> *cs++ = MI_LOAD_REGISTER_IMM(1);
> *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
> *cs++ = px_base(ppgtt->pd)->ggtt_offset << 10;
> @@ -1359,10 +1355,6 @@ static int load_pd_dir(struct i915_request *rq,
> *cs++ = intel_gt_scratch_offset(engine->gt,
> INTEL_GT_SCRATCH_FIELD_DEFAULT);
>
> - *cs++ = MI_LOAD_REGISTER_IMM(1);
> - *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));
> - *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
> -
> intel_ring_advance(rq, cs);
>
> return rq->engine->emit_flush(rq, EMIT_FLUSH);
> --
> 2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing
2020-02-06 1:44 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing Chris Wilson
` (3 preceding siblings ...)
2020-02-06 4:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-02-06 16:35 ` Mika Kuoppala
2020-02-06 19:27 ` Chris Wilson
2020-02-08 16:35 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] " Patchwork
5 siblings, 1 reply; 11+ messages in thread
From: Mika Kuoppala @ 2020-02-06 16:35 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Don't immediately write the seqno into the breadcrumb slot, but wait
> until we've attempted to flush the writes; that is we need to ensure the
> memory is coherent prior to updating the breadcrumb so that any
> observers who see the new seqno can proceed.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> .../gpu/drm/i915/gt/intel_ring_submission.c | 24 ++++++++++++-------
> 1 file changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 9537d4912225..42168d7cf5b5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -446,31 +446,39 @@ static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> return cs;
> }
>
> -#define GEN7_XCS_WA 32
> -static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> +#define GEN7_XCS_WA 8
> +static u32 *
> +__gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 addr, u32 *cs)
> {
> int i;
>
> - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
> - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
> -
> *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |
> MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
> - *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
> + *cs++ = addr | MI_FLUSH_DW_USE_GTT;
> *cs++ = rq->fence.seqno;
>
> for (i = 0; i < GEN7_XCS_WA; i++) {
> *cs++ = MI_STORE_DWORD_INDEX;
> - *cs++ = I915_GEM_HWS_SEQNO_ADDR;
> + *cs++ = addr;
> *cs++ = rq->fence.seqno;
> }
>
> + return cs;
> +}
> +
> +static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> +{
> + GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
> + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
> +
> + cs = __gen7_xcs_emit_breadcrumb(rq, I915_GEM_HWS_SEQNO_ADDR + 4, cs);
One fake for the above before the real thing?
-Mika
> + cs = __gen7_xcs_emit_breadcrumb(rq, I915_GEM_HWS_SEQNO_ADDR, cs);
> +
> *cs++ = MI_FLUSH_DW;
> *cs++ = 0;
> *cs++ = 0;
>
> *cs++ = MI_USER_INTERRUPT;
> - *cs++ = MI_NOOP;
>
> rq->tail = intel_ring_offset(rq, cs);
> assert_ring_tail_valid(rq->ring, rq->tail);
> --
> 2.25.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/gt: Stop invalidating the PD cachelines for gen7
2020-02-06 16:32 ` Mika Kuoppala
@ 2020-02-06 19:26 ` Chris Wilson
0 siblings, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2020-02-06 19:26 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2020-02-06 16:32:22)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > Trust that the HW does the right thing after simply updating the
> > PD_DIR_BASE?
>
> Bspec offers an invalidate before writing the base.
>
> So, lets assume the DCLV write is superfluous as it will be
> the same.
>
> Then the sequence would be TLB_INVLIDATE followed by
> PP_DIR_BASE (which will all pds)
I can recommend not doing the
*cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
first.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing
2020-02-06 16:35 ` [Intel-gfx] [PATCH 1/3] " Mika Kuoppala
@ 2020-02-06 19:27 ` Chris Wilson
0 siblings, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2020-02-06 19:27 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2020-02-06 16:35:12)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > Don't immediately write the seqno into the breadcrumb slot, but wait
> > until we've attempted to flush the writes; that is we need to ensure the
> > memory is coherent prior to updating the breadcrumb so that any
> > observers who see the new seqno can proceed.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> > .../gpu/drm/i915/gt/intel_ring_submission.c | 24 ++++++++++++-------
> > 1 file changed, 16 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > index 9537d4912225..42168d7cf5b5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > @@ -446,31 +446,39 @@ static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> > return cs;
> > }
> >
> > -#define GEN7_XCS_WA 32
> > -static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> > +#define GEN7_XCS_WA 8
> > +static u32 *
> > +__gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 addr, u32 *cs)
> > {
> > int i;
> >
> > - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
> > - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
> > -
> > *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |
> > MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
> > - *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
> > + *cs++ = addr | MI_FLUSH_DW_USE_GTT;
> > *cs++ = rq->fence.seqno;
> >
> > for (i = 0; i < GEN7_XCS_WA; i++) {
> > *cs++ = MI_STORE_DWORD_INDEX;
> > - *cs++ = I915_GEM_HWS_SEQNO_ADDR;
> > + *cs++ = addr;
> > *cs++ = rq->fence.seqno;
> > }
> >
> > + return cs;
> > +}
> > +
> > +static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
> > +{
> > + GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
> > + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
> > +
> > + cs = __gen7_xcs_emit_breadcrumb(rq, I915_GEM_HWS_SEQNO_ADDR + 4, cs);
>
> One fake for the above before the real thing?
That's what I did later. Doesn't seem to make much difference either
way, but confirmation bias says at least 1 fake is better.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing
2020-02-06 1:44 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing Chris Wilson
` (4 preceding siblings ...)
2020-02-06 16:35 ` [Intel-gfx] [PATCH 1/3] " Mika Kuoppala
@ 2020-02-08 16:35 ` Patchwork
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-02-08 16:35 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing
URL : https://patchwork.freedesktop.org/series/73068/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7874_full -> Patchwork_16450_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_16450_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-kbl7/igt@gem_ctx_isolation@rcs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-kbl4/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_shared@exec-single-timeline-bsd1:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +11 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd1.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-iclb7/igt@gem_ctx_shared@exec-single-timeline-bsd1.html
* igt@gem_exec_schedule@pi-shared-iova-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#677])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-iclb8/igt@gem_exec_schedule@pi-shared-iova-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-iclb1/igt@gem_exec_schedule@pi-shared-iova-bsd.html
* igt@gem_exec_schedule@preempt-contexts-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-iclb5/igt@gem_exec_schedule@preempt-contexts-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-iclb2/igt@gem_exec_schedule@preempt-contexts-bsd.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#644])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-glk8/igt@gem_ppgtt@flink-and-close-vma-leak.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-glk2/igt@gem_ppgtt@flink-and-close-vma-leak.html
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#644])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-tglb7/igt@gem_ppgtt@flink-and-close-vma-leak.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-tglb1/igt@gem_ppgtt@flink-and-close-vma-leak.html
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#644])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-skl9/igt@gem_ppgtt@flink-and-close-vma-leak.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-skl7/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gen7_exec_parse@basic-allocation:
- shard-hsw: [PASS][15] -> [FAIL][16] ([i915#694]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-hsw8/igt@gen7_exec_parse@basic-allocation.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-hsw8/igt@gen7_exec_parse@basic-allocation.html
* igt@i915_pm_rpm@legacy-planes:
- shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([fdo#109960] / [i915#189])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-iclb5/igt@i915_pm_rpm@legacy-planes.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-iclb4/igt@i915_pm_rpm@legacy-planes.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [PASS][19] -> [INCOMPLETE][20] ([i915#151] / [i915#69])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-skl8/igt@i915_pm_rpm@system-suspend-execbuf.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-skl1/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@i915_pm_rps@min-max-config-loaded:
- shard-iclb: [PASS][21] -> [FAIL][22] ([i915#370])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-iclb3/igt@i915_pm_rps@min-max-config-loaded.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-iclb6/igt@i915_pm_rps@min-max-config-loaded.html
* igt@i915_pm_rps@reset:
- shard-iclb: [PASS][23] -> [FAIL][24] ([i915#413])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-iclb3/igt@i915_pm_rps@reset.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-iclb5/igt@i915_pm_rps@reset.html
* igt@i915_selftest@live_blt:
- shard-hsw: [PASS][25] -> [DMESG-FAIL][26] ([i915#725])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-hsw5/igt@i915_selftest@live_blt.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-hsw8/igt@i915_selftest@live_blt.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][27] -> [FAIL][28] ([i915#79])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +3 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-glk: [PASS][31] -> [FAIL][32] ([i915#899])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-glk5/igt@kms_plane_lowres@pipe-a-tiling-x.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-glk4/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@perf_pmu@init-busy-vcs1:
- shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#112080]) +8 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-iclb1/igt@perf_pmu@init-busy-vcs1.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-iclb3/igt@perf_pmu@init-busy-vcs1.html
#### Possible fixes ####
* igt@gem_blits@basic:
- shard-kbl: [DMESG-WARN][37] ([i915#836]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-kbl2/igt@gem_blits@basic.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-kbl7/igt@gem_blits@basic.html
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][39] ([fdo#112080]) -> [PASS][40] +9 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-iclb7/igt@gem_busy@busy-vcs1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-iclb4/igt@gem_busy@busy-vcs1.html
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [SKIP][41] ([fdo#112146]) -> [PASS][42] +4 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-iclb1/igt@gem_exec_schedule@in-order-bsd.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-iclb6/igt@gem_exec_schedule@in-order-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [SKIP][43] ([fdo#109276]) -> [PASS][44] +11 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-iclb1/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-hsw: [FAIL][45] ([i915#694]) -> [PASS][46] +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-hsw5/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-hsw8/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_workarounds@suspend-resume-context:
- shard-kbl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-kbl7/igt@gem_workarounds@suspend-resume-context.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-kbl4/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pm_rps@waitboost:
- shard-iclb: [FAIL][49] ([i915#413]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-iclb7/igt@i915_pm_rps@waitboost.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-iclb8/igt@i915_pm_rps@waitboost.html
* igt@kms_draw_crc@draw-method-rgb565-render-xtiled:
- shard-snb: [SKIP][51] ([fdo#109271]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-snb4/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-snb2/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled:
- shard-skl: [FAIL][53] ([fdo#108145] / [i915#52] / [i915#54]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-skl10/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-skl8/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [FAIL][55] ([i915#79]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-glk6/igt@kms_flip@flip-vs-expired-vblank.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-glk6/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu:
- shard-skl: [FAIL][59] ([i915#49]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-skl10/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-skl8/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-skl: [INCOMPLETE][61] ([i915#69]) -> [PASS][62] +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-skl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-skl8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][63] ([fdo#108145]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_vblank@pipe-c-query-forked-hang:
- shard-hsw: [INCOMPLETE][65] ([CI#80] / [i915#61]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-hsw8/igt@kms_vblank@pipe-c-query-forked-hang.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-hsw5/igt@kms_vblank@pipe-c-query-forked-hang.html
* igt@prime_mmap_coherency@ioctl-errors:
- shard-hsw: [FAIL][67] ([i915#831]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-hsw4/igt@prime_mmap_coherency@ioctl-errors.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-hsw1/igt@prime_mmap_coherency@ioctl-errors.html
#### Warnings ####
* igt@gem_tiled_blits@normal:
- shard-hsw: [FAIL][69] ([i915#818]) -> [FAIL][70] ([i915#694])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-hsw2/igt@gem_tiled_blits@normal.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-hsw6/igt@gem_tiled_blits@normal.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: [SKIP][71] ([i915#468]) -> [FAIL][72] ([i915#454])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/shard-tglb8/igt@i915_pm_dc@dc6-dpms.html
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109960]: https://bugs.freedesktop.org/show_bug.cgi?id=109960
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189
[i915#370]: https://gitlab.freedesktop.org/drm/intel/issues/370
[i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818
[i915#831]: https://gitlab.freedesktop.org/drm/intel/issues/831
[i915#836]: https://gitlab.freedesktop.org/drm/intel/issues/836
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7874 -> Patchwork_16450
CI-20190529: 20190529
CI_DRM_7874: 3f234d1ab91ec2321312150116c1285bcb0a260b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5420: 497e13d2b4c1053bcd01bd15739fef55e7694a03 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16450: 9a7a58a2f90a9615540ad59a219bbfcb92ef66fa @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-02-08 16:35 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-06 1:44 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing Chris Wilson
2020-02-06 1:44 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Set the PP_DIR registers upon enabling ring submission Chris Wilson
2020-02-06 16:14 ` Mika Kuoppala
2020-02-06 1:44 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: Stop invalidating the PD cachelines for gen7 Chris Wilson
2020-02-06 16:32 ` Mika Kuoppala
2020-02-06 19:26 ` Chris Wilson
2020-02-06 4:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing Patchwork
2020-02-06 4:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-02-06 16:35 ` [Intel-gfx] [PATCH 1/3] " Mika Kuoppala
2020-02-06 19:27 ` Chris Wilson
2020-02-08 16:35 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.