* [PATCH] drm/i915: Move bxt exclusive workarounds from gen9 func to bxt one.
@ 2017-03-02 19:15 Rodrigo Vivi
2017-03-02 19:20 ` Ville Syrjälä
2017-03-02 20:18 ` ✓ Fi.CI.BAT: success for " Patchwork
0 siblings, 2 replies; 6+ messages in thread
From: Rodrigo Vivi @ 2017-03-02 19:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Mika Kuoppala, Dhinakaran Pandiyan, Rodrigo Vivi
No functional change. Just a proper organization of the gen9 workarounds.
Cc: Imre Deak <imre.deak@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 42 +++++++++++++++++-----------------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index c4d4698..796d652 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -703,22 +703,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
- /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
- WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
- GEN9_DG_MIRROR_FIX_ENABLE);
-
- /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
- WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
- GEN9_RHWO_OPTIMIZATION_DISABLE);
- /*
- * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
- * but we do that in per ctx batchbuffer as there is an issue
- * with this register not getting restored on ctx restore
- */
- }
-
/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
GEN9_ENABLE_GPGPU_PREEMPTION);
@@ -732,11 +716,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
GEN9_CCS_TLB_PREFETCH_ENABLE);
- /* WaDisableMaskBasedCammingInRCC:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
- WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
- PIXEL_MASK_CAMMING_DISABLE);
-
/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
WA_SET_BIT_MASKED(HDC_CHICKEN0,
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
@@ -882,6 +861,27 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
if (ret)
return ret;
+ /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
+ WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
+ GEN9_DG_MIRROR_FIX_ENABLE);
+
+ /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
+ WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
+ GEN9_RHWO_OPTIMIZATION_DISABLE);
+ /*
+ * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
+ * but we do that in per ctx batchbuffer as there is an issue
+ * with this register not getting restored on ctx restore
+ */
+ }
+
+ /* WaDisableMaskBasedCammingInRCC:bxt */
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
+ WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
+ PIXEL_MASK_CAMMING_DISABLE);
+
/* WaStoreMultiplePTEenable:bxt */
/* This is a requirement according to Hardware specification */
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Move bxt exclusive workarounds from gen9 func to bxt one.
2017-03-02 19:15 [PATCH] drm/i915: Move bxt exclusive workarounds from gen9 func to bxt one Rodrigo Vivi
@ 2017-03-02 19:20 ` Ville Syrjälä
2017-03-02 20:27 ` Vivi, Rodrigo
2017-03-02 20:18 ` ✓ Fi.CI.BAT: success for " Patchwork
1 sibling, 1 reply; 6+ messages in thread
From: Ville Syrjälä @ 2017-03-02 19:20 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Dhinakaran Pandiyan, Mika Kuoppala
On Thu, Mar 02, 2017 at 11:15:29AM -0800, Rodrigo Vivi wrote:
> No functional change. Just a proper organization of the gen9 workarounds.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 42 +++++++++++++++++-----------------
> 1 file changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index c4d4698..796d652 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -703,22 +703,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
>
> - /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> - WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> - GEN9_DG_MIRROR_FIX_ENABLE);
> -
> - /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> - WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> - GEN9_RHWO_OPTIMIZATION_DISABLE);
> - /*
> - * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
> - * but we do that in per ctx batchbuffer as there is an issue
> - * with this register not getting restored on ctx restore
> - */
> - }
> -
> /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
> WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
> GEN9_ENABLE_GPGPU_PREEMPTION);
> @@ -732,11 +716,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> GEN9_CCS_TLB_PREFETCH_ENABLE);
>
> - /* WaDisableMaskBasedCammingInRCC:bxt */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> - WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> - PIXEL_MASK_CAMMING_DISABLE);
> -
> /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
> WA_SET_BIT_MASKED(HDC_CHICKEN0,
> HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
> @@ -882,6 +861,27 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
> if (ret)
> return ret;
>
> + /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
Hmm. I thought someone had already nuked all BXT pre-production
workarounds. I wonder why these still exist...
> + WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> + GEN9_DG_MIRROR_FIX_ENABLE);
> +
> + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> + WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> + GEN9_RHWO_OPTIMIZATION_DISABLE);
> + /*
> + * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
> + * but we do that in per ctx batchbuffer as there is an issue
> + * with this register not getting restored on ctx restore
> + */
> + }
> +
> + /* WaDisableMaskBasedCammingInRCC:bxt */
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> + WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> + PIXEL_MASK_CAMMING_DISABLE);
> +
> /* WaStoreMultiplePTEenable:bxt */
> /* This is a requirement according to Hardware specification */
> if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Move bxt exclusive workarounds from gen9 func to bxt one.
2017-03-02 19:15 [PATCH] drm/i915: Move bxt exclusive workarounds from gen9 func to bxt one Rodrigo Vivi
2017-03-02 19:20 ` Ville Syrjälä
@ 2017-03-02 20:18 ` Patchwork
1 sibling, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-03-02 20:18 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Move bxt exclusive workarounds from gen9 func to bxt one.
URL : https://patchwork.freedesktop.org/series/20582/
State : success
== Summary ==
Series 20582v1 drm/i915: Move bxt exclusive workarounds from gen9 func to bxt one.
https://patchwork.freedesktop.org/api/1.0/series/20582/revisions/1/mbox/
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
fail -> PASS (fi-snb-2600) fdo#100007
fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11
fi-bsw-n3050 total:278 pass:239 dwarn:0 dfail:0 fail:0 skip:39
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19
fi-bxt-t5700 total:278 pass:258 dwarn:0 dfail:0 fail:0 skip:20
fi-byt-j1900 total:278 pass:251 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-n2820 total:278 pass:247 dwarn:0 dfail:0 fail:0 skip:31
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16
fi-hsw-4770r total:278 pass:261 dwarn:0 dfail:0 fail:1 skip:16
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18
fi-kbl-7500u total:278 pass:259 dwarn:1 dfail:0 fail:0 skip:18
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10
fi-skl-6700hq total:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29
06dbfb1f6e3af2f332189d566a9f2f1227acda76 drm-tip: 2017y-03m-02d-18h-25m-10s UTC integration manifest
afbe960 drm/i915: Move bxt exclusive workarounds from gen9 func to bxt one.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4044/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Move bxt exclusive workarounds from gen9 func to bxt one.
2017-03-02 19:20 ` Ville Syrjälä
@ 2017-03-02 20:27 ` Vivi, Rodrigo
2017-03-03 13:34 ` Imre Deak
0 siblings, 1 reply; 6+ messages in thread
From: Vivi, Rodrigo @ 2017-03-02 20:27 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx, Pandiyan, Dhinakaran, Kuoppala, Mika
On Thu, 2017-03-02 at 21:20 +0200, Ville Syrjälä wrote:
> On Thu, Mar 02, 2017 at 11:15:29AM -0800, Rodrigo Vivi wrote:
> > No functional change. Just a proper organization of the gen9 workarounds.
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_engine_cs.c | 42 +++++++++++++++++-----------------
> > 1 file changed, 21 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index c4d4698..796d652 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -703,22 +703,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> > GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
> >
> > - /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
> > - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> > - WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> > - GEN9_DG_MIRROR_FIX_ENABLE);
> > -
> > - /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> > - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> > - WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> > - GEN9_RHWO_OPTIMIZATION_DISABLE);
> > - /*
> > - * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
> > - * but we do that in per ctx batchbuffer as there is an issue
> > - * with this register not getting restored on ctx restore
> > - */
> > - }
> > -
> > /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
> > WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
> > GEN9_ENABLE_GPGPU_PREEMPTION);
> > @@ -732,11 +716,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> > WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> > GEN9_CCS_TLB_PREFETCH_ENABLE);
> >
> > - /* WaDisableMaskBasedCammingInRCC:bxt */
> > - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> > - WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> > - PIXEL_MASK_CAMMING_DISABLE);
> > -
> > /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
> > WA_SET_BIT_MASKED(HDC_CHICKEN0,
> > HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
> > @@ -882,6 +861,27 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
> > if (ret)
> > return ret;
> >
> > + /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
> > + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
>
> Hmm. I thought someone had already nuked all BXT pre-production
> workarounds. I wonder why these still exist...
Well, now that they are organized by the REVID I believe it doesn't hurt
to keep them here. In case someone internally end up using a pre-prod
hardware for something... or for future reference when adding next
platforms.
>
> > + WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> > + GEN9_DG_MIRROR_FIX_ENABLE);
> > +
> > + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> > + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> > + WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> > + GEN9_RHWO_OPTIMIZATION_DISABLE);
> > + /*
> > + * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
> > + * but we do that in per ctx batchbuffer as there is an issue
> > + * with this register not getting restored on ctx restore
> > + */
> > + }
> > +
> > + /* WaDisableMaskBasedCammingInRCC:bxt */
> > + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> > + WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> > + PIXEL_MASK_CAMMING_DISABLE);
> > +
> > /* WaStoreMultiplePTEenable:bxt */
> > /* This is a requirement according to Hardware specification */
> > if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Move bxt exclusive workarounds from gen9 func to bxt one.
2017-03-02 20:27 ` Vivi, Rodrigo
@ 2017-03-03 13:34 ` Imre Deak
2017-03-03 15:37 ` Jani Nikula
0 siblings, 1 reply; 6+ messages in thread
From: Imre Deak @ 2017-03-03 13:34 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx, Pandiyan, Dhinakaran, Kuoppala, Mika
On Thu, Mar 02, 2017 at 08:27:28PM +0000, Vivi, Rodrigo wrote:
> On Thu, 2017-03-02 at 21:20 +0200, Ville Syrjälä wrote:
> > On Thu, Mar 02, 2017 at 11:15:29AM -0800, Rodrigo Vivi wrote:
> > > No functional change. Just a proper organization of the gen9 workarounds.
> > >
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_engine_cs.c | 42 +++++++++++++++++-----------------
> > > 1 file changed, 21 insertions(+), 21 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > > index c4d4698..796d652 100644
> > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > > @@ -703,22 +703,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> > > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> > > GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
> > >
> > > - /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
> > > - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> > > - WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> > > - GEN9_DG_MIRROR_FIX_ENABLE);
> > > -
> > > - /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> > > - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> > > - WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> > > - GEN9_RHWO_OPTIMIZATION_DISABLE);
> > > - /*
> > > - * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
> > > - * but we do that in per ctx batchbuffer as there is an issue
> > > - * with this register not getting restored on ctx restore
> > > - */
> > > - }
> > > -
> > > /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
> > > WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
> > > GEN9_ENABLE_GPGPU_PREEMPTION);
> > > @@ -732,11 +716,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> > > WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> > > GEN9_CCS_TLB_PREFETCH_ENABLE);
> > >
> > > - /* WaDisableMaskBasedCammingInRCC:bxt */
> > > - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> > > - WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> > > - PIXEL_MASK_CAMMING_DISABLE);
> > > -
> > > /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
> > > WA_SET_BIT_MASKED(HDC_CHICKEN0,
> > > HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
> > > @@ -882,6 +861,27 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
> > > if (ret)
> > > return ret;
> > >
> > > + /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
> > > + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> >
> > Hmm. I thought someone had already nuked all BXT pre-production
> > workarounds. I wonder why these still exist...
>
> Well, now that they are organized by the REVID I believe it doesn't hurt
> to keep them here. In case someone internally end up using a pre-prod
> hardware for something...
This won't work anyway, since we removed the rest of the BTX pre-prod WAs.
> or for future reference when adding next platforms.
No strong opinion on this, but we removed the pre-prod WAs on other
platforms too. I'd follow the rule not to keep any unused code around,
it can be found from git if needed.
--Imre
>
> >
> > > + WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> > > + GEN9_DG_MIRROR_FIX_ENABLE);
> > > +
> > > + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> > > + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> > > + WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> > > + GEN9_RHWO_OPTIMIZATION_DISABLE);
> > > + /*
> > > + * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
> > > + * but we do that in per ctx batchbuffer as there is an issue
> > > + * with this register not getting restored on ctx restore
> > > + */
> > > + }
> > > +
> > > + /* WaDisableMaskBasedCammingInRCC:bxt */
> > > + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> > > + WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> > > + PIXEL_MASK_CAMMING_DISABLE);
> > > +
> > > /* WaStoreMultiplePTEenable:bxt */
> > > /* This is a requirement according to Hardware specification */
> > > if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> > > --
> > > 1.9.1
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Move bxt exclusive workarounds from gen9 func to bxt one.
2017-03-03 13:34 ` Imre Deak
@ 2017-03-03 15:37 ` Jani Nikula
0 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2017-03-03 15:37 UTC (permalink / raw)
To: imre.deak, Vivi, Rodrigo; +Cc: intel-gfx, Pandiyan, Dhinakaran, Kuoppala, Mika
On Fri, 03 Mar 2017, Imre Deak <imre.deak@intel.com> wrote:
> On Thu, Mar 02, 2017 at 08:27:28PM +0000, Vivi, Rodrigo wrote:
>> On Thu, 2017-03-02 at 21:20 +0200, Ville Syrjälä wrote:
>> > On Thu, Mar 02, 2017 at 11:15:29AM -0800, Rodrigo Vivi wrote:
>> > > + /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
>> > > + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
>> >
>> > Hmm. I thought someone had already nuked all BXT pre-production
>> > workarounds. I wonder why these still exist...
>>
>> Well, now that they are organized by the REVID I believe it doesn't hurt
>> to keep them here. In case someone internally end up using a pre-prod
>> hardware for something...
>
> This won't work anyway, since we removed the rest of the BTX pre-prod WAs.
>
>> or for future reference when adding next platforms.
>
> No strong opinion on this, but we removed the pre-prod WAs on other
> platforms too. I'd follow the rule not to keep any unused code around,
> it can be found from git if needed.
Strong opinion, nuke 'em. When there's production hardware available,
pretending to support early steppings is a waste of time.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-03-03 15:37 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-02 19:15 [PATCH] drm/i915: Move bxt exclusive workarounds from gen9 func to bxt one Rodrigo Vivi
2017-03-02 19:20 ` Ville Syrjälä
2017-03-02 20:27 ` Vivi, Rodrigo
2017-03-03 13:34 ` Imre Deak
2017-03-03 15:37 ` Jani Nikula
2017-03-02 20:18 ` ✓ Fi.CI.BAT: success for " Patchwork
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