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* [PATCH 0/2] target/arm: Pass arguments by value for sve FMLA/FCMLA
@ 2020-02-12  2:51 Richard Henderson
  2020-02-12  2:51 ` [PATCH 1/2] tcg: Add tcg_gen_gvec_5_ptr Richard Henderson
  2020-02-12  2:51 ` [PATCH 2/2] target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA Richard Henderson
  0 siblings, 2 replies; 10+ messages in thread
From: Richard Henderson @ 2020-02-12  2:51 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell, tsimpson, alex.bennee

Based-on: <1580942510-2820-1-git-send-email-tsimpson@quicinc.com>

These functions had been passing arguments by regno,
encoded into simd_data, because we couldn't pass 7 args.


r~


Richard Henderson (2):
  tcg: Add tcg_gen_gvec_5_ptr
  target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA

 include/tcg/tcg-op-gvec.h  |   7 ++
 target/arm/helper-sve.h    |  45 +++++++----
 target/arm/sve_helper.c    | 157 ++++++++++++++-----------------------
 target/arm/translate-sve.c |  68 ++++++----------
 tcg/tcg-op-gvec.c          |  32 ++++++++
 5 files changed, 153 insertions(+), 156 deletions(-)

-- 
2.20.1



^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH 1/2] tcg: Add tcg_gen_gvec_5_ptr
  2020-02-12  2:51 [PATCH 0/2] target/arm: Pass arguments by value for sve FMLA/FCMLA Richard Henderson
@ 2020-02-12  2:51 ` Richard Henderson
  2020-02-12  6:09   ` Philippe Mathieu-Daudé
                     ` (2 more replies)
  2020-02-12  2:51 ` [PATCH 2/2] target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA Richard Henderson
  1 sibling, 3 replies; 10+ messages in thread
From: Richard Henderson @ 2020-02-12  2:51 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell, tsimpson, alex.bennee

Extend the vector generator infrastructure to handle
5 vector arguments.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg-op-gvec.h |  7 +++++++
 tcg/tcg-op-gvec.c         | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
index 830d68f697..74534e2480 100644
--- a/include/tcg/tcg-op-gvec.h
+++ b/include/tcg/tcg-op-gvec.h
@@ -83,6 +83,13 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
                         uint32_t maxsz, int32_t data,
                         gen_helper_gvec_4_ptr *fn);
 
+typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
+                                   TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+                        uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
+                        uint32_t oprsz, uint32_t maxsz, int32_t data,
+                        gen_helper_gvec_5_ptr *fn);
+
 /* Expand a gvec operation.  Either inline or out-of-line depending on
    the actual vector size and the operations supported by the host.  */
 typedef struct {
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 41b4a3c661..327d9588e0 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -290,6 +290,38 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
     tcg_temp_free_i32(desc);
 }
 
+/* Generate a call to a gvec-style helper with five vector operands
+   and an extra pointer operand.  */
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+                        uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
+                        uint32_t oprsz, uint32_t maxsz, int32_t data,
+                        gen_helper_gvec_5_ptr *fn)
+{
+    TCGv_ptr a0, a1, a2, a3, a4;
+    TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+
+    a0 = tcg_temp_new_ptr();
+    a1 = tcg_temp_new_ptr();
+    a2 = tcg_temp_new_ptr();
+    a3 = tcg_temp_new_ptr();
+    a4 = tcg_temp_new_ptr();
+
+    tcg_gen_addi_ptr(a0, cpu_env, dofs);
+    tcg_gen_addi_ptr(a1, cpu_env, aofs);
+    tcg_gen_addi_ptr(a2, cpu_env, bofs);
+    tcg_gen_addi_ptr(a3, cpu_env, cofs);
+    tcg_gen_addi_ptr(a4, cpu_env, eofs);
+
+    fn(a0, a1, a2, a3, a4, ptr, desc);
+
+    tcg_temp_free_ptr(a0);
+    tcg_temp_free_ptr(a1);
+    tcg_temp_free_ptr(a2);
+    tcg_temp_free_ptr(a3);
+    tcg_temp_free_ptr(a4);
+    tcg_temp_free_i32(desc);
+}
+
 /* Return true if we want to implement something of OPRSZ bytes
    in units of LNSZ.  This limits the expansion of inline code.  */
 static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
-- 
2.20.1



^ permalink raw reply related	[flat|nested] 10+ messages in thread

* [PATCH 2/2] target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
  2020-02-12  2:51 [PATCH 0/2] target/arm: Pass arguments by value for sve FMLA/FCMLA Richard Henderson
  2020-02-12  2:51 ` [PATCH 1/2] tcg: Add tcg_gen_gvec_5_ptr Richard Henderson
@ 2020-02-12  2:51 ` Richard Henderson
  2020-02-12  6:14   ` Philippe Mathieu-Daudé
                     ` (2 more replies)
  1 sibling, 3 replies; 10+ messages in thread
From: Richard Henderson @ 2020-02-12  2:51 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell, tsimpson, alex.bennee

Now that we can pass 7 parameters, do not encode register
operands within simd_data.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper-sve.h    |  45 +++++++----
 target/arm/sve_helper.c    | 157 ++++++++++++++-----------------------
 target/arm/translate-sve.c |  68 ++++++----------
 3 files changed, 114 insertions(+), 156 deletions(-)

diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 9e79182ab4..bd8b91bdb6 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -1099,25 +1099,40 @@ DEF_HELPER_FLAGS_6(sve_fcadd_s, TCG_CALL_NO_RWG,
 DEF_HELPER_FLAGS_6(sve_fcadd_d, TCG_CALL_NO_RWG,
                    void, ptr, ptr, ptr, ptr, ptr, i32)
 
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
 
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
 
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
 
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
 
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index fdfa652094..33b5a54a47 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -3372,23 +3372,11 @@ DO_ZPZ_FP(sve_ucvt_dd, uint64_t,     , uint64_to_float64)
 
 #undef DO_ZPZ_FP
 
-/* 4-operand predicated multiply-add.  This requires 7 operands to pass
- * "properly", so we need to encode some of the registers into DESC.
- */
-QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 20 > 32);
-
-static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
+static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg,
+                            float_status *status, uint32_t desc,
                             uint16_t neg1, uint16_t neg3)
 {
     intptr_t i = simd_oprsz(desc);
-    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
-    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
-    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
-    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
-    void *vd = &env->vfp.zregs[rd];
-    void *vn = &env->vfp.zregs[rn];
-    void *vm = &env->vfp.zregs[rm];
-    void *va = &env->vfp.zregs[ra];
     uint64_t *g = vg;
 
     do {
@@ -3401,45 +3389,42 @@ static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
                 e1 = *(uint16_t *)(vn + H1_2(i)) ^ neg1;
                 e2 = *(uint16_t *)(vm + H1_2(i));
                 e3 = *(uint16_t *)(va + H1_2(i)) ^ neg3;
-                r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status_f16);
+                r = float16_muladd(e1, e2, e3, 0, status);
                 *(uint16_t *)(vd + H1_2(i)) = r;
             }
         } while (i & 63);
     } while (i != 0);
 }
 
-void HELPER(sve_fmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
+void HELPER(sve_fmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
+                              void *vg, void *status, uint32_t desc)
 {
-    do_fmla_zpzzz_h(env, vg, desc, 0, 0);
+    do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0);
 }
 
-void HELPER(sve_fmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
+void HELPER(sve_fmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
+                              void *vg, void *status, uint32_t desc)
 {
-    do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0);
+    do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0);
 }
 
-void HELPER(sve_fnmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
+void HELPER(sve_fnmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
+                               void *vg, void *status, uint32_t desc)
 {
-    do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0x8000);
+    do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000);
 }
 
-void HELPER(sve_fnmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
+void HELPER(sve_fnmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
+                               void *vg, void *status, uint32_t desc)
 {
-    do_fmla_zpzzz_h(env, vg, desc, 0, 0x8000);
+    do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000);
 }
 
-static void do_fmla_zpzzz_s(CPUARMState *env, void *vg, uint32_t desc,
+static void do_fmla_zpzzz_s(void *vd, void *vn, void *vm, void *va, void *vg,
+                            float_status *status, uint32_t desc,
                             uint32_t neg1, uint32_t neg3)
 {
     intptr_t i = simd_oprsz(desc);
-    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
-    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
-    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
-    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
-    void *vd = &env->vfp.zregs[rd];
-    void *vn = &env->vfp.zregs[rn];
-    void *vm = &env->vfp.zregs[rm];
-    void *va = &env->vfp.zregs[ra];
     uint64_t *g = vg;
 
     do {
@@ -3452,45 +3437,42 @@ static void do_fmla_zpzzz_s(CPUARMState *env, void *vg, uint32_t desc,
                 e1 = *(uint32_t *)(vn + H1_4(i)) ^ neg1;
                 e2 = *(uint32_t *)(vm + H1_4(i));
                 e3 = *(uint32_t *)(va + H1_4(i)) ^ neg3;
-                r = float32_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
+                r = float32_muladd(e1, e2, e3, 0, status);
                 *(uint32_t *)(vd + H1_4(i)) = r;
             }
         } while (i & 63);
     } while (i != 0);
 }
 
-void HELPER(sve_fmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
+void HELPER(sve_fmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
+                              void *vg, void *status, uint32_t desc)
 {
-    do_fmla_zpzzz_s(env, vg, desc, 0, 0);
+    do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0);
 }
 
-void HELPER(sve_fmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
+void HELPER(sve_fmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
+                              void *vg, void *status, uint32_t desc)
 {
-    do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0);
+    do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0);
 }
 
-void HELPER(sve_fnmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
+void HELPER(sve_fnmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
+                               void *vg, void *status, uint32_t desc)
 {
-    do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0x80000000);
+    do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0x80000000);
 }
 
-void HELPER(sve_fnmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
+void HELPER(sve_fnmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
+                               void *vg, void *status, uint32_t desc)
 {
-    do_fmla_zpzzz_s(env, vg, desc, 0, 0x80000000);
+    do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000);
 }
 
-static void do_fmla_zpzzz_d(CPUARMState *env, void *vg, uint32_t desc,
+static void do_fmla_zpzzz_d(void *vd, void *vn, void *vm, void *va, void *vg,
+                            float_status *status, uint32_t desc,
                             uint64_t neg1, uint64_t neg3)
 {
     intptr_t i = simd_oprsz(desc);
-    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
-    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
-    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
-    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
-    void *vd = &env->vfp.zregs[rd];
-    void *vn = &env->vfp.zregs[rn];
-    void *vm = &env->vfp.zregs[rm];
-    void *va = &env->vfp.zregs[ra];
     uint64_t *g = vg;
 
     do {
@@ -3503,31 +3485,35 @@ static void do_fmla_zpzzz_d(CPUARMState *env, void *vg, uint32_t desc,
                 e1 = *(uint64_t *)(vn + i) ^ neg1;
                 e2 = *(uint64_t *)(vm + i);
                 e3 = *(uint64_t *)(va + i) ^ neg3;
-                r = float64_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
+                r = float64_muladd(e1, e2, e3, 0, status);
                 *(uint64_t *)(vd + i) = r;
             }
         } while (i & 63);
     } while (i != 0);
 }
 
-void HELPER(sve_fmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
+void HELPER(sve_fmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
+                              void *vg, void *status, uint32_t desc)
 {
-    do_fmla_zpzzz_d(env, vg, desc, 0, 0);
+    do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0);
 }
 
-void HELPER(sve_fmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
+void HELPER(sve_fmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
+                              void *vg, void *status, uint32_t desc)
 {
-    do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, 0);
+    do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0);
 }
 
-void HELPER(sve_fnmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
+void HELPER(sve_fnmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
+                               void *vg, void *status, uint32_t desc)
 {
-    do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, INT64_MIN);
+    do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, INT64_MIN);
 }
 
-void HELPER(sve_fnmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
+void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
+                               void *vg, void *status, uint32_t desc)
 {
-    do_fmla_zpzzz_d(env, vg, desc, 0, INT64_MIN);
+    do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN);
 }
 
 /* Two operand floating-point comparison controlled by a predicate.
@@ -3809,22 +3795,13 @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
  * FP Complex Multiply
  */
 
-QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 22 > 32);
-
-void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
+void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
+                               void *vg, void *status, uint32_t desc)
 {
     intptr_t j, i = simd_oprsz(desc);
-    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
-    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
-    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
-    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
-    unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
+    unsigned rot = simd_data(desc);
     bool flip = rot & 1;
     float16 neg_imag, neg_real;
-    void *vd = &env->vfp.zregs[rd];
-    void *vn = &env->vfp.zregs[rn];
-    void *vm = &env->vfp.zregs[rm];
-    void *va = &env->vfp.zregs[ra];
     uint64_t *g = vg;
 
     neg_imag = float16_set_sign(0, (rot & 2) != 0);
@@ -3851,32 +3828,25 @@ void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
 
             if (likely((pg >> (i & 63)) & 1)) {
                 d = *(float16 *)(va + H1_2(i));
-                d = float16_muladd(e2, e1, d, 0, &env->vfp.fp_status_f16);
+                d = float16_muladd(e2, e1, d, 0, status);
                 *(float16 *)(vd + H1_2(i)) = d;
             }
             if (likely((pg >> (j & 63)) & 1)) {
                 d = *(float16 *)(va + H1_2(j));
-                d = float16_muladd(e4, e3, d, 0, &env->vfp.fp_status_f16);
+                d = float16_muladd(e4, e3, d, 0, status);
                 *(float16 *)(vd + H1_2(j)) = d;
             }
         } while (i & 63);
     } while (i != 0);
 }
 
-void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
+void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
+                               void *vg, void *status, uint32_t desc)
 {
     intptr_t j, i = simd_oprsz(desc);
-    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
-    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
-    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
-    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
-    unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
+    unsigned rot = simd_data(desc);
     bool flip = rot & 1;
     float32 neg_imag, neg_real;
-    void *vd = &env->vfp.zregs[rd];
-    void *vn = &env->vfp.zregs[rn];
-    void *vm = &env->vfp.zregs[rm];
-    void *va = &env->vfp.zregs[ra];
     uint64_t *g = vg;
 
     neg_imag = float32_set_sign(0, (rot & 2) != 0);
@@ -3903,32 +3873,25 @@ void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
 
             if (likely((pg >> (i & 63)) & 1)) {
                 d = *(float32 *)(va + H1_2(i));
-                d = float32_muladd(e2, e1, d, 0, &env->vfp.fp_status);
+                d = float32_muladd(e2, e1, d, 0, status);
                 *(float32 *)(vd + H1_2(i)) = d;
             }
             if (likely((pg >> (j & 63)) & 1)) {
                 d = *(float32 *)(va + H1_2(j));
-                d = float32_muladd(e4, e3, d, 0, &env->vfp.fp_status);
+                d = float32_muladd(e4, e3, d, 0, status);
                 *(float32 *)(vd + H1_2(j)) = d;
             }
         } while (i & 63);
     } while (i != 0);
 }
 
-void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
+void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
+                               void *vg, void *status, uint32_t desc)
 {
     intptr_t j, i = simd_oprsz(desc);
-    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
-    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
-    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
-    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
-    unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
+    unsigned rot = simd_data(desc);
     bool flip = rot & 1;
     float64 neg_imag, neg_real;
-    void *vd = &env->vfp.zregs[rd];
-    void *vn = &env->vfp.zregs[rn];
-    void *vm = &env->vfp.zregs[rm];
-    void *va = &env->vfp.zregs[ra];
     uint64_t *g = vg;
 
     neg_imag = float64_set_sign(0, (rot & 2) != 0);
@@ -3955,12 +3918,12 @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
 
             if (likely((pg >> (i & 63)) & 1)) {
                 d = *(float64 *)(va + H1_2(i));
-                d = float64_muladd(e2, e1, d, 0, &env->vfp.fp_status);
+                d = float64_muladd(e2, e1, d, 0, status);
                 *(float64 *)(vd + H1_2(i)) = d;
             }
             if (likely((pg >> (j & 63)) & 1)) {
                 d = *(float64 *)(va + H1_2(j));
-                d = float64_muladd(e4, e3, d, 0, &env->vfp.fp_status);
+                d = float64_muladd(e4, e3, d, 0, status);
                 *(float64 *)(vd + H1_2(j)) = d;
             }
         } while (i & 63);
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index b35bad245e..7607593f6b 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3950,40 +3950,30 @@ static bool trans_FCADD(DisasContext *s, arg_FCADD *a)
 
 typedef void gen_helper_sve_fmla(TCGv_env, TCGv_ptr, TCGv_i32);
 
-static bool do_fmla(DisasContext *s, arg_rprrr_esz *a, gen_helper_sve_fmla *fn)
+static bool do_fmla(DisasContext *s, arg_rprrr_esz *a,
+                    gen_helper_gvec_5_ptr *fn)
 {
-    if (fn == NULL) {
+    if (a->esz == 0) {
         return false;
     }
-    if (!sve_access_check(s)) {
-        return true;
+    if (sve_access_check(s)) {
+        unsigned vsz = vec_full_reg_size(s);
+        TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
+        tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
+                           vec_full_reg_offset(s, a->rn),
+                           vec_full_reg_offset(s, a->rm),
+                           vec_full_reg_offset(s, a->ra),
+                           pred_full_reg_offset(s, a->pg),
+                           status, vsz, vsz, 0, fn);
+        tcg_temp_free_ptr(status);
     }
-
-    unsigned vsz = vec_full_reg_size(s);
-    unsigned desc;
-    TCGv_i32 t_desc;
-    TCGv_ptr pg = tcg_temp_new_ptr();
-
-    /* We would need 7 operands to pass these arguments "properly".
-     * So we encode all the register numbers into the descriptor.
-     */
-    desc = deposit32(a->rd, 5, 5, a->rn);
-    desc = deposit32(desc, 10, 5, a->rm);
-    desc = deposit32(desc, 15, 5, a->ra);
-    desc = simd_desc(vsz, vsz, desc);
-
-    t_desc = tcg_const_i32(desc);
-    tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
-    fn(cpu_env, pg, t_desc);
-    tcg_temp_free_i32(t_desc);
-    tcg_temp_free_ptr(pg);
     return true;
 }
 
 #define DO_FMLA(NAME, name) \
 static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a)          \
 {                                                                    \
-    static gen_helper_sve_fmla * const fns[4] = {                    \
+    static gen_helper_gvec_5_ptr * const fns[4] = {                  \
         NULL, gen_helper_sve_##name##_h,                             \
         gen_helper_sve_##name##_s, gen_helper_sve_##name##_d         \
     };                                                               \
@@ -3999,7 +3989,8 @@ DO_FMLA(FNMLS_zpzzz, fnmls_zpzzz)
 
 static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
 {
-    static gen_helper_sve_fmla * const fns[3] = {
+    static gen_helper_gvec_5_ptr * const fns[4] = {
+        NULL,
         gen_helper_sve_fcmla_zpzzz_h,
         gen_helper_sve_fcmla_zpzzz_s,
         gen_helper_sve_fcmla_zpzzz_d,
@@ -4010,25 +4001,14 @@ static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
     }
     if (sve_access_check(s)) {
         unsigned vsz = vec_full_reg_size(s);
-        unsigned desc;
-        TCGv_i32 t_desc;
-        TCGv_ptr pg = tcg_temp_new_ptr();
-
-        /* We would need 7 operands to pass these arguments "properly".
-         * So we encode all the register numbers into the descriptor.
-         */
-        desc = deposit32(a->rd, 5, 5, a->rn);
-        desc = deposit32(desc, 10, 5, a->rm);
-        desc = deposit32(desc, 15, 5, a->ra);
-        desc = deposit32(desc, 20, 2, a->rot);
-        desc = sextract32(desc, 0, 22);
-        desc = simd_desc(vsz, vsz, desc);
-
-        t_desc = tcg_const_i32(desc);
-        tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
-        fns[a->esz - 1](cpu_env, pg, t_desc);
-        tcg_temp_free_i32(t_desc);
-        tcg_temp_free_ptr(pg);
+        TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
+        tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
+                           vec_full_reg_offset(s, a->rn),
+                           vec_full_reg_offset(s, a->rm),
+                           vec_full_reg_offset(s, a->ra),
+                           pred_full_reg_offset(s, a->pg),
+                           status, vsz, vsz, a->rot, fns[a->esz]);
+        tcg_temp_free_ptr(status);
     }
     return true;
 }
-- 
2.20.1



^ permalink raw reply related	[flat|nested] 10+ messages in thread

* Re: [PATCH 1/2] tcg: Add tcg_gen_gvec_5_ptr
  2020-02-12  2:51 ` [PATCH 1/2] tcg: Add tcg_gen_gvec_5_ptr Richard Henderson
@ 2020-02-12  6:09   ` Philippe Mathieu-Daudé
  2020-02-12 10:47   ` Alex Bennée
  2020-02-12 16:28   ` Taylor Simpson
  2 siblings, 0 replies; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-02-12  6:09 UTC (permalink / raw)
  To: Richard Henderson, qemu-devel; +Cc: peter.maydell, tsimpson, alex.bennee

On 2/12/20 3:51 AM, Richard Henderson wrote:
> Extend the vector generator infrastructure to handle
> 5 vector arguments.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   include/tcg/tcg-op-gvec.h |  7 +++++++
>   tcg/tcg-op-gvec.c         | 32 ++++++++++++++++++++++++++++++++
>   2 files changed, 39 insertions(+)
> 
> diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
> index 830d68f697..74534e2480 100644
> --- a/include/tcg/tcg-op-gvec.h
> +++ b/include/tcg/tcg-op-gvec.h
> @@ -83,6 +83,13 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
>                           uint32_t maxsz, int32_t data,
>                           gen_helper_gvec_4_ptr *fn);
>   
> +typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
> +                                   TCGv_ptr, TCGv_ptr, TCGv_i32);
> +void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
> +                        uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
> +                        uint32_t oprsz, uint32_t maxsz, int32_t data,
> +                        gen_helper_gvec_5_ptr *fn);
> +
>   /* Expand a gvec operation.  Either inline or out-of-line depending on
>      the actual vector size and the operations supported by the host.  */
>   typedef struct {
> diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
> index 41b4a3c661..327d9588e0 100644
> --- a/tcg/tcg-op-gvec.c
> +++ b/tcg/tcg-op-gvec.c
> @@ -290,6 +290,38 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
>       tcg_temp_free_i32(desc);
>   }
>   
> +/* Generate a call to a gvec-style helper with five vector operands
> +   and an extra pointer operand.  */
> +void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
> +                        uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
> +                        uint32_t oprsz, uint32_t maxsz, int32_t data,
> +                        gen_helper_gvec_5_ptr *fn)
> +{
> +    TCGv_ptr a0, a1, a2, a3, a4;
> +    TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
> +
> +    a0 = tcg_temp_new_ptr();
> +    a1 = tcg_temp_new_ptr();
> +    a2 = tcg_temp_new_ptr();
> +    a3 = tcg_temp_new_ptr();
> +    a4 = tcg_temp_new_ptr();
> +
> +    tcg_gen_addi_ptr(a0, cpu_env, dofs);
> +    tcg_gen_addi_ptr(a1, cpu_env, aofs);
> +    tcg_gen_addi_ptr(a2, cpu_env, bofs);
> +    tcg_gen_addi_ptr(a3, cpu_env, cofs);
> +    tcg_gen_addi_ptr(a4, cpu_env, eofs);
> +
> +    fn(a0, a1, a2, a3, a4, ptr, desc);
> +
> +    tcg_temp_free_ptr(a0);
> +    tcg_temp_free_ptr(a1);
> +    tcg_temp_free_ptr(a2);
> +    tcg_temp_free_ptr(a3);
> +    tcg_temp_free_ptr(a4);
> +    tcg_temp_free_i32(desc);
> +}
> +
>   /* Return true if we want to implement something of OPRSZ bytes
>      in units of LNSZ.  This limits the expansion of inline code.  */
>   static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
> 

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>



^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 2/2] target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
  2020-02-12  2:51 ` [PATCH 2/2] target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA Richard Henderson
@ 2020-02-12  6:14   ` Philippe Mathieu-Daudé
  2020-02-12 10:50   ` Alex Bennée
  2020-02-12 16:28   ` Taylor Simpson
  2 siblings, 0 replies; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-02-12  6:14 UTC (permalink / raw)
  To: Richard Henderson, qemu-devel
  Cc: peter.maydell, tsimpson, alex.bennee, David Hildenbrand

On 2/12/20 3:51 AM, Richard Henderson wrote:
> Now that we can pass 7 parameters, do not encode register
> operands within simd_data.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/arm/helper-sve.h    |  45 +++++++----
>   target/arm/sve_helper.c    | 157 ++++++++++++++-----------------------
>   target/arm/translate-sve.c |  68 ++++++----------
>   3 files changed, 114 insertions(+), 156 deletions(-)
> 
> diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
> index 9e79182ab4..bd8b91bdb6 100644
> --- a/target/arm/helper-sve.h
> +++ b/target/arm/helper-sve.h
> @@ -1099,25 +1099,40 @@ DEF_HELPER_FLAGS_6(sve_fcadd_s, TCG_CALL_NO_RWG,
>   DEF_HELPER_FLAGS_6(sve_fcadd_d, TCG_CALL_NO_RWG,
>                      void, ptr, ptr, ptr, ptr, ptr, i32)
>   
> -DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
>   
> -DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
>   
> -DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
>   
> -DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
>   
> -DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
>   
>   DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
>   DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
> diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
> index fdfa652094..33b5a54a47 100644
> --- a/target/arm/sve_helper.c
> +++ b/target/arm/sve_helper.c
> @@ -3372,23 +3372,11 @@ DO_ZPZ_FP(sve_ucvt_dd, uint64_t,     , uint64_to_float64)
>   
>   #undef DO_ZPZ_FP
>   
> -/* 4-operand predicated multiply-add.  This requires 7 operands to pass
> - * "properly", so we need to encode some of the registers into DESC.
> - */
> -QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 20 > 32);
> -
> -static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
> +static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg,
> +                            float_status *status, uint32_t desc,
>                               uint16_t neg1, uint16_t neg3)
>   {
>       intptr_t i = simd_oprsz(desc);
> -    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
> -    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
> -    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
> -    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
> -    void *vd = &env->vfp.zregs[rd];
> -    void *vn = &env->vfp.zregs[rn];
> -    void *vm = &env->vfp.zregs[rm];
> -    void *va = &env->vfp.zregs[ra];
>       uint64_t *g = vg;
>   
>       do {
> @@ -3401,45 +3389,42 @@ static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
>                   e1 = *(uint16_t *)(vn + H1_2(i)) ^ neg1;
>                   e2 = *(uint16_t *)(vm + H1_2(i));
>                   e3 = *(uint16_t *)(va + H1_2(i)) ^ neg3;
> -                r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status_f16);
> +                r = float16_muladd(e1, e2, e3, 0, status);
>                   *(uint16_t *)(vd + H1_2(i)) = r;
>               }
>           } while (i & 63);
>       } while (i != 0);
>   }
>   
> -void HELPER(sve_fmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
> +void HELPER(sve_fmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
> +                              void *vg, void *status, uint32_t desc)
>   {
> -    do_fmla_zpzzz_h(env, vg, desc, 0, 0);
> +    do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0);
>   }
>   
> -void HELPER(sve_fmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
> +void HELPER(sve_fmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
> +                              void *vg, void *status, uint32_t desc)
>   {
> -    do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0);
> +    do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0);
>   }
>   
> -void HELPER(sve_fnmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
> +void HELPER(sve_fnmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>   {
> -    do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0x8000);
> +    do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000);
>   }
>   
> -void HELPER(sve_fnmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
> +void HELPER(sve_fnmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>   {
> -    do_fmla_zpzzz_h(env, vg, desc, 0, 0x8000);
> +    do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000);
>   }
>   
> -static void do_fmla_zpzzz_s(CPUARMState *env, void *vg, uint32_t desc,
> +static void do_fmla_zpzzz_s(void *vd, void *vn, void *vm, void *va, void *vg,
> +                            float_status *status, uint32_t desc,
>                               uint32_t neg1, uint32_t neg3)
>   {
>       intptr_t i = simd_oprsz(desc);
> -    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
> -    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
> -    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
> -    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
> -    void *vd = &env->vfp.zregs[rd];
> -    void *vn = &env->vfp.zregs[rn];
> -    void *vm = &env->vfp.zregs[rm];
> -    void *va = &env->vfp.zregs[ra];
>       uint64_t *g = vg;
>   
>       do {
> @@ -3452,45 +3437,42 @@ static void do_fmla_zpzzz_s(CPUARMState *env, void *vg, uint32_t desc,
>                   e1 = *(uint32_t *)(vn + H1_4(i)) ^ neg1;
>                   e2 = *(uint32_t *)(vm + H1_4(i));
>                   e3 = *(uint32_t *)(va + H1_4(i)) ^ neg3;
> -                r = float32_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
> +                r = float32_muladd(e1, e2, e3, 0, status);
>                   *(uint32_t *)(vd + H1_4(i)) = r;
>               }
>           } while (i & 63);
>       } while (i != 0);
>   }
>   
> -void HELPER(sve_fmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
> +void HELPER(sve_fmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
> +                              void *vg, void *status, uint32_t desc)
>   {
> -    do_fmla_zpzzz_s(env, vg, desc, 0, 0);
> +    do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0);
>   }
>   
> -void HELPER(sve_fmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
> +void HELPER(sve_fmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
> +                              void *vg, void *status, uint32_t desc)
>   {
> -    do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0);
> +    do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0);
>   }
>   
> -void HELPER(sve_fnmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
> +void HELPER(sve_fnmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>   {
> -    do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0x80000000);
> +    do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0x80000000);
>   }
>   
> -void HELPER(sve_fnmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
> +void HELPER(sve_fnmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>   {
> -    do_fmla_zpzzz_s(env, vg, desc, 0, 0x80000000);
> +    do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000);
>   }
>   
> -static void do_fmla_zpzzz_d(CPUARMState *env, void *vg, uint32_t desc,
> +static void do_fmla_zpzzz_d(void *vd, void *vn, void *vm, void *va, void *vg,
> +                            float_status *status, uint32_t desc,
>                               uint64_t neg1, uint64_t neg3)
>   {
>       intptr_t i = simd_oprsz(desc);
> -    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
> -    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
> -    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
> -    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
> -    void *vd = &env->vfp.zregs[rd];
> -    void *vn = &env->vfp.zregs[rn];
> -    void *vm = &env->vfp.zregs[rm];
> -    void *va = &env->vfp.zregs[ra];
>       uint64_t *g = vg;
>   
>       do {
> @@ -3503,31 +3485,35 @@ static void do_fmla_zpzzz_d(CPUARMState *env, void *vg, uint32_t desc,
>                   e1 = *(uint64_t *)(vn + i) ^ neg1;
>                   e2 = *(uint64_t *)(vm + i);
>                   e3 = *(uint64_t *)(va + i) ^ neg3;
> -                r = float64_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
> +                r = float64_muladd(e1, e2, e3, 0, status);
>                   *(uint64_t *)(vd + i) = r;
>               }
>           } while (i & 63);
>       } while (i != 0);
>   }
>   
> -void HELPER(sve_fmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
> +void HELPER(sve_fmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
> +                              void *vg, void *status, uint32_t desc)
>   {
> -    do_fmla_zpzzz_d(env, vg, desc, 0, 0);
> +    do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0);
>   }
>   
> -void HELPER(sve_fmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
> +void HELPER(sve_fmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
> +                              void *vg, void *status, uint32_t desc)
>   {
> -    do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, 0);
> +    do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0);
>   }
>   
> -void HELPER(sve_fnmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
> +void HELPER(sve_fnmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>   {
> -    do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, INT64_MIN);
> +    do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, INT64_MIN);
>   }
>   
> -void HELPER(sve_fnmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
> +void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>   {
> -    do_fmla_zpzzz_d(env, vg, desc, 0, INT64_MIN);
> +    do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN);
>   }
>   
>   /* Two operand floating-point comparison controlled by a predicate.
> @@ -3809,22 +3795,13 @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
>    * FP Complex Multiply
>    */
>   
> -QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 22 > 32);
> -
> -void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
> +void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>   {
>       intptr_t j, i = simd_oprsz(desc);
> -    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
> -    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
> -    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
> -    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
> -    unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
> +    unsigned rot = simd_data(desc);
>       bool flip = rot & 1;
>       float16 neg_imag, neg_real;
> -    void *vd = &env->vfp.zregs[rd];
> -    void *vn = &env->vfp.zregs[rn];
> -    void *vm = &env->vfp.zregs[rm];
> -    void *va = &env->vfp.zregs[ra];
>       uint64_t *g = vg;
>   
>       neg_imag = float16_set_sign(0, (rot & 2) != 0);
> @@ -3851,32 +3828,25 @@ void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
>   
>               if (likely((pg >> (i & 63)) & 1)) {
>                   d = *(float16 *)(va + H1_2(i));
> -                d = float16_muladd(e2, e1, d, 0, &env->vfp.fp_status_f16);
> +                d = float16_muladd(e2, e1, d, 0, status);
>                   *(float16 *)(vd + H1_2(i)) = d;
>               }
>               if (likely((pg >> (j & 63)) & 1)) {
>                   d = *(float16 *)(va + H1_2(j));
> -                d = float16_muladd(e4, e3, d, 0, &env->vfp.fp_status_f16);
> +                d = float16_muladd(e4, e3, d, 0, status);
>                   *(float16 *)(vd + H1_2(j)) = d;
>               }
>           } while (i & 63);
>       } while (i != 0);
>   }
>   
> -void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
> +void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>   {
>       intptr_t j, i = simd_oprsz(desc);
> -    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
> -    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
> -    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
> -    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
> -    unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
> +    unsigned rot = simd_data(desc);
>       bool flip = rot & 1;
>       float32 neg_imag, neg_real;
> -    void *vd = &env->vfp.zregs[rd];
> -    void *vn = &env->vfp.zregs[rn];
> -    void *vm = &env->vfp.zregs[rm];
> -    void *va = &env->vfp.zregs[ra];
>       uint64_t *g = vg;
>   
>       neg_imag = float32_set_sign(0, (rot & 2) != 0);
> @@ -3903,32 +3873,25 @@ void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
>   
>               if (likely((pg >> (i & 63)) & 1)) {
>                   d = *(float32 *)(va + H1_2(i));
> -                d = float32_muladd(e2, e1, d, 0, &env->vfp.fp_status);
> +                d = float32_muladd(e2, e1, d, 0, status);
>                   *(float32 *)(vd + H1_2(i)) = d;
>               }
>               if (likely((pg >> (j & 63)) & 1)) {
>                   d = *(float32 *)(va + H1_2(j));
> -                d = float32_muladd(e4, e3, d, 0, &env->vfp.fp_status);
> +                d = float32_muladd(e4, e3, d, 0, status);
>                   *(float32 *)(vd + H1_2(j)) = d;
>               }
>           } while (i & 63);
>       } while (i != 0);
>   }
>   
> -void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
> +void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>   {
>       intptr_t j, i = simd_oprsz(desc);
> -    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
> -    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
> -    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
> -    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
> -    unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
> +    unsigned rot = simd_data(desc);
>       bool flip = rot & 1;
>       float64 neg_imag, neg_real;
> -    void *vd = &env->vfp.zregs[rd];
> -    void *vn = &env->vfp.zregs[rn];
> -    void *vm = &env->vfp.zregs[rm];
> -    void *va = &env->vfp.zregs[ra];
>       uint64_t *g = vg;
>   
>       neg_imag = float64_set_sign(0, (rot & 2) != 0);
> @@ -3955,12 +3918,12 @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
>   
>               if (likely((pg >> (i & 63)) & 1)) {
>                   d = *(float64 *)(va + H1_2(i));
> -                d = float64_muladd(e2, e1, d, 0, &env->vfp.fp_status);
> +                d = float64_muladd(e2, e1, d, 0, status);
>                   *(float64 *)(vd + H1_2(i)) = d;
>               }
>               if (likely((pg >> (j & 63)) & 1)) {
>                   d = *(float64 *)(va + H1_2(j));
> -                d = float64_muladd(e4, e3, d, 0, &env->vfp.fp_status);
> +                d = float64_muladd(e4, e3, d, 0, status);
>                   *(float64 *)(vd + H1_2(j)) = d;
>               }
>           } while (i & 63);
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index b35bad245e..7607593f6b 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -3950,40 +3950,30 @@ static bool trans_FCADD(DisasContext *s, arg_FCADD *a)
>   
>   typedef void gen_helper_sve_fmla(TCGv_env, TCGv_ptr, TCGv_i32);

You can remove that typedef now.

>   
> -static bool do_fmla(DisasContext *s, arg_rprrr_esz *a, gen_helper_sve_fmla *fn)
> +static bool do_fmla(DisasContext *s, arg_rprrr_esz *a,
> +                    gen_helper_gvec_5_ptr *fn)
>   {
> -    if (fn == NULL) {
> +    if (a->esz == 0) {
>           return false;
>       }
> -    if (!sve_access_check(s)) {
> -        return true;
> +    if (sve_access_check(s)) {
> +        unsigned vsz = vec_full_reg_size(s);
> +        TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
> +        tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
> +                           vec_full_reg_offset(s, a->rn),
> +                           vec_full_reg_offset(s, a->rm),
> +                           vec_full_reg_offset(s, a->ra),
> +                           pred_full_reg_offset(s, a->pg),
> +                           status, vsz, vsz, 0, fn);
> +        tcg_temp_free_ptr(status);
>       }
> -
> -    unsigned vsz = vec_full_reg_size(s);
> -    unsigned desc;
> -    TCGv_i32 t_desc;
> -    TCGv_ptr pg = tcg_temp_new_ptr();
> -
> -    /* We would need 7 operands to pass these arguments "properly".
> -     * So we encode all the register numbers into the descriptor.
> -     */
> -    desc = deposit32(a->rd, 5, 5, a->rn);
> -    desc = deposit32(desc, 10, 5, a->rm);
> -    desc = deposit32(desc, 15, 5, a->ra);
> -    desc = simd_desc(vsz, vsz, desc);
> -
> -    t_desc = tcg_const_i32(desc);
> -    tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
> -    fn(cpu_env, pg, t_desc);
> -    tcg_temp_free_i32(t_desc);
> -    tcg_temp_free_ptr(pg);
>       return true;
>   }
>   
>   #define DO_FMLA(NAME, name) \
>   static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a)          \
>   {                                                                    \
> -    static gen_helper_sve_fmla * const fns[4] = {                    \
> +    static gen_helper_gvec_5_ptr * const fns[4] = {                  \
>           NULL, gen_helper_sve_##name##_h,                             \
>           gen_helper_sve_##name##_s, gen_helper_sve_##name##_d         \
>       };                                                               \
> @@ -3999,7 +3989,8 @@ DO_FMLA(FNMLS_zpzzz, fnmls_zpzzz)
>   
>   static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
>   {
> -    static gen_helper_sve_fmla * const fns[3] = {
> +    static gen_helper_gvec_5_ptr * const fns[4] = {
> +        NULL,
>           gen_helper_sve_fcmla_zpzzz_h,
>           gen_helper_sve_fcmla_zpzzz_s,
>           gen_helper_sve_fcmla_zpzzz_d,
> @@ -4010,25 +4001,14 @@ static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
>       }
>       if (sve_access_check(s)) {
>           unsigned vsz = vec_full_reg_size(s);
> -        unsigned desc;
> -        TCGv_i32 t_desc;
> -        TCGv_ptr pg = tcg_temp_new_ptr();
> -
> -        /* We would need 7 operands to pass these arguments "properly".
> -         * So we encode all the register numbers into the descriptor.
> -         */
> -        desc = deposit32(a->rd, 5, 5, a->rn);
> -        desc = deposit32(desc, 10, 5, a->rm);
> -        desc = deposit32(desc, 15, 5, a->ra);
> -        desc = deposit32(desc, 20, 2, a->rot);
> -        desc = sextract32(desc, 0, 22);
> -        desc = simd_desc(vsz, vsz, desc);
> -
> -        t_desc = tcg_const_i32(desc);
> -        tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
> -        fns[a->esz - 1](cpu_env, pg, t_desc);
> -        tcg_temp_free_i32(t_desc);
> -        tcg_temp_free_ptr(pg);
> +        TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
> +        tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
> +                           vec_full_reg_offset(s, a->rn),
> +                           vec_full_reg_offset(s, a->rm),
> +                           vec_full_reg_offset(s, a->ra),
> +                           pred_full_reg_offset(s, a->pg),
> +                           status, vsz, vsz, a->rot, fns[a->esz]);
> +        tcg_temp_free_ptr(status);
>       }
>       return true;
>   }
> 



^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 1/2] tcg: Add tcg_gen_gvec_5_ptr
  2020-02-12  2:51 ` [PATCH 1/2] tcg: Add tcg_gen_gvec_5_ptr Richard Henderson
  2020-02-12  6:09   ` Philippe Mathieu-Daudé
@ 2020-02-12 10:47   ` Alex Bennée
  2020-02-12 16:28   ` Taylor Simpson
  2 siblings, 0 replies; 10+ messages in thread
From: Alex Bennée @ 2020-02-12 10:47 UTC (permalink / raw)
  To: Richard Henderson; +Cc: peter.maydell, tsimpson, qemu-devel


Richard Henderson <richard.henderson@linaro.org> writes:

> Extend the vector generator infrastructure to handle
> 5 vector arguments.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  include/tcg/tcg-op-gvec.h |  7 +++++++
>  tcg/tcg-op-gvec.c         | 32 ++++++++++++++++++++++++++++++++
>  2 files changed, 39 insertions(+)
>
> diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
> index 830d68f697..74534e2480 100644
> --- a/include/tcg/tcg-op-gvec.h
> +++ b/include/tcg/tcg-op-gvec.h
> @@ -83,6 +83,13 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
>                          uint32_t maxsz, int32_t data,
>                          gen_helper_gvec_4_ptr *fn);
>  
> +typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
> +                                   TCGv_ptr, TCGv_ptr, TCGv_i32);
> +void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
> +                        uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
> +                        uint32_t oprsz, uint32_t maxsz, int32_t data,
> +                        gen_helper_gvec_5_ptr *fn);
> +
>  /* Expand a gvec operation.  Either inline or out-of-line depending on
>     the actual vector size and the operations supported by the host.  */
>  typedef struct {
> diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
> index 41b4a3c661..327d9588e0 100644
> --- a/tcg/tcg-op-gvec.c
> +++ b/tcg/tcg-op-gvec.c
> @@ -290,6 +290,38 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
>      tcg_temp_free_i32(desc);
>  }
>  
> +/* Generate a call to a gvec-style helper with five vector operands
> +   and an extra pointer operand.  */
> +void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
> +                        uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
> +                        uint32_t oprsz, uint32_t maxsz, int32_t data,
> +                        gen_helper_gvec_5_ptr *fn)
> +{
> +    TCGv_ptr a0, a1, a2, a3, a4;
> +    TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
> +
> +    a0 = tcg_temp_new_ptr();
> +    a1 = tcg_temp_new_ptr();
> +    a2 = tcg_temp_new_ptr();
> +    a3 = tcg_temp_new_ptr();
> +    a4 = tcg_temp_new_ptr();
> +
> +    tcg_gen_addi_ptr(a0, cpu_env, dofs);
> +    tcg_gen_addi_ptr(a1, cpu_env, aofs);
> +    tcg_gen_addi_ptr(a2, cpu_env, bofs);
> +    tcg_gen_addi_ptr(a3, cpu_env, cofs);
> +    tcg_gen_addi_ptr(a4, cpu_env, eofs);
> +
> +    fn(a0, a1, a2, a3, a4, ptr, desc);
> +
> +    tcg_temp_free_ptr(a0);
> +    tcg_temp_free_ptr(a1);
> +    tcg_temp_free_ptr(a2);
> +    tcg_temp_free_ptr(a3);
> +    tcg_temp_free_ptr(a4);
> +    tcg_temp_free_i32(desc);
> +}
> +
>  /* Return true if we want to implement something of OPRSZ bytes
>     in units of LNSZ.  This limits the expansion of inline code.  */
>  static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)


-- 
Alex Bennée


^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 2/2] target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
  2020-02-12  2:51 ` [PATCH 2/2] target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA Richard Henderson
  2020-02-12  6:14   ` Philippe Mathieu-Daudé
@ 2020-02-12 10:50   ` Alex Bennée
  2020-02-12 19:52     ` Richard Henderson
  2020-02-12 16:28   ` Taylor Simpson
  2 siblings, 1 reply; 10+ messages in thread
From: Alex Bennée @ 2020-02-12 10:50 UTC (permalink / raw)
  To: Richard Henderson; +Cc: peter.maydell, tsimpson, qemu-devel


Richard Henderson <richard.henderson@linaro.org> writes:

> Now that we can pass 7 parameters, do not encode register
> operands within simd_data.

What defines the upper limit? Is it the ABI of the backend or just the
efficiency of implementing the prologue for the call?
> --- a/target/arm/sve_helper.c
> +++ b/target/arm/sve_helper.c
> @@ -3372,23 +3372,11 @@ DO_ZPZ_FP(sve_ucvt_dd, uint64_t,     , uint64_to_float64)
>  
>  #undef DO_ZPZ_FP
>  
> -/* 4-operand predicated multiply-add.  This requires 7 operands to pass
> - * "properly", so we need to encode some of the registers into DESC.
> - */
> -QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 20 > 32);
> -
> -static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
> +static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg,
> +                            float_status *status, uint32_t desc,
>                              uint16_t neg1, uint16_t neg3)
>  {
>      intptr_t i = simd_oprsz(desc);
> -    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
> -    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
> -    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
> -    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
> -    void *vd = &env->vfp.zregs[rd];
> -    void *vn = &env->vfp.zregs[rn];
> -    void *vm = &env->vfp.zregs[rm];
> -    void *va = &env->vfp.zregs[ra];
<snip>
> @@ -4010,25 +4001,14 @@ static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
>      }
>      if (sve_access_check(s)) {
>          unsigned vsz = vec_full_reg_size(s);
> -        unsigned desc;
> -        TCGv_i32 t_desc;
> -        TCGv_ptr pg = tcg_temp_new_ptr();
> -
> -        /* We would need 7 operands to pass these arguments "properly".
> -         * So we encode all the register numbers into the descriptor.
> -         */
> -        desc = deposit32(a->rd, 5, 5, a->rn);
> -        desc = deposit32(desc, 10, 5, a->rm);
> -        desc = deposit32(desc, 15, 5, a->ra);
> -        desc = deposit32(desc, 20, 2, a->rot);
> -        desc = sextract32(desc, 0, 22);
> -        desc = simd_desc(vsz, vsz, desc);
> -
> -        t_desc = tcg_const_i32(desc);
> -        tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
> -        fns[a->esz - 1](cpu_env, pg, t_desc);
> -        tcg_temp_free_i32(t_desc);
> -        tcg_temp_free_ptr(pg);
> +        TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
> +        tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
> +                           vec_full_reg_offset(s, a->rn),
> +                           vec_full_reg_offset(s, a->rm),
> +                           vec_full_reg_offset(s, a->ra),
> +                           pred_full_reg_offset(s, a->pg),
> +                           status, vsz, vsz, a->rot, fns[a->esz]);
> +        tcg_temp_free_ptr(status);
>      }
>      return true;
>  }

Good to see the code simplified ;-)

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

-- 
Alex Bennée


^ permalink raw reply	[flat|nested] 10+ messages in thread

* RE: [PATCH 2/2] target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
  2020-02-12  2:51 ` [PATCH 2/2] target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA Richard Henderson
  2020-02-12  6:14   ` Philippe Mathieu-Daudé
  2020-02-12 10:50   ` Alex Bennée
@ 2020-02-12 16:28   ` Taylor Simpson
  2 siblings, 0 replies; 10+ messages in thread
From: Taylor Simpson @ 2020-02-12 16:28 UTC (permalink / raw)
  To: Richard Henderson, qemu-devel; +Cc: peter.maydell, alex.bennee

Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>

> -----Original Message-----
> From: Richard Henderson <richard.henderson@linaro.org>
> Sent: Tuesday, February 11, 2020 8:52 PM
> To: qemu-devel@nongnu.org
> Cc: peter.maydell@linaro.org; alex.bennee@linaro.org; Taylor Simpson
> <tsimpson@quicinc.com>
> Subject: [PATCH 2/2] target/arm: Use tcg_gen_gvec_5_ptr for sve
> FMLA/FCMLA
>
> Now that we can pass 7 parameters, do not encode register
> operands within simd_data.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/helper-sve.h    |  45 +++++++----
>  target/arm/sve_helper.c    | 157 ++++++++++++++-----------------------
>  target/arm/translate-sve.c |  68 ++++++----------
>  3 files changed, 114 insertions(+), 156 deletions(-)
>
> diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
> index 9e79182ab4..bd8b91bdb6 100644
> --- a/target/arm/helper-sve.h
> +++ b/target/arm/helper-sve.h
> @@ -1099,25 +1099,40 @@ DEF_HELPER_FLAGS_6(sve_fcadd_s,
> TCG_CALL_NO_RWG,
>  DEF_HELPER_FLAGS_6(sve_fcadd_d, TCG_CALL_NO_RWG,
>                     void, ptr, ptr, ptr, ptr, ptr, i32)
>
> -DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG, void, env,
> ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG, void, env,
> ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG, void, env,
> ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
>
> -DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG, void, env,
> ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG, void, env,
> ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG, void, env,
> ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
>
> -DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG, void,
> env, ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG, void, env,
> ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG, void,
> env, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
>
> -DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG, void, env,
> ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG, void, env,
> ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG, void, env,
> ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
>
> -DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG, void, env,
> ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG, void, env,
> ptr, i32)
> -DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG, void, env,
> ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
>
>  DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr,
> ptr, ptr, i32)
>  DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr,
> ptr, ptr, i32)
> diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
> index fdfa652094..33b5a54a47 100644
> --- a/target/arm/sve_helper.c
> +++ b/target/arm/sve_helper.c
> @@ -3372,23 +3372,11 @@ DO_ZPZ_FP(sve_ucvt_dd, uint64_t,     ,
> uint64_to_float64)
>
>  #undef DO_ZPZ_FP
>
> -/* 4-operand predicated multiply-add.  This requires 7 operands to pass
> - * "properly", so we need to encode some of the registers into DESC.
> - */
> -QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 20 > 32);
> -
> -static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
> +static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void
> *vg,
> +                            float_status *status, uint32_t desc,
>                              uint16_t neg1, uint16_t neg3)
>  {
>      intptr_t i = simd_oprsz(desc);
> -    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
> -    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
> -    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
> -    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
> -    void *vd = &env->vfp.zregs[rd];
> -    void *vn = &env->vfp.zregs[rn];
> -    void *vm = &env->vfp.zregs[rm];
> -    void *va = &env->vfp.zregs[ra];
>      uint64_t *g = vg;
>
>      do {
> @@ -3401,45 +3389,42 @@ static void do_fmla_zpzzz_h(CPUARMState
> *env, void *vg, uint32_t desc,
>                  e1 = *(uint16_t *)(vn + H1_2(i)) ^ neg1;
>                  e2 = *(uint16_t *)(vm + H1_2(i));
>                  e3 = *(uint16_t *)(va + H1_2(i)) ^ neg3;
> -                r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status_f16);
> +                r = float16_muladd(e1, e2, e3, 0, status);
>                  *(uint16_t *)(vd + H1_2(i)) = r;
>              }
>          } while (i & 63);
>      } while (i != 0);
>  }
>
> -void HELPER(sve_fmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t
> desc)
> +void HELPER(sve_fmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
> +                              void *vg, void *status, uint32_t desc)
>  {
> -    do_fmla_zpzzz_h(env, vg, desc, 0, 0);
> +    do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0);
>  }
>
> -void HELPER(sve_fmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t
> desc)
> +void HELPER(sve_fmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
> +                              void *vg, void *status, uint32_t desc)
>  {
> -    do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0);
> +    do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0);
>  }
>
> -void HELPER(sve_fnmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t
> desc)
> +void HELPER(sve_fnmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>  {
> -    do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0x8000);
> +    do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000);
>  }
>
> -void HELPER(sve_fnmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t
> desc)
> +void HELPER(sve_fnmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>  {
> -    do_fmla_zpzzz_h(env, vg, desc, 0, 0x8000);
> +    do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000);
>  }
>
> -static void do_fmla_zpzzz_s(CPUARMState *env, void *vg, uint32_t desc,
> +static void do_fmla_zpzzz_s(void *vd, void *vn, void *vm, void *va, void
> *vg,
> +                            float_status *status, uint32_t desc,
>                              uint32_t neg1, uint32_t neg3)
>  {
>      intptr_t i = simd_oprsz(desc);
> -    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
> -    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
> -    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
> -    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
> -    void *vd = &env->vfp.zregs[rd];
> -    void *vn = &env->vfp.zregs[rn];
> -    void *vm = &env->vfp.zregs[rm];
> -    void *va = &env->vfp.zregs[ra];
>      uint64_t *g = vg;
>
>      do {
> @@ -3452,45 +3437,42 @@ static void do_fmla_zpzzz_s(CPUARMState *env,
> void *vg, uint32_t desc,
>                  e1 = *(uint32_t *)(vn + H1_4(i)) ^ neg1;
>                  e2 = *(uint32_t *)(vm + H1_4(i));
>                  e3 = *(uint32_t *)(va + H1_4(i)) ^ neg3;
> -                r = float32_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
> +                r = float32_muladd(e1, e2, e3, 0, status);
>                  *(uint32_t *)(vd + H1_4(i)) = r;
>              }
>          } while (i & 63);
>      } while (i != 0);
>  }
>
> -void HELPER(sve_fmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t
> desc)
> +void HELPER(sve_fmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
> +                              void *vg, void *status, uint32_t desc)
>  {
> -    do_fmla_zpzzz_s(env, vg, desc, 0, 0);
> +    do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0);
>  }
>
> -void HELPER(sve_fmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t
> desc)
> +void HELPER(sve_fmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
> +                              void *vg, void *status, uint32_t desc)
>  {
> -    do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0);
> +    do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0);
>  }
>
> -void HELPER(sve_fnmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t
> desc)
> +void HELPER(sve_fnmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>  {
> -    do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0x80000000);
> +    do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000,
> 0x80000000);
>  }
>
> -void HELPER(sve_fnmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t
> desc)
> +void HELPER(sve_fnmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>  {
> -    do_fmla_zpzzz_s(env, vg, desc, 0, 0x80000000);
> +    do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000);
>  }
>
> -static void do_fmla_zpzzz_d(CPUARMState *env, void *vg, uint32_t desc,
> +static void do_fmla_zpzzz_d(void *vd, void *vn, void *vm, void *va, void
> *vg,
> +                            float_status *status, uint32_t desc,
>                              uint64_t neg1, uint64_t neg3)
>  {
>      intptr_t i = simd_oprsz(desc);
> -    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
> -    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
> -    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
> -    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
> -    void *vd = &env->vfp.zregs[rd];
> -    void *vn = &env->vfp.zregs[rn];
> -    void *vm = &env->vfp.zregs[rm];
> -    void *va = &env->vfp.zregs[ra];
>      uint64_t *g = vg;
>
>      do {
> @@ -3503,31 +3485,35 @@ static void do_fmla_zpzzz_d(CPUARMState
> *env, void *vg, uint32_t desc,
>                  e1 = *(uint64_t *)(vn + i) ^ neg1;
>                  e2 = *(uint64_t *)(vm + i);
>                  e3 = *(uint64_t *)(va + i) ^ neg3;
> -                r = float64_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
> +                r = float64_muladd(e1, e2, e3, 0, status);
>                  *(uint64_t *)(vd + i) = r;
>              }
>          } while (i & 63);
>      } while (i != 0);
>  }
>
> -void HELPER(sve_fmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t
> desc)
> +void HELPER(sve_fmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
> +                              void *vg, void *status, uint32_t desc)
>  {
> -    do_fmla_zpzzz_d(env, vg, desc, 0, 0);
> +    do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0);
>  }
>
> -void HELPER(sve_fmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t
> desc)
> +void HELPER(sve_fmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
> +                              void *vg, void *status, uint32_t desc)
>  {
> -    do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, 0);
> +    do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0);
>  }
>
> -void HELPER(sve_fnmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t
> desc)
> +void HELPER(sve_fnmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>  {
> -    do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, INT64_MIN);
> +    do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN,
> INT64_MIN);
>  }
>
> -void HELPER(sve_fnmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t
> desc)
> +void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>  {
> -    do_fmla_zpzzz_d(env, vg, desc, 0, INT64_MIN);
> +    do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN);
>  }
>
>  /* Two operand floating-point comparison controlled by a predicate.
> @@ -3809,22 +3795,13 @@ void HELPER(sve_fcadd_d)(void *vd, void *vn,
> void *vm, void *vg,
>   * FP Complex Multiply
>   */
>
> -QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 22 > 32);
> -
> -void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t
> desc)
> +void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>  {
>      intptr_t j, i = simd_oprsz(desc);
> -    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
> -    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
> -    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
> -    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
> -    unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
> +    unsigned rot = simd_data(desc);
>      bool flip = rot & 1;
>      float16 neg_imag, neg_real;
> -    void *vd = &env->vfp.zregs[rd];
> -    void *vn = &env->vfp.zregs[rn];
> -    void *vm = &env->vfp.zregs[rm];
> -    void *va = &env->vfp.zregs[ra];
>      uint64_t *g = vg;
>
>      neg_imag = float16_set_sign(0, (rot & 2) != 0);
> @@ -3851,32 +3828,25 @@ void HELPER(sve_fcmla_zpzzz_h)(CPUARMState
> *env, void *vg, uint32_t desc)
>
>              if (likely((pg >> (i & 63)) & 1)) {
>                  d = *(float16 *)(va + H1_2(i));
> -                d = float16_muladd(e2, e1, d, 0, &env->vfp.fp_status_f16);
> +                d = float16_muladd(e2, e1, d, 0, status);
>                  *(float16 *)(vd + H1_2(i)) = d;
>              }
>              if (likely((pg >> (j & 63)) & 1)) {
>                  d = *(float16 *)(va + H1_2(j));
> -                d = float16_muladd(e4, e3, d, 0, &env->vfp.fp_status_f16);
> +                d = float16_muladd(e4, e3, d, 0, status);
>                  *(float16 *)(vd + H1_2(j)) = d;
>              }
>          } while (i & 63);
>      } while (i != 0);
>  }
>
> -void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t
> desc)
> +void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>  {
>      intptr_t j, i = simd_oprsz(desc);
> -    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
> -    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
> -    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
> -    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
> -    unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
> +    unsigned rot = simd_data(desc);
>      bool flip = rot & 1;
>      float32 neg_imag, neg_real;
> -    void *vd = &env->vfp.zregs[rd];
> -    void *vn = &env->vfp.zregs[rn];
> -    void *vm = &env->vfp.zregs[rm];
> -    void *va = &env->vfp.zregs[ra];
>      uint64_t *g = vg;
>
>      neg_imag = float32_set_sign(0, (rot & 2) != 0);
> @@ -3903,32 +3873,25 @@ void HELPER(sve_fcmla_zpzzz_s)(CPUARMState
> *env, void *vg, uint32_t desc)
>
>              if (likely((pg >> (i & 63)) & 1)) {
>                  d = *(float32 *)(va + H1_2(i));
> -                d = float32_muladd(e2, e1, d, 0, &env->vfp.fp_status);
> +                d = float32_muladd(e2, e1, d, 0, status);
>                  *(float32 *)(vd + H1_2(i)) = d;
>              }
>              if (likely((pg >> (j & 63)) & 1)) {
>                  d = *(float32 *)(va + H1_2(j));
> -                d = float32_muladd(e4, e3, d, 0, &env->vfp.fp_status);
> +                d = float32_muladd(e4, e3, d, 0, status);
>                  *(float32 *)(vd + H1_2(j)) = d;
>              }
>          } while (i & 63);
>      } while (i != 0);
>  }
>
> -void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t
> desc)
> +void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
> +                               void *vg, void *status, uint32_t desc)
>  {
>      intptr_t j, i = simd_oprsz(desc);
> -    unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
> -    unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
> -    unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
> -    unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
> -    unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
> +    unsigned rot = simd_data(desc);
>      bool flip = rot & 1;
>      float64 neg_imag, neg_real;
> -    void *vd = &env->vfp.zregs[rd];
> -    void *vn = &env->vfp.zregs[rn];
> -    void *vm = &env->vfp.zregs[rm];
> -    void *va = &env->vfp.zregs[ra];
>      uint64_t *g = vg;
>
>      neg_imag = float64_set_sign(0, (rot & 2) != 0);
> @@ -3955,12 +3918,12 @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState
> *env, void *vg, uint32_t desc)
>
>              if (likely((pg >> (i & 63)) & 1)) {
>                  d = *(float64 *)(va + H1_2(i));
> -                d = float64_muladd(e2, e1, d, 0, &env->vfp.fp_status);
> +                d = float64_muladd(e2, e1, d, 0, status);
>                  *(float64 *)(vd + H1_2(i)) = d;
>              }
>              if (likely((pg >> (j & 63)) & 1)) {
>                  d = *(float64 *)(va + H1_2(j));
> -                d = float64_muladd(e4, e3, d, 0, &env->vfp.fp_status);
> +                d = float64_muladd(e4, e3, d, 0, status);
>                  *(float64 *)(vd + H1_2(j)) = d;
>              }
>          } while (i & 63);
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index b35bad245e..7607593f6b 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -3950,40 +3950,30 @@ static bool trans_FCADD(DisasContext *s,
> arg_FCADD *a)
>
>  typedef void gen_helper_sve_fmla(TCGv_env, TCGv_ptr, TCGv_i32);
>
> -static bool do_fmla(DisasContext *s, arg_rprrr_esz *a,
> gen_helper_sve_fmla *fn)
> +static bool do_fmla(DisasContext *s, arg_rprrr_esz *a,
> +                    gen_helper_gvec_5_ptr *fn)
>  {
> -    if (fn == NULL) {
> +    if (a->esz == 0) {
>          return false;
>      }
> -    if (!sve_access_check(s)) {
> -        return true;
> +    if (sve_access_check(s)) {
> +        unsigned vsz = vec_full_reg_size(s);
> +        TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
> +        tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
> +                           vec_full_reg_offset(s, a->rn),
> +                           vec_full_reg_offset(s, a->rm),
> +                           vec_full_reg_offset(s, a->ra),
> +                           pred_full_reg_offset(s, a->pg),
> +                           status, vsz, vsz, 0, fn);
> +        tcg_temp_free_ptr(status);
>      }
> -
> -    unsigned vsz = vec_full_reg_size(s);
> -    unsigned desc;
> -    TCGv_i32 t_desc;
> -    TCGv_ptr pg = tcg_temp_new_ptr();
> -
> -    /* We would need 7 operands to pass these arguments "properly".
> -     * So we encode all the register numbers into the descriptor.
> -     */
> -    desc = deposit32(a->rd, 5, 5, a->rn);
> -    desc = deposit32(desc, 10, 5, a->rm);
> -    desc = deposit32(desc, 15, 5, a->ra);
> -    desc = simd_desc(vsz, vsz, desc);
> -
> -    t_desc = tcg_const_i32(desc);
> -    tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
> -    fn(cpu_env, pg, t_desc);
> -    tcg_temp_free_i32(t_desc);
> -    tcg_temp_free_ptr(pg);
>      return true;
>  }
>
>  #define DO_FMLA(NAME, name) \
>  static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a)          \
>  {                                                                    \
> -    static gen_helper_sve_fmla * const fns[4] = {                    \
> +    static gen_helper_gvec_5_ptr * const fns[4] = {                  \
>          NULL, gen_helper_sve_##name##_h,                             \
>          gen_helper_sve_##name##_s, gen_helper_sve_##name##_d         \
>      };                                                               \
> @@ -3999,7 +3989,8 @@ DO_FMLA(FNMLS_zpzzz, fnmls_zpzzz)
>
>  static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
>  {
> -    static gen_helper_sve_fmla * const fns[3] = {
> +    static gen_helper_gvec_5_ptr * const fns[4] = {
> +        NULL,
>          gen_helper_sve_fcmla_zpzzz_h,
>          gen_helper_sve_fcmla_zpzzz_s,
>          gen_helper_sve_fcmla_zpzzz_d,
> @@ -4010,25 +4001,14 @@ static bool trans_FCMLA_zpzzz(DisasContext *s,
> arg_FCMLA_zpzzz *a)
>      }
>      if (sve_access_check(s)) {
>          unsigned vsz = vec_full_reg_size(s);
> -        unsigned desc;
> -        TCGv_i32 t_desc;
> -        TCGv_ptr pg = tcg_temp_new_ptr();
> -
> -        /* We would need 7 operands to pass these arguments "properly".
> -         * So we encode all the register numbers into the descriptor.
> -         */
> -        desc = deposit32(a->rd, 5, 5, a->rn);
> -        desc = deposit32(desc, 10, 5, a->rm);
> -        desc = deposit32(desc, 15, 5, a->ra);
> -        desc = deposit32(desc, 20, 2, a->rot);
> -        desc = sextract32(desc, 0, 22);
> -        desc = simd_desc(vsz, vsz, desc);
> -
> -        t_desc = tcg_const_i32(desc);
> -        tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
> -        fns[a->esz - 1](cpu_env, pg, t_desc);
> -        tcg_temp_free_i32(t_desc);
> -        tcg_temp_free_ptr(pg);
> +        TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
> +        tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
> +                           vec_full_reg_offset(s, a->rn),
> +                           vec_full_reg_offset(s, a->rm),
> +                           vec_full_reg_offset(s, a->ra),
> +                           pred_full_reg_offset(s, a->pg),
> +                           status, vsz, vsz, a->rot, fns[a->esz]);
> +        tcg_temp_free_ptr(status);
>      }
>      return true;
>  }
> --
> 2.20.1
>



^ permalink raw reply	[flat|nested] 10+ messages in thread

* RE: [PATCH 1/2] tcg: Add tcg_gen_gvec_5_ptr
  2020-02-12  2:51 ` [PATCH 1/2] tcg: Add tcg_gen_gvec_5_ptr Richard Henderson
  2020-02-12  6:09   ` Philippe Mathieu-Daudé
  2020-02-12 10:47   ` Alex Bennée
@ 2020-02-12 16:28   ` Taylor Simpson
  2 siblings, 0 replies; 10+ messages in thread
From: Taylor Simpson @ 2020-02-12 16:28 UTC (permalink / raw)
  To: Richard Henderson, qemu-devel; +Cc: peter.maydell, alex.bennee

Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>


> -----Original Message-----
> From: Richard Henderson <richard.henderson@linaro.org>
> Sent: Tuesday, February 11, 2020 8:52 PM
> To: qemu-devel@nongnu.org
> Cc: peter.maydell@linaro.org; alex.bennee@linaro.org; Taylor Simpson
> <tsimpson@quicinc.com>
> Subject: [PATCH 1/2] tcg: Add tcg_gen_gvec_5_ptr
>
> Extend the vector generator infrastructure to handle
> 5 vector arguments.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  include/tcg/tcg-op-gvec.h |  7 +++++++
>  tcg/tcg-op-gvec.c         | 32 ++++++++++++++++++++++++++++++++
>  2 files changed, 39 insertions(+)
>
> diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
> index 830d68f697..74534e2480 100644
> --- a/include/tcg/tcg-op-gvec.h
> +++ b/include/tcg/tcg-op-gvec.h
> @@ -83,6 +83,13 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs,
> uint32_t bofs,
>                          uint32_t maxsz, int32_t data,
>                          gen_helper_gvec_4_ptr *fn);
>
> +typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr,
> TCGv_ptr,
> +                                   TCGv_ptr, TCGv_ptr, TCGv_i32);
> +void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
> +                        uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
> +                        uint32_t oprsz, uint32_t maxsz, int32_t data,
> +                        gen_helper_gvec_5_ptr *fn);
> +
>  /* Expand a gvec operation.  Either inline or out-of-line depending on
>     the actual vector size and the operations supported by the host.  */
>  typedef struct {
> diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
> index 41b4a3c661..327d9588e0 100644
> --- a/tcg/tcg-op-gvec.c
> +++ b/tcg/tcg-op-gvec.c
> @@ -290,6 +290,38 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t
> aofs, uint32_t bofs,
>      tcg_temp_free_i32(desc);
>  }
>
> +/* Generate a call to a gvec-style helper with five vector operands
> +   and an extra pointer operand.  */
> +void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
> +                        uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
> +                        uint32_t oprsz, uint32_t maxsz, int32_t data,
> +                        gen_helper_gvec_5_ptr *fn)
> +{
> +    TCGv_ptr a0, a1, a2, a3, a4;
> +    TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
> +
> +    a0 = tcg_temp_new_ptr();
> +    a1 = tcg_temp_new_ptr();
> +    a2 = tcg_temp_new_ptr();
> +    a3 = tcg_temp_new_ptr();
> +    a4 = tcg_temp_new_ptr();
> +
> +    tcg_gen_addi_ptr(a0, cpu_env, dofs);
> +    tcg_gen_addi_ptr(a1, cpu_env, aofs);
> +    tcg_gen_addi_ptr(a2, cpu_env, bofs);
> +    tcg_gen_addi_ptr(a3, cpu_env, cofs);
> +    tcg_gen_addi_ptr(a4, cpu_env, eofs);
> +
> +    fn(a0, a1, a2, a3, a4, ptr, desc);
> +
> +    tcg_temp_free_ptr(a0);
> +    tcg_temp_free_ptr(a1);
> +    tcg_temp_free_ptr(a2);
> +    tcg_temp_free_ptr(a3);
> +    tcg_temp_free_ptr(a4);
> +    tcg_temp_free_i32(desc);
> +}
> +
>  /* Return true if we want to implement something of OPRSZ bytes
>     in units of LNSZ.  This limits the expansion of inline code.  */
>  static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
> --
> 2.20.1
>



^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 2/2] target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
  2020-02-12 10:50   ` Alex Bennée
@ 2020-02-12 19:52     ` Richard Henderson
  0 siblings, 0 replies; 10+ messages in thread
From: Richard Henderson @ 2020-02-12 19:52 UTC (permalink / raw)
  To: Alex Bennée; +Cc: peter.maydell, tsimpson, qemu-devel

On 2/12/20 2:50 AM, Alex Bennée wrote:
> 
> Richard Henderson <richard.henderson@linaro.org> writes:
> 
>> Now that we can pass 7 parameters, do not encode register
>> operands within simd_data.
> 
> What defines the upper limit? Is it the ABI of the backend or just the
> efficiency of implementing the prologue for the call?

The current upper limit is from the lifetime tracking data.  Which gives us 14
arguments within the bits of the uint16_t.  Which gives us 7 uint64_t arguments
on a 32-bit host.


r~


^ permalink raw reply	[flat|nested] 10+ messages in thread

end of thread, other threads:[~2020-02-12 19:53 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-12  2:51 [PATCH 0/2] target/arm: Pass arguments by value for sve FMLA/FCMLA Richard Henderson
2020-02-12  2:51 ` [PATCH 1/2] tcg: Add tcg_gen_gvec_5_ptr Richard Henderson
2020-02-12  6:09   ` Philippe Mathieu-Daudé
2020-02-12 10:47   ` Alex Bennée
2020-02-12 16:28   ` Taylor Simpson
2020-02-12  2:51 ` [PATCH 2/2] target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA Richard Henderson
2020-02-12  6:14   ` Philippe Mathieu-Daudé
2020-02-12 10:50   ` Alex Bennée
2020-02-12 19:52     ` Richard Henderson
2020-02-12 16:28   ` Taylor Simpson

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