[PATCH 0/5] CHV and VLV separation and clean up

[PATCH 0/5] CHV and VLV separation and clean up

[Wayne Boyer]

The cherryview device shares many characteristics with the valleyview
device.  When support was added to the driver for cherryview, the
corresponding device info structure included .is_valleyview = 1.
This is not correct and leads to some confusion.

In addition to separating cherryview from valleyview, this series
helps to organize and prepare the code for future platforms.  It helps
avoid confusion like there was with IS_SKYLAKE and IS_KABYLAKE, and it
makes things easier if we decide to add .is_atom_lp to these platform
definitions.  Finally, it provides fixes to issues that were identified
in the first iteration of the separation changes.

Wayne Boyer (5):
  drm/i915: Separate cherryview from valleyview
  drm/i915: Use HAS_PCH_SPLIT to determine correct devices
  drm/i915: Remove VLV A0 hack
  drm/i915: Only set gem object L3 cache level for IVB devices
  drm/i915: Remove BUG_ON call in vlv_enable_pll

 drivers/gpu/drm/i915/i915_debugfs.c     | 68 ++++++++++++++++-----------------
 drivers/gpu/drm/i915/i915_dma.c         |  8 ++--
 drivers/gpu/drm/i915/i915_drv.c         | 10 ++---
 drivers/gpu/drm/i915/i915_drv.h         | 16 +++++---
 drivers/gpu/drm/i915/i915_gem.c         | 10 +----
 drivers/gpu/drm/i915/i915_gem_context.c |  8 ++--
 drivers/gpu/drm/i915/i915_irq.c         |  8 ++--
 drivers/gpu/drm/i915/i915_suspend.c     |  4 +-
 drivers/gpu/drm/i915/i915_sysfs.c       | 10 ++---
 drivers/gpu/drm/i915/intel_audio.c      |  7 ++--
 drivers/gpu/drm/i915/intel_bios.c       |  4 +-
 drivers/gpu/drm/i915/intel_crt.c        |  2 +-
 drivers/gpu/drm/i915/intel_display.c    | 57 +++++++++++++--------------
 drivers/gpu/drm/i915/intel_dp.c         | 40 +++++++++----------
 drivers/gpu/drm/i915/intel_dsi.c        | 14 +++----
 drivers/gpu/drm/i915/intel_dsi_pll.c    |  6 +--
 drivers/gpu/drm/i915/intel_hdmi.c       |  4 +-
 drivers/gpu/drm/i915/intel_hotplug.c    |  2 +-
 drivers/gpu/drm/i915/intel_i2c.c        |  2 +-
 drivers/gpu/drm/i915/intel_panel.c      |  2 +-
 drivers/gpu/drm/i915/intel_pm.c         |  8 ++--
 drivers/gpu/drm/i915/intel_psr.c        |  6 +--
 drivers/gpu/drm/i915/intel_sprite.c     |  4 +-
 drivers/gpu/drm/i915/intel_uncore.c     |  4 +-
 24 files changed, 150 insertions(+), 154 deletions(-)

-- 
2.6.3

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[PATCH 1/5] drm/i915: Separate cherryview from valleyview

[Wayne Boyer]

The cherryview device shares many characteristics with the valleyview
device.  When support was added to the driver for cherryview, the
corresponding device info structure included .is_valleyview = 1.
This is not correct and leads to some confusion.

This patch changes .is_valleyview to .is_cherryview in the cherryview
device info structure and simplifies the IS_CHERRYVIEW macro.
Then where appropriate, instances of IS_VALLEYVIEW are replaced with
IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent.

v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro.
    Also add followup patches to fix issues discovered during the first
    review. (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c     | 68 ++++++++++++++++-----------------
 drivers/gpu/drm/i915/i915_dma.c         |  8 ++--
 drivers/gpu/drm/i915/i915_drv.c         | 10 ++---
 drivers/gpu/drm/i915/i915_drv.h         | 16 +++++---
 drivers/gpu/drm/i915/i915_gem.c         |  4 +-
 drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
 drivers/gpu/drm/i915/i915_irq.c         |  8 ++--
 drivers/gpu/drm/i915/i915_suspend.c     |  4 +-
 drivers/gpu/drm/i915/i915_sysfs.c       | 10 ++---
 drivers/gpu/drm/i915/intel_audio.c      |  7 ++--
 drivers/gpu/drm/i915/intel_bios.c       |  4 +-
 drivers/gpu/drm/i915/intel_crt.c        |  2 +-
 drivers/gpu/drm/i915/intel_display.c    | 54 ++++++++++++++------------
 drivers/gpu/drm/i915/intel_dp.c         | 40 +++++++++----------
 drivers/gpu/drm/i915/intel_dsi.c        | 14 +++----
 drivers/gpu/drm/i915/intel_dsi_pll.c    |  6 +--
 drivers/gpu/drm/i915/intel_hdmi.c       |  4 +-
 drivers/gpu/drm/i915/intel_hotplug.c    |  2 +-
 drivers/gpu/drm/i915/intel_i2c.c        |  2 +-
 drivers/gpu/drm/i915/intel_panel.c      |  2 +-
 drivers/gpu/drm/i915/intel_pm.c         |  8 ++--
 drivers/gpu/drm/i915/intel_psr.c        |  6 +--
 drivers/gpu/drm/i915/intel_sprite.c     |  4 +-
 drivers/gpu/drm/i915/intel_uncore.c     |  4 +-
 24 files changed, 149 insertions(+), 140 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a8721fc..a9ae642 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1142,8 +1142,34 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 			   MEMSTAT_VID_SHIFT);
 		seq_printf(m, "Current P-state: %d\n",
 			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
-	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
-		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+		u32 freq_sts;
+
+		mutex_lock(&dev_priv->rps.hw_lock);
+		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
+		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
+
+		seq_printf(m, "actual GPU freq: %d MHz\n",
+			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
+
+		seq_printf(m, "current GPU freq: %d MHz\n",
+			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
+
+		seq_printf(m, "max GPU freq: %d MHz\n",
+			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
+
+		seq_printf(m, "min GPU freq: %d MHz\n",
+			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
+
+		seq_printf(m, "idle GPU freq: %d MHz\n",
+			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
+
+		seq_printf(m,
+			   "efficient (RPe) frequency: %d MHz\n",
+			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
+		mutex_unlock(&dev_priv->rps.hw_lock);
+	} else if (IS_GEN6(dev) || IS_BROADWELL(dev) || IS_GEN9(dev)) {
 		u32 rp_state_limits;
 		u32 gt_perf_status;
 		u32 rp_state_cap;
@@ -1284,33 +1310,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		seq_printf(m,
 			   "efficient (RPe) frequency: %d MHz\n",
 			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
-	} else if (IS_VALLEYVIEW(dev)) {
-		u32 freq_sts;
-
-		mutex_lock(&dev_priv->rps.hw_lock);
-		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
-		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
-		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
-
-		seq_printf(m, "actual GPU freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
-
-		seq_printf(m, "current GPU freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
-
-		seq_printf(m, "max GPU freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
-
-		seq_printf(m, "min GPU freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
-
-		seq_printf(m, "idle GPU freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
-
-		seq_printf(m,
-			   "efficient (RPe) frequency: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
-		mutex_unlock(&dev_priv->rps.hw_lock);
 	} else {
 		seq_puts(m, "no P-state info available\n");
 	}
@@ -1602,7 +1601,7 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
 	struct drm_info_node *node = m->private;
 	struct drm_device *dev = node->minor->dev;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		return vlv_drpc_info(m);
 	else if (INTEL_INFO(dev)->gen >= 6)
 		return gen6_drpc_info(m);
@@ -1743,7 +1742,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 	else if (IS_PINEVIEW(dev))
 		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 
 	intel_runtime_pm_put(dev_priv);
@@ -3983,7 +3982,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
 		ret = i8xx_pipe_crc_ctl_reg(&source, &val);
 	else if (INTEL_INFO(dev)->gen < 5)
 		ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
 	else if (IS_GEN5(dev) || IS_GEN6(dev))
 		ret = ilk_pipe_crc_ctl_reg(&source, &val);
@@ -4052,7 +4051,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
 
 		if (IS_G4X(dev))
 			g4x_undo_pipe_scramble_reset(dev, pipe);
-		else if (IS_VALLEYVIEW(dev))
+		else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 			vlv_undo_pipe_scramble_reset(dev, pipe);
 		else if (IS_HASWELL(dev) && pipe == PIPE_A)
 			hsw_trans_edp_pipe_A_crc_wa(dev, false);
@@ -4442,7 +4441,8 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
 		 * - WM1+ latency values in 0.5us units
 		 * - latencies are in us on gen9/vlv/chv
 		 */
-		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
+		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
+		    IS_CHERRYVIEW(dev))
 			latency *= 10;
 		else if (level > 0)
 			latency *= 5;
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a81c766..b156b08e 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -256,7 +256,7 @@ intel_setup_mchbar(struct drm_device *dev)
 	u32 temp;
 	bool enabled;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		return;
 
 	dev_priv->mchbar_need_disable = false;
@@ -779,7 +779,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 		info->num_sprites[PIPE_A] = 2;
 		info->num_sprites[PIPE_B] = 2;
 		info->num_sprites[PIPE_C] = 1;
-	} else if (IS_VALLEYVIEW(dev))
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		for_each_pipe(dev_priv, pipe)
 			info->num_sprites[pipe] = 2;
 	else
@@ -791,7 +791,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 		info->num_pipes = 0;
 	} else if (info->num_pipes > 0 &&
 		   (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
-		   !IS_VALLEYVIEW(dev)) {
+		   !(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) {
 		u32 fuse_strap = I915_READ(FUSE_STRAP);
 		u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 
@@ -836,7 +836,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 
 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 {
-	if (!IS_VALLEYVIEW(dev_priv))
+	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 		return;
 
 	/*
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e6935f1..841c3c4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -311,7 +311,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.gen = 8, .num_pipes = 3,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
-	.is_valleyview = 1,
+	.is_cherryview = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
 	GEN_CHV_PIPEOFFSETS,
 	CURSOR_OFFSETS,
@@ -802,7 +802,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
 	pci_set_master(dev->pdev);
 
-	if (IS_VALLEYVIEW(dev_priv))
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		ret = vlv_resume_prepare(dev_priv, false);
 	if (ret)
 		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
@@ -1532,7 +1532,7 @@ static int intel_runtime_resume(struct device *device)
 		ret = bxt_resume_prepare(dev_priv);
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		hsw_disable_pc8(dev_priv);
-	else if (IS_VALLEYVIEW(dev_priv))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		ret = vlv_resume_prepare(dev_priv, true);
 
 	/*
@@ -1549,7 +1549,7 @@ static int intel_runtime_resume(struct device *device)
 	 * power well, so hpd is reinitialized from there. For
 	 * everyone else do it here.
 	 */
-	if (!IS_VALLEYVIEW(dev_priv))
+	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 		intel_hpd_init(dev_priv);
 
 	intel_enable_gt_powersave(dev);
@@ -1574,7 +1574,7 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv)
 		ret = bxt_suspend_complete(dev_priv);
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		ret = hsw_suspend_complete(dev_priv);
-	else if (IS_VALLEYVIEW(dev_priv))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		ret = vlv_suspend_complete(dev_priv);
 	else
 		ret = 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f1a8a53..3899f23 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -763,6 +763,7 @@ struct intel_csr {
 	func(is_crestline) sep \
 	func(is_ivybridge) sep \
 	func(is_valleyview) sep \
+	func(is_cherryview) sep \
 	func(is_haswell) sep \
 	func(is_skylake) sep \
 	func(is_broxton) sep \
@@ -2455,9 +2456,9 @@ struct drm_i915_cmd_table {
 				 INTEL_DEVID(dev) == 0x0152 || \
 				 INTEL_DEVID(dev) == 0x015a)
 #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
-#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
+#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
 #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
-#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
+#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
 #define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
 #define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
 #define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
@@ -2584,7 +2585,8 @@ struct drm_i915_cmd_table {
 				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
 				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
-				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
+				 IS_KABYLAKE(dev))
 #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
 #define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
 
@@ -2597,7 +2599,8 @@ struct drm_i915_cmd_table {
 				    INTEL_INFO(dev)->gen >= 8)
 
 #define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
-				 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
+				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
+				 !IS_BROXTON(dev))
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
@@ -2620,7 +2623,8 @@ struct drm_i915_cmd_table {
 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
 
-#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
+#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
+			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 
 /* DPF == dynamic parity feature */
 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
@@ -3511,7 +3515,7 @@ __raw_write(64, q)
 
 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
 {
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		return VLV_VGACNTRL;
 	else if (INTEL_INFO(dev)->gen >= 5)
 		return CPU_VGACNTRL;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index dfaf25b..b722a61 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4838,7 +4838,7 @@ int i915_gem_init(struct drm_device *dev)
 
 	mutex_lock(&dev->struct_mutex);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/* VLVA0 (potential hack), BIOS isn't actually waking us */
 		I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
 		if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
@@ -4963,7 +4963,7 @@ i915_gem_load(struct drm_device *dev)
 
 	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
 
-	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
+	if (INTEL_INFO(dev)->gen >= 7 && !(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
 		dev_priv->num_fence_regs = 32;
 	else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 		dev_priv->num_fence_regs = 16;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 43761c5..4b1161d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -190,7 +190,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
 	 * would make the object snooped which might have a
 	 * negative performance impact.
 	 */
-	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) {
+	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
 		/* Failure shouldn't ever happen this early */
 		if (WARN_ON(ret)) {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e88d692..23a0aad 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -581,7 +581,7 @@ i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 {
 	u32 enable_mask;
 
-	if (IS_VALLEYVIEW(dev_priv->dev))
+	if (IS_VALLEYVIEW(dev_priv->dev) || IS_CHERRYVIEW(dev_priv->dev))
 		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 							   status_mask);
 	else
@@ -595,7 +595,7 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 {
 	u32 enable_mask;
 
-	if (IS_VALLEYVIEW(dev_priv->dev))
+	if (IS_VALLEYVIEW(dev_priv->dev) || IS_CHERRYVIEW(dev_priv->dev))
 		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 							   status_mask);
 	else
@@ -1723,7 +1723,7 @@ static void i9xx_hpd_irq_handler(struct drm_device *dev)
 	 */
 	POSTING_READ(PORT_HOTPLUG_STAT);
 
-	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
+	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
 
 		if (hotplug_trigger) {
@@ -4412,7 +4412,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
 
 	/* Let's track the enabled rps events */
-	if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
+	if (IS_VALLEYVIEW(dev_priv))
 		/* WaGsvRC0ResidencyMethod:vlv */
 		dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
 	else
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 2d91821..371a770 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -49,7 +49,7 @@ static void i915_save_display(struct drm_device *dev)
 		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
 		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
 		dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
-	} else if (!IS_VALLEYVIEW(dev)) {
+	} else if (!(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) {
 		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
 		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
 		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
@@ -84,7 +84,7 @@ static void i915_restore_display(struct drm_device *dev)
 		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
 		I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
 		I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
-	} else if (!IS_VALLEYVIEW(dev)) {
+	} else if (!(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) {
 		I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
 		I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
 		I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index f929c61..86c3020 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -49,7 +49,7 @@ static u32 calc_residency(struct drm_device *dev,
 	intel_runtime_pm_get(dev_priv);
 
 	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		units = 1;
 		div = dev_priv->czclk_freq;
 
@@ -284,7 +284,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
 	intel_runtime_pm_get(dev_priv);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
-	if (IS_VALLEYVIEW(dev_priv->dev)) {
+	if (IS_VALLEYVIEW(dev_priv->dev) || IS_CHERRYVIEW(dev_priv->dev)) {
 		u32 freq;
 		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
@@ -598,7 +598,7 @@ void i915_setup_sysfs(struct drm_device *dev)
 		if (ret)
 			DRM_ERROR("RC6p residency sysfs setup failed\n");
 	}
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		ret = sysfs_merge_group(&dev->primary->kdev->kobj,
 					&media_rc6_attr_group);
 		if (ret)
@@ -619,7 +619,7 @@ void i915_setup_sysfs(struct drm_device *dev)
 	}
 
 	ret = 0;
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs);
 	else if (INTEL_INFO(dev)->gen >= 6)
 		ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs);
@@ -635,7 +635,7 @@ void i915_setup_sysfs(struct drm_device *dev)
 void i915_teardown_sysfs(struct drm_device *dev)
 {
 	sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr);
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs);
 	else
 		sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs);
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 9aa83e7..06fffae 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -375,7 +375,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder)
 	if (HAS_PCH_IBX(dev_priv->dev)) {
 		aud_config = IBX_AUD_CFG(pipe);
 		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
-	} else if (IS_VALLEYVIEW(dev_priv)) {
+	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		aud_config = VLV_AUD_CFG(pipe);
 		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 	} else {
@@ -435,7 +435,8 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
 		aud_config = IBX_AUD_CFG(pipe);
 		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
-	} else if (IS_VALLEYVIEW(connector->dev)) {
+	} else if (IS_VALLEYVIEW(connector->dev) ||
+		   IS_CHERRYVIEW(connector->dev)) {
 		hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 		aud_config = VLV_AUD_CFG(pipe);
 		aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
@@ -559,7 +560,7 @@ void intel_init_audio(struct drm_device *dev)
 	if (IS_G4X(dev)) {
 		dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 	} else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 070470f..e384d24 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -357,8 +357,8 @@ parse_general_features(struct drm_i915_private *dev_priv,
 	if (general) {
 		dev_priv->vbt.int_tv_support = general->int_tv_support;
 		/* int_crt_support can't be trusted on earlier platforms */
-		if (bdb->version >= 155 &&
-		    (HAS_DDI(dev_priv) || IS_VALLEYVIEW(dev_priv)))
+		if (bdb->version >= 155 && (HAS_DDI(dev_priv) ||
+		    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 			dev_priv->vbt.int_crt_support = general->int_crt_support;
 		dev_priv->vbt.lvds_use_ssc = general->enable_ssc;
 		dev_priv->vbt.lvds_ssc_freq =
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 12008af..962cccc 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -786,7 +786,7 @@ void intel_crt_init(struct drm_device *dev)
 
 	if (HAS_PCH_SPLIT(dev))
 		adpa_reg = PCH_ADPA;
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		adpa_reg = VLV_ADPA;
 	else
 		adpa_reg = ADPA;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b59a2d8..05458a6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -187,7 +187,7 @@ int intel_hrawclk(struct drm_device *dev)
 	uint32_t clkcfg;
 
 	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		return 200;
 
 	clkcfg = I915_READ(CLKCFG);
@@ -215,7 +215,7 @@ int intel_hrawclk(struct drm_device *dev)
 
 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 {
-	if (!IS_VALLEYVIEW(dev_priv))
+	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 		return;
 
 	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
@@ -716,11 +716,12 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
 	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 		INTELPllInvalid("m1 out of range\n");
 
-	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
+	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
+	    !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 		if (clock->m1 <= clock->m2)
 			INTELPllInvalid("m1 <= m2\n");
 
-	if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
+	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 		if (clock->p < limit->p.min || limit->p.max < clock->p)
 			INTELPllInvalid("p out of range\n");
 		if (clock->m < limit->m.min || limit->m.max < clock->m)
@@ -1305,7 +1306,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 		    I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
 			panel_pipe = PIPE_B;
 		/* XXX: else fix for eDP */
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/* presumably write lock depends on pipe, not port select */
 		pp_reg = VLV_PIPE_PP_CONTROL(pipe);
 		panel_pipe = pipe;
@@ -1423,7 +1424,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
 			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
 			     sprite, pipe_name(pipe));
 		}
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		for_each_sprite(dev_priv, pipe, sprite) {
 			u32 val = I915_READ(SPCNTR(pipe, sprite));
 			I915_STATE_WARN(val & SP_ENABLE,
@@ -2319,7 +2320,7 @@ static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
 	if (INTEL_INFO(dev_priv)->gen >= 9)
 		return 256 * 1024;
 	else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
-		 IS_VALLEYVIEW(dev_priv))
+		 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return 128 * 1024;
 	else if (INTEL_INFO(dev_priv)->gen >= 4)
 		return 4 * 1024;
@@ -5455,7 +5456,7 @@ static void intel_update_cdclk(struct drm_device *dev)
 	 * BSpec erroneously claims we should aim for 4MHz, but
 	 * in fact 1MHz is the correct frequency.
 	 */
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/*
 		 * Program the gmbus_freq based on the cdclk frequency.
 		 * BSpec erroneously claims we should aim for 4MHz, but
@@ -7180,7 +7181,7 @@ static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 
 	WARN_ON(!crtc_state->base.state);
 
-	if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
 		refclk = 100000;
 	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
 	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
@@ -7879,7 +7880,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
 		pipeconf |= PIPECONF_DOUBLE_WIDE;
 
 	/* only g4x and later have fancy bpc/dither controls */
-	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
+	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/* Bspec claims that we can't use dithering for 30bpp pipes. */
 		if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
 			pipeconf |= PIPECONF_DITHER_EN |
@@ -7919,7 +7920,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
 	} else
 		pipeconf |= PIPECONF_PROGRESSIVE;
 
-	if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
+	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+	     intel_crtc->config->limited_color_range)
 		pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
 
 	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
@@ -8166,7 +8168,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 	if (!(tmp & PIPECONF_ENABLE))
 		return false;
 
-	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
+	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		switch (tmp & PIPECONF_BPC_MASK) {
 		case PIPECONF_6BPC:
 			pipe_config->pipe_bpp = 18;
@@ -8182,7 +8184,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 		}
 	}
 
-	if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
+	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
 		pipe_config->limited_color_range = true;
 
 	if (INTEL_INFO(dev)->gen < 4)
@@ -8210,7 +8213,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 		pipe_config->pixel_multiplier = 1;
 	}
 	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
-	if (!IS_VALLEYVIEW(dev)) {
+	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 		/*
 		 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
 		 * on 830. Filter it out here so that we don't
@@ -11537,7 +11540,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
 		work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		ring = &dev_priv->ring[BCS];
 		if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
 			/* vlv: DISPLAY_FLIP fails to change tiling */
@@ -12016,7 +12019,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
 	struct drm_connector_state *connector_state;
 	int bpp, i;
 
-	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
+	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
 		bpp = 10*3;
 	else if (INTEL_INFO(dev)->gen >= 5)
 		bpp = 12*3;
@@ -12626,7 +12629,7 @@ intel_pipe_config_compare(struct drm_device *dev,
 	PIPE_CONF_CHECK_I(pixel_multiplier);
 	PIPE_CONF_CHECK_I(has_hdmi_sink);
 	if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
-	    IS_VALLEYVIEW(dev))
+	    IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		PIPE_CONF_CHECK_I(limited_color_range);
 	PIPE_CONF_CHECK_I(has_infoframe);
 
@@ -14378,7 +14381,7 @@ static void intel_setup_outputs(struct drm_device *dev)
 
 		if (I915_READ(PCH_DP_D) & DP_DETECTED)
 			intel_dp_init(dev, PCH_DP_D, PORT_D);
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/*
 		 * The DP_DETECTED bit is the latched state of the DDC
 		 * SDA pin at boot. However since eDP doesn't require DDC
@@ -14527,7 +14530,7 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
 		 *  pixels and 32K bytes."
 		 */
 		 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
-	} else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
+	} else if (gen >= 5 && !(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) {
 		return 32*1024;
 	} else if (gen >= 4) {
 		if (fb_modifier == I915_FORMAT_MOD_X_TILED)
@@ -14631,7 +14634,8 @@ static int intel_framebuffer_init(struct drm_device *dev,
 		}
 		break;
 	case DRM_FORMAT_ABGR8888:
-		if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
+		if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
+		    INTEL_INFO(dev)->gen < 9) {
 			DRM_DEBUG("unsupported pixel format: %s\n",
 				  drm_get_format_name(mode_cmd->pixel_format));
 			return -EINVAL;
@@ -14647,7 +14651,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
 		}
 		break;
 	case DRM_FORMAT_ABGR2101010:
-		if (!IS_VALLEYVIEW(dev)) {
+		if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 			DRM_DEBUG("unsupported pixel format: %s\n",
 				  drm_get_format_name(mode_cmd->pixel_format));
 			return -EINVAL;
@@ -14775,7 +14779,7 @@ static void intel_init_display(struct drm_device *dev)
 		dev_priv->display.crtc_disable = ironlake_crtc_disable;
 		dev_priv->display.update_primary_plane =
 			ironlake_update_primary_plane;
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			i9xx_get_initial_plane_config;
@@ -14808,7 +14812,7 @@ static void intel_init_display(struct drm_device *dev)
 	else if (IS_HASWELL(dev))
 		dev_priv->display.get_display_clock_speed =
 			haswell_get_display_clock_speed;
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		dev_priv->display.get_display_clock_speed =
 			valleyview_get_display_clock_speed;
 	else if (IS_GEN5(dev))
@@ -14866,7 +14870,7 @@ static void intel_init_display(struct drm_device *dev)
 			dev_priv->display.modeset_calc_cdclk =
 				broadwell_modeset_calc_cdclk;
 		}
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->display.modeset_commit_cdclk =
 			valleyview_modeset_commit_cdclk;
 		dev_priv->display.modeset_calc_cdclk =
@@ -15640,7 +15644,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
 		pll->on = false;
 	}
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_wm_get_hw_state(dev);
 	else if (IS_GEN9(dev))
 		skl_wm_get_hw_state(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f335c92..e36f741 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -517,7 +517,7 @@ void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 	struct drm_device *dev = dev_priv->dev;
 	struct intel_encoder *encoder;
 
-	if (WARN_ON(!IS_VALLEYVIEW(dev)))
+	if (WARN_ON(!(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))))
 		return;
 
 	/*
@@ -582,7 +582,7 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 
 	pps_lock(intel_dp);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 		i915_reg_t pp_ctrl_reg, pp_div_reg;
 		u32 pp_div;
@@ -610,7 +610,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
-	if (IS_VALLEYVIEW(dev) &&
+	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 	    intel_dp->pps_pipe == INVALID_PIPE)
 		return false;
 
@@ -624,7 +624,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
-	if (IS_VALLEYVIEW(dev) &&
+	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 	    intel_dp->pps_pipe == INVALID_PIPE)
 		return false;
 
@@ -1723,7 +1723,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
 		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
 	} else {
 		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
-		    crtc->config->limited_color_range)
+		    !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
 			intel_dp->DP |= DP_COLOR_RANGE_16_235;
 
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
@@ -2418,7 +2418,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 	pipe_config->base.adjusted_mode.flags |= flags;
 
 	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
-	    tmp & DP_COLOR_RANGE_16_235)
+	    !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
 		pipe_config->limited_color_range = true;
 
 	pipe_config->has_dp_encoder = true;
@@ -2694,7 +2694,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
 
 	pps_lock(intel_dp);
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_init_panel_power_sequencer(intel_dp);
 
 	/*
@@ -2728,7 +2728,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
 
 	pps_unlock(intel_dp);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		unsigned int lane_mask = 0x0;
 
 		if (IS_CHERRYVIEW(dev))
@@ -3218,7 +3218,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
 		if (dev_priv->edp_low_vswing && port == PORT_A)
 			return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
-	} else if (IS_VALLEYVIEW(dev))
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 	else if (IS_GEN7(dev) && port == PORT_A)
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
@@ -3259,7 +3259,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 		default:
 			return DP_TRAIN_PRE_EMPH_LEVEL_0;
 		}
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			return DP_TRAIN_PRE_EMPH_LEVEL_3;
@@ -4539,7 +4539,7 @@ bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
 		return cpt_digital_port_connected(dev_priv, port);
 	else if (IS_BROXTON(dev_priv))
 		return bxt_digital_port_connected(dev_priv, port);
-	else if (IS_VALLEYVIEW(dev_priv))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return vlv_digital_port_connected(dev_priv, port);
 	else
 		return g4x_digital_port_connected(dev_priv, port);
@@ -4933,7 +4933,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
 	 * Read out the current power sequencer assignment,
 	 * in case the BIOS did something with it.
 	 */
-	if (IS_VALLEYVIEW(encoder->dev))
+	if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
 		vlv_initial_power_sequencer_setup(intel_dp);
 
 	intel_edp_panel_vdd_sanitize(intel_dp);
@@ -5293,7 +5293,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 
 	/* Haswell doesn't have any port selection bits for the panel
 	 * power sequencer any more. */
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		port_sel = PANEL_PORT_SELECT_VLV(port);
 	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
 		if (port == PORT_A)
@@ -5405,12 +5405,12 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 
 		val = I915_READ(reg);
 		if (index > DRRS_HIGH_RR) {
-			if (IS_VALLEYVIEW(dev))
+			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
 			else
 				val |= PIPECONF_EDP_RR_MODE_SWITCH;
 		} else {
-			if (IS_VALLEYVIEW(dev))
+			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
 			else
 				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
@@ -5777,7 +5777,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	}
 	mutex_unlock(&dev->mode_config.mutex);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
 		register_reboot_notifier(&intel_dp->edp_notifier);
 
@@ -5825,7 +5825,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	/* intel_dp vfuncs */
 	if (INTEL_INFO(dev)->gen >= 9)
 		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
 	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
@@ -5860,8 +5860,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 		intel_encoder->type = INTEL_OUTPUT_EDP;
 
 	/* eDP only on port B and/or C on vlv/chv */
-	if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
-		    port != PORT_B && port != PORT_C))
+	if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+		    is_edp(intel_dp) && port != PORT_B && port != PORT_C))
 		return false;
 
 	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
@@ -5912,7 +5912,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	if (is_edp(intel_dp)) {
 		pps_lock(intel_dp);
 		intel_dp_init_panel_power_timestamps(intel_dp);
-		if (IS_VALLEYVIEW(dev))
+		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 			vlv_initial_power_sequencer_setup(intel_dp);
 		else
 			intel_dp_init_panel_power_sequencer(dev, intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 230957f..cada737 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -369,7 +369,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_dsi_device_ready(encoder);
 	else if (IS_BROXTON(dev))
 		bxt_dsi_device_ready(encoder);
@@ -487,7 +487,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 
 	msleep(intel_dsi->panel_on_delay);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/*
 		 * Disable DPOunit clock gating, can stall pipe
 		 * and we need DPLL REFA always enabled
@@ -684,8 +684,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 		 * Enable bit does not get set. To check whether DSI Port C
 		 * was enabled in BIOS, check the Pipe B enable bit
 		 */
-		if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
-		    (port == PORT_C))
+		if (IS_VALLEYVIEW(dev) && (port == PORT_C))
 			dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
 							PIPECONF_ENABLE;
 
@@ -716,7 +715,8 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
 
 	if (IS_BROXTON(encoder->base.dev))
 		pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
-	else if (IS_VALLEYVIEW(encoder->base.dev))
+	else if (IS_VALLEYVIEW(encoder->base.dev) ||
+		 IS_CHERRYVIEW(encoder->base.dev))
 		pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
 
 	if (!pclk)
@@ -869,7 +869,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-		if (IS_VALLEYVIEW(dev)) {
+		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 			/*
 			 * escape clock divider, 20MHz, shared for A and C.
 			 * device ready must be off when doing this! txclkesc?
@@ -1129,7 +1129,7 @@ void intel_dsi_init(struct drm_device *dev)
 	if (!dev_priv->vbt.has_mipi)
 		return;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
 	} else {
 		DRM_ERROR("Unsupported Mipi device to reg base");
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index cb3cf39..fbd2b51 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -561,7 +561,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_enable_dsi_pll(encoder);
 	else if (IS_BROXTON(dev))
 		bxt_enable_dsi_pll(encoder);
@@ -571,7 +571,7 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_disable_dsi_pll(encoder);
 	else if (IS_BROXTON(dev))
 		bxt_disable_dsi_pll(encoder);
@@ -599,6 +599,6 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
 
 	if (IS_BROXTON(dev))
 		bxt_dsi_reset_clocks(encoder, port);
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_dsi_reset_clocks(encoder, port);
 }
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index c3978ba..be7fab9 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -638,7 +638,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
 
 	if (HAS_DDI(dev_priv))
 		reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
-	else if (IS_VALLEYVIEW(dev_priv))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 	else if (HAS_PCH_SPLIT(dev_priv->dev))
 		reg = TVIDEO_DIP_GCP(crtc->pipe);
@@ -2100,7 +2100,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 		BUG();
 	}
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		intel_hdmi->write_infoframe = vlv_write_infoframe;
 		intel_hdmi->set_infoframes = vlv_set_infoframes;
 		intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
index b177857..a294a3c 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -407,7 +407,7 @@ void intel_hpd_irq_handler(struct drm_device *dev,
 			 * hotplug bits itself. So only WARN about unexpected
 			 * interrupts on saner platforms.
 			 */
-			WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
+			WARN_ONCE(!HAS_GMCH_DISPLAY(dev),
 				  "Received HPD interrupt on pin %d although disabled\n", i);
 			continue;
 		}
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index e26e22a..25254b5 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -636,7 +636,7 @@ int intel_setup_gmbus(struct drm_device *dev)
 	if (HAS_PCH_NOP(dev))
 		return 0;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
 	else if (!HAS_GMCH_DISPLAY(dev_priv))
 		dev_priv->gpio_mmio_base =
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index ae808b6..72183a0 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1784,7 +1784,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
 		panel->backlight.set = pch_set_backlight;
 		panel->backlight.get = pch_get_backlight;
 		panel->backlight.hz_to_pwm = pch_hz_to_pwm;
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		if (dev_priv->vbt.has_mipi) {
 			panel->backlight.setup = pwm_setup_backlight;
 			panel->backlight.enable = pwm_enable_backlight;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ee05ce8..fe56181 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -291,7 +291,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 	struct drm_device *dev = dev_priv->dev;
 	u32 val;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 		POSTING_READ(FW_BLC_SELF_VLV);
 		dev_priv->wm.vlv.cxsr = enable;
@@ -4405,7 +4405,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
-		if (IS_VALLEYVIEW(dev))
+		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 			vlv_set_rps_idle(dev_priv);
 		else
 			gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
@@ -4458,7 +4458,7 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
 
 void intel_set_rps(struct drm_device *dev, u8 val)
 {
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		valleyview_set_rps(dev, val);
 	else
 		gen6_set_rps(dev, val);
@@ -4502,7 +4502,7 @@ static void valleyview_disable_rps(struct drm_device *dev)
 
 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
 {
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
 			mode = GEN6_RC_CTL_RC6_ENABLE;
 		else
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b6609e6..1778a7d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -332,8 +332,8 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 		return false;
 	}
 
-	if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||
-				    (dig_port->port != PORT_A))) {
+	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
+	    ((dev_priv->vbt.psr.full_link) || (dig_port->port != PORT_A))) {
 		DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n");
 		return false;
 	}
@@ -650,7 +650,7 @@ void intel_psr_single_frame_update(struct drm_device *dev,
 	 * Single frame update is already supported on BDW+ but it requires
 	 * many W/A and it isn't really needed.
 	 */
-	if (!IS_VALLEYVIEW(dev))
+	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
 		return;
 
 	mutex_lock(&dev_priv->psr.lock);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 2b96f33..f8bf622 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -951,7 +951,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 	if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 		return -EINVAL;
 
-	if (IS_VALLEYVIEW(dev) &&
+	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 	    set->flags & I915_SET_COLORKEY_DESTINATION)
 		return -EINVAL;
 
@@ -1086,7 +1086,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
 			intel_plane->max_downscale = 1;
 		}
 
-		if (IS_VALLEYVIEW(dev)) {
+		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 			intel_plane->update_plane = vlv_update_plane;
 			intel_plane->disable_plane = vlv_disable_plane;
 
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index c2358ba..fcf04fe 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1115,7 +1115,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
 		d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
 	}
 
-	if (IS_VALLEYVIEW(dev_priv))
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		d->reg_post = FORCEWAKE_ACK_VLV;
 	else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
 		d->reg_post = ECOBUS;
@@ -1148,7 +1148,7 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
 			       FORCEWAKE_ACK_BLITTER_GEN9);
 		fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
 			       FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
 		if (!IS_CHERRYVIEW(dev))
 			dev_priv->uncore.funcs.force_wake_put =
-- 
2.6.3

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/5] drm/i915: Use HAS_PCH_SPLIT to determine correct devices

[Wayne Boyer]

Do some further clean up based on the initial review of
drm/i915: Separate cherryview from valleyview.

In this case check for '(GEN7 || GEN8) && HAS_PCH_SPLIT' since we're
reading FUSE_STRAP and SFUSE_STRAP which live in the PCH.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index b156b08e..d816aa2 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -791,7 +791,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 		info->num_pipes = 0;
 	} else if (info->num_pipes > 0 &&
 		   (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
-		   !(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) {
+		   HAS_PCH_SPLIT(dev)) {
 		u32 fuse_strap = I915_READ(FUSE_STRAP);
 		u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 
-- 
2.6.3

_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 3/5] drm/i915: Remove VLV A0 hack

[Wayne Boyer]

Do some further clean up based on the initial review of
drm/i915: Separate cherryview from valleyview.

In this case remove a hack for VLV A0.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b722a61..4556500 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4838,14 +4838,6 @@ int i915_gem_init(struct drm_device *dev)
 
 	mutex_lock(&dev->struct_mutex);
 
-	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
-		/* VLVA0 (potential hack), BIOS isn't actually waking us */
-		I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
-		if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
-			      VLV_GTLC_ALLOWWAKEACK), 10))
-			DRM_DEBUG_DRIVER("allow wake ack timed out\n");
-	}
-
 	if (!i915.enable_execlists) {
 		dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
 		dev_priv->gt.init_rings = i915_gem_init_rings;
-- 
2.6.3

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[PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

[Wayne Boyer]

Do some further clean up based on the initial review of
drm/i915: Separate cherryview from valleyview.

In this case, in i915_gem_alloc_context_obj() only call
i915_gem_object_set_cache_level() for Ivy Bridge devices
since later platforms don't have L3 control bits in the PTE.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 4b1161d..e4de433 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -185,12 +185,10 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
 	/*
 	 * Try to make the context utilize L3 as well as LLC.
 	 *
-	 * On VLV we don't have L3 controls in the PTEs so we
-	 * shouldn't touch the cache level, especially as that
-	 * would make the object snooped which might have a
-	 * negative performance impact.
+	 * This is only applicable for Ivy Bridge devices since
+	 * later platforms don't have L3 control bits in the PTE.
 	 */
-	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
+	if (IS_IVYBRIDGE(dev)) {
 		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
 		/* Failure shouldn't ever happen this early */
 		if (WARN_ON(ret)) {
-- 
2.6.3

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[PATCH 5/5] drm/i915: Remove BUG_ON call in vlv_enable_pll

[Wayne Boyer]

Do some further clean up based on the initial review of
drm/i915: Separate cherryview from valleyview.

In this case remove the BUG_ON call in vlv_enable_pll().

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 05458a6..2b7d27d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1607,9 +1607,6 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
 
 	assert_pipe_disabled(dev_priv, crtc->pipe);
 
-	/* No really, not for ILK+ */
-	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
-
 	/* PLL is protected by panel, make sure we can write it */
 	if (IS_MOBILE(dev_priv->dev))
 		assert_panel_unlocked(dev_priv, crtc->pipe);
-- 
2.6.3

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Re: [PATCH 2/5] drm/i915: Use HAS_PCH_SPLIT to determine correct devices

[Ville Syrjälä]

On Mon, Dec 07, 2015 at 10:51:07AM -0800, Wayne Boyer wrote:
> Do some further clean up based on the initial review of
> drm/i915: Separate cherryview from valleyview.
> 
> In this case check for '(GEN7 || GEN8) && HAS_PCH_SPLIT' since we're
> reading FUSE_STRAP and SFUSE_STRAP which live in the PCH.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_dma.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index b156b08e..d816aa2 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -791,7 +791,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>  		info->num_pipes = 0;
>  	} else if (info->num_pipes > 0 &&
>  		   (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
> -		   !(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) {
> +		   HAS_PCH_SPLIT(dev)) {
>  		u32 fuse_strap = I915_READ(FUSE_STRAP);
>  		u32 sfuse_strap = I915_READ(SFUSE_STRAP);
>  
> -- 
> 2.6.3

-- 
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Re: [PATCH 3/5] drm/i915: Remove VLV A0 hack

[Ville Syrjälä]

On Mon, Dec 07, 2015 at 10:51:08AM -0800, Wayne Boyer wrote:
> Do some further clean up based on the initial review of
> drm/i915: Separate cherryview from valleyview.
> 
> In this case remove a hack for VLV A0.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 8 --------
>  1 file changed, 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index b722a61..4556500 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4838,14 +4838,6 @@ int i915_gem_init(struct drm_device *dev)
>  
>  	mutex_lock(&dev->struct_mutex);
>  
> -	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> -		/* VLVA0 (potential hack), BIOS isn't actually waking us */
> -		I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
> -		if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
> -			      VLV_GTLC_ALLOWWAKEACK), 10))
> -			DRM_DEBUG_DRIVER("allow wake ack timed out\n");
> -	}
> -

Yeah, this old thing shouldn't be needed.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  	if (!i915.enable_execlists) {
>  		dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
>  		dev_priv->gt.init_rings = i915_gem_init_rings;
> -- 
> 2.6.3

-- 
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Re: [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

[Ville Syrjälä]

On Mon, Dec 07, 2015 at 10:51:09AM -0800, Wayne Boyer wrote:
> Do some further clean up based on the initial review of
> drm/i915: Separate cherryview from valleyview.
> 
> In this case, in i915_gem_alloc_context_obj() only call
> i915_gem_object_set_cache_level() for Ivy Bridge devices
> since later platforms don't have L3 control bits in the PTE.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_context.c | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 4b1161d..e4de433 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -185,12 +185,10 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
>  	/*
>  	 * Try to make the context utilize L3 as well as LLC.
>  	 *
> -	 * On VLV we don't have L3 controls in the PTEs so we
> -	 * shouldn't touch the cache level, especially as that
> -	 * would make the object snooped which might have a
> -	 * negative performance impact.
> +	 * This is only applicable for Ivy Bridge devices since
> +	 * later platforms don't have L3 control bits in the PTE.
>  	 */
> -	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
> +	if (IS_IVYBRIDGE(dev)) {

This would actually change the snoop setting on BXT, but that
should be fine since BXT still has the GTT -> PAT 0 thing which
means we get snooping anyway IIRC.

Imre, we discussed this stuff at some point, and I hope I'm not
forgetting something crucial here that would break BXT. Probably best
if you sanity check my thinking here...

We should probably mention this PAT 0 business in a comment somewhere
here since it's a very easy thing to miss.

>  		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
>  		/* Failure shouldn't ever happen this early */
>  		if (WARN_ON(ret)) {
> -- 
> 2.6.3

-- 
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Re: [PATCH 5/5] drm/i915: Remove BUG_ON call in vlv_enable_pll

[Ville Syrjälä]

On Mon, Dec 07, 2015 at 10:51:10AM -0800, Wayne Boyer wrote:
> Do some further clean up based on the initial review of
> drm/i915: Separate cherryview from valleyview.
> 
> In this case remove the BUG_ON call in vlv_enable_pll().

Yeah, BUG_ONs aren't very nice.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 05458a6..2b7d27d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1607,9 +1607,6 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
>  
>  	assert_pipe_disabled(dev_priv, crtc->pipe);
>  
> -	/* No really, not for ILK+ */
> -	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
> -
>  	/* PLL is protected by panel, make sure we can write it */
>  	if (IS_MOBILE(dev_priv->dev))
>  		assert_panel_unlocked(dev_priv, crtc->pipe);
> -- 
> 2.6.3

-- 
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Intel OTC
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Re: [PATCH 5/5] drm/i915: Remove BUG_ON call in vlv_enable_pll

[Ville Syrjälä]

On Mon, Dec 07, 2015 at 09:29:32PM +0200, Ville Syrjälä wrote:
> On Mon, Dec 07, 2015 at 10:51:10AM -0800, Wayne Boyer wrote:
> > Do some further clean up based on the initial review of
> > drm/i915: Separate cherryview from valleyview.
> > 
> > In this case remove the BUG_ON call in vlv_enable_pll().
> 
> Yeah, BUG_ONs aren't very nice.

Hmm. You didn't catch the other one in chv_enable_pll()?

> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 3 ---
> >  1 file changed, 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 05458a6..2b7d27d 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1607,9 +1607,6 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
> >  
> >  	assert_pipe_disabled(dev_priv, crtc->pipe);
> >  
> > -	/* No really, not for ILK+ */
> > -	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
> > -
> >  	/* PLL is protected by panel, make sure we can write it */
> >  	if (IS_MOBILE(dev_priv->dev))
> >  		assert_panel_unlocked(dev_priv, crtc->pipe);
> > -- 
> > 2.6.3
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
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Re: [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

[Imre Deak]

On Mon, 2015-12-07 at 21:28 +0200, Ville Syrjälä wrote:
> On Mon, Dec 07, 2015 at 10:51:09AM -0800, Wayne Boyer wrote:
> > Do some further clean up based on the initial review of
> > drm/i915: Separate cherryview from valleyview.
> > 
> > In this case, in i915_gem_alloc_context_obj() only call
> > i915_gem_object_set_cache_level() for Ivy Bridge devices
> > since later platforms don't have L3 control bits in the PTE.
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_gem_context.c | 8 +++-----
> >  1 file changed, 3 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> > b/drivers/gpu/drm/i915/i915_gem_context.c
> > index 4b1161d..e4de433 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -185,12 +185,10 @@ i915_gem_alloc_context_obj(struct drm_device
> > *dev, size_t size)
> >  	/*
> >  	 * Try to make the context utilize L3 as well as LLC.
> >  	 *
> > -	 * On VLV we don't have L3 controls in the PTEs so we
> > -	 * shouldn't touch the cache level, especially as that
> > -	 * would make the object snooped which might have a
> > -	 * negative performance impact.
> > +	 * This is only applicable for Ivy Bridge devices since
> > +	 * later platforms don't have L3 control bits in the PTE.
> >  	 */
> > -	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) &&
> > !IS_CHERRYVIEW(dev)) {
> > +	if (IS_IVYBRIDGE(dev)) {
> 
> This would actually change the snoop setting on BXT, but that
> should be fine since BXT still has the GTT -> PAT 0 thing which
> means we get snooping anyway IIRC.
> 
> Imre, we discussed this stuff at some point, and I hope I'm not
> forgetting something crucial here that would break BXT. Probably best
> if you sanity check my thinking here...

Yes, AFAIU it doesn't matter what level we set, because of the PAT
mapping constraint you describe above. Atm we also don't use this
function on BXT, b/c of the different codepaths for LRC vs. ringbuffer
mode. But that could/should be unified at one point, so yea it's better
to keep things working for BXT too here. In the corresponding
intel_lr_context_deferred_alloc() we don't set the cache level, which
also agrees with the above, so I think this change is fine.

> We should probably mention this PAT 0 business in a comment somewhere
> here since it's a very easy thing to miss.

Yep, a comment about this would be in order.

> 
> >  		ret = i915_gem_object_set_cache_level(obj,
> > I915_CACHE_L3_LLC);
> >  		/* Failure shouldn't ever happen this early */
> >  		if (WARN_ON(ret)) {
> > -- 
> > 2.6.3
> 
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Re: [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

[Boyer, Wayne]

On 12/7/15, 11:56 AM, "Deak, Imre" <imre.deak@intel.com> wrote:


>On Mon, 2015-12-07 at 21:28 +0200, Ville Syrjälä wrote:
>> On Mon, Dec 07, 2015 at 10:51:09AM -0800, Wayne Boyer wrote:
>> > Do some further clean up based on the initial review of
>> > drm/i915: Separate cherryview from valleyview.
>> > 
>> > In this case, in i915_gem_alloc_context_obj() only call
>> > i915_gem_object_set_cache_level() for Ivy Bridge devices
>> > since later platforms don't have L3 control bits in the PTE.
>> > 
>> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> > Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/i915_gem_context.c | 8 +++-----
>> >  1 file changed, 3 insertions(+), 5 deletions(-)
>> > 
>> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
>> > b/drivers/gpu/drm/i915/i915_gem_context.c
>> > index 4b1161d..e4de433 100644
>> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
>> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
>> > @@ -185,12 +185,10 @@ i915_gem_alloc_context_obj(struct drm_device
>> > *dev, size_t size)
>> >  	/*
>> >  	 * Try to make the context utilize L3 as well as LLC.
>> >  	 *
>> > -	 * On VLV we don't have L3 controls in the PTEs so we
>> > -	 * shouldn't touch the cache level, especially as that
>> > -	 * would make the object snooped which might have a
>> > -	 * negative performance impact.
>> > +	 * This is only applicable for Ivy Bridge devices since
>> > +	 * later platforms don't have L3 control bits in the PTE.
>> >  	 */
>> > -	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) &&
>> > !IS_CHERRYVIEW(dev)) {
>> > +	if (IS_IVYBRIDGE(dev)) {
>> 
>> This would actually change the snoop setting on BXT, but that
>> should be fine since BXT still has the GTT -> PAT 0 thing which
>> means we get snooping anyway IIRC.
>> 
>> Imre, we discussed this stuff at some point, and I hope I'm not
>> forgetting something crucial here that would break BXT. Probably best
>> if you sanity check my thinking here...
>
>Yes, AFAIU it doesn't matter what level we set, because of the PAT
>mapping constraint you describe above. Atm we also don't use this
>function on BXT, b/c of the different codepaths for LRC vs. ringbuffer
>mode. But that could/should be unified at one point, so yea it's better
>to keep things working for BXT too here. In the corresponding
>intel_lr_context_deferred_alloc() we don't set the cache level, which
>also agrees with the above, so I think this change is fine.
>
>> We should probably mention this PAT 0 business in a comment somewhere
>> here since it's a very easy thing to miss.
>
>Yep, a comment about this would be in order.

Ville, Imre, how does this look for an updated comment?

/*
 * Try to make the context utilize L3 as well as LLC.
 *
 * On VLV we don't have L3 controls in the PTE so we
 * shouldn't touch the cache level, especially as that
 * would make the object snooped which might have a
 * negative performance impact.
 *
 * On CHV and BXT we set PPAT 0 in chv_setup_private_ppat()
 * which means we get snooping anyway.
 *
 * This is only applicable for Ivy Bridge devices since
 * later platforms don't have L3 control bits in the PTE.
 */

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[PATCH 5/5] drm/i915: Remove BUG_ON call in vlv_enable_pll

[Wayne Boyer]

Do some further clean up based on the initial review of
drm/i915: Separate cherryview from valleyview.

In this case remove the BUG_ON call in vlv_enable_pll().

v2: Also remove the BUG_ON call in chv_enable_pll(). (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 05458a6..3c86649 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1607,9 +1607,6 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
 
 	assert_pipe_disabled(dev_priv, crtc->pipe);
 
-	/* No really, not for ILK+ */
-	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
-
 	/* PLL is protected by panel, make sure we can write it */
 	if (IS_MOBILE(dev_priv->dev))
 		assert_panel_unlocked(dev_priv, crtc->pipe);
@@ -1647,8 +1644,6 @@ static void chv_enable_pll(struct intel_crtc *crtc,
 
 	assert_pipe_disabled(dev_priv, crtc->pipe);
 
-	BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
-
 	mutex_lock(&dev_priv->sb_lock);
 
 	/* Enable back the 10bit clock to display controller */
-- 
2.6.3

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Re: [PATCH 1/5] drm/i915: Separate cherryview from valleyview

[Jani Nikula]

On Mon, 07 Dec 2015, Wayne Boyer <wayne.boyer@intel.com> wrote:
> The cherryview device shares many characteristics with the valleyview
> device.  When support was added to the driver for cherryview, the
> corresponding device info structure included .is_valleyview = 1.
> This is not correct and leads to some confusion.
>
> This patch changes .is_valleyview to .is_cherryview in the cherryview
> device info structure and simplifies the IS_CHERRYVIEW macro.
> Then where appropriate, instances of IS_VALLEYVIEW are replaced with
> IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent.
>
> v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro.
>     Also add followup patches to fix issues discovered during the first
>     review. (Ville)
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>

I eyeballed through the changes here, comments inline. I didn't check
which places you missed, if any.

BR,
Jani.


> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index a8721fc..a9ae642 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1142,8 +1142,34 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  			   MEMSTAT_VID_SHIFT);
>  		seq_printf(m, "Current P-state: %d\n",
>  			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
> -	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
> -		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> +		u32 freq_sts;
> +
> +		mutex_lock(&dev_priv->rps.hw_lock);
> +		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
> +		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
> +
> +		seq_printf(m, "actual GPU freq: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
> +
> +		seq_printf(m, "current GPU freq: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
> +
> +		seq_printf(m, "max GPU freq: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
> +
> +		seq_printf(m, "min GPU freq: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
> +
> +		seq_printf(m, "idle GPU freq: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
> +
> +		seq_printf(m,
> +			   "efficient (RPe) frequency: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +	} else if (IS_GEN6(dev) || IS_BROADWELL(dev) || IS_GEN9(dev)) {

Where did IS_GEN7() go?

>  		u32 rp_state_limits;
>  		u32 gt_perf_status;
>  		u32 rp_state_cap;
> @@ -1284,33 +1310,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		seq_printf(m,
>  			   "efficient (RPe) frequency: %d MHz\n",
>  			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
> -	} else if (IS_VALLEYVIEW(dev)) {
> -		u32 freq_sts;
> -
> -		mutex_lock(&dev_priv->rps.hw_lock);
> -		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> -		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
> -		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
> -
> -		seq_printf(m, "actual GPU freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
> -
> -		seq_printf(m, "current GPU freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
> -
> -		seq_printf(m, "max GPU freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
> -
> -		seq_printf(m, "min GPU freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
> -
> -		seq_printf(m, "idle GPU freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
> -
> -		seq_printf(m,
> -			   "efficient (RPe) frequency: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
> -		mutex_unlock(&dev_priv->rps.hw_lock);
>  	} else {
>  		seq_puts(m, "no P-state info available\n");
>  	}

> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index a81c766..b156b08e 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c

> @@ -836,7 +836,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>  
>  static void intel_init_dpio(struct drm_i915_private *dev_priv)
>  {
> -	if (!IS_VALLEYVIEW(dev_priv))
> +	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))

Hmm, I think I'd probably end up writing this as:

	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))

Matter of style and phase of the moon I guess. But it's nicer
particularly when it's combined with other !platforms.

>  		return;
>  
>  	/*


> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 43761c5..4b1161d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -190,7 +190,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
>  	 * would make the object snooped which might have a
>  	 * negative performance impact.
>  	 */
> -	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) {
> +	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {

Ahah, you seem to be ambivalent about !(vlv || chv) vs. !vlv && !chv
yourself. ;)

Also makes me think you didn't use sed or coccinelle for the change.

>  		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
>  		/* Failure shouldn't ever happen this early */
>  		if (WARN_ON(ret)) {


> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 070470f..e384d24 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -357,8 +357,8 @@ parse_general_features(struct drm_i915_private *dev_priv,
>  	if (general) {
>  		dev_priv->vbt.int_tv_support = general->int_tv_support;
>  		/* int_crt_support can't be trusted on earlier platforms */
> -		if (bdb->version >= 155 &&
> -		    (HAS_DDI(dev_priv) || IS_VALLEYVIEW(dev_priv)))
> +		if (bdb->version >= 155 && (HAS_DDI(dev_priv) ||
> +		    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))

Hmm, is that the same as gen >= 7 && !ivb?

>  			dev_priv->vbt.int_crt_support = general->int_crt_support;
>  		dev_priv->vbt.lvds_use_ssc = general->enable_ssc;
>  		dev_priv->vbt.lvds_ssc_freq =


-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

[Ville Syrjälä]

On Mon, Dec 07, 2015 at 10:26:15PM +0000, Boyer, Wayne wrote:
> On 12/7/15, 11:56 AM, "Deak, Imre" <imre.deak@intel.com> wrote:
> 
> 
> >On Mon, 2015-12-07 at 21:28 +0200, Ville Syrjälä wrote:
> >> On Mon, Dec 07, 2015 at 10:51:09AM -0800, Wayne Boyer wrote:
> >> > Do some further clean up based on the initial review of
> >> > drm/i915: Separate cherryview from valleyview.
> >> > 
> >> > In this case, in i915_gem_alloc_context_obj() only call
> >> > i915_gem_object_set_cache_level() for Ivy Bridge devices
> >> > since later platforms don't have L3 control bits in the PTE.
> >> > 
> >> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >> > Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/i915_gem_context.c | 8 +++-----
> >> >  1 file changed, 3 insertions(+), 5 deletions(-)
> >> > 
> >> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> >> > b/drivers/gpu/drm/i915/i915_gem_context.c
> >> > index 4b1161d..e4de433 100644
> >> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> >> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> >> > @@ -185,12 +185,10 @@ i915_gem_alloc_context_obj(struct drm_device
> >> > *dev, size_t size)
> >> >  	/*
> >> >  	 * Try to make the context utilize L3 as well as LLC.
> >> >  	 *
> >> > -	 * On VLV we don't have L3 controls in the PTEs so we
> >> > -	 * shouldn't touch the cache level, especially as that
> >> > -	 * would make the object snooped which might have a
> >> > -	 * negative performance impact.
> >> > +	 * This is only applicable for Ivy Bridge devices since
> >> > +	 * later platforms don't have L3 control bits in the PTE.
> >> >  	 */
> >> > -	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) &&
> >> > !IS_CHERRYVIEW(dev)) {
> >> > +	if (IS_IVYBRIDGE(dev)) {
> >> 
> >> This would actually change the snoop setting on BXT, but that
> >> should be fine since BXT still has the GTT -> PAT 0 thing which
> >> means we get snooping anyway IIRC.
> >> 
> >> Imre, we discussed this stuff at some point, and I hope I'm not
> >> forgetting something crucial here that would break BXT. Probably best
> >> if you sanity check my thinking here...
> >
> >Yes, AFAIU it doesn't matter what level we set, because of the PAT
> >mapping constraint you describe above. Atm we also don't use this
> >function on BXT, b/c of the different codepaths for LRC vs. ringbuffer
> >mode. But that could/should be unified at one point, so yea it's better
> >to keep things working for BXT too here. In the corresponding
> >intel_lr_context_deferred_alloc() we don't set the cache level, which
> >also agrees with the above, so I think this change is fine.
> >
> >> We should probably mention this PAT 0 business in a comment somewhere
> >> here since it's a very easy thing to miss.
> >
> >Yep, a comment about this would be in order.
> 
> Ville, Imre, how does this look for an updated comment?
> 
> /*
>  * Try to make the context utilize L3 as well as LLC.
>  *
>  * On VLV we don't have L3 controls in the PTE so we
>  * shouldn't touch the cache level, especially as that
>  * would make the object snooped which might have a
>  * negative performance impact.
>  *
>  * On CHV and BXT we set PPAT 0 in chv_setup_private_ppat()
>  * which means we get snooping anyway.

Maybe something like this:
"Snooping is required on non-llc platforms in execlist
mode, but since all GGTT accesses use PAT entry 0 we
get snooping anyway regardless of cache_level.

Otherwise lgtm.

>  *
>  * This is only applicable for Ivy Bridge devices since
>  * later platforms don't have L3 control bits in the PTE.
>  */

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 5/5] drm/i915: Remove BUG_ON call in vlv_enable_pll

[Ville Syrjälä]

On Mon, Dec 07, 2015 at 03:02:42PM -0800, Wayne Boyer wrote:
> Do some further clean up based on the initial review of
> drm/i915: Separate cherryview from valleyview.
> 
> In this case remove the BUG_ON call in vlv_enable_pll().
> 
> v2: Also remove the BUG_ON call in chv_enable_pll(). (Ville)
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 05458a6..3c86649 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1607,9 +1607,6 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
>  
>  	assert_pipe_disabled(dev_priv, crtc->pipe);
>  
> -	/* No really, not for ILK+ */
> -	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
> -
>  	/* PLL is protected by panel, make sure we can write it */
>  	if (IS_MOBILE(dev_priv->dev))
>  		assert_panel_unlocked(dev_priv, crtc->pipe);
> @@ -1647,8 +1644,6 @@ static void chv_enable_pll(struct intel_crtc *crtc,
>  
>  	assert_pipe_disabled(dev_priv, crtc->pipe);
>  
> -	BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
> -
>  	mutex_lock(&dev_priv->sb_lock);
>  
>  	/* Enable back the 10bit clock to display controller */
> -- 
> 2.6.3

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 1/5] drm/i915: Separate cherryview from valleyview

[Ville Syrjälä]

On Tue, Dec 08, 2015 at 01:44:10PM +0200, Jani Nikula wrote:
> On Mon, 07 Dec 2015, Wayne Boyer <wayne.boyer@intel.com> wrote:
> > The cherryview device shares many characteristics with the valleyview
> > device.  When support was added to the driver for cherryview, the
> > corresponding device info structure included .is_valleyview = 1.
> > This is not correct and leads to some confusion.
> >
> > This patch changes .is_valleyview to .is_cherryview in the cherryview
> > device info structure and simplifies the IS_CHERRYVIEW macro.
> > Then where appropriate, instances of IS_VALLEYVIEW are replaced with
> > IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent.
> >
> > v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro.
> >     Also add followup patches to fix issues discovered during the first
> >     review. (Ville)
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
> 
> I eyeballed through the changes here, comments inline. I didn't check
> which places you missed, if any.
> 
> BR,
> Jani.
> 
> 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index a8721fc..a9ae642 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -1142,8 +1142,34 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> >  			   MEMSTAT_VID_SHIFT);
> >  		seq_printf(m, "Current P-state: %d\n",
> >  			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
> > -	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
> > -		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
> > +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> > +		u32 freq_sts;
> > +
> > +		mutex_lock(&dev_priv->rps.hw_lock);
> > +		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> > +		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
> > +		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
> > +
> > +		seq_printf(m, "actual GPU freq: %d MHz\n",
> > +			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
> > +
> > +		seq_printf(m, "current GPU freq: %d MHz\n",
> > +			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
> > +
> > +		seq_printf(m, "max GPU freq: %d MHz\n",
> > +			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
> > +
> > +		seq_printf(m, "min GPU freq: %d MHz\n",
> > +			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
> > +
> > +		seq_printf(m, "idle GPU freq: %d MHz\n",
> > +			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
> > +
> > +		seq_printf(m,
> > +			   "efficient (RPe) frequency: %d MHz\n",
> > +			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
> > +		mutex_unlock(&dev_priv->rps.hw_lock);
> > +	} else if (IS_GEN6(dev) || IS_BROADWELL(dev) || IS_GEN9(dev)) {
> 
> Where did IS_GEN7() go?

With VLV/CHV out of the way This can be 'gen >= 6 && gen < 10'. Maybe we
could even drop the upper bound and just assume it'll keep working?

> 
> >  		u32 rp_state_limits;
> >  		u32 gt_perf_status;
> >  		u32 rp_state_cap;
> > @@ -1284,33 +1310,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> >  		seq_printf(m,
> >  			   "efficient (RPe) frequency: %d MHz\n",
> >  			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
> > -	} else if (IS_VALLEYVIEW(dev)) {
> > -		u32 freq_sts;
> > -
> > -		mutex_lock(&dev_priv->rps.hw_lock);
> > -		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> > -		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
> > -		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
> > -
> > -		seq_printf(m, "actual GPU freq: %d MHz\n",
> > -			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
> > -
> > -		seq_printf(m, "current GPU freq: %d MHz\n",
> > -			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
> > -
> > -		seq_printf(m, "max GPU freq: %d MHz\n",
> > -			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
> > -
> > -		seq_printf(m, "min GPU freq: %d MHz\n",
> > -			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
> > -
> > -		seq_printf(m, "idle GPU freq: %d MHz\n",
> > -			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
> > -
> > -		seq_printf(m,
> > -			   "efficient (RPe) frequency: %d MHz\n",
> > -			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
> > -		mutex_unlock(&dev_priv->rps.hw_lock);
> >  	} else {
> >  		seq_puts(m, "no P-state info available\n");
> >  	}
> 
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> > index a81c766..b156b08e 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> 
> > @@ -836,7 +836,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> >  
> >  static void intel_init_dpio(struct drm_i915_private *dev_priv)
> >  {
> > -	if (!IS_VALLEYVIEW(dev_priv))
> > +	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
> 
> Hmm, I think I'd probably end up writing this as:
> 
> 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
> 
> Matter of style and phase of the moon I guess. But it's nicer
> particularly when it's combined with other !platforms.
> 
> >  		return;
> >  
> >  	/*
> 
> 
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> > index 43761c5..4b1161d 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -190,7 +190,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
> >  	 * would make the object snooped which might have a
> >  	 * negative performance impact.
> >  	 */
> > -	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) {
> > +	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
> 
> Ahah, you seem to be ambivalent about !(vlv || chv) vs. !vlv && !chv
> yourself. ;)
> 
> Also makes me think you didn't use sed or coccinelle for the change.
> 
> >  		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
> >  		/* Failure shouldn't ever happen this early */
> >  		if (WARN_ON(ret)) {
> 
> 
> > diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> > index 070470f..e384d24 100644
> > --- a/drivers/gpu/drm/i915/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/intel_bios.c
> > @@ -357,8 +357,8 @@ parse_general_features(struct drm_i915_private *dev_priv,
> >  	if (general) {
> >  		dev_priv->vbt.int_tv_support = general->int_tv_support;
> >  		/* int_crt_support can't be trusted on earlier platforms */
> > -		if (bdb->version >= 155 &&
> > -		    (HAS_DDI(dev_priv) || IS_VALLEYVIEW(dev_priv)))
> > +		if (bdb->version >= 155 && (HAS_DDI(dev_priv) ||
> > +		    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
> 
> Hmm, is that the same as gen >= 7 && !ivb?

This can be left alone. CHV doesn't do CRT anyway.

> 
> >  			dev_priv->vbt.int_crt_support = general->int_crt_support;
> >  		dev_priv->vbt.lvds_use_ssc = general->enable_ssc;
> >  		dev_priv->vbt.lvds_ssc_freq =
> 
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
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[PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

[Wayne Boyer]

Do some further clean up based on the initial review of
drm/i915: Separate cherryview from valleyview.

In this case, in i915_gem_alloc_context_obj() only call
i915_gem_object_set_cache_level() for Ivy Bridge devices
since later platforms don't have L3 control bits in the PTE.

v2: Expand comment to mention snooping requirement. (Ville, Imre)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 4b1161d..900ffd0 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -189,8 +189,15 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
 	 * shouldn't touch the cache level, especially as that
 	 * would make the object snooped which might have a
 	 * negative performance impact.
+	 *
+	 * Snooping is required on non-llc platforms in execlist
+	 * mode, but since all GGTT accesses use PAT entry 0 we
+	 * get snooping anyway regardless of cache_level.
+	 *
+	 * This is only applicable for Ivy Bridge devices since
+	 * later platforms don't have L3 control bits in the PTE.
 	 */
-	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
+	if (IS_IVYBRIDGE(dev)) {
 		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
 		/* Failure shouldn't ever happen this early */
 		if (WARN_ON(ret)) {
-- 
2.6.3

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Re: [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

[Ville Syrjälä]

On Tue, Dec 08, 2015 at 09:38:52AM -0800, Wayne Boyer wrote:
> Do some further clean up based on the initial review of
> drm/i915: Separate cherryview from valleyview.
> 
> In this case, in i915_gem_alloc_context_obj() only call
> i915_gem_object_set_cache_level() for Ivy Bridge devices
> since later platforms don't have L3 control bits in the PTE.
> 
> v2: Expand comment to mention snooping requirement. (Ville, Imre)
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem_context.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 4b1161d..900ffd0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -189,8 +189,15 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
>  	 * shouldn't touch the cache level, especially as that
>  	 * would make the object snooped which might have a
>  	 * negative performance impact.
> +	 *
> +	 * Snooping is required on non-llc platforms in execlist
> +	 * mode, but since all GGTT accesses use PAT entry 0 we
> +	 * get snooping anyway regardless of cache_level.
> +	 *
> +	 * This is only applicable for Ivy Bridge devices since
> +	 * later platforms don't have L3 control bits in the PTE.
>  	 */
> -	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
> +	if (IS_IVYBRIDGE(dev)) {
>  		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
>  		/* Failure shouldn't ever happen this early */
>  		if (WARN_ON(ret)) {
> -- 
> 2.6.3

-- 
Ville Syrjälä
Intel OTC
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[PATCH 1/5] drm/i915: Separate cherryview from valleyview

[Wayne Boyer]

The cherryview device shares many characteristics with the valleyview
device.  When support was added to the driver for cherryview, the
corresponding device info structure included .is_valleyview = 1.
This is not correct and leads to some confusion.

This patch changes .is_valleyview to .is_cherryview in the cherryview
device info structure and simplifies the IS_CHERRYVIEW macro.
Then where appropriate, instances of IS_VALLEYVIEW are replaced with
IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent.

v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro.
    Also add followup patches to fix issues discovered during the first
    review. (Ville)
v3: Fix some style issues and one gen check. Remove CRT related changes
    as CRT is not supported on CHV. (Imre, Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c     | 68 ++++++++++++++++-----------------
 drivers/gpu/drm/i915/i915_dma.c         |  8 ++--
 drivers/gpu/drm/i915/i915_drv.c         | 10 ++---
 drivers/gpu/drm/i915/i915_drv.h         | 16 +++++---
 drivers/gpu/drm/i915/i915_gem.c         |  4 +-
 drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
 drivers/gpu/drm/i915/i915_irq.c         |  8 ++--
 drivers/gpu/drm/i915/i915_suspend.c     |  4 +-
 drivers/gpu/drm/i915/i915_sysfs.c       | 10 ++---
 drivers/gpu/drm/i915/intel_audio.c      |  7 ++--
 drivers/gpu/drm/i915/intel_display.c    | 54 ++++++++++++++------------
 drivers/gpu/drm/i915/intel_dp.c         | 40 +++++++++----------
 drivers/gpu/drm/i915/intel_dsi.c        | 14 +++----
 drivers/gpu/drm/i915/intel_dsi_pll.c    |  6 +--
 drivers/gpu/drm/i915/intel_hdmi.c       |  4 +-
 drivers/gpu/drm/i915/intel_hotplug.c    |  2 +-
 drivers/gpu/drm/i915/intel_i2c.c        |  2 +-
 drivers/gpu/drm/i915/intel_panel.c      |  2 +-
 drivers/gpu/drm/i915/intel_pm.c         |  8 ++--
 drivers/gpu/drm/i915/intel_psr.c        |  6 +--
 drivers/gpu/drm/i915/intel_sprite.c     |  4 +-
 drivers/gpu/drm/i915/intel_uncore.c     |  4 +-
 22 files changed, 146 insertions(+), 137 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a8721fc..fff31253 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1142,8 +1142,34 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 			   MEMSTAT_VID_SHIFT);
 		seq_printf(m, "Current P-state: %d\n",
 			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
-	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
-		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+		u32 freq_sts;
+
+		mutex_lock(&dev_priv->rps.hw_lock);
+		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
+		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
+
+		seq_printf(m, "actual GPU freq: %d MHz\n",
+			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
+
+		seq_printf(m, "current GPU freq: %d MHz\n",
+			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
+
+		seq_printf(m, "max GPU freq: %d MHz\n",
+			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
+
+		seq_printf(m, "min GPU freq: %d MHz\n",
+			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
+
+		seq_printf(m, "idle GPU freq: %d MHz\n",
+			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
+
+		seq_printf(m,
+			   "efficient (RPe) frequency: %d MHz\n",
+			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
+		mutex_unlock(&dev_priv->rps.hw_lock);
+	} else if (INTEL_INFO(dev)->gen >= 6) {
 		u32 rp_state_limits;
 		u32 gt_perf_status;
 		u32 rp_state_cap;
@@ -1284,33 +1310,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		seq_printf(m,
 			   "efficient (RPe) frequency: %d MHz\n",
 			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
-	} else if (IS_VALLEYVIEW(dev)) {
-		u32 freq_sts;
-
-		mutex_lock(&dev_priv->rps.hw_lock);
-		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
-		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
-		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
-
-		seq_printf(m, "actual GPU freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
-
-		seq_printf(m, "current GPU freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
-
-		seq_printf(m, "max GPU freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
-
-		seq_printf(m, "min GPU freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
-
-		seq_printf(m, "idle GPU freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
-
-		seq_printf(m,
-			   "efficient (RPe) frequency: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
-		mutex_unlock(&dev_priv->rps.hw_lock);
 	} else {
 		seq_puts(m, "no P-state info available\n");
 	}
@@ -1602,7 +1601,7 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
 	struct drm_info_node *node = m->private;
 	struct drm_device *dev = node->minor->dev;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		return vlv_drpc_info(m);
 	else if (INTEL_INFO(dev)->gen >= 6)
 		return gen6_drpc_info(m);
@@ -1743,7 +1742,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 	else if (IS_PINEVIEW(dev))
 		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 
 	intel_runtime_pm_put(dev_priv);
@@ -3983,7 +3982,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
 		ret = i8xx_pipe_crc_ctl_reg(&source, &val);
 	else if (INTEL_INFO(dev)->gen < 5)
 		ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
 	else if (IS_GEN5(dev) || IS_GEN6(dev))
 		ret = ilk_pipe_crc_ctl_reg(&source, &val);
@@ -4052,7 +4051,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
 
 		if (IS_G4X(dev))
 			g4x_undo_pipe_scramble_reset(dev, pipe);
-		else if (IS_VALLEYVIEW(dev))
+		else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 			vlv_undo_pipe_scramble_reset(dev, pipe);
 		else if (IS_HASWELL(dev) && pipe == PIPE_A)
 			hsw_trans_edp_pipe_A_crc_wa(dev, false);
@@ -4442,7 +4441,8 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
 		 * - WM1+ latency values in 0.5us units
 		 * - latencies are in us on gen9/vlv/chv
 		 */
-		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
+		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
+		    IS_CHERRYVIEW(dev))
 			latency *= 10;
 		else if (level > 0)
 			latency *= 5;
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a81c766..7f08ba8 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -256,7 +256,7 @@ intel_setup_mchbar(struct drm_device *dev)
 	u32 temp;
 	bool enabled;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		return;
 
 	dev_priv->mchbar_need_disable = false;
@@ -779,7 +779,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 		info->num_sprites[PIPE_A] = 2;
 		info->num_sprites[PIPE_B] = 2;
 		info->num_sprites[PIPE_C] = 1;
-	} else if (IS_VALLEYVIEW(dev))
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		for_each_pipe(dev_priv, pipe)
 			info->num_sprites[pipe] = 2;
 	else
@@ -791,7 +791,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 		info->num_pipes = 0;
 	} else if (info->num_pipes > 0 &&
 		   (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
-		   !IS_VALLEYVIEW(dev)) {
+		   !(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) {
 		u32 fuse_strap = I915_READ(FUSE_STRAP);
 		u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 
@@ -836,7 +836,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 
 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 {
-	if (!IS_VALLEYVIEW(dev_priv))
+	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
 		return;
 
 	/*
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e6935f1..841c3c4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -311,7 +311,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.gen = 8, .num_pipes = 3,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
-	.is_valleyview = 1,
+	.is_cherryview = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
 	GEN_CHV_PIPEOFFSETS,
 	CURSOR_OFFSETS,
@@ -802,7 +802,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
 	pci_set_master(dev->pdev);
 
-	if (IS_VALLEYVIEW(dev_priv))
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		ret = vlv_resume_prepare(dev_priv, false);
 	if (ret)
 		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
@@ -1532,7 +1532,7 @@ static int intel_runtime_resume(struct device *device)
 		ret = bxt_resume_prepare(dev_priv);
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		hsw_disable_pc8(dev_priv);
-	else if (IS_VALLEYVIEW(dev_priv))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		ret = vlv_resume_prepare(dev_priv, true);
 
 	/*
@@ -1549,7 +1549,7 @@ static int intel_runtime_resume(struct device *device)
 	 * power well, so hpd is reinitialized from there. For
 	 * everyone else do it here.
 	 */
-	if (!IS_VALLEYVIEW(dev_priv))
+	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 		intel_hpd_init(dev_priv);
 
 	intel_enable_gt_powersave(dev);
@@ -1574,7 +1574,7 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv)
 		ret = bxt_suspend_complete(dev_priv);
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		ret = hsw_suspend_complete(dev_priv);
-	else if (IS_VALLEYVIEW(dev_priv))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		ret = vlv_suspend_complete(dev_priv);
 	else
 		ret = 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f1a8a53..3899f23 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -763,6 +763,7 @@ struct intel_csr {
 	func(is_crestline) sep \
 	func(is_ivybridge) sep \
 	func(is_valleyview) sep \
+	func(is_cherryview) sep \
 	func(is_haswell) sep \
 	func(is_skylake) sep \
 	func(is_broxton) sep \
@@ -2455,9 +2456,9 @@ struct drm_i915_cmd_table {
 				 INTEL_DEVID(dev) == 0x0152 || \
 				 INTEL_DEVID(dev) == 0x015a)
 #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
-#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
+#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
 #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
-#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
+#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
 #define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
 #define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
 #define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
@@ -2584,7 +2585,8 @@ struct drm_i915_cmd_table {
 				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
 				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
-				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
+				 IS_KABYLAKE(dev))
 #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
 #define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
 
@@ -2597,7 +2599,8 @@ struct drm_i915_cmd_table {
 				    INTEL_INFO(dev)->gen >= 8)
 
 #define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
-				 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
+				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
+				 !IS_BROXTON(dev))
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
@@ -2620,7 +2623,8 @@ struct drm_i915_cmd_table {
 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
 
-#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
+#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
+			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 
 /* DPF == dynamic parity feature */
 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
@@ -3511,7 +3515,7 @@ __raw_write(64, q)
 
 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
 {
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		return VLV_VGACNTRL;
 	else if (INTEL_INFO(dev)->gen >= 5)
 		return CPU_VGACNTRL;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index dfaf25b..e96e496 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4838,7 +4838,7 @@ int i915_gem_init(struct drm_device *dev)
 
 	mutex_lock(&dev->struct_mutex);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/* VLVA0 (potential hack), BIOS isn't actually waking us */
 		I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
 		if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
@@ -4963,7 +4963,7 @@ i915_gem_load(struct drm_device *dev)
 
 	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
 
-	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
+	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
 		dev_priv->num_fence_regs = 32;
 	else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 		dev_priv->num_fence_regs = 16;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 43761c5..4b1161d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -190,7 +190,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
 	 * would make the object snooped which might have a
 	 * negative performance impact.
 	 */
-	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) {
+	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
 		/* Failure shouldn't ever happen this early */
 		if (WARN_ON(ret)) {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e88d692..23a0aad 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -581,7 +581,7 @@ i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 {
 	u32 enable_mask;
 
-	if (IS_VALLEYVIEW(dev_priv->dev))
+	if (IS_VALLEYVIEW(dev_priv->dev) || IS_CHERRYVIEW(dev_priv->dev))
 		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 							   status_mask);
 	else
@@ -595,7 +595,7 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 {
 	u32 enable_mask;
 
-	if (IS_VALLEYVIEW(dev_priv->dev))
+	if (IS_VALLEYVIEW(dev_priv->dev) || IS_CHERRYVIEW(dev_priv->dev))
 		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 							   status_mask);
 	else
@@ -1723,7 +1723,7 @@ static void i9xx_hpd_irq_handler(struct drm_device *dev)
 	 */
 	POSTING_READ(PORT_HOTPLUG_STAT);
 
-	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
+	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
 
 		if (hotplug_trigger) {
@@ -4412,7 +4412,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
 
 	/* Let's track the enabled rps events */
-	if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
+	if (IS_VALLEYVIEW(dev_priv))
 		/* WaGsvRC0ResidencyMethod:vlv */
 		dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
 	else
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 2d91821..a2aa09c 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -49,7 +49,7 @@ static void i915_save_display(struct drm_device *dev)
 		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
 		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
 		dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
-	} else if (!IS_VALLEYVIEW(dev)) {
+	} else if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
 		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
 		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
@@ -84,7 +84,7 @@ static void i915_restore_display(struct drm_device *dev)
 		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
 		I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
 		I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
-	} else if (!IS_VALLEYVIEW(dev)) {
+	} else if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 		I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
 		I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
 		I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index f929c61..86c3020 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -49,7 +49,7 @@ static u32 calc_residency(struct drm_device *dev,
 	intel_runtime_pm_get(dev_priv);
 
 	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		units = 1;
 		div = dev_priv->czclk_freq;
 
@@ -284,7 +284,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
 	intel_runtime_pm_get(dev_priv);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
-	if (IS_VALLEYVIEW(dev_priv->dev)) {
+	if (IS_VALLEYVIEW(dev_priv->dev) || IS_CHERRYVIEW(dev_priv->dev)) {
 		u32 freq;
 		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
@@ -598,7 +598,7 @@ void i915_setup_sysfs(struct drm_device *dev)
 		if (ret)
 			DRM_ERROR("RC6p residency sysfs setup failed\n");
 	}
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		ret = sysfs_merge_group(&dev->primary->kdev->kobj,
 					&media_rc6_attr_group);
 		if (ret)
@@ -619,7 +619,7 @@ void i915_setup_sysfs(struct drm_device *dev)
 	}
 
 	ret = 0;
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs);
 	else if (INTEL_INFO(dev)->gen >= 6)
 		ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs);
@@ -635,7 +635,7 @@ void i915_setup_sysfs(struct drm_device *dev)
 void i915_teardown_sysfs(struct drm_device *dev)
 {
 	sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr);
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs);
 	else
 		sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs);
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 9aa83e7..06fffae 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -375,7 +375,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder)
 	if (HAS_PCH_IBX(dev_priv->dev)) {
 		aud_config = IBX_AUD_CFG(pipe);
 		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
-	} else if (IS_VALLEYVIEW(dev_priv)) {
+	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		aud_config = VLV_AUD_CFG(pipe);
 		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 	} else {
@@ -435,7 +435,8 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
 		aud_config = IBX_AUD_CFG(pipe);
 		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
-	} else if (IS_VALLEYVIEW(connector->dev)) {
+	} else if (IS_VALLEYVIEW(connector->dev) ||
+		   IS_CHERRYVIEW(connector->dev)) {
 		hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 		aud_config = VLV_AUD_CFG(pipe);
 		aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
@@ -559,7 +560,7 @@ void intel_init_audio(struct drm_device *dev)
 	if (IS_G4X(dev)) {
 		dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 	} else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b59a2d8..d3b643b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -187,7 +187,7 @@ int intel_hrawclk(struct drm_device *dev)
 	uint32_t clkcfg;
 
 	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		return 200;
 
 	clkcfg = I915_READ(CLKCFG);
@@ -215,7 +215,7 @@ int intel_hrawclk(struct drm_device *dev)
 
 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 {
-	if (!IS_VALLEYVIEW(dev_priv))
+	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 		return;
 
 	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
@@ -716,11 +716,12 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
 	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 		INTELPllInvalid("m1 out of range\n");
 
-	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
+	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
+	    !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 		if (clock->m1 <= clock->m2)
 			INTELPllInvalid("m1 <= m2\n");
 
-	if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
+	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 		if (clock->p < limit->p.min || limit->p.max < clock->p)
 			INTELPllInvalid("p out of range\n");
 		if (clock->m < limit->m.min || limit->m.max < clock->m)
@@ -1305,7 +1306,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 		    I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
 			panel_pipe = PIPE_B;
 		/* XXX: else fix for eDP */
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/* presumably write lock depends on pipe, not port select */
 		pp_reg = VLV_PIPE_PP_CONTROL(pipe);
 		panel_pipe = pipe;
@@ -1423,7 +1424,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
 			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
 			     sprite, pipe_name(pipe));
 		}
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		for_each_sprite(dev_priv, pipe, sprite) {
 			u32 val = I915_READ(SPCNTR(pipe, sprite));
 			I915_STATE_WARN(val & SP_ENABLE,
@@ -2319,7 +2320,7 @@ static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
 	if (INTEL_INFO(dev_priv)->gen >= 9)
 		return 256 * 1024;
 	else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
-		 IS_VALLEYVIEW(dev_priv))
+		 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return 128 * 1024;
 	else if (INTEL_INFO(dev_priv)->gen >= 4)
 		return 4 * 1024;
@@ -5455,7 +5456,7 @@ static void intel_update_cdclk(struct drm_device *dev)
 	 * BSpec erroneously claims we should aim for 4MHz, but
 	 * in fact 1MHz is the correct frequency.
 	 */
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/*
 		 * Program the gmbus_freq based on the cdclk frequency.
 		 * BSpec erroneously claims we should aim for 4MHz, but
@@ -7180,7 +7181,7 @@ static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 
 	WARN_ON(!crtc_state->base.state);
 
-	if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
 		refclk = 100000;
 	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
 	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
@@ -7879,7 +7880,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
 		pipeconf |= PIPECONF_DOUBLE_WIDE;
 
 	/* only g4x and later have fancy bpc/dither controls */
-	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
+	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/* Bspec claims that we can't use dithering for 30bpp pipes. */
 		if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
 			pipeconf |= PIPECONF_DITHER_EN |
@@ -7919,7 +7920,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
 	} else
 		pipeconf |= PIPECONF_PROGRESSIVE;
 
-	if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
+	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+	     intel_crtc->config->limited_color_range)
 		pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
 
 	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
@@ -8166,7 +8168,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 	if (!(tmp & PIPECONF_ENABLE))
 		return false;
 
-	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
+	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		switch (tmp & PIPECONF_BPC_MASK) {
 		case PIPECONF_6BPC:
 			pipe_config->pipe_bpp = 18;
@@ -8182,7 +8184,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 		}
 	}
 
-	if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
+	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
 		pipe_config->limited_color_range = true;
 
 	if (INTEL_INFO(dev)->gen < 4)
@@ -8210,7 +8213,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 		pipe_config->pixel_multiplier = 1;
 	}
 	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
-	if (!IS_VALLEYVIEW(dev)) {
+	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 		/*
 		 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
 		 * on 830. Filter it out here so that we don't
@@ -11537,7 +11540,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
 		work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		ring = &dev_priv->ring[BCS];
 		if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
 			/* vlv: DISPLAY_FLIP fails to change tiling */
@@ -12016,7 +12019,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
 	struct drm_connector_state *connector_state;
 	int bpp, i;
 
-	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
+	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
 		bpp = 10*3;
 	else if (INTEL_INFO(dev)->gen >= 5)
 		bpp = 12*3;
@@ -12626,7 +12629,7 @@ intel_pipe_config_compare(struct drm_device *dev,
 	PIPE_CONF_CHECK_I(pixel_multiplier);
 	PIPE_CONF_CHECK_I(has_hdmi_sink);
 	if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
-	    IS_VALLEYVIEW(dev))
+	    IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		PIPE_CONF_CHECK_I(limited_color_range);
 	PIPE_CONF_CHECK_I(has_infoframe);
 
@@ -14378,7 +14381,7 @@ static void intel_setup_outputs(struct drm_device *dev)
 
 		if (I915_READ(PCH_DP_D) & DP_DETECTED)
 			intel_dp_init(dev, PCH_DP_D, PORT_D);
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/*
 		 * The DP_DETECTED bit is the latched state of the DDC
 		 * SDA pin at boot. However since eDP doesn't require DDC
@@ -14527,7 +14530,7 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
 		 *  pixels and 32K bytes."
 		 */
 		 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
-	} else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
+	} else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 		return 32*1024;
 	} else if (gen >= 4) {
 		if (fb_modifier == I915_FORMAT_MOD_X_TILED)
@@ -14631,7 +14634,8 @@ static int intel_framebuffer_init(struct drm_device *dev,
 		}
 		break;
 	case DRM_FORMAT_ABGR8888:
-		if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
+		if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
+		    INTEL_INFO(dev)->gen < 9) {
 			DRM_DEBUG("unsupported pixel format: %s\n",
 				  drm_get_format_name(mode_cmd->pixel_format));
 			return -EINVAL;
@@ -14647,7 +14651,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
 		}
 		break;
 	case DRM_FORMAT_ABGR2101010:
-		if (!IS_VALLEYVIEW(dev)) {
+		if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 			DRM_DEBUG("unsupported pixel format: %s\n",
 				  drm_get_format_name(mode_cmd->pixel_format));
 			return -EINVAL;
@@ -14775,7 +14779,7 @@ static void intel_init_display(struct drm_device *dev)
 		dev_priv->display.crtc_disable = ironlake_crtc_disable;
 		dev_priv->display.update_primary_plane =
 			ironlake_update_primary_plane;
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			i9xx_get_initial_plane_config;
@@ -14808,7 +14812,7 @@ static void intel_init_display(struct drm_device *dev)
 	else if (IS_HASWELL(dev))
 		dev_priv->display.get_display_clock_speed =
 			haswell_get_display_clock_speed;
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		dev_priv->display.get_display_clock_speed =
 			valleyview_get_display_clock_speed;
 	else if (IS_GEN5(dev))
@@ -14866,7 +14870,7 @@ static void intel_init_display(struct drm_device *dev)
 			dev_priv->display.modeset_calc_cdclk =
 				broadwell_modeset_calc_cdclk;
 		}
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->display.modeset_commit_cdclk =
 			valleyview_modeset_commit_cdclk;
 		dev_priv->display.modeset_calc_cdclk =
@@ -15640,7 +15644,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
 		pll->on = false;
 	}
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_wm_get_hw_state(dev);
 	else if (IS_GEN9(dev))
 		skl_wm_get_hw_state(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f335c92..e36f741 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -517,7 +517,7 @@ void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 	struct drm_device *dev = dev_priv->dev;
 	struct intel_encoder *encoder;
 
-	if (WARN_ON(!IS_VALLEYVIEW(dev)))
+	if (WARN_ON(!(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))))
 		return;
 
 	/*
@@ -582,7 +582,7 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 
 	pps_lock(intel_dp);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 		i915_reg_t pp_ctrl_reg, pp_div_reg;
 		u32 pp_div;
@@ -610,7 +610,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
-	if (IS_VALLEYVIEW(dev) &&
+	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 	    intel_dp->pps_pipe == INVALID_PIPE)
 		return false;
 
@@ -624,7 +624,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
-	if (IS_VALLEYVIEW(dev) &&
+	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 	    intel_dp->pps_pipe == INVALID_PIPE)
 		return false;
 
@@ -1723,7 +1723,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
 		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
 	} else {
 		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
-		    crtc->config->limited_color_range)
+		    !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
 			intel_dp->DP |= DP_COLOR_RANGE_16_235;
 
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
@@ -2418,7 +2418,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 	pipe_config->base.adjusted_mode.flags |= flags;
 
 	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
-	    tmp & DP_COLOR_RANGE_16_235)
+	    !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
 		pipe_config->limited_color_range = true;
 
 	pipe_config->has_dp_encoder = true;
@@ -2694,7 +2694,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
 
 	pps_lock(intel_dp);
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_init_panel_power_sequencer(intel_dp);
 
 	/*
@@ -2728,7 +2728,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
 
 	pps_unlock(intel_dp);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		unsigned int lane_mask = 0x0;
 
 		if (IS_CHERRYVIEW(dev))
@@ -3218,7 +3218,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
 		if (dev_priv->edp_low_vswing && port == PORT_A)
 			return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
-	} else if (IS_VALLEYVIEW(dev))
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 	else if (IS_GEN7(dev) && port == PORT_A)
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
@@ -3259,7 +3259,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 		default:
 			return DP_TRAIN_PRE_EMPH_LEVEL_0;
 		}
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			return DP_TRAIN_PRE_EMPH_LEVEL_3;
@@ -4539,7 +4539,7 @@ bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
 		return cpt_digital_port_connected(dev_priv, port);
 	else if (IS_BROXTON(dev_priv))
 		return bxt_digital_port_connected(dev_priv, port);
-	else if (IS_VALLEYVIEW(dev_priv))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return vlv_digital_port_connected(dev_priv, port);
 	else
 		return g4x_digital_port_connected(dev_priv, port);
@@ -4933,7 +4933,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
 	 * Read out the current power sequencer assignment,
 	 * in case the BIOS did something with it.
 	 */
-	if (IS_VALLEYVIEW(encoder->dev))
+	if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
 		vlv_initial_power_sequencer_setup(intel_dp);
 
 	intel_edp_panel_vdd_sanitize(intel_dp);
@@ -5293,7 +5293,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 
 	/* Haswell doesn't have any port selection bits for the panel
 	 * power sequencer any more. */
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		port_sel = PANEL_PORT_SELECT_VLV(port);
 	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
 		if (port == PORT_A)
@@ -5405,12 +5405,12 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 
 		val = I915_READ(reg);
 		if (index > DRRS_HIGH_RR) {
-			if (IS_VALLEYVIEW(dev))
+			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
 			else
 				val |= PIPECONF_EDP_RR_MODE_SWITCH;
 		} else {
-			if (IS_VALLEYVIEW(dev))
+			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
 			else
 				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
@@ -5777,7 +5777,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	}
 	mutex_unlock(&dev->mode_config.mutex);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
 		register_reboot_notifier(&intel_dp->edp_notifier);
 
@@ -5825,7 +5825,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	/* intel_dp vfuncs */
 	if (INTEL_INFO(dev)->gen >= 9)
 		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
 	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
@@ -5860,8 +5860,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 		intel_encoder->type = INTEL_OUTPUT_EDP;
 
 	/* eDP only on port B and/or C on vlv/chv */
-	if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
-		    port != PORT_B && port != PORT_C))
+	if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+		    is_edp(intel_dp) && port != PORT_B && port != PORT_C))
 		return false;
 
 	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
@@ -5912,7 +5912,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	if (is_edp(intel_dp)) {
 		pps_lock(intel_dp);
 		intel_dp_init_panel_power_timestamps(intel_dp);
-		if (IS_VALLEYVIEW(dev))
+		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 			vlv_initial_power_sequencer_setup(intel_dp);
 		else
 			intel_dp_init_panel_power_sequencer(dev, intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 230957f..cada737 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -369,7 +369,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_dsi_device_ready(encoder);
 	else if (IS_BROXTON(dev))
 		bxt_dsi_device_ready(encoder);
@@ -487,7 +487,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 
 	msleep(intel_dsi->panel_on_delay);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/*
 		 * Disable DPOunit clock gating, can stall pipe
 		 * and we need DPLL REFA always enabled
@@ -684,8 +684,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 		 * Enable bit does not get set. To check whether DSI Port C
 		 * was enabled in BIOS, check the Pipe B enable bit
 		 */
-		if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
-		    (port == PORT_C))
+		if (IS_VALLEYVIEW(dev) && (port == PORT_C))
 			dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
 							PIPECONF_ENABLE;
 
@@ -716,7 +715,8 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
 
 	if (IS_BROXTON(encoder->base.dev))
 		pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
-	else if (IS_VALLEYVIEW(encoder->base.dev))
+	else if (IS_VALLEYVIEW(encoder->base.dev) ||
+		 IS_CHERRYVIEW(encoder->base.dev))
 		pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
 
 	if (!pclk)
@@ -869,7 +869,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-		if (IS_VALLEYVIEW(dev)) {
+		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 			/*
 			 * escape clock divider, 20MHz, shared for A and C.
 			 * device ready must be off when doing this! txclkesc?
@@ -1129,7 +1129,7 @@ void intel_dsi_init(struct drm_device *dev)
 	if (!dev_priv->vbt.has_mipi)
 		return;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
 	} else {
 		DRM_ERROR("Unsupported Mipi device to reg base");
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index cb3cf39..fbd2b51 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -561,7 +561,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_enable_dsi_pll(encoder);
 	else if (IS_BROXTON(dev))
 		bxt_enable_dsi_pll(encoder);
@@ -571,7 +571,7 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_disable_dsi_pll(encoder);
 	else if (IS_BROXTON(dev))
 		bxt_disable_dsi_pll(encoder);
@@ -599,6 +599,6 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
 
 	if (IS_BROXTON(dev))
 		bxt_dsi_reset_clocks(encoder, port);
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_dsi_reset_clocks(encoder, port);
 }
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index c3978ba..be7fab9 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -638,7 +638,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
 
 	if (HAS_DDI(dev_priv))
 		reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
-	else if (IS_VALLEYVIEW(dev_priv))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 	else if (HAS_PCH_SPLIT(dev_priv->dev))
 		reg = TVIDEO_DIP_GCP(crtc->pipe);
@@ -2100,7 +2100,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 		BUG();
 	}
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		intel_hdmi->write_infoframe = vlv_write_infoframe;
 		intel_hdmi->set_infoframes = vlv_set_infoframes;
 		intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
index b177857..a294a3c 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -407,7 +407,7 @@ void intel_hpd_irq_handler(struct drm_device *dev,
 			 * hotplug bits itself. So only WARN about unexpected
 			 * interrupts on saner platforms.
 			 */
-			WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
+			WARN_ONCE(!HAS_GMCH_DISPLAY(dev),
 				  "Received HPD interrupt on pin %d although disabled\n", i);
 			continue;
 		}
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index e26e22a..25254b5 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -636,7 +636,7 @@ int intel_setup_gmbus(struct drm_device *dev)
 	if (HAS_PCH_NOP(dev))
 		return 0;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
 	else if (!HAS_GMCH_DISPLAY(dev_priv))
 		dev_priv->gpio_mmio_base =
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index ae808b6..72183a0 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1784,7 +1784,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
 		panel->backlight.set = pch_set_backlight;
 		panel->backlight.get = pch_get_backlight;
 		panel->backlight.hz_to_pwm = pch_hz_to_pwm;
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		if (dev_priv->vbt.has_mipi) {
 			panel->backlight.setup = pwm_setup_backlight;
 			panel->backlight.enable = pwm_enable_backlight;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ee05ce8..fe56181 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -291,7 +291,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 	struct drm_device *dev = dev_priv->dev;
 	u32 val;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 		POSTING_READ(FW_BLC_SELF_VLV);
 		dev_priv->wm.vlv.cxsr = enable;
@@ -4405,7 +4405,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
-		if (IS_VALLEYVIEW(dev))
+		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 			vlv_set_rps_idle(dev_priv);
 		else
 			gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
@@ -4458,7 +4458,7 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
 
 void intel_set_rps(struct drm_device *dev, u8 val)
 {
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		valleyview_set_rps(dev, val);
 	else
 		gen6_set_rps(dev, val);
@@ -4502,7 +4502,7 @@ static void valleyview_disable_rps(struct drm_device *dev)
 
 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
 {
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
 			mode = GEN6_RC_CTL_RC6_ENABLE;
 		else
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b6609e6..1778a7d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -332,8 +332,8 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 		return false;
 	}
 
-	if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||
-				    (dig_port->port != PORT_A))) {
+	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
+	    ((dev_priv->vbt.psr.full_link) || (dig_port->port != PORT_A))) {
 		DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n");
 		return false;
 	}
@@ -650,7 +650,7 @@ void intel_psr_single_frame_update(struct drm_device *dev,
 	 * Single frame update is already supported on BDW+ but it requires
 	 * many W/A and it isn't really needed.
 	 */
-	if (!IS_VALLEYVIEW(dev))
+	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
 		return;
 
 	mutex_lock(&dev_priv->psr.lock);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 2b96f33..f8bf622 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -951,7 +951,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 	if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 		return -EINVAL;
 
-	if (IS_VALLEYVIEW(dev) &&
+	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 	    set->flags & I915_SET_COLORKEY_DESTINATION)
 		return -EINVAL;
 
@@ -1086,7 +1086,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
 			intel_plane->max_downscale = 1;
 		}
 
-		if (IS_VALLEYVIEW(dev)) {
+		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 			intel_plane->update_plane = vlv_update_plane;
 			intel_plane->disable_plane = vlv_disable_plane;
 
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index c2358ba..fcf04fe 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1115,7 +1115,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
 		d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
 	}
 
-	if (IS_VALLEYVIEW(dev_priv))
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		d->reg_post = FORCEWAKE_ACK_VLV;
 	else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
 		d->reg_post = ECOBUS;
@@ -1148,7 +1148,7 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
 			       FORCEWAKE_ACK_BLITTER_GEN9);
 		fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
 			       FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
 		if (!IS_CHERRYVIEW(dev))
 			dev_priv->uncore.funcs.force_wake_put =
-- 
2.6.3

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Re: [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

[Chris Wilson]

On Tue, Dec 08, 2015 at 07:45:50PM +0200, Ville Syrjälä wrote:
> On Tue, Dec 08, 2015 at 09:38:52AM -0800, Wayne Boyer wrote:
> > Do some further clean up based on the initial review of
> > drm/i915: Separate cherryview from valleyview.
> > 
> > In this case, in i915_gem_alloc_context_obj() only call
> > i915_gem_object_set_cache_level() for Ivy Bridge devices
> > since later platforms don't have L3 control bits in the PTE.
> > 
> > v2: Expand comment to mention snooping requirement. (Ville, Imre)
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Loses Haswell.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

[Ville Syrjälä]

On Tue, Dec 08, 2015 at 08:50:48PM +0000, Chris Wilson wrote:
> On Tue, Dec 08, 2015 at 07:45:50PM +0200, Ville Syrjälä wrote:
> > On Tue, Dec 08, 2015 at 09:38:52AM -0800, Wayne Boyer wrote:
> > > Do some further clean up based on the initial review of
> > > drm/i915: Separate cherryview from valleyview.
> > > 
> > > In this case, in i915_gem_alloc_context_obj() only call
> > > i915_gem_object_set_cache_level() for Ivy Bridge devices
> > > since later platforms don't have L3 control bits in the PTE.
> > > 
> > > v2: Expand comment to mention snooping requirement. (Ville, Imre)
> > > 
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
> > 
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Loses Haswell.

Nope. HSW doesn't do L3 via PTEs.

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

[Chris Wilson]

On Tue, Dec 08, 2015 at 11:07:01PM +0200, Ville Syrjälä wrote:
> On Tue, Dec 08, 2015 at 08:50:48PM +0000, Chris Wilson wrote:
> > On Tue, Dec 08, 2015 at 07:45:50PM +0200, Ville Syrjälä wrote:
> > > On Tue, Dec 08, 2015 at 09:38:52AM -0800, Wayne Boyer wrote:
> > > > Do some further clean up based on the initial review of
> > > > drm/i915: Separate cherryview from valleyview.
> > > > 
> > > > In this case, in i915_gem_alloc_context_obj() only call
> > > > i915_gem_object_set_cache_level() for Ivy Bridge devices
> > > > since later platforms don't have L3 control bits in the PTE.
> > > > 
> > > > v2: Expand comment to mention snooping requirement. (Ville, Imre)
> > > > 
> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
> > > 
> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Loses Haswell.
> 
> Nope. HSW doesn't do L3 via PTEs.

I was actually thinking of eLLC, but we never differentiate that bit in
our cache levels.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [PATCH 1/5] drm/i915: Separate cherryview from valleyview

[Ville Syrjälä]

On Tue, Dec 08, 2015 at 11:46:53AM -0800, Wayne Boyer wrote:
> The cherryview device shares many characteristics with the valleyview
> device.  When support was added to the driver for cherryview, the
> corresponding device info structure included .is_valleyview = 1.
> This is not correct and leads to some confusion.
> 
> This patch changes .is_valleyview to .is_cherryview in the cherryview
> device info structure and simplifies the IS_CHERRYVIEW macro.
> Then where appropriate, instances of IS_VALLEYVIEW are replaced with
> IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent.
> 
> v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro.
>     Also add followup patches to fix issues discovered during the first
>     review. (Ville)
> v3: Fix some style issues and one gen check. Remove CRT related changes
>     as CRT is not supported on CHV. (Imre, Ville)
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c     | 68 ++++++++++++++++-----------------
>  drivers/gpu/drm/i915/i915_dma.c         |  8 ++--
>  drivers/gpu/drm/i915/i915_drv.c         | 10 ++---
>  drivers/gpu/drm/i915/i915_drv.h         | 16 +++++---
>  drivers/gpu/drm/i915/i915_gem.c         |  4 +-
>  drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
>  drivers/gpu/drm/i915/i915_irq.c         |  8 ++--
>  drivers/gpu/drm/i915/i915_suspend.c     |  4 +-
>  drivers/gpu/drm/i915/i915_sysfs.c       | 10 ++---
>  drivers/gpu/drm/i915/intel_audio.c      |  7 ++--
>  drivers/gpu/drm/i915/intel_display.c    | 54 ++++++++++++++------------
>  drivers/gpu/drm/i915/intel_dp.c         | 40 +++++++++----------
>  drivers/gpu/drm/i915/intel_dsi.c        | 14 +++----
>  drivers/gpu/drm/i915/intel_dsi_pll.c    |  6 +--
>  drivers/gpu/drm/i915/intel_hdmi.c       |  4 +-
>  drivers/gpu/drm/i915/intel_hotplug.c    |  2 +-
>  drivers/gpu/drm/i915/intel_i2c.c        |  2 +-
>  drivers/gpu/drm/i915/intel_panel.c      |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c         |  8 ++--
>  drivers/gpu/drm/i915/intel_psr.c        |  6 +--
>  drivers/gpu/drm/i915/intel_sprite.c     |  4 +-
>  drivers/gpu/drm/i915/intel_uncore.c     |  4 +-

Looks like you missed:
sanitize_enable_ppgtt() in i915_gem_gtt.c
Well, it just has a pointless !CHV in left in there.

I didn't find anything wrong in there anymore. Just some minor
simplifications and bikesheds that could be done as part of this
patch, or maybe some of them could be followups. See below.

>  22 files changed, 146 insertions(+), 137 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index a8721fc..fff31253 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1142,8 +1142,34 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  			   MEMSTAT_VID_SHIFT);
>  		seq_printf(m, "Current P-state: %d\n",
>  			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
> -	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
> -		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> +		u32 freq_sts;
> +
> +		mutex_lock(&dev_priv->rps.hw_lock);
> +		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
> +		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
> +
> +		seq_printf(m, "actual GPU freq: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
> +
> +		seq_printf(m, "current GPU freq: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
> +
> +		seq_printf(m, "max GPU freq: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
> +
> +		seq_printf(m, "min GPU freq: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
> +
> +		seq_printf(m, "idle GPU freq: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
> +
> +		seq_printf(m,
> +			   "efficient (RPe) frequency: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +	} else if (INTEL_INFO(dev)->gen >= 6) {
>  		u32 rp_state_limits;
>  		u32 gt_perf_status;
>  		u32 rp_state_cap;
> @@ -1284,33 +1310,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		seq_printf(m,
>  			   "efficient (RPe) frequency: %d MHz\n",
>  			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
> -	} else if (IS_VALLEYVIEW(dev)) {
> -		u32 freq_sts;
> -
> -		mutex_lock(&dev_priv->rps.hw_lock);
> -		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> -		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
> -		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
> -
> -		seq_printf(m, "actual GPU freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
> -
> -		seq_printf(m, "current GPU freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
> -
> -		seq_printf(m, "max GPU freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
> -
> -		seq_printf(m, "min GPU freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
> -
> -		seq_printf(m, "idle GPU freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
> -
> -		seq_printf(m,
> -			   "efficient (RPe) frequency: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
> -		mutex_unlock(&dev_priv->rps.hw_lock);
>  	} else {
>  		seq_puts(m, "no P-state info available\n");
>  	}
> @@ -1602,7 +1601,7 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
>  	struct drm_info_node *node = m->private;
>  	struct drm_device *dev = node->minor->dev;
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		return vlv_drpc_info(m);
>  	else if (INTEL_INFO(dev)->gen >= 6)
>  		return gen6_drpc_info(m);
> @@ -1743,7 +1742,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>  		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
>  	else if (IS_PINEVIEW(dev))
>  		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
> -	else if (IS_VALLEYVIEW(dev))
> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>  
>  	intel_runtime_pm_put(dev_priv);
> @@ -3983,7 +3982,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
>  		ret = i8xx_pipe_crc_ctl_reg(&source, &val);
>  	else if (INTEL_INFO(dev)->gen < 5)
>  		ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
> -	else if (IS_VALLEYVIEW(dev))
> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
>  	else if (IS_GEN5(dev) || IS_GEN6(dev))
>  		ret = ilk_pipe_crc_ctl_reg(&source, &val);
> @@ -4052,7 +4051,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
>  
>  		if (IS_G4X(dev))
>  			g4x_undo_pipe_scramble_reset(dev, pipe);
> -		else if (IS_VALLEYVIEW(dev))
> +		else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  			vlv_undo_pipe_scramble_reset(dev, pipe);
>  		else if (IS_HASWELL(dev) && pipe == PIPE_A)
>  			hsw_trans_edp_pipe_A_crc_wa(dev, false);
> @@ -4442,7 +4441,8 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
>  		 * - WM1+ latency values in 0.5us units
>  		 * - latencies are in us on gen9/vlv/chv
>  		 */
> -		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
> +		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
> +		    IS_CHERRYVIEW(dev))
>  			latency *= 10;
>  		else if (level > 0)
>  			latency *= 5;
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index a81c766..7f08ba8 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -256,7 +256,7 @@ intel_setup_mchbar(struct drm_device *dev)
>  	u32 temp;
>  	bool enabled;
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		return;
>  
>  	dev_priv->mchbar_need_disable = false;
> @@ -779,7 +779,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>  		info->num_sprites[PIPE_A] = 2;
>  		info->num_sprites[PIPE_B] = 2;
>  		info->num_sprites[PIPE_C] = 1;
> -	} else if (IS_VALLEYVIEW(dev))
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		for_each_pipe(dev_priv, pipe)
>  			info->num_sprites[pipe] = 2;
>  	else
> @@ -791,7 +791,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>  		info->num_pipes = 0;
>  	} else if (info->num_pipes > 0 &&
>  		   (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
> -		   !IS_VALLEYVIEW(dev)) {
> +		   !(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) {
>  		u32 fuse_strap = I915_READ(FUSE_STRAP);
>  		u32 sfuse_strap = I915_READ(SFUSE_STRAP);
>  
> @@ -836,7 +836,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>  
>  static void intel_init_dpio(struct drm_i915_private *dev_priv)
>  {
> -	if (!IS_VALLEYVIEW(dev_priv))
> +	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
>  		return;

Here we could drop this early check and just do

  if (IS_CHV) {
  	...
- } else {
+ } else if (IS_VLV) {
 	...
  }

>  
>  	/*
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index e6935f1..841c3c4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -311,7 +311,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.gen = 8, .num_pipes = 3,
>  	.need_gfx_hws = 1, .has_hotplug = 1,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> -	.is_valleyview = 1,
> +	.is_cherryview = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
>  	GEN_CHV_PIPEOFFSETS,
>  	CURSOR_OFFSETS,
> @@ -802,7 +802,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
>  
>  	pci_set_master(dev->pdev);
>  
> -	if (IS_VALLEYVIEW(dev_priv))
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		ret = vlv_resume_prepare(dev_priv, false);
>  	if (ret)
>  		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
> @@ -1532,7 +1532,7 @@ static int intel_runtime_resume(struct device *device)
>  		ret = bxt_resume_prepare(dev_priv);
>  	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		hsw_disable_pc8(dev_priv);
> -	else if (IS_VALLEYVIEW(dev_priv))
> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		ret = vlv_resume_prepare(dev_priv, true);
>  
>  	/*
> @@ -1549,7 +1549,7 @@ static int intel_runtime_resume(struct device *device)
>  	 * power well, so hpd is reinitialized from there. For
>  	 * everyone else do it here.
>  	 */
> -	if (!IS_VALLEYVIEW(dev_priv))
> +	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))

'!VLV && !CHV' again perhaps?

>  		intel_hpd_init(dev_priv);
>  
>  	intel_enable_gt_powersave(dev);
> @@ -1574,7 +1574,7 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv)
>  		ret = bxt_suspend_complete(dev_priv);
>  	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		ret = hsw_suspend_complete(dev_priv);
> -	else if (IS_VALLEYVIEW(dev_priv))
> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		ret = vlv_suspend_complete(dev_priv);
>  	else
>  		ret = 0;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f1a8a53..3899f23 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -763,6 +763,7 @@ struct intel_csr {
>  	func(is_crestline) sep \
>  	func(is_ivybridge) sep \
>  	func(is_valleyview) sep \
> +	func(is_cherryview) sep \
>  	func(is_haswell) sep \
>  	func(is_skylake) sep \
>  	func(is_broxton) sep \
> @@ -2455,9 +2456,9 @@ struct drm_i915_cmd_table {
>  				 INTEL_DEVID(dev) == 0x0152 || \
>  				 INTEL_DEVID(dev) == 0x015a)
>  #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
> -#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
> +#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
>  #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
> -#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
> +#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
>  #define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
>  #define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
>  #define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
> @@ -2584,7 +2585,8 @@ struct drm_i915_cmd_table {
>  				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
>  #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
>  				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
> -				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
> +				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \

BDW||CHV could be replaced with IS_GEN8

> +				 IS_KABYLAKE(dev))
>  #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
>  #define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
>  
> @@ -2597,7 +2599,8 @@ struct drm_i915_cmd_table {
>  				    INTEL_INFO(dev)->gen >= 8)
>  
>  #define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
> -				 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
> +				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
> +				 !IS_BROXTON(dev))
>  
>  #define INTEL_PCH_DEVICE_ID_MASK		0xff00
>  #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
> @@ -2620,7 +2623,8 @@ struct drm_i915_cmd_table {
>  #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
>  #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
>  
> -#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
> +#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
> +			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  
>  /* DPF == dynamic parity feature */
>  #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
> @@ -3511,7 +3515,7 @@ __raw_write(64, q)
>  
>  static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
>  {
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		return VLV_VGACNTRL;
>  	else if (INTEL_INFO(dev)->gen >= 5)
>  		return CPU_VGACNTRL;
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index dfaf25b..e96e496 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4838,7 +4838,7 @@ int i915_gem_init(struct drm_device *dev)
>  
>  	mutex_lock(&dev->struct_mutex);
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		/* VLVA0 (potential hack), BIOS isn't actually waking us */
>  		I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
>  		if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
> @@ -4963,7 +4963,7 @@ i915_gem_load(struct drm_device *dev)
>  
>  	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
>  
> -	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
> +	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
>  		dev_priv->num_fence_regs = 32;
>  	else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
>  		dev_priv->num_fence_regs = 16;
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 43761c5..4b1161d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -190,7 +190,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
>  	 * would make the object snooped which might have a
>  	 * negative performance impact.
>  	 */
> -	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) {
> +	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>  		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
>  		/* Failure shouldn't ever happen this early */
>  		if (WARN_ON(ret)) {
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e88d692..23a0aad 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -581,7 +581,7 @@ i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
>  {
>  	u32 enable_mask;
>  
> -	if (IS_VALLEYVIEW(dev_priv->dev))
> +	if (IS_VALLEYVIEW(dev_priv->dev) || IS_CHERRYVIEW(dev_priv->dev))

Can drop the ->dev while at it.

>  		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
>  							   status_mask);
>  	else
> @@ -595,7 +595,7 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
>  {
>  	u32 enable_mask;
>  
> -	if (IS_VALLEYVIEW(dev_priv->dev))
> +	if (IS_VALLEYVIEW(dev_priv->dev) || IS_CHERRYVIEW(dev_priv->dev))

ditto

>  		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
>  							   status_mask);
>  	else
> @@ -1723,7 +1723,7 @@ static void i9xx_hpd_irq_handler(struct drm_device *dev)
>  	 */
>  	POSTING_READ(PORT_HOTPLUG_STAT);
>  
> -	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
> +	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
>  
>  		if (hotplug_trigger) {
> @@ -4412,7 +4412,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
>  
>  	/* Let's track the enabled rps events */
> -	if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
> +	if (IS_VALLEYVIEW(dev_priv))
>  		/* WaGsvRC0ResidencyMethod:vlv */
>  		dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
>  	else
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 2d91821..a2aa09c 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -49,7 +49,7 @@ static void i915_save_display(struct drm_device *dev)
>  		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
>  		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
>  		dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
> -	} else if (!IS_VALLEYVIEW(dev)) {
> +	} else if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>  		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
>  		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
>  		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
> @@ -84,7 +84,7 @@ static void i915_restore_display(struct drm_device *dev)
>  		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
>  		I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
>  		I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
> -	} else if (!IS_VALLEYVIEW(dev)) {
> +	} else if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>  		I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
>  		I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
>  		I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index f929c61..86c3020 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -49,7 +49,7 @@ static u32 calc_residency(struct drm_device *dev,
>  	intel_runtime_pm_get(dev_priv);
>  
>  	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		units = 1;
>  		div = dev_priv->czclk_freq;
>  
> @@ -284,7 +284,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
>  	intel_runtime_pm_get(dev_priv);
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
> -	if (IS_VALLEYVIEW(dev_priv->dev)) {
> +	if (IS_VALLEYVIEW(dev_priv->dev) || IS_CHERRYVIEW(dev_priv->dev)) {

Can drop the ->dev again

>  		u32 freq;
>  		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>  		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
> @@ -598,7 +598,7 @@ void i915_setup_sysfs(struct drm_device *dev)
>  		if (ret)
>  			DRM_ERROR("RC6p residency sysfs setup failed\n");
>  	}
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		ret = sysfs_merge_group(&dev->primary->kdev->kobj,
>  					&media_rc6_attr_group);
>  		if (ret)
> @@ -619,7 +619,7 @@ void i915_setup_sysfs(struct drm_device *dev)
>  	}
>  
>  	ret = 0;
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs);
>  	else if (INTEL_INFO(dev)->gen >= 6)
>  		ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs);
> @@ -635,7 +635,7 @@ void i915_setup_sysfs(struct drm_device *dev)
>  void i915_teardown_sysfs(struct drm_device *dev)
>  {
>  	sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr);
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs);
>  	else
>  		sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs);
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 9aa83e7..06fffae 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -375,7 +375,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder)
>  	if (HAS_PCH_IBX(dev_priv->dev)) {
>  		aud_config = IBX_AUD_CFG(pipe);
>  		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
> -	} else if (IS_VALLEYVIEW(dev_priv)) {
> +	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		aud_config = VLV_AUD_CFG(pipe);
>  		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
>  	} else {
> @@ -435,7 +435,8 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
>  		aud_config = IBX_AUD_CFG(pipe);
>  		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
>  		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
> -	} else if (IS_VALLEYVIEW(connector->dev)) {
> +	} else if (IS_VALLEYVIEW(connector->dev) ||
> +		   IS_CHERRYVIEW(connector->dev)) {
>  		hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
>  		aud_config = VLV_AUD_CFG(pipe);
>  		aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
> @@ -559,7 +560,7 @@ void intel_init_audio(struct drm_device *dev)
>  	if (IS_G4X(dev)) {
>  		dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
>  		dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
>  		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
>  	} else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b59a2d8..d3b643b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -187,7 +187,7 @@ int intel_hrawclk(struct drm_device *dev)
>  	uint32_t clkcfg;
>  
>  	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		return 200;
>  
>  	clkcfg = I915_READ(CLKCFG);
> @@ -215,7 +215,7 @@ int intel_hrawclk(struct drm_device *dev)
>  
>  static void intel_update_czclk(struct drm_i915_private *dev_priv)
>  {
> -	if (!IS_VALLEYVIEW(dev_priv))
> +	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
>  		return;
>  
>  	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
> @@ -716,11 +716,12 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
>  	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
>  		INTELPllInvalid("m1 out of range\n");
>  
> -	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
> +	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
> +	    !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
>  		if (clock->m1 <= clock->m2)
>  			INTELPllInvalid("m1 <= m2\n");
>  
> -	if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
>  		if (clock->p < limit->p.min || limit->p.max < clock->p)
>  			INTELPllInvalid("p out of range\n");
>  		if (clock->m < limit->m.min || limit->m.max < clock->m)
> @@ -1305,7 +1306,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv,
>  		    I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
>  			panel_pipe = PIPE_B;
>  		/* XXX: else fix for eDP */
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		/* presumably write lock depends on pipe, not port select */
>  		pp_reg = VLV_PIPE_PP_CONTROL(pipe);
>  		panel_pipe = pipe;
> @@ -1423,7 +1424,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
>  			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
>  			     sprite, pipe_name(pipe));
>  		}
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		for_each_sprite(dev_priv, pipe, sprite) {
>  			u32 val = I915_READ(SPCNTR(pipe, sprite));
>  			I915_STATE_WARN(val & SP_ENABLE,
> @@ -2319,7 +2320,7 @@ static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
>  	if (INTEL_INFO(dev_priv)->gen >= 9)
>  		return 256 * 1024;
>  	else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
> -		 IS_VALLEYVIEW(dev_priv))
> +		 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		return 128 * 1024;
>  	else if (INTEL_INFO(dev_priv)->gen >= 4)
>  		return 4 * 1024;
> @@ -5455,7 +5456,7 @@ static void intel_update_cdclk(struct drm_device *dev)
>  	 * BSpec erroneously claims we should aim for 4MHz, but
>  	 * in fact 1MHz is the correct frequency.
>  	 */
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		/*
>  		 * Program the gmbus_freq based on the cdclk frequency.
>  		 * BSpec erroneously claims we should aim for 4MHz, but
> @@ -7180,7 +7181,7 @@ static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
>  
>  	WARN_ON(!crtc_state->base.state);
>  
> -	if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
>  		refclk = 100000;
>  	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
>  	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
> @@ -7879,7 +7880,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
>  		pipeconf |= PIPECONF_DOUBLE_WIDE;
>  
>  	/* only g4x and later have fancy bpc/dither controls */
> -	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
> +	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		/* Bspec claims that we can't use dithering for 30bpp pipes. */
>  		if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
>  			pipeconf |= PIPECONF_DITHER_EN |
> @@ -7919,7 +7920,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
>  	} else
>  		pipeconf |= PIPECONF_PROGRESSIVE;
>  
> -	if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> +	     intel_crtc->config->limited_color_range)
>  		pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
>  
>  	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
> @@ -8166,7 +8168,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  	if (!(tmp & PIPECONF_ENABLE))
>  		return false;
>  
> -	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
> +	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		switch (tmp & PIPECONF_BPC_MASK) {
>  		case PIPECONF_6BPC:
>  			pipe_config->pipe_bpp = 18;
> @@ -8182,7 +8184,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  		}
>  	}
>  
> -	if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> +	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
>  		pipe_config->limited_color_range = true;
>  
>  	if (INTEL_INFO(dev)->gen < 4)
> @@ -8210,7 +8213,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  		pipe_config->pixel_multiplier = 1;
>  	}
>  	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
> -	if (!IS_VALLEYVIEW(dev)) {
> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>  		/*
>  		 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
>  		 * on 830. Filter it out here so that we don't
> @@ -11537,7 +11540,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>  	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
>  		work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		ring = &dev_priv->ring[BCS];
>  		if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
>  			/* vlv: DISPLAY_FLIP fails to change tiling */
> @@ -12016,7 +12019,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
>  	struct drm_connector_state *connector_state;
>  	int bpp, i;
>  
> -	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
> +	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
>  		bpp = 10*3;
>  	else if (INTEL_INFO(dev)->gen >= 5)
>  		bpp = 12*3;
> @@ -12626,7 +12629,7 @@ intel_pipe_config_compare(struct drm_device *dev,
>  	PIPE_CONF_CHECK_I(pixel_multiplier);
>  	PIPE_CONF_CHECK_I(has_hdmi_sink);
>  	if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
> -	    IS_VALLEYVIEW(dev))
> +	    IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))

!HAS_DDI would seem to cover all of it.

>  		PIPE_CONF_CHECK_I(limited_color_range);
>  	PIPE_CONF_CHECK_I(has_infoframe);
>  
> @@ -14378,7 +14381,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>  
>  		if (I915_READ(PCH_DP_D) & DP_DETECTED)
>  			intel_dp_init(dev, PCH_DP_D, PORT_D);
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		/*
>  		 * The DP_DETECTED bit is the latched state of the DDC
>  		 * SDA pin at boot. However since eDP doesn't require DDC
> @@ -14527,7 +14530,7 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
>  		 *  pixels and 32K bytes."
>  		 */
>  		 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
> -	} else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
> +	} else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {

HAS_PCH_SPLIT() would actually cover all of this.

>  		return 32*1024;
>  	} else if (gen >= 4) {
>  		if (fb_modifier == I915_FORMAT_MOD_X_TILED)
> @@ -14631,7 +14634,8 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  		}
>  		break;
>  	case DRM_FORMAT_ABGR8888:
> -		if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
> +		if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> +		    INTEL_INFO(dev)->gen < 9) {
>  			DRM_DEBUG("unsupported pixel format: %s\n",
>  				  drm_get_format_name(mode_cmd->pixel_format));
>  			return -EINVAL;
> @@ -14647,7 +14651,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  		}
>  		break;
>  	case DRM_FORMAT_ABGR2101010:
> -		if (!IS_VALLEYVIEW(dev)) {
> +		if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>  			DRM_DEBUG("unsupported pixel format: %s\n",
>  				  drm_get_format_name(mode_cmd->pixel_format));
>  			return -EINVAL;
> @@ -14775,7 +14779,7 @@ static void intel_init_display(struct drm_device *dev)
>  		dev_priv->display.crtc_disable = ironlake_crtc_disable;
>  		dev_priv->display.update_primary_plane =
>  			ironlake_update_primary_plane;
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
>  		dev_priv->display.get_initial_plane_config =
>  			i9xx_get_initial_plane_config;
> @@ -14808,7 +14812,7 @@ static void intel_init_display(struct drm_device *dev)
>  	else if (IS_HASWELL(dev))
>  		dev_priv->display.get_display_clock_speed =
>  			haswell_get_display_clock_speed;
> -	else if (IS_VALLEYVIEW(dev))
> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		dev_priv->display.get_display_clock_speed =
>  			valleyview_get_display_clock_speed;
>  	else if (IS_GEN5(dev))
> @@ -14866,7 +14870,7 @@ static void intel_init_display(struct drm_device *dev)
>  			dev_priv->display.modeset_calc_cdclk =
>  				broadwell_modeset_calc_cdclk;
>  		}
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		dev_priv->display.modeset_commit_cdclk =
>  			valleyview_modeset_commit_cdclk;
>  		dev_priv->display.modeset_calc_cdclk =
> @@ -15640,7 +15644,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
>  		pll->on = false;
>  	}
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		vlv_wm_get_hw_state(dev);
>  	else if (IS_GEN9(dev))
>  		skl_wm_get_hw_state(dev);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f335c92..e36f741 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -517,7 +517,7 @@ void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
>  	struct drm_device *dev = dev_priv->dev;
>  	struct intel_encoder *encoder;
>  
> -	if (WARN_ON(!IS_VALLEYVIEW(dev)))
> +	if (WARN_ON(!(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))))

!VLV && !CHV

>  		return;
>  
>  	/*
> @@ -582,7 +582,7 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
>  
>  	pps_lock(intel_dp);
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
>  		i915_reg_t pp_ctrl_reg, pp_div_reg;
>  		u32 pp_div;
> @@ -610,7 +610,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
>  
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
> -	if (IS_VALLEYVIEW(dev) &&
> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>  	    intel_dp->pps_pipe == INVALID_PIPE)
>  		return false;
>  
> @@ -624,7 +624,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>  
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
> -	if (IS_VALLEYVIEW(dev) &&
> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>  	    intel_dp->pps_pipe == INVALID_PIPE)
>  		return false;
>  
> @@ -1723,7 +1723,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
>  		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
>  	} else {
>  		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
> -		    crtc->config->limited_color_range)
> +		    !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)

Could actually replace all that with IS_G4X

>  			intel_dp->DP |= DP_COLOR_RANGE_16_235;
>  
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> @@ -2418,7 +2418,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
>  	pipe_config->base.adjusted_mode.flags |= flags;
>  
>  	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
> -	    tmp & DP_COLOR_RANGE_16_235)
> +	    !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)

ditto

>  		pipe_config->limited_color_range = true;
>  
>  	pipe_config->has_dp_encoder = true;
> @@ -2694,7 +2694,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
>  
>  	pps_lock(intel_dp);
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		vlv_init_panel_power_sequencer(intel_dp);
>  
>  	/*
> @@ -2728,7 +2728,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
>  
>  	pps_unlock(intel_dp);
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		unsigned int lane_mask = 0x0;
>  
>  		if (IS_CHERRYVIEW(dev))
> @@ -3218,7 +3218,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>  		if (dev_priv->edp_low_vswing && port == PORT_A)
>  			return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> -	} else if (IS_VALLEYVIEW(dev))
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  	else if (IS_GEN7(dev) && port == PORT_A)
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> @@ -3259,7 +3259,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  		default:
>  			return DP_TRAIN_PRE_EMPH_LEVEL_0;
>  		}
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>  		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>  			return DP_TRAIN_PRE_EMPH_LEVEL_3;
> @@ -4539,7 +4539,7 @@ bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
>  		return cpt_digital_port_connected(dev_priv, port);
>  	else if (IS_BROXTON(dev_priv))
>  		return bxt_digital_port_connected(dev_priv, port);
> -	else if (IS_VALLEYVIEW(dev_priv))
> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		return vlv_digital_port_connected(dev_priv, port);
>  	else
>  		return g4x_digital_port_connected(dev_priv, port);
> @@ -4933,7 +4933,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
>  	 * Read out the current power sequencer assignment,
>  	 * in case the BIOS did something with it.
>  	 */
> -	if (IS_VALLEYVIEW(encoder->dev))
> +	if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
>  		vlv_initial_power_sequencer_setup(intel_dp);
>  
>  	intel_edp_panel_vdd_sanitize(intel_dp);
> @@ -5293,7 +5293,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>  
>  	/* Haswell doesn't have any port selection bits for the panel
>  	 * power sequencer any more. */
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		port_sel = PANEL_PORT_SELECT_VLV(port);
>  	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
>  		if (port == PORT_A)
> @@ -5405,12 +5405,12 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>  
>  		val = I915_READ(reg);
>  		if (index > DRRS_HIGH_RR) {
> -			if (IS_VALLEYVIEW(dev))
> +			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
>  			else
>  				val |= PIPECONF_EDP_RR_MODE_SWITCH;
>  		} else {
> -			if (IS_VALLEYVIEW(dev))
> +			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
>  			else
>  				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
> @@ -5777,7 +5777,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
>  	}
>  	mutex_unlock(&dev->mode_config.mutex);
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
>  		register_reboot_notifier(&intel_dp->edp_notifier);
>  
> @@ -5825,7 +5825,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  	/* intel_dp vfuncs */
>  	if (INTEL_INFO(dev)->gen >= 9)
>  		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
> -	else if (IS_VALLEYVIEW(dev))
> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
>  	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
> @@ -5860,8 +5860,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  		intel_encoder->type = INTEL_OUTPUT_EDP;
>  
>  	/* eDP only on port B and/or C on vlv/chv */
> -	if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
> -		    port != PORT_B && port != PORT_C))
> +	if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> +		    is_edp(intel_dp) && port != PORT_B && port != PORT_C))
>  		return false;
>  
>  	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
> @@ -5912,7 +5912,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  	if (is_edp(intel_dp)) {
>  		pps_lock(intel_dp);
>  		intel_dp_init_panel_power_timestamps(intel_dp);
> -		if (IS_VALLEYVIEW(dev))
> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  			vlv_initial_power_sequencer_setup(intel_dp);
>  		else
>  			intel_dp_init_panel_power_sequencer(dev, intel_dp);
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 230957f..cada737 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -369,7 +369,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
>  {
>  	struct drm_device *dev = encoder->base.dev;
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		vlv_dsi_device_ready(encoder);
>  	else if (IS_BROXTON(dev))
>  		bxt_dsi_device_ready(encoder);
> @@ -487,7 +487,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
>  
>  	msleep(intel_dsi->panel_on_delay);
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		/*
>  		 * Disable DPOunit clock gating, can stall pipe
>  		 * and we need DPLL REFA always enabled
> @@ -684,8 +684,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>  		 * Enable bit does not get set. To check whether DSI Port C
>  		 * was enabled in BIOS, check the Pipe B enable bit
>  		 */
> -		if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> -		    (port == PORT_C))
> +		if (IS_VALLEYVIEW(dev) && (port == PORT_C))

Could throw away the extra parens around the == while it at.

>  			dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
>  							PIPECONF_ENABLE;
>  
> @@ -716,7 +715,8 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
>  
>  	if (IS_BROXTON(encoder->base.dev))
>  		pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
> -	else if (IS_VALLEYVIEW(encoder->base.dev))
> +	else if (IS_VALLEYVIEW(encoder->base.dev) ||
> +		 IS_CHERRYVIEW(encoder->base.dev))
>  		pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
>  
>  	if (!pclk)
> @@ -869,7 +869,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
>  	}
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {
> -		if (IS_VALLEYVIEW(dev)) {
> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  			/*
>  			 * escape clock divider, 20MHz, shared for A and C.
>  			 * device ready must be off when doing this! txclkesc?
> @@ -1129,7 +1129,7 @@ void intel_dsi_init(struct drm_device *dev)
>  	if (!dev_priv->vbt.has_mipi)
>  		return;
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
>  	} else {
>  		DRM_ERROR("Unsupported Mipi device to reg base");
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index cb3cf39..fbd2b51 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -561,7 +561,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder)
>  {
>  	struct drm_device *dev = encoder->base.dev;
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		vlv_enable_dsi_pll(encoder);
>  	else if (IS_BROXTON(dev))
>  		bxt_enable_dsi_pll(encoder);
> @@ -571,7 +571,7 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
>  {
>  	struct drm_device *dev = encoder->base.dev;
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		vlv_disable_dsi_pll(encoder);
>  	else if (IS_BROXTON(dev))
>  		bxt_disable_dsi_pll(encoder);
> @@ -599,6 +599,6 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>  
>  	if (IS_BROXTON(dev))
>  		bxt_dsi_reset_clocks(encoder, port);
> -	else if (IS_VALLEYVIEW(dev))
> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		vlv_dsi_reset_clocks(encoder, port);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index c3978ba..be7fab9 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -638,7 +638,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
>  
>  	if (HAS_DDI(dev_priv))
>  		reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
> -	else if (IS_VALLEYVIEW(dev_priv))
> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
>  	else if (HAS_PCH_SPLIT(dev_priv->dev))
>  		reg = TVIDEO_DIP_GCP(crtc->pipe);
> @@ -2100,7 +2100,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
>  		BUG();
>  	}
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		intel_hdmi->write_infoframe = vlv_write_infoframe;
>  		intel_hdmi->set_infoframes = vlv_set_infoframes;
>  		intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
> diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
> index b177857..a294a3c 100644
> --- a/drivers/gpu/drm/i915/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/intel_hotplug.c
> @@ -407,7 +407,7 @@ void intel_hpd_irq_handler(struct drm_device *dev,
>  			 * hotplug bits itself. So only WARN about unexpected
>  			 * interrupts on saner platforms.
>  			 */
> -			WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
> +			WARN_ONCE(!HAS_GMCH_DISPLAY(dev),
>  				  "Received HPD interrupt on pin %d although disabled\n", i);
>  			continue;
>  		}
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index e26e22a..25254b5 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -636,7 +636,7 @@ int intel_setup_gmbus(struct drm_device *dev)
>  	if (HAS_PCH_NOP(dev))
>  		return 0;
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
>  	else if (!HAS_GMCH_DISPLAY(dev_priv))
>  		dev_priv->gpio_mmio_base =
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index ae808b6..72183a0 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1784,7 +1784,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
>  		panel->backlight.set = pch_set_backlight;
>  		panel->backlight.get = pch_get_backlight;
>  		panel->backlight.hz_to_pwm = pch_hz_to_pwm;
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		if (dev_priv->vbt.has_mipi) {
>  			panel->backlight.setup = pwm_setup_backlight;
>  			panel->backlight.enable = pwm_enable_backlight;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ee05ce8..fe56181 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -291,7 +291,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
>  	struct drm_device *dev = dev_priv->dev;
>  	u32 val;
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
>  		POSTING_READ(FW_BLC_SELF_VLV);
>  		dev_priv->wm.vlv.cxsr = enable;
> @@ -4405,7 +4405,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  	if (dev_priv->rps.enabled) {
> -		if (IS_VALLEYVIEW(dev))
> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  			vlv_set_rps_idle(dev_priv);
>  		else
>  			gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
> @@ -4458,7 +4458,7 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
>  
>  void intel_set_rps(struct drm_device *dev, u8 val)
>  {
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		valleyview_set_rps(dev, val);
>  	else
>  		gen6_set_rps(dev, val);
> @@ -4502,7 +4502,7 @@ static void valleyview_disable_rps(struct drm_device *dev)
>  
>  static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
>  {
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
>  			mode = GEN6_RC_CTL_RC6_ENABLE;
>  		else
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index b6609e6..1778a7d 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -332,8 +332,8 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>  		return false;
>  	}
>  
> -	if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||
> -				    (dig_port->port != PORT_A))) {
> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> +	    ((dev_priv->vbt.psr.full_link) || (dig_port->port != PORT_A))) {

Could remove some of the usless parens here too.

>  		DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n");
>  		return false;
>  	}
> @@ -650,7 +650,7 @@ void intel_psr_single_frame_update(struct drm_device *dev,
>  	 * Single frame update is already supported on BDW+ but it requires
>  	 * many W/A and it isn't really needed.
>  	 */
> -	if (!IS_VALLEYVIEW(dev))
> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
>  		return;
>  
>  	mutex_lock(&dev_priv->psr.lock);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 2b96f33..f8bf622 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -951,7 +951,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
>  	if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
>  		return -EINVAL;
>  
> -	if (IS_VALLEYVIEW(dev) &&
> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>  	    set->flags & I915_SET_COLORKEY_DESTINATION)
>  		return -EINVAL;
>  
> @@ -1086,7 +1086,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
>  			intel_plane->max_downscale = 1;
>  		}
>  
> -		if (IS_VALLEYVIEW(dev)) {
> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  			intel_plane->update_plane = vlv_update_plane;
>  			intel_plane->disable_plane = vlv_disable_plane;
>  
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index c2358ba..fcf04fe 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1115,7 +1115,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
>  		d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
>  	}
>  
> -	if (IS_VALLEYVIEW(dev_priv))
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		d->reg_post = FORCEWAKE_ACK_VLV;
>  	else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
>  		d->reg_post = ECOBUS;
> @@ -1148,7 +1148,7 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
>  			       FORCEWAKE_ACK_BLITTER_GEN9);
>  		fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
>  			       FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
>  		if (!IS_CHERRYVIEW(dev))
>  			dev_priv->uncore.funcs.force_wake_put =
> -- 
> 2.6.3

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/5] drm/i915: Separate cherryview from valleyview

[Boyer, Wayne]

Thanks Ville.  I'll send one more update with some of the changes.  I'll
leave the others for a different patch.  Details below.

Wayne
 
On 12/9/15, 9:10 AM, "Ville Syrjälä" <ville.syrjala@linux.intel.com> wrote:


>On Tue, Dec 08, 2015 at 11:46:53AM -0800, Wayne Boyer wrote:
>> The cherryview device shares many characteristics with the valleyview
>> device.  When support was added to the driver for cherryview, the
>> corresponding device info structure included .is_valleyview = 1.
>> This is not correct and leads to some confusion.
>> 
>> This patch changes .is_valleyview to .is_cherryview in the cherryview
>> device info structure and simplifies the IS_CHERRYVIEW macro.
>> Then where appropriate, instances of IS_VALLEYVIEW are replaced with
>> IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent.
>> 
>> v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro.
>>     Also add followup patches to fix issues discovered during the first
>>     review. (Ville)
>> v3: Fix some style issues and one gen check. Remove CRT related changes
>>     as CRT is not supported on CHV. (Imre, Ville)
>> 
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_debugfs.c     | 68
>>++++++++++++++++-----------------
>>  drivers/gpu/drm/i915/i915_dma.c         |  8 ++--
>>  drivers/gpu/drm/i915/i915_drv.c         | 10 ++---
>>  drivers/gpu/drm/i915/i915_drv.h         | 16 +++++---
>>  drivers/gpu/drm/i915/i915_gem.c         |  4 +-
>>  drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
>>  drivers/gpu/drm/i915/i915_irq.c         |  8 ++--
>>  drivers/gpu/drm/i915/i915_suspend.c     |  4 +-
>>  drivers/gpu/drm/i915/i915_sysfs.c       | 10 ++---
>>  drivers/gpu/drm/i915/intel_audio.c      |  7 ++--
>>  drivers/gpu/drm/i915/intel_display.c    | 54 ++++++++++++++------------
>>  drivers/gpu/drm/i915/intel_dp.c         | 40 +++++++++----------
>>  drivers/gpu/drm/i915/intel_dsi.c        | 14 +++----
>>  drivers/gpu/drm/i915/intel_dsi_pll.c    |  6 +--
>>  drivers/gpu/drm/i915/intel_hdmi.c       |  4 +-
>>  drivers/gpu/drm/i915/intel_hotplug.c    |  2 +-
>>  drivers/gpu/drm/i915/intel_i2c.c        |  2 +-
>>  drivers/gpu/drm/i915/intel_panel.c      |  2 +-
>>  drivers/gpu/drm/i915/intel_pm.c         |  8 ++--
>>  drivers/gpu/drm/i915/intel_psr.c        |  6 +--
>>  drivers/gpu/drm/i915/intel_sprite.c     |  4 +-
>>  drivers/gpu/drm/i915/intel_uncore.c     |  4 +-
>
>Looks like you missed:
>sanitize_enable_ppgtt() in i915_gem_gtt.c
>Well, it just has a pointless !CHV in left in there.

Fixed.

>
>I didn't find anything wrong in there anymore. Just some minor
>simplifications and bikesheds that could be done as part of this
>patch, or maybe some of them could be followups. See below.
>
>>  22 files changed, 146 insertions(+), 137 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>>b/drivers/gpu/drm/i915/i915_debugfs.c
>> index a8721fc..fff31253 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1142,8 +1142,34 @@ static int i915_frequency_info(struct seq_file
>>*m, void *unused)
>>  			   MEMSTAT_VID_SHIFT);
>>  		seq_printf(m, "Current P-state: %d\n",
>>  			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
>> -	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
>> -		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>> +		u32 freq_sts;
>> +
>> +		mutex_lock(&dev_priv->rps.hw_lock);
>> +		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>> +		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
>> +		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
>> +
>> +		seq_printf(m, "actual GPU freq: %d MHz\n",
>> +			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
>> +
>> +		seq_printf(m, "current GPU freq: %d MHz\n",
>> +			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
>> +
>> +		seq_printf(m, "max GPU freq: %d MHz\n",
>> +			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
>> +
>> +		seq_printf(m, "min GPU freq: %d MHz\n",
>> +			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
>> +
>> +		seq_printf(m, "idle GPU freq: %d MHz\n",
>> +			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
>> +
>> +		seq_printf(m,
>> +			   "efficient (RPe) frequency: %d MHz\n",
>> +			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
>> +		mutex_unlock(&dev_priv->rps.hw_lock);
>> +	} else if (INTEL_INFO(dev)->gen >= 6) {
>>  		u32 rp_state_limits;
>>  		u32 gt_perf_status;
>>  		u32 rp_state_cap;
>> @@ -1284,33 +1310,6 @@ static int i915_frequency_info(struct seq_file
>>*m, void *unused)
>>  		seq_printf(m,
>>  			   "efficient (RPe) frequency: %d MHz\n",
>>  			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> -		u32 freq_sts;
>> -
>> -		mutex_lock(&dev_priv->rps.hw_lock);
>> -		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>> -		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
>> -		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
>> -
>> -		seq_printf(m, "actual GPU freq: %d MHz\n",
>> -			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
>> -
>> -		seq_printf(m, "current GPU freq: %d MHz\n",
>> -			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
>> -
>> -		seq_printf(m, "max GPU freq: %d MHz\n",
>> -			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
>> -
>> -		seq_printf(m, "min GPU freq: %d MHz\n",
>> -			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
>> -
>> -		seq_printf(m, "idle GPU freq: %d MHz\n",
>> -			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
>> -
>> -		seq_printf(m,
>> -			   "efficient (RPe) frequency: %d MHz\n",
>> -			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
>> -		mutex_unlock(&dev_priv->rps.hw_lock);
>>  	} else {
>>  		seq_puts(m, "no P-state info available\n");
>>  	}
>> @@ -1602,7 +1601,7 @@ static int i915_drpc_info(struct seq_file *m,
>>void *unused)
>>  	struct drm_info_node *node = m->private;
>>  	struct drm_device *dev = node->minor->dev;
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		return vlv_drpc_info(m);
>>  	else if (INTEL_INFO(dev)->gen >= 6)
>>  		return gen6_drpc_info(m);
>> @@ -1743,7 +1742,7 @@ static int i915_sr_status(struct seq_file *m,
>>void *unused)
>>  		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
>>  	else if (IS_PINEVIEW(dev))
>>  		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
>> -	else if (IS_VALLEYVIEW(dev))
>> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>>  
>>  	intel_runtime_pm_put(dev_priv);
>> @@ -3983,7 +3982,7 @@ static int pipe_crc_set_source(struct drm_device
>>*dev, enum pipe pipe,
>>  		ret = i8xx_pipe_crc_ctl_reg(&source, &val);
>>  	else if (INTEL_INFO(dev)->gen < 5)
>>  		ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
>> -	else if (IS_VALLEYVIEW(dev))
>> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
>>  	else if (IS_GEN5(dev) || IS_GEN6(dev))
>>  		ret = ilk_pipe_crc_ctl_reg(&source, &val);
>> @@ -4052,7 +4051,7 @@ static int pipe_crc_set_source(struct drm_device
>>*dev, enum pipe pipe,
>>  
>>  		if (IS_G4X(dev))
>>  			g4x_undo_pipe_scramble_reset(dev, pipe);
>> -		else if (IS_VALLEYVIEW(dev))
>> +		else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  			vlv_undo_pipe_scramble_reset(dev, pipe);
>>  		else if (IS_HASWELL(dev) && pipe == PIPE_A)
>>  			hsw_trans_edp_pipe_A_crc_wa(dev, false);
>> @@ -4442,7 +4441,8 @@ static void wm_latency_show(struct seq_file *m,
>>const uint16_t wm[8])
>>  		 * - WM1+ latency values in 0.5us units
>>  		 * - latencies are in us on gen9/vlv/chv
>>  		 */
>> -		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
>> +		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
>> +		    IS_CHERRYVIEW(dev))
>>  			latency *= 10;
>>  		else if (level > 0)
>>  			latency *= 5;
>> diff --git a/drivers/gpu/drm/i915/i915_dma.c
>>b/drivers/gpu/drm/i915/i915_dma.c
>> index a81c766..7f08ba8 100644
>> --- a/drivers/gpu/drm/i915/i915_dma.c
>> +++ b/drivers/gpu/drm/i915/i915_dma.c
>> @@ -256,7 +256,7 @@ intel_setup_mchbar(struct drm_device *dev)
>>  	u32 temp;
>>  	bool enabled;
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		return;
>>  
>>  	dev_priv->mchbar_need_disable = false;
>> @@ -779,7 +779,7 @@ static void intel_device_info_runtime_init(struct
>>drm_device *dev)
>>  		info->num_sprites[PIPE_A] = 2;
>>  		info->num_sprites[PIPE_B] = 2;
>>  		info->num_sprites[PIPE_C] = 1;
>> -	} else if (IS_VALLEYVIEW(dev))
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		for_each_pipe(dev_priv, pipe)
>>  			info->num_sprites[pipe] = 2;
>>  	else
>> @@ -791,7 +791,7 @@ static void intel_device_info_runtime_init(struct
>>drm_device *dev)
>>  		info->num_pipes = 0;
>>  	} else if (info->num_pipes > 0 &&
>>  		   (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
>> -		   !IS_VALLEYVIEW(dev)) {
>> +		   !(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) {
>>  		u32 fuse_strap = I915_READ(FUSE_STRAP);
>>  		u32 sfuse_strap = I915_READ(SFUSE_STRAP);
>>  
>> @@ -836,7 +836,7 @@ static void intel_device_info_runtime_init(struct
>>drm_device *dev)
>>  
>>  static void intel_init_dpio(struct drm_i915_private *dev_priv)
>>  {
>> -	if (!IS_VALLEYVIEW(dev_priv))
>> +	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
>>  		return;
>
>Here we could drop this early check and just do
>
>  if (IS_CHV) {
>  	...
>- } else {
>+ } else if (IS_VLV) {
> 	...
>  }

Fixed.

>
>>  
>>  	/*
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>>b/drivers/gpu/drm/i915/i915_drv.c
>> index e6935f1..841c3c4 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -311,7 +311,7 @@ static const struct intel_device_info
>>intel_cherryview_info = {
>>  	.gen = 8, .num_pipes = 3,
>>  	.need_gfx_hws = 1, .has_hotplug = 1,
>>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>> -	.is_valleyview = 1,
>> +	.is_cherryview = 1,
>>  	.display_mmio_offset = VLV_DISPLAY_BASE,
>>  	GEN_CHV_PIPEOFFSETS,
>>  	CURSOR_OFFSETS,
>> @@ -802,7 +802,7 @@ static int i915_drm_resume_early(struct drm_device
>>*dev)
>>  
>>  	pci_set_master(dev->pdev);
>>  
>> -	if (IS_VALLEYVIEW(dev_priv))
>> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		ret = vlv_resume_prepare(dev_priv, false);
>>  	if (ret)
>>  		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
>> @@ -1532,7 +1532,7 @@ static int intel_runtime_resume(struct device
>>*device)
>>  		ret = bxt_resume_prepare(dev_priv);
>>  	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>>  		hsw_disable_pc8(dev_priv);
>> -	else if (IS_VALLEYVIEW(dev_priv))
>> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		ret = vlv_resume_prepare(dev_priv, true);
>>  
>>  	/*
>> @@ -1549,7 +1549,7 @@ static int intel_runtime_resume(struct device
>>*device)
>>  	 * power well, so hpd is reinitialized from there. For
>>  	 * everyone else do it here.
>>  	 */
>> -	if (!IS_VALLEYVIEW(dev_priv))
>> +	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
>
>'!VLV && !CHV' again perhaps?

Fixed.

>
>>  		intel_hpd_init(dev_priv);
>>  
>>  	intel_enable_gt_powersave(dev);
>> @@ -1574,7 +1574,7 @@ static int intel_suspend_complete(struct
>>drm_i915_private *dev_priv)
>>  		ret = bxt_suspend_complete(dev_priv);
>>  	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>>  		ret = hsw_suspend_complete(dev_priv);
>> -	else if (IS_VALLEYVIEW(dev_priv))
>> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		ret = vlv_suspend_complete(dev_priv);
>>  	else
>>  		ret = 0;
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>b/drivers/gpu/drm/i915/i915_drv.h
>> index f1a8a53..3899f23 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -763,6 +763,7 @@ struct intel_csr {
>>  	func(is_crestline) sep \
>>  	func(is_ivybridge) sep \
>>  	func(is_valleyview) sep \
>> +	func(is_cherryview) sep \
>>  	func(is_haswell) sep \
>>  	func(is_skylake) sep \
>>  	func(is_broxton) sep \
>> @@ -2455,9 +2456,9 @@ struct drm_i915_cmd_table {
>>  				 INTEL_DEVID(dev) == 0x0152 || \
>>  				 INTEL_DEVID(dev) == 0x015a)
>>  #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
>> -#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview &&
>>IS_GEN8(dev))
>> +#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
>>  #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
>> -#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview &&
>>IS_GEN8(dev))
>> +#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_cherryview &&
>>IS_GEN8(dev))
>>  #define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
>>  #define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
>>  #define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
>> @@ -2584,7 +2585,8 @@ struct drm_i915_cmd_table {
>>  				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
>>  #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
>>  				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
>> -				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
>> +				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
>
>BDW||CHV could be replaced with IS_GEN8

Change in a separate patch.

>
>> +				 IS_KABYLAKE(dev))
>>  #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
>>  #define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
>>  
>> @@ -2597,7 +2599,8 @@ struct drm_i915_cmd_table {
>>  				    INTEL_INFO(dev)->gen >= 8)
>>  
>>  #define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
>> -				 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
>> +				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
>> +				 !IS_BROXTON(dev))
>>  
>>  #define INTEL_PCH_DEVICE_ID_MASK		0xff00
>>  #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
>> @@ -2620,7 +2623,8 @@ struct drm_i915_cmd_table {
>>  #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
>>  #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
>>  
>> -#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 ||
>>IS_VALLEYVIEW(dev))
>> +#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
>> +			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  
>>  /* DPF == dynamic parity feature */
>>  #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
>> @@ -3511,7 +3515,7 @@ __raw_write(64, q)
>>  
>>  static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
>>  {
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		return VLV_VGACNTRL;
>>  	else if (INTEL_INFO(dev)->gen >= 5)
>>  		return CPU_VGACNTRL;
>> diff --git a/drivers/gpu/drm/i915/i915_gem.c
>>b/drivers/gpu/drm/i915/i915_gem.c
>> index dfaf25b..e96e496 100644
>> --- a/drivers/gpu/drm/i915/i915_gem.c
>> +++ b/drivers/gpu/drm/i915/i915_gem.c
>> @@ -4838,7 +4838,7 @@ int i915_gem_init(struct drm_device *dev)
>>  
>>  	mutex_lock(&dev->struct_mutex);
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		/* VLVA0 (potential hack), BIOS isn't actually waking us */
>>  		I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
>>  		if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
>> @@ -4963,7 +4963,7 @@ i915_gem_load(struct drm_device *dev)
>>  
>>  	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
>>  
>> -	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
>> +	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) &&
>>!IS_CHERRYVIEW(dev))
>>  		dev_priv->num_fence_regs = 32;
>>  	else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev)
>>|| IS_G33(dev))
>>  		dev_priv->num_fence_regs = 16;
>> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
>>b/drivers/gpu/drm/i915/i915_gem_context.c
>> index 43761c5..4b1161d 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
>> @@ -190,7 +190,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev,
>>size_t size)
>>  	 * would make the object snooped which might have a
>>  	 * negative performance impact.
>>  	 */
>> -	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) {
>> +	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) &&
>>!IS_CHERRYVIEW(dev)) {
>>  		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
>>  		/* Failure shouldn't ever happen this early */
>>  		if (WARN_ON(ret)) {
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c
>>b/drivers/gpu/drm/i915/i915_irq.c
>> index e88d692..23a0aad 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -581,7 +581,7 @@ i915_enable_pipestat(struct drm_i915_private
>>*dev_priv, enum pipe pipe,
>>  {
>>  	u32 enable_mask;
>>  
>> -	if (IS_VALLEYVIEW(dev_priv->dev))
>> +	if (IS_VALLEYVIEW(dev_priv->dev) || IS_CHERRYVIEW(dev_priv->dev))
>
>Can drop the ->dev while at it.

Fixed.

>
>>  		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
>>  							   status_mask);
>>  	else
>> @@ -595,7 +595,7 @@ i915_disable_pipestat(struct drm_i915_private
>>*dev_priv, enum pipe pipe,
>>  {
>>  	u32 enable_mask;
>>  
>> -	if (IS_VALLEYVIEW(dev_priv->dev))
>> +	if (IS_VALLEYVIEW(dev_priv->dev) || IS_CHERRYVIEW(dev_priv->dev))
>
>Ditto

Fixed.

>
>>  		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
>>  							   status_mask);
>>  	else
>> @@ -1723,7 +1723,7 @@ static void i9xx_hpd_irq_handler(struct
>>drm_device *dev)
>>  	 */
>>  	POSTING_READ(PORT_HOTPLUG_STAT);
>>  
>> -	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
>> +	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
>>  
>>  		if (hotplug_trigger) {
>> @@ -4412,7 +4412,7 @@ void intel_irq_init(struct drm_i915_private
>>*dev_priv)
>>  	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
>>  
>>  	/* Let's track the enabled rps events */
>> -	if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
>> +	if (IS_VALLEYVIEW(dev_priv))
>>  		/* WaGsvRC0ResidencyMethod:vlv */
>>  		dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED |
>>GEN6_PM_RP_UP_EI_EXPIRED;
>>  	else
>> diff --git a/drivers/gpu/drm/i915/i915_suspend.c
>>b/drivers/gpu/drm/i915/i915_suspend.c
>> index 2d91821..a2aa09c 100644
>> --- a/drivers/gpu/drm/i915/i915_suspend.c
>> +++ b/drivers/gpu/drm/i915/i915_suspend.c
>> @@ -49,7 +49,7 @@ static void i915_save_display(struct drm_device *dev)
>>  		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
>>  		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
>>  		dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
>> -	} else if (!IS_VALLEYVIEW(dev)) {
>> +	} else if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>>  		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
>>  		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
>>  		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
>> @@ -84,7 +84,7 @@ static void i915_restore_display(struct drm_device
>>*dev)
>>  		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
>>  		I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
>>  		I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
>> -	} else if (!IS_VALLEYVIEW(dev)) {
>> +	} else if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>>  		I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
>>  		I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
>>  		I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
>> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
>>b/drivers/gpu/drm/i915/i915_sysfs.c
>> index f929c61..86c3020 100644
>> --- a/drivers/gpu/drm/i915/i915_sysfs.c
>> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
>> @@ -49,7 +49,7 @@ static u32 calc_residency(struct drm_device *dev,
>>  	intel_runtime_pm_get(dev_priv);
>>  
>>  	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		units = 1;
>>  		div = dev_priv->czclk_freq;
>>  
>> @@ -284,7 +284,7 @@ static ssize_t gt_act_freq_mhz_show(struct device
>>*kdev,
>>  	intel_runtime_pm_get(dev_priv);
>>  
>>  	mutex_lock(&dev_priv->rps.hw_lock);
>> -	if (IS_VALLEYVIEW(dev_priv->dev)) {
>> +	if (IS_VALLEYVIEW(dev_priv->dev) || IS_CHERRYVIEW(dev_priv->dev)) {
>
>Can drop the ->dev again

Fixed.

>
>>  		u32 freq;
>>  		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>>  		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
>> @@ -598,7 +598,7 @@ void i915_setup_sysfs(struct drm_device *dev)
>>  		if (ret)
>>  			DRM_ERROR("RC6p residency sysfs setup failed\n");
>>  	}
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		ret = sysfs_merge_group(&dev->primary->kdev->kobj,
>>  					&media_rc6_attr_group);
>>  		if (ret)
>> @@ -619,7 +619,7 @@ void i915_setup_sysfs(struct drm_device *dev)
>>  	}
>>  
>>  	ret = 0;
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs);
>>  	else if (INTEL_INFO(dev)->gen >= 6)
>>  		ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs);
>> @@ -635,7 +635,7 @@ void i915_setup_sysfs(struct drm_device *dev)
>>  void i915_teardown_sysfs(struct drm_device *dev)
>>  {
>>  	sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr);
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs);
>>  	else
>>  		sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs);
>> diff --git a/drivers/gpu/drm/i915/intel_audio.c
>>b/drivers/gpu/drm/i915/intel_audio.c
>> index 9aa83e7..06fffae 100644
>> --- a/drivers/gpu/drm/i915/intel_audio.c
>> +++ b/drivers/gpu/drm/i915/intel_audio.c
>> @@ -375,7 +375,7 @@ static void ilk_audio_codec_disable(struct
>>intel_encoder *encoder)
>>  	if (HAS_PCH_IBX(dev_priv->dev)) {
>>  		aud_config = IBX_AUD_CFG(pipe);
>>  		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
>> -	} else if (IS_VALLEYVIEW(dev_priv)) {
>> +	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>>  		aud_config = VLV_AUD_CFG(pipe);
>>  		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
>>  	} else {
>> @@ -435,7 +435,8 @@ static void ilk_audio_codec_enable(struct
>>drm_connector *connector,
>>  		aud_config = IBX_AUD_CFG(pipe);
>>  		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
>>  		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
>> -	} else if (IS_VALLEYVIEW(connector->dev)) {
>> +	} else if (IS_VALLEYVIEW(connector->dev) ||
>> +		   IS_CHERRYVIEW(connector->dev)) {
>>  		hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
>>  		aud_config = VLV_AUD_CFG(pipe);
>>  		aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
>> @@ -559,7 +560,7 @@ void intel_init_audio(struct drm_device *dev)
>>  	if (IS_G4X(dev)) {
>>  		dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
>>  		dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
>>  		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
>>  	} else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>>b/drivers/gpu/drm/i915/intel_display.c
>> index b59a2d8..d3b643b 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -187,7 +187,7 @@ int intel_hrawclk(struct drm_device *dev)
>>  	uint32_t clkcfg;
>>  
>>  	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		return 200;
>>  
>>  	clkcfg = I915_READ(CLKCFG);
>> @@ -215,7 +215,7 @@ int intel_hrawclk(struct drm_device *dev)
>>  
>>  static void intel_update_czclk(struct drm_i915_private *dev_priv)
>>  {
>> -	if (!IS_VALLEYVIEW(dev_priv))
>> +	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
>>  		return;
>>  
>>  	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
>> @@ -716,11 +716,12 @@ static bool intel_PLL_is_valid(struct drm_device
>>*dev,
>>  	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
>>  		INTELPllInvalid("m1 out of range\n");
>>  
>> -	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
>> +	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
>> +	    !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
>>  		if (clock->m1 <= clock->m2)
>>  			INTELPllInvalid("m1 <= m2\n");
>>  
>> -	if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
>> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
>>  		if (clock->p < limit->p.min || limit->p.max < clock->p)
>>  			INTELPllInvalid("p out of range\n");
>>  		if (clock->m < limit->m.min || limit->m.max < clock->m)
>> @@ -1305,7 +1306,7 @@ void assert_panel_unlocked(struct
>>drm_i915_private *dev_priv,
>>  		    I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
>>  			panel_pipe = PIPE_B;
>>  		/* XXX: else fix for eDP */
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		/* presumably write lock depends on pipe, not port select */
>>  		pp_reg = VLV_PIPE_PP_CONTROL(pipe);
>>  		panel_pipe = pipe;
>> @@ -1423,7 +1424,7 @@ static void assert_sprites_disabled(struct
>>drm_i915_private *dev_priv,
>>  			     "plane %d assertion failure, should be off on pipe %c but is
>>still active\n",
>>  			     sprite, pipe_name(pipe));
>>  		}
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		for_each_sprite(dev_priv, pipe, sprite) {
>>  			u32 val = I915_READ(SPCNTR(pipe, sprite));
>>  			I915_STATE_WARN(val & SP_ENABLE,
>> @@ -2319,7 +2320,7 @@ static unsigned int intel_linear_alignment(struct
>>drm_i915_private *dev_priv)
>>  	if (INTEL_INFO(dev_priv)->gen >= 9)
>>  		return 256 * 1024;
>>  	else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
>> -		 IS_VALLEYVIEW(dev_priv))
>> +		 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		return 128 * 1024;
>>  	else if (INTEL_INFO(dev_priv)->gen >= 4)
>>  		return 4 * 1024;
>> @@ -5455,7 +5456,7 @@ static void intel_update_cdclk(struct drm_device
>>*dev)
>>  	 * BSpec erroneously claims we should aim for 4MHz, but
>>  	 * in fact 1MHz is the correct frequency.
>>  	 */
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		/*
>>  		 * Program the gmbus_freq based on the cdclk frequency.
>>  		 * BSpec erroneously claims we should aim for 4MHz, but
>> @@ -7180,7 +7181,7 @@ static int i9xx_get_refclk(const struct
>>intel_crtc_state *crtc_state,
>>  
>>  	WARN_ON(!crtc_state->base.state);
>>  
>> -	if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
>>  		refclk = 100000;
>>  	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
>>  	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
>> @@ -7879,7 +7880,7 @@ static void i9xx_set_pipeconf(struct intel_crtc
>>*intel_crtc)
>>  		pipeconf |= PIPECONF_DOUBLE_WIDE;
>>  
>>  	/* only g4x and later have fancy bpc/dither controls */
>> -	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
>> +	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		/* Bspec claims that we can't use dithering for 30bpp pipes. */
>>  		if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
>>  			pipeconf |= PIPECONF_DITHER_EN |
>> @@ -7919,7 +7920,8 @@ static void i9xx_set_pipeconf(struct intel_crtc
>>*intel_crtc)
>>  	} else
>>  		pipeconf |= PIPECONF_PROGRESSIVE;
>>  
>> -	if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
>> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>> +	     intel_crtc->config->limited_color_range)
>>  		pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
>>  
>>  	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
>> @@ -8166,7 +8168,7 @@ static bool i9xx_get_pipe_config(struct
>>intel_crtc *crtc,
>>  	if (!(tmp & PIPECONF_ENABLE))
>>  		return false;
>>  
>> -	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
>> +	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		switch (tmp & PIPECONF_BPC_MASK) {
>>  		case PIPECONF_6BPC:
>>  			pipe_config->pipe_bpp = 18;
>> @@ -8182,7 +8184,8 @@ static bool i9xx_get_pipe_config(struct
>>intel_crtc *crtc,
>>  		}
>>  	}
>>  
>> -	if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
>> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>> +	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
>>  		pipe_config->limited_color_range = true;
>>  
>>  	if (INTEL_INFO(dev)->gen < 4)
>> @@ -8210,7 +8213,7 @@ static bool i9xx_get_pipe_config(struct
>>intel_crtc *crtc,
>>  		pipe_config->pixel_multiplier = 1;
>>  	}
>>  	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
>> -	if (!IS_VALLEYVIEW(dev)) {
>> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>>  		/*
>>  		 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
>>  		 * on 830. Filter it out here so that we don't
>> @@ -11537,7 +11540,7 @@ static int intel_crtc_page_flip(struct drm_crtc
>>*crtc,
>>  	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
>>  		work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		ring = &dev_priv->ring[BCS];
>>  		if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
>>  			/* vlv: DISPLAY_FLIP fails to change tiling */
>> @@ -12016,7 +12019,7 @@ compute_baseline_pipe_bpp(struct intel_crtc
>>*crtc,
>>  	struct drm_connector_state *connector_state;
>>  	int bpp, i;
>>  
>> -	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
>> +	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
>>  		bpp = 10*3;
>>  	else if (INTEL_INFO(dev)->gen >= 5)
>>  		bpp = 12*3;
>> @@ -12626,7 +12629,7 @@ intel_pipe_config_compare(struct drm_device
>>*dev,
>>  	PIPE_CONF_CHECK_I(pixel_multiplier);
>>  	PIPE_CONF_CHECK_I(has_hdmi_sink);
>>  	if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
>> -	    IS_VALLEYVIEW(dev))
>> +	    IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>
>!HAS_DDI would seem to cover all of it.

Change in a separate patch.


>
>>  		PIPE_CONF_CHECK_I(limited_color_range);
>>  	PIPE_CONF_CHECK_I(has_infoframe);
>>  
>> @@ -14378,7 +14381,7 @@ static void intel_setup_outputs(struct
>>drm_device *dev)
>>  
>>  		if (I915_READ(PCH_DP_D) & DP_DETECTED)
>>  			intel_dp_init(dev, PCH_DP_D, PORT_D);
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		/*
>>  		 * The DP_DETECTED bit is the latched state of the DDC
>>  		 * SDA pin at boot. However since eDP doesn't require DDC
>> @@ -14527,7 +14530,7 @@ u32 intel_fb_pitch_limit(struct drm_device
>>*dev, uint64_t fb_modifier,
>>  		 *  pixels and 32K bytes."
>>  		 */
>>  		 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
>> -	} else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
>> +	} else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>
>HAS_PCH_SPLIT() would actually cover all of this.

Change in a separate patch.


>
>>  		return 32*1024;
>>  	} else if (gen >= 4) {
>>  		if (fb_modifier == I915_FORMAT_MOD_X_TILED)
>> @@ -14631,7 +14634,8 @@ static int intel_framebuffer_init(struct
>>drm_device *dev,
>>  		}
>>  		break;
>>  	case DRM_FORMAT_ABGR8888:
>> -		if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
>> +		if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
>> +		    INTEL_INFO(dev)->gen < 9) {
>>  			DRM_DEBUG("unsupported pixel format: %s\n",
>>  				  drm_get_format_name(mode_cmd->pixel_format));
>>  			return -EINVAL;
>> @@ -14647,7 +14651,7 @@ static int intel_framebuffer_init(struct
>>drm_device *dev,
>>  		}
>>  		break;
>>  	case DRM_FORMAT_ABGR2101010:
>> -		if (!IS_VALLEYVIEW(dev)) {
>> +		if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>>  			DRM_DEBUG("unsupported pixel format: %s\n",
>>  				  drm_get_format_name(mode_cmd->pixel_format));
>>  			return -EINVAL;
>> @@ -14775,7 +14779,7 @@ static void intel_init_display(struct
>>drm_device *dev)
>>  		dev_priv->display.crtc_disable = ironlake_crtc_disable;
>>  		dev_priv->display.update_primary_plane =
>>  			ironlake_update_primary_plane;
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
>>  		dev_priv->display.get_initial_plane_config =
>>  			i9xx_get_initial_plane_config;
>> @@ -14808,7 +14812,7 @@ static void intel_init_display(struct 
>>drm_device *dev)
>>  	else if (IS_HASWELL(dev))
>>  		dev_priv->display.get_display_clock_speed =
>>  			haswell_get_display_clock_speed;
>> -	else if (IS_VALLEYVIEW(dev))
>> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		dev_priv->display.get_display_clock_speed =
>>  			valleyview_get_display_clock_speed;
>>  	else if (IS_GEN5(dev))
>> @@ -14866,7 +14870,7 @@ static void intel_init_display(struct 
>>drm_device *dev)
>>  			dev_priv->display.modeset_calc_cdclk =
>>  				broadwell_modeset_calc_cdclk;
>>  		}
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		dev_priv->display.modeset_commit_cdclk =
>>  			valleyview_modeset_commit_cdclk;
>>  		dev_priv->display.modeset_calc_cdclk =
>> @@ -15640,7 +15644,7 @@ intel_modeset_setup_hw_state(struct drm_device 
>>*dev)
>>  		pll->on = false;
>>  	}
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		vlv_wm_get_hw_state(dev);
>>  	else if (IS_GEN9(dev))
>>  		skl_wm_get_hw_state(dev);
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c 
>>b/drivers/gpu/drm/i915/intel_dp.c
>> index f335c92..e36f741 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -517,7 +517,7 @@ void vlv_power_sequencer_reset(struct 
>>drm_i915_private *dev_priv)
>>  	struct drm_device *dev = dev_priv->dev;
>>  	struct intel_encoder *encoder;
>>  
>> -	if (WARN_ON(!IS_VALLEYVIEW(dev)))
>> +	if (WARN_ON(!(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))))
>
>!VLV && !CHV

Fixed.

>
>>  		return;
>>  
>>  	/*
>> @@ -582,7 +582,7 @@ static int edp_notify_handler(struct notifier_block 
>>*this, unsigned long code,
>>  
>>  	pps_lock(intel_dp);
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
>>  		i915_reg_t pp_ctrl_reg, pp_div_reg;
>>  		u32 pp_div;
>> @@ -610,7 +610,7 @@ static bool edp_have_panel_power(struct intel_dp 
>>*intel_dp)
>>  
>>  	lockdep_assert_held(&dev_priv->pps_mutex);
>>  
>> -	if (IS_VALLEYVIEW(dev) &&
>> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>>  	    intel_dp->pps_pipe == INVALID_PIPE)
>>  		return false;
>>  
>> @@ -624,7 +624,7 @@ static bool edp_have_panel_vdd(struct intel_dp 
>>*intel_dp)
>>  
>>  	lockdep_assert_held(&dev_priv->pps_mutex);
>>  
>> -	if (IS_VALLEYVIEW(dev) &&
>> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>>  	    intel_dp->pps_pipe == INVALID_PIPE)
>>  		return false;
>>  
>> @@ -1723,7 +1723,7 @@ static void intel_dp_prepare(struct intel_encoder 
>>*encoder)
>>  		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
>>  	} else {
>>  		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
>> -		    crtc->config->limited_color_range)
>> +		    !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
>
>Could actually replace all that with IS_G4X

Change in a separate patch.


>
>>  			intel_dp->DP |= DP_COLOR_RANGE_16_235;
>>  
>>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
>> @@ -2418,7 +2418,7 @@ static void intel_dp_get_config(struct 
>>intel_encoder *encoder,
>>  	pipe_config->base.adjusted_mode.flags |= flags;
>>  
>>  	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
>> -	    tmp & DP_COLOR_RANGE_16_235)
>> +	    !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
>
>Ditto

Change in a separate patch.


>
>>  		pipe_config->limited_color_range = true;
>>  
>>  	pipe_config->has_dp_encoder = true;
>> @@ -2694,7 +2694,7 @@ static void intel_enable_dp(struct intel_encoder 
>>*encoder)
>>  
>>  	pps_lock(intel_dp);
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		vlv_init_panel_power_sequencer(intel_dp);
>>  
>>  	/*
>> @@ -2728,7 +2728,7 @@ static void intel_enable_dp(struct intel_encoder 
>>*encoder)
>>  
>>  	pps_unlock(intel_dp);
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		unsigned int lane_mask = 0x0;
>>  
>>  		if (IS_CHERRYVIEW(dev))
>> @@ -3218,7 +3218,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>>  		if (dev_priv->edp_low_vswing && port == PORT_A)
>>  			return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
>> -	} else if (IS_VALLEYVIEW(dev))
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>>  	else if (IS_GEN7(dev) && port == PORT_A)
>>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
>> @@ -3259,7 +3259,7 @@ intel_dp_pre_emphasis_max(struct intel_dp 
>>*intel_dp, uint8_t voltage_swing)
>>  		default:
>>  			return DP_TRAIN_PRE_EMPH_LEVEL_0;
>>  		}
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>>  		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>>  			return DP_TRAIN_PRE_EMPH_LEVEL_3;
>> @@ -4539,7 +4539,7 @@ bool intel_digital_port_connected(struct 
>>drm_i915_private *dev_priv,
>>  		return cpt_digital_port_connected(dev_priv, port);
>>  	else if (IS_BROXTON(dev_priv))
>>  		return bxt_digital_port_connected(dev_priv, port);
>> -	else if (IS_VALLEYVIEW(dev_priv))
>> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		return vlv_digital_port_connected(dev_priv, port);
>>  	else
>>  		return g4x_digital_port_connected(dev_priv, port);
>> @@ -4933,7 +4933,7 @@ static void intel_dp_encoder_reset(struct 
>>drm_encoder *encoder)
>>  	 * Read out the current power sequencer assignment,
>>  	 * in case the BIOS did something with it.
>>  	 */
>> -	if (IS_VALLEYVIEW(encoder->dev))
>> +	if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
>>  		vlv_initial_power_sequencer_setup(intel_dp);
>>  
>>  	intel_edp_panel_vdd_sanitize(intel_dp);
>> @@ -5293,7 +5293,7 @@ 
>>intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>>  
>>  	/* Haswell doesn't have any port selection bits for the panel
>>  	 * power sequencer any more. */
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		port_sel = PANEL_PORT_SELECT_VLV(port);
>>  	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
>>  		if (port == PORT_A)
>> @@ -5405,12 +5405,12 @@ static void intel_dp_set_drrs_state(struct 
>>drm_device *dev, int refresh_rate)
>>  
>>  		val = I915_READ(reg);
>>  		if (index > DRRS_HIGH_RR) {
>> -			if (IS_VALLEYVIEW(dev))
>> +			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
>>  			else
>>  				val |= PIPECONF_EDP_RR_MODE_SWITCH;
>>  		} else {
>> -			if (IS_VALLEYVIEW(dev))
>> +			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
>>  			else
>>  				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
>> @@ -5777,7 +5777,7 @@ static bool intel_edp_init_connector(struct 
>>intel_dp *intel_dp,
>>  	}
>>  	mutex_unlock(&dev->mode_config.mutex);
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
>>  		register_reboot_notifier(&intel_dp->edp_notifier);
>>  
>> @@ -5825,7 +5825,7 @@ intel_dp_init_connector(struct intel_digital_port 
>>*intel_dig_port,
>>  	/* intel_dp vfuncs */
>>  	if (INTEL_INFO(dev)->gen >= 9)
>>  		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
>> -	else if (IS_VALLEYVIEW(dev))
>> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
>>  	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>>  		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
>> @@ -5860,8 +5860,8 @@ intel_dp_init_connector(struct intel_digital_port 
>>*intel_dig_port,
>>  		intel_encoder->type = INTEL_OUTPUT_EDP;
>>  
>>  	/* eDP only on port B and/or C on vlv/chv */
>> -	if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
>> -		    port != PORT_B && port != PORT_C))
>> +	if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>> +		    is_edp(intel_dp) && port != PORT_B && port != PORT_C))
>>  		return false;
>>  
>>  	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
>> @@ -5912,7 +5912,7 @@ intel_dp_init_connector(struct intel_digital_port 
>>*intel_dig_port,
>>  	if (is_edp(intel_dp)) {
>>  		pps_lock(intel_dp);
>>  		intel_dp_init_panel_power_timestamps(intel_dp);
>> -		if (IS_VALLEYVIEW(dev))
>> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  			vlv_initial_power_sequencer_setup(intel_dp);
>>  		else
>>  			intel_dp_init_panel_power_sequencer(dev, intel_dp);
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c 
>>b/drivers/gpu/drm/i915/intel_dsi.c
>> index 230957f..cada737 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -369,7 +369,7 @@ static void intel_dsi_device_ready(struct 
>>intel_encoder *encoder)
>>  {
>>  	struct drm_device *dev = encoder->base.dev;
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		vlv_dsi_device_ready(encoder);
>>  	else if (IS_BROXTON(dev))
>>  		bxt_dsi_device_ready(encoder);
>> @@ -487,7 +487,7 @@ static void intel_dsi_pre_enable(struct 
>>intel_encoder *encoder)
>>  
>>  	msleep(intel_dsi->panel_on_delay);
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		/*
>>  		 * Disable DPOunit clock gating, can stall pipe
>>  		 * and we need DPLL REFA always enabled
>> @@ -684,8 +684,7 @@ static bool intel_dsi_get_hw_state(struct 
>>intel_encoder *encoder,
>>  		 * Enable bit does not get set. To check whether DSI Port C
>>  		 * was enabled in BIOS, check the Pipe B enable bit
>>  		 */
>> -		if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
>> -		    (port == PORT_C))
>> +		if (IS_VALLEYVIEW(dev) && (port == PORT_C))
>
>Could throw away the extra parens around the == while it at.

Fixed.

>
>>  			dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
>>  							PIPECONF_ENABLE;
>>  
>> @@ -716,7 +715,8 @@ static void intel_dsi_get_config(struct 
>>intel_encoder *encoder,
>>  
>>  	if (IS_BROXTON(encoder->base.dev))
>>  		pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
>> -	else if (IS_VALLEYVIEW(encoder->base.dev))
>> +	else if (IS_VALLEYVIEW(encoder->base.dev) ||
>> +		 IS_CHERRYVIEW(encoder->base.dev))
>>  		pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
>>  
>>  	if (!pclk)
>> @@ -869,7 +869,7 @@ static void intel_dsi_prepare(struct intel_encoder 
>>*intel_encoder)
>>  	}
>>  
>>  	for_each_dsi_port(port, intel_dsi->ports) {
>> -		if (IS_VALLEYVIEW(dev)) {
>> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  			/*
>>  			 * escape clock divider, 20MHz, shared for A and C.
>>  			 * device ready must be off when doing this! txclkesc?
>> @@ -1129,7 +1129,7 @@ void intel_dsi_init(struct drm_device *dev)
>>  	if (!dev_priv->vbt.has_mipi)
>>  		return;
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
>>  	} else {
>>  		DRM_ERROR("Unsupported Mipi device to reg base");
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c 
>>b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> index cb3cf39..fbd2b51 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> @@ -561,7 +561,7 @@ void intel_enable_dsi_pll(struct intel_encoder 
>>*encoder)
>>  {
>>  	struct drm_device *dev = encoder->base.dev;
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		vlv_enable_dsi_pll(encoder);
>>  	else if (IS_BROXTON(dev))
>>  		bxt_enable_dsi_pll(encoder);
>> @@ -571,7 +571,7 @@ void intel_disable_dsi_pll(struct intel_encoder 
>>*encoder)
>>  {
>>  	struct drm_device *dev = encoder->base.dev;
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		vlv_disable_dsi_pll(encoder);
>>  	else if (IS_BROXTON(dev))
>>  		bxt_disable_dsi_pll(encoder);
>> @@ -599,6 +599,6 @@ void intel_dsi_reset_clocks(struct intel_encoder 
>>*encoder, enum port port)
>>  
>>  	if (IS_BROXTON(dev))
>>  		bxt_dsi_reset_clocks(encoder, port);
>> -	else if (IS_VALLEYVIEW(dev))
>> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		vlv_dsi_reset_clocks(encoder, port);
>>  }
>> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
>>b/drivers/gpu/drm/i915/intel_hdmi.c
>> index c3978ba..be7fab9 100644
>> --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> @@ -638,7 +638,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct 
>>drm_encoder *encoder)
>>  
>>  	if (HAS_DDI(dev_priv))
>>  		reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
>> -	else if (IS_VALLEYVIEW(dev_priv))
>> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
>>  	else if (HAS_PCH_SPLIT(dev_priv->dev))
>>  		reg = TVIDEO_DIP_GCP(crtc->pipe);
>> @@ -2100,7 +2100,7 @@ void intel_hdmi_init_connector(struct 
>>intel_digital_port *intel_dig_port,
>>  		BUG();
>>  	}
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		intel_hdmi->write_infoframe = vlv_write_infoframe;
>>  		intel_hdmi->set_infoframes = vlv_set_infoframes;
>>  		intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
>> diff --git a/drivers/gpu/drm/i915/intel_hotplug.c 
>>b/drivers/gpu/drm/i915/intel_hotplug.c
>> index b177857..a294a3c 100644
>> --- a/drivers/gpu/drm/i915/intel_hotplug.c
>> +++ b/drivers/gpu/drm/i915/intel_hotplug.c
>> @@ -407,7 +407,7 @@ void intel_hpd_irq_handler(struct drm_device *dev,
>>  			 * hotplug bits itself. So only WARN about unexpected
>>  			 * interrupts on saner platforms.
>>  			 */
>> -			WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
>> +			WARN_ONCE(!HAS_GMCH_DISPLAY(dev),
>>  				  "Received HPD interrupt on pin %d although disabled\n", i);
>>  			continue;
>>  		}
>> diff --git a/drivers/gpu/drm/i915/intel_i2c.c 
>>b/drivers/gpu/drm/i915/intel_i2c.c
>> index e26e22a..25254b5 100644
>> --- a/drivers/gpu/drm/i915/intel_i2c.c
>> +++ b/drivers/gpu/drm/i915/intel_i2c.c
>> @@ -636,7 +636,7 @@ int intel_setup_gmbus(struct drm_device *dev)
>>  	if (HAS_PCH_NOP(dev))
>>  		return 0;
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
>>  	else if (!HAS_GMCH_DISPLAY(dev_priv))
>>  		dev_priv->gpio_mmio_base =
>> diff --git a/drivers/gpu/drm/i915/intel_panel.c 
>>b/drivers/gpu/drm/i915/intel_panel.c
>> index ae808b6..72183a0 100644
>> --- a/drivers/gpu/drm/i915/intel_panel.c
>> +++ b/drivers/gpu/drm/i915/intel_panel.c
>> @@ -1784,7 +1784,7 @@ intel_panel_init_backlight_funcs(struct 
>>intel_panel *panel)
>>  		panel->backlight.set = pch_set_backlight;
>>  		panel->backlight.get = pch_get_backlight;
>>  		panel->backlight.hz_to_pwm = pch_hz_to_pwm;
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		if (dev_priv->vbt.has_mipi) {
>>  			panel->backlight.setup = pwm_setup_backlight;
>>  			panel->backlight.enable = pwm_enable_backlight;
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c 
>>b/drivers/gpu/drm/i915/intel_pm.c
>> index ee05ce8..fe56181 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -291,7 +291,7 @@ void intel_set_memory_cxsr(struct drm_i915_private 
>>*dev_priv, bool enable)
>>  	struct drm_device *dev = dev_priv->dev;
>>  	u32 val;
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
>>  		POSTING_READ(FW_BLC_SELF_VLV);
>>  		dev_priv->wm.vlv.cxsr = enable;
>> @@ -4405,7 +4405,7 @@ void gen6_rps_idle(struct drm_i915_private 
>>*dev_priv)
>>  
>>  	mutex_lock(&dev_priv->rps.hw_lock);
>>  	if (dev_priv->rps.enabled) {
>> -		if (IS_VALLEYVIEW(dev))
>> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  			vlv_set_rps_idle(dev_priv);
>>  		else
>>  			gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
>> @@ -4458,7 +4458,7 @@ void gen6_rps_boost(struct drm_i915_private 
>>*dev_priv,
>>  
>>  void intel_set_rps(struct drm_device *dev, u8 val)
>>  {
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		valleyview_set_rps(dev, val);
>>  	else
>>  		gen6_set_rps(dev, val);
>> @@ -4502,7 +4502,7 @@ static void valleyview_disable_rps(struct 
>>drm_device *dev)
>>  
>>  static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
>>  {
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
>>  			mode = GEN6_RC_CTL_RC6_ENABLE;
>>  		else
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
>>b/drivers/gpu/drm/i915/intel_psr.c
>> index b6609e6..1778a7d 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -332,8 +332,8 @@ static bool intel_psr_match_conditions(struct 
>>intel_dp *intel_dp)
>>  		return false;
>>  	}
>>  
>> -	if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||
>> -				    (dig_port->port != PORT_A))) {
>> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
>> +	    ((dev_priv->vbt.psr.full_link) || (dig_port->port != PORT_A))) {
>
>Could remove some of the usless parens here too.

Not changed.  This makes sense but the compiler throws a warning without 
the parens.


>
>>  		DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed 
>>but not supported on this platform\n");
>>  		return false;
>>  	}
>> @@ -650,7 +650,7 @@ void intel_psr_single_frame_update(struct 
>>drm_device *dev,
>>  	 * Single frame update is already supported on BDW+ but it requires
>>  	 * many W/A and it isn't really needed.
>>  	 */
>> -	if (!IS_VALLEYVIEW(dev))
>> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
>>  		return;
>>  
>>  	mutex_lock(&dev_priv->psr.lock);
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
>>b/drivers/gpu/drm/i915/intel_sprite.c
>> index 2b96f33..f8bf622 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -951,7 +951,7 @@ int intel_sprite_set_colorkey(struct drm_device 
>>*dev, void *data,
>>  	if ((set->flags & (I915_SET_COLORKEY_DESTINATION | 
>>I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | 
>>I915_SET_COLORKEY_SOURCE))
>>  		return -EINVAL;
>>  
>> -	if (IS_VALLEYVIEW(dev) &&
>> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>>  	    set->flags & I915_SET_COLORKEY_DESTINATION)
>>  		return -EINVAL;
>>  
>> @@ -1086,7 +1086,7 @@ intel_plane_init(struct drm_device *dev, enum 
>>pipe pipe, int plane)
>>  			intel_plane->max_downscale = 1;
>>  		}
>>  
>> -		if (IS_VALLEYVIEW(dev)) {
>> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  			intel_plane->update_plane = vlv_update_plane;
>>  			intel_plane->disable_plane = vlv_disable_plane;
>>  
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
>>b/drivers/gpu/drm/i915/intel_uncore.c
>> index c2358ba..fcf04fe 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -1115,7 +1115,7 @@ static void fw_domain_init(struct 
>>drm_i915_private *dev_priv,
>>  		d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
>>  	}
>>  
>> -	if (IS_VALLEYVIEW(dev_priv))
>> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		d->reg_post = FORCEWAKE_ACK_VLV;
>>  	else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
>>  		d->reg_post = ECOBUS;
>> @@ -1148,7 +1148,7 @@ static void intel_uncore_fw_domains_init(struct 
>>drm_device *dev)
>>  			       FORCEWAKE_ACK_BLITTER_GEN9);
>>  		fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
>>  			       FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
>>  		if (!IS_CHERRYVIEW(dev))
>>  			dev_priv->uncore.funcs.force_wake_put =
>> -- 
>> 2.6.3
>
>-- 
>Ville Syrjälä
>Intel OTC

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 1/5] drm/i915: Separate cherryview from valleyview

[Wayne Boyer]

The cherryview device shares many characteristics with the valleyview
device.  When support was added to the driver for cherryview, the
corresponding device info structure included .is_valleyview = 1.
This is not correct and leads to some confusion.

This patch changes .is_valleyview to .is_cherryview in the cherryview
device info structure and simplifies the IS_CHERRYVIEW macro.
Then where appropriate, instances of IS_VALLEYVIEW are replaced with
IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent.

v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro.
    Also add followup patches to fix issues discovered during the first
    review. (Ville)
v3: Fix some style issues and one gen check. Remove CRT related changes
    as CRT is not supported on CHV. (Imre, Ville)
v4: Make a few more optimizations. (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c     | 68 ++++++++++++++++-----------------
 drivers/gpu/drm/i915/i915_dma.c         | 11 ++----
 drivers/gpu/drm/i915/i915_drv.c         | 10 ++---
 drivers/gpu/drm/i915/i915_drv.h         | 16 +++++---
 drivers/gpu/drm/i915/i915_gem.c         |  4 +-
 drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c     |  3 +-
 drivers/gpu/drm/i915/i915_irq.c         |  8 ++--
 drivers/gpu/drm/i915/i915_suspend.c     |  4 +-
 drivers/gpu/drm/i915/i915_sysfs.c       | 10 ++---
 drivers/gpu/drm/i915/intel_audio.c      |  7 ++--
 drivers/gpu/drm/i915/intel_display.c    | 54 ++++++++++++++------------
 drivers/gpu/drm/i915/intel_dp.c         | 40 +++++++++----------
 drivers/gpu/drm/i915/intel_dsi.c        | 14 +++----
 drivers/gpu/drm/i915/intel_dsi_pll.c    |  6 +--
 drivers/gpu/drm/i915/intel_hdmi.c       |  4 +-
 drivers/gpu/drm/i915/intel_hotplug.c    |  2 +-
 drivers/gpu/drm/i915/intel_i2c.c        |  2 +-
 drivers/gpu/drm/i915/intel_panel.c      |  2 +-
 drivers/gpu/drm/i915/intel_pm.c         |  8 ++--
 drivers/gpu/drm/i915/intel_psr.c        |  6 +--
 drivers/gpu/drm/i915/intel_sprite.c     |  4 +-
 drivers/gpu/drm/i915/intel_uncore.c     |  4 +-
 23 files changed, 147 insertions(+), 142 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a8721fc..fff31253 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1142,8 +1142,34 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 			   MEMSTAT_VID_SHIFT);
 		seq_printf(m, "Current P-state: %d\n",
 			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
-	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
-		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+		u32 freq_sts;
+
+		mutex_lock(&dev_priv->rps.hw_lock);
+		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
+		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
+
+		seq_printf(m, "actual GPU freq: %d MHz\n",
+			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
+
+		seq_printf(m, "current GPU freq: %d MHz\n",
+			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
+
+		seq_printf(m, "max GPU freq: %d MHz\n",
+			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
+
+		seq_printf(m, "min GPU freq: %d MHz\n",
+			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
+
+		seq_printf(m, "idle GPU freq: %d MHz\n",
+			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
+
+		seq_printf(m,
+			   "efficient (RPe) frequency: %d MHz\n",
+			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
+		mutex_unlock(&dev_priv->rps.hw_lock);
+	} else if (INTEL_INFO(dev)->gen >= 6) {
 		u32 rp_state_limits;
 		u32 gt_perf_status;
 		u32 rp_state_cap;
@@ -1284,33 +1310,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		seq_printf(m,
 			   "efficient (RPe) frequency: %d MHz\n",
 			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
-	} else if (IS_VALLEYVIEW(dev)) {
-		u32 freq_sts;
-
-		mutex_lock(&dev_priv->rps.hw_lock);
-		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
-		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
-		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
-
-		seq_printf(m, "actual GPU freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
-
-		seq_printf(m, "current GPU freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
-
-		seq_printf(m, "max GPU freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
-
-		seq_printf(m, "min GPU freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
-
-		seq_printf(m, "idle GPU freq: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
-
-		seq_printf(m,
-			   "efficient (RPe) frequency: %d MHz\n",
-			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
-		mutex_unlock(&dev_priv->rps.hw_lock);
 	} else {
 		seq_puts(m, "no P-state info available\n");
 	}
@@ -1602,7 +1601,7 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
 	struct drm_info_node *node = m->private;
 	struct drm_device *dev = node->minor->dev;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		return vlv_drpc_info(m);
 	else if (INTEL_INFO(dev)->gen >= 6)
 		return gen6_drpc_info(m);
@@ -1743,7 +1742,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 	else if (IS_PINEVIEW(dev))
 		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 
 	intel_runtime_pm_put(dev_priv);
@@ -3983,7 +3982,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
 		ret = i8xx_pipe_crc_ctl_reg(&source, &val);
 	else if (INTEL_INFO(dev)->gen < 5)
 		ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
 	else if (IS_GEN5(dev) || IS_GEN6(dev))
 		ret = ilk_pipe_crc_ctl_reg(&source, &val);
@@ -4052,7 +4051,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
 
 		if (IS_G4X(dev))
 			g4x_undo_pipe_scramble_reset(dev, pipe);
-		else if (IS_VALLEYVIEW(dev))
+		else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 			vlv_undo_pipe_scramble_reset(dev, pipe);
 		else if (IS_HASWELL(dev) && pipe == PIPE_A)
 			hsw_trans_edp_pipe_A_crc_wa(dev, false);
@@ -4442,7 +4441,8 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
 		 * - WM1+ latency values in 0.5us units
 		 * - latencies are in us on gen9/vlv/chv
 		 */
-		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
+		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
+		    IS_CHERRYVIEW(dev))
 			latency *= 10;
 		else if (level > 0)
 			latency *= 5;
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a81c766..083e2c0 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -256,7 +256,7 @@ intel_setup_mchbar(struct drm_device *dev)
 	u32 temp;
 	bool enabled;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		return;
 
 	dev_priv->mchbar_need_disable = false;
@@ -779,7 +779,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 		info->num_sprites[PIPE_A] = 2;
 		info->num_sprites[PIPE_B] = 2;
 		info->num_sprites[PIPE_C] = 1;
-	} else if (IS_VALLEYVIEW(dev))
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		for_each_pipe(dev_priv, pipe)
 			info->num_sprites[pipe] = 2;
 	else
@@ -791,7 +791,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 		info->num_pipes = 0;
 	} else if (info->num_pipes > 0 &&
 		   (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
-		   !IS_VALLEYVIEW(dev)) {
+		   !(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) {
 		u32 fuse_strap = I915_READ(FUSE_STRAP);
 		u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 
@@ -836,9 +836,6 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 
 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 {
-	if (!IS_VALLEYVIEW(dev_priv))
-		return;
-
 	/*
 	 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 	 * CHV x1 PHY (DP/HDMI D)
@@ -847,7 +844,7 @@ static void intel_init_dpio(struct drm_i915_private *dev_priv)
 	if (IS_CHERRYVIEW(dev_priv)) {
 		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 		DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
-	} else {
+	} else if (IS_VALLEYVIEW(dev_priv)) {
 		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 	}
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e6935f1..1fbbe8e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -311,7 +311,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.gen = 8, .num_pipes = 3,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
-	.is_valleyview = 1,
+	.is_cherryview = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
 	GEN_CHV_PIPEOFFSETS,
 	CURSOR_OFFSETS,
@@ -802,7 +802,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
 	pci_set_master(dev->pdev);
 
-	if (IS_VALLEYVIEW(dev_priv))
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		ret = vlv_resume_prepare(dev_priv, false);
 	if (ret)
 		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
@@ -1532,7 +1532,7 @@ static int intel_runtime_resume(struct device *device)
 		ret = bxt_resume_prepare(dev_priv);
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		hsw_disable_pc8(dev_priv);
-	else if (IS_VALLEYVIEW(dev_priv))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		ret = vlv_resume_prepare(dev_priv, true);
 
 	/*
@@ -1549,7 +1549,7 @@ static int intel_runtime_resume(struct device *device)
 	 * power well, so hpd is reinitialized from there. For
 	 * everyone else do it here.
 	 */
-	if (!IS_VALLEYVIEW(dev_priv))
+	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
 		intel_hpd_init(dev_priv);
 
 	intel_enable_gt_powersave(dev);
@@ -1574,7 +1574,7 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv)
 		ret = bxt_suspend_complete(dev_priv);
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		ret = hsw_suspend_complete(dev_priv);
-	else if (IS_VALLEYVIEW(dev_priv))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		ret = vlv_suspend_complete(dev_priv);
 	else
 		ret = 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f1a8a53..3899f23 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -763,6 +763,7 @@ struct intel_csr {
 	func(is_crestline) sep \
 	func(is_ivybridge) sep \
 	func(is_valleyview) sep \
+	func(is_cherryview) sep \
 	func(is_haswell) sep \
 	func(is_skylake) sep \
 	func(is_broxton) sep \
@@ -2455,9 +2456,9 @@ struct drm_i915_cmd_table {
 				 INTEL_DEVID(dev) == 0x0152 || \
 				 INTEL_DEVID(dev) == 0x015a)
 #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
-#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
+#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
 #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
-#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
+#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
 #define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
 #define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
 #define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
@@ -2584,7 +2585,8 @@ struct drm_i915_cmd_table {
 				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
 				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
-				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
+				 IS_KABYLAKE(dev))
 #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
 #define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
 
@@ -2597,7 +2599,8 @@ struct drm_i915_cmd_table {
 				    INTEL_INFO(dev)->gen >= 8)
 
 #define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
-				 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
+				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
+				 !IS_BROXTON(dev))
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
@@ -2620,7 +2623,8 @@ struct drm_i915_cmd_table {
 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
 
-#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
+#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
+			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 
 /* DPF == dynamic parity feature */
 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
@@ -3511,7 +3515,7 @@ __raw_write(64, q)
 
 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
 {
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		return VLV_VGACNTRL;
 	else if (INTEL_INFO(dev)->gen >= 5)
 		return CPU_VGACNTRL;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index dfaf25b..e96e496 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4838,7 +4838,7 @@ int i915_gem_init(struct drm_device *dev)
 
 	mutex_lock(&dev->struct_mutex);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/* VLVA0 (potential hack), BIOS isn't actually waking us */
 		I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
 		if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
@@ -4963,7 +4963,7 @@ i915_gem_load(struct drm_device *dev)
 
 	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
 
-	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
+	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
 		dev_priv->num_fence_regs = 32;
 	else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 		dev_priv->num_fence_regs = 16;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 43761c5..4b1161d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -190,7 +190,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
 	 * would make the object snooped which might have a
 	 * negative performance impact.
 	 */
-	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) {
+	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
 		/* Failure shouldn't ever happen this early */
 		if (WARN_ON(ret)) {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 1f7e6b9..963d9b6 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -140,8 +140,7 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 #endif
 
 	/* Early VLV doesn't have this */
-	if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
-	    dev->pdev->revision < 0xb) {
+	if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) {
 		DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 		return 0;
 	}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e88d692..86664d1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -581,7 +581,7 @@ i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 {
 	u32 enable_mask;
 
-	if (IS_VALLEYVIEW(dev_priv->dev))
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 							   status_mask);
 	else
@@ -595,7 +595,7 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 {
 	u32 enable_mask;
 
-	if (IS_VALLEYVIEW(dev_priv->dev))
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 							   status_mask);
 	else
@@ -1723,7 +1723,7 @@ static void i9xx_hpd_irq_handler(struct drm_device *dev)
 	 */
 	POSTING_READ(PORT_HOTPLUG_STAT);
 
-	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
+	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
 
 		if (hotplug_trigger) {
@@ -4412,7 +4412,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
 
 	/* Let's track the enabled rps events */
-	if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
+	if (IS_VALLEYVIEW(dev_priv))
 		/* WaGsvRC0ResidencyMethod:vlv */
 		dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
 	else
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 2d91821..a2aa09c 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -49,7 +49,7 @@ static void i915_save_display(struct drm_device *dev)
 		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
 		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
 		dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
-	} else if (!IS_VALLEYVIEW(dev)) {
+	} else if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
 		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
 		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
@@ -84,7 +84,7 @@ static void i915_restore_display(struct drm_device *dev)
 		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
 		I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
 		I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
-	} else if (!IS_VALLEYVIEW(dev)) {
+	} else if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 		I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
 		I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
 		I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index f929c61..37e3f0d 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -49,7 +49,7 @@ static u32 calc_residency(struct drm_device *dev,
 	intel_runtime_pm_get(dev_priv);
 
 	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		units = 1;
 		div = dev_priv->czclk_freq;
 
@@ -284,7 +284,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
 	intel_runtime_pm_get(dev_priv);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
-	if (IS_VALLEYVIEW(dev_priv->dev)) {
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		u32 freq;
 		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
@@ -598,7 +598,7 @@ void i915_setup_sysfs(struct drm_device *dev)
 		if (ret)
 			DRM_ERROR("RC6p residency sysfs setup failed\n");
 	}
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		ret = sysfs_merge_group(&dev->primary->kdev->kobj,
 					&media_rc6_attr_group);
 		if (ret)
@@ -619,7 +619,7 @@ void i915_setup_sysfs(struct drm_device *dev)
 	}
 
 	ret = 0;
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs);
 	else if (INTEL_INFO(dev)->gen >= 6)
 		ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs);
@@ -635,7 +635,7 @@ void i915_setup_sysfs(struct drm_device *dev)
 void i915_teardown_sysfs(struct drm_device *dev)
 {
 	sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr);
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs);
 	else
 		sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs);
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 9aa83e7..06fffae 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -375,7 +375,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder)
 	if (HAS_PCH_IBX(dev_priv->dev)) {
 		aud_config = IBX_AUD_CFG(pipe);
 		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
-	} else if (IS_VALLEYVIEW(dev_priv)) {
+	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		aud_config = VLV_AUD_CFG(pipe);
 		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 	} else {
@@ -435,7 +435,8 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
 		aud_config = IBX_AUD_CFG(pipe);
 		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
-	} else if (IS_VALLEYVIEW(connector->dev)) {
+	} else if (IS_VALLEYVIEW(connector->dev) ||
+		   IS_CHERRYVIEW(connector->dev)) {
 		hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 		aud_config = VLV_AUD_CFG(pipe);
 		aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
@@ -559,7 +560,7 @@ void intel_init_audio(struct drm_device *dev)
 	if (IS_G4X(dev)) {
 		dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 	} else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b59a2d8..d3b643b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -187,7 +187,7 @@ int intel_hrawclk(struct drm_device *dev)
 	uint32_t clkcfg;
 
 	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		return 200;
 
 	clkcfg = I915_READ(CLKCFG);
@@ -215,7 +215,7 @@ int intel_hrawclk(struct drm_device *dev)
 
 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 {
-	if (!IS_VALLEYVIEW(dev_priv))
+	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 		return;
 
 	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
@@ -716,11 +716,12 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
 	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 		INTELPllInvalid("m1 out of range\n");
 
-	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
+	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
+	    !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 		if (clock->m1 <= clock->m2)
 			INTELPllInvalid("m1 <= m2\n");
 
-	if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
+	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 		if (clock->p < limit->p.min || limit->p.max < clock->p)
 			INTELPllInvalid("p out of range\n");
 		if (clock->m < limit->m.min || limit->m.max < clock->m)
@@ -1305,7 +1306,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 		    I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
 			panel_pipe = PIPE_B;
 		/* XXX: else fix for eDP */
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/* presumably write lock depends on pipe, not port select */
 		pp_reg = VLV_PIPE_PP_CONTROL(pipe);
 		panel_pipe = pipe;
@@ -1423,7 +1424,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
 			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
 			     sprite, pipe_name(pipe));
 		}
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		for_each_sprite(dev_priv, pipe, sprite) {
 			u32 val = I915_READ(SPCNTR(pipe, sprite));
 			I915_STATE_WARN(val & SP_ENABLE,
@@ -2319,7 +2320,7 @@ static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
 	if (INTEL_INFO(dev_priv)->gen >= 9)
 		return 256 * 1024;
 	else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
-		 IS_VALLEYVIEW(dev_priv))
+		 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return 128 * 1024;
 	else if (INTEL_INFO(dev_priv)->gen >= 4)
 		return 4 * 1024;
@@ -5455,7 +5456,7 @@ static void intel_update_cdclk(struct drm_device *dev)
 	 * BSpec erroneously claims we should aim for 4MHz, but
 	 * in fact 1MHz is the correct frequency.
 	 */
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/*
 		 * Program the gmbus_freq based on the cdclk frequency.
 		 * BSpec erroneously claims we should aim for 4MHz, but
@@ -7180,7 +7181,7 @@ static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 
 	WARN_ON(!crtc_state->base.state);
 
-	if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
 		refclk = 100000;
 	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
 	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
@@ -7879,7 +7880,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
 		pipeconf |= PIPECONF_DOUBLE_WIDE;
 
 	/* only g4x and later have fancy bpc/dither controls */
-	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
+	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/* Bspec claims that we can't use dithering for 30bpp pipes. */
 		if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
 			pipeconf |= PIPECONF_DITHER_EN |
@@ -7919,7 +7920,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
 	} else
 		pipeconf |= PIPECONF_PROGRESSIVE;
 
-	if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
+	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+	     intel_crtc->config->limited_color_range)
 		pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
 
 	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
@@ -8166,7 +8168,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 	if (!(tmp & PIPECONF_ENABLE))
 		return false;
 
-	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
+	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		switch (tmp & PIPECONF_BPC_MASK) {
 		case PIPECONF_6BPC:
 			pipe_config->pipe_bpp = 18;
@@ -8182,7 +8184,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 		}
 	}
 
-	if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
+	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
 		pipe_config->limited_color_range = true;
 
 	if (INTEL_INFO(dev)->gen < 4)
@@ -8210,7 +8213,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 		pipe_config->pixel_multiplier = 1;
 	}
 	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
-	if (!IS_VALLEYVIEW(dev)) {
+	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 		/*
 		 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
 		 * on 830. Filter it out here so that we don't
@@ -11537,7 +11540,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
 		work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		ring = &dev_priv->ring[BCS];
 		if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
 			/* vlv: DISPLAY_FLIP fails to change tiling */
@@ -12016,7 +12019,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
 	struct drm_connector_state *connector_state;
 	int bpp, i;
 
-	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
+	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
 		bpp = 10*3;
 	else if (INTEL_INFO(dev)->gen >= 5)
 		bpp = 12*3;
@@ -12626,7 +12629,7 @@ intel_pipe_config_compare(struct drm_device *dev,
 	PIPE_CONF_CHECK_I(pixel_multiplier);
 	PIPE_CONF_CHECK_I(has_hdmi_sink);
 	if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
-	    IS_VALLEYVIEW(dev))
+	    IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		PIPE_CONF_CHECK_I(limited_color_range);
 	PIPE_CONF_CHECK_I(has_infoframe);
 
@@ -14378,7 +14381,7 @@ static void intel_setup_outputs(struct drm_device *dev)
 
 		if (I915_READ(PCH_DP_D) & DP_DETECTED)
 			intel_dp_init(dev, PCH_DP_D, PORT_D);
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/*
 		 * The DP_DETECTED bit is the latched state of the DDC
 		 * SDA pin at boot. However since eDP doesn't require DDC
@@ -14527,7 +14530,7 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
 		 *  pixels and 32K bytes."
 		 */
 		 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
-	} else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
+	} else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 		return 32*1024;
 	} else if (gen >= 4) {
 		if (fb_modifier == I915_FORMAT_MOD_X_TILED)
@@ -14631,7 +14634,8 @@ static int intel_framebuffer_init(struct drm_device *dev,
 		}
 		break;
 	case DRM_FORMAT_ABGR8888:
-		if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
+		if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
+		    INTEL_INFO(dev)->gen < 9) {
 			DRM_DEBUG("unsupported pixel format: %s\n",
 				  drm_get_format_name(mode_cmd->pixel_format));
 			return -EINVAL;
@@ -14647,7 +14651,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
 		}
 		break;
 	case DRM_FORMAT_ABGR2101010:
-		if (!IS_VALLEYVIEW(dev)) {
+		if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
 			DRM_DEBUG("unsupported pixel format: %s\n",
 				  drm_get_format_name(mode_cmd->pixel_format));
 			return -EINVAL;
@@ -14775,7 +14779,7 @@ static void intel_init_display(struct drm_device *dev)
 		dev_priv->display.crtc_disable = ironlake_crtc_disable;
 		dev_priv->display.update_primary_plane =
 			ironlake_update_primary_plane;
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			i9xx_get_initial_plane_config;
@@ -14808,7 +14812,7 @@ static void intel_init_display(struct drm_device *dev)
 	else if (IS_HASWELL(dev))
 		dev_priv->display.get_display_clock_speed =
 			haswell_get_display_clock_speed;
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		dev_priv->display.get_display_clock_speed =
 			valleyview_get_display_clock_speed;
 	else if (IS_GEN5(dev))
@@ -14866,7 +14870,7 @@ static void intel_init_display(struct drm_device *dev)
 			dev_priv->display.modeset_calc_cdclk =
 				broadwell_modeset_calc_cdclk;
 		}
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->display.modeset_commit_cdclk =
 			valleyview_modeset_commit_cdclk;
 		dev_priv->display.modeset_calc_cdclk =
@@ -15640,7 +15644,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
 		pll->on = false;
 	}
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_wm_get_hw_state(dev);
 	else if (IS_GEN9(dev))
 		skl_wm_get_hw_state(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f335c92..1edeb3e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -517,7 +517,7 @@ void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 	struct drm_device *dev = dev_priv->dev;
 	struct intel_encoder *encoder;
 
-	if (WARN_ON(!IS_VALLEYVIEW(dev)))
+	if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)))
 		return;
 
 	/*
@@ -582,7 +582,7 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 
 	pps_lock(intel_dp);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 		i915_reg_t pp_ctrl_reg, pp_div_reg;
 		u32 pp_div;
@@ -610,7 +610,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
-	if (IS_VALLEYVIEW(dev) &&
+	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 	    intel_dp->pps_pipe == INVALID_PIPE)
 		return false;
 
@@ -624,7 +624,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
-	if (IS_VALLEYVIEW(dev) &&
+	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 	    intel_dp->pps_pipe == INVALID_PIPE)
 		return false;
 
@@ -1723,7 +1723,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
 		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
 	} else {
 		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
-		    crtc->config->limited_color_range)
+		    !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
 			intel_dp->DP |= DP_COLOR_RANGE_16_235;
 
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
@@ -2418,7 +2418,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 	pipe_config->base.adjusted_mode.flags |= flags;
 
 	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
-	    tmp & DP_COLOR_RANGE_16_235)
+	    !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
 		pipe_config->limited_color_range = true;
 
 	pipe_config->has_dp_encoder = true;
@@ -2694,7 +2694,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
 
 	pps_lock(intel_dp);
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_init_panel_power_sequencer(intel_dp);
 
 	/*
@@ -2728,7 +2728,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
 
 	pps_unlock(intel_dp);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		unsigned int lane_mask = 0x0;
 
 		if (IS_CHERRYVIEW(dev))
@@ -3218,7 +3218,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
 		if (dev_priv->edp_low_vswing && port == PORT_A)
 			return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
-	} else if (IS_VALLEYVIEW(dev))
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 	else if (IS_GEN7(dev) && port == PORT_A)
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
@@ -3259,7 +3259,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 		default:
 			return DP_TRAIN_PRE_EMPH_LEVEL_0;
 		}
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			return DP_TRAIN_PRE_EMPH_LEVEL_3;
@@ -4539,7 +4539,7 @@ bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
 		return cpt_digital_port_connected(dev_priv, port);
 	else if (IS_BROXTON(dev_priv))
 		return bxt_digital_port_connected(dev_priv, port);
-	else if (IS_VALLEYVIEW(dev_priv))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return vlv_digital_port_connected(dev_priv, port);
 	else
 		return g4x_digital_port_connected(dev_priv, port);
@@ -4933,7 +4933,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
 	 * Read out the current power sequencer assignment,
 	 * in case the BIOS did something with it.
 	 */
-	if (IS_VALLEYVIEW(encoder->dev))
+	if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
 		vlv_initial_power_sequencer_setup(intel_dp);
 
 	intel_edp_panel_vdd_sanitize(intel_dp);
@@ -5293,7 +5293,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 
 	/* Haswell doesn't have any port selection bits for the panel
 	 * power sequencer any more. */
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		port_sel = PANEL_PORT_SELECT_VLV(port);
 	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
 		if (port == PORT_A)
@@ -5405,12 +5405,12 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 
 		val = I915_READ(reg);
 		if (index > DRRS_HIGH_RR) {
-			if (IS_VALLEYVIEW(dev))
+			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
 			else
 				val |= PIPECONF_EDP_RR_MODE_SWITCH;
 		} else {
-			if (IS_VALLEYVIEW(dev))
+			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
 			else
 				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
@@ -5777,7 +5777,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	}
 	mutex_unlock(&dev->mode_config.mutex);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
 		register_reboot_notifier(&intel_dp->edp_notifier);
 
@@ -5825,7 +5825,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	/* intel_dp vfuncs */
 	if (INTEL_INFO(dev)->gen >= 9)
 		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
 	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
@@ -5860,8 +5860,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 		intel_encoder->type = INTEL_OUTPUT_EDP;
 
 	/* eDP only on port B and/or C on vlv/chv */
-	if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
-		    port != PORT_B && port != PORT_C))
+	if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+		    is_edp(intel_dp) && port != PORT_B && port != PORT_C))
 		return false;
 
 	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
@@ -5912,7 +5912,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	if (is_edp(intel_dp)) {
 		pps_lock(intel_dp);
 		intel_dp_init_panel_power_timestamps(intel_dp);
-		if (IS_VALLEYVIEW(dev))
+		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 			vlv_initial_power_sequencer_setup(intel_dp);
 		else
 			intel_dp_init_panel_power_sequencer(dev, intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 230957f..25bdf1c 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -369,7 +369,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_dsi_device_ready(encoder);
 	else if (IS_BROXTON(dev))
 		bxt_dsi_device_ready(encoder);
@@ -487,7 +487,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 
 	msleep(intel_dsi->panel_on_delay);
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/*
 		 * Disable DPOunit clock gating, can stall pipe
 		 * and we need DPLL REFA always enabled
@@ -684,8 +684,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 		 * Enable bit does not get set. To check whether DSI Port C
 		 * was enabled in BIOS, check the Pipe B enable bit
 		 */
-		if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
-		    (port == PORT_C))
+		if (IS_VALLEYVIEW(dev) && port == PORT_C)
 			dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
 							PIPECONF_ENABLE;
 
@@ -716,7 +715,8 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
 
 	if (IS_BROXTON(encoder->base.dev))
 		pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
-	else if (IS_VALLEYVIEW(encoder->base.dev))
+	else if (IS_VALLEYVIEW(encoder->base.dev) ||
+		 IS_CHERRYVIEW(encoder->base.dev))
 		pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
 
 	if (!pclk)
@@ -869,7 +869,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-		if (IS_VALLEYVIEW(dev)) {
+		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 			/*
 			 * escape clock divider, 20MHz, shared for A and C.
 			 * device ready must be off when doing this! txclkesc?
@@ -1129,7 +1129,7 @@ void intel_dsi_init(struct drm_device *dev)
 	if (!dev_priv->vbt.has_mipi)
 		return;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
 	} else {
 		DRM_ERROR("Unsupported Mipi device to reg base");
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index cb3cf39..fbd2b51 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -561,7 +561,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_enable_dsi_pll(encoder);
 	else if (IS_BROXTON(dev))
 		bxt_enable_dsi_pll(encoder);
@@ -571,7 +571,7 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_disable_dsi_pll(encoder);
 	else if (IS_BROXTON(dev))
 		bxt_disable_dsi_pll(encoder);
@@ -599,6 +599,6 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
 
 	if (IS_BROXTON(dev))
 		bxt_dsi_reset_clocks(encoder, port);
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_dsi_reset_clocks(encoder, port);
 }
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index c3978ba..be7fab9 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -638,7 +638,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
 
 	if (HAS_DDI(dev_priv))
 		reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
-	else if (IS_VALLEYVIEW(dev_priv))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 	else if (HAS_PCH_SPLIT(dev_priv->dev))
 		reg = TVIDEO_DIP_GCP(crtc->pipe);
@@ -2100,7 +2100,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 		BUG();
 	}
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		intel_hdmi->write_infoframe = vlv_write_infoframe;
 		intel_hdmi->set_infoframes = vlv_set_infoframes;
 		intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
index b177857..a294a3c 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -407,7 +407,7 @@ void intel_hpd_irq_handler(struct drm_device *dev,
 			 * hotplug bits itself. So only WARN about unexpected
 			 * interrupts on saner platforms.
 			 */
-			WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
+			WARN_ONCE(!HAS_GMCH_DISPLAY(dev),
 				  "Received HPD interrupt on pin %d although disabled\n", i);
 			continue;
 		}
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index e26e22a..25254b5 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -636,7 +636,7 @@ int intel_setup_gmbus(struct drm_device *dev)
 	if (HAS_PCH_NOP(dev))
 		return 0;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
 	else if (!HAS_GMCH_DISPLAY(dev_priv))
 		dev_priv->gpio_mmio_base =
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index ae808b6..72183a0 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1784,7 +1784,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
 		panel->backlight.set = pch_set_backlight;
 		panel->backlight.get = pch_get_backlight;
 		panel->backlight.hz_to_pwm = pch_hz_to_pwm;
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		if (dev_priv->vbt.has_mipi) {
 			panel->backlight.setup = pwm_setup_backlight;
 			panel->backlight.enable = pwm_enable_backlight;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ee05ce8..fe56181 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -291,7 +291,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 	struct drm_device *dev = dev_priv->dev;
 	u32 val;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 		POSTING_READ(FW_BLC_SELF_VLV);
 		dev_priv->wm.vlv.cxsr = enable;
@@ -4405,7 +4405,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
-		if (IS_VALLEYVIEW(dev))
+		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 			vlv_set_rps_idle(dev_priv);
 		else
 			gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
@@ -4458,7 +4458,7 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
 
 void intel_set_rps(struct drm_device *dev, u8 val)
 {
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		valleyview_set_rps(dev, val);
 	else
 		gen6_set_rps(dev, val);
@@ -4502,7 +4502,7 @@ static void valleyview_disable_rps(struct drm_device *dev)
 
 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
 {
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
 			mode = GEN6_RC_CTL_RC6_ENABLE;
 		else
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b6609e6..1778a7d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -332,8 +332,8 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 		return false;
 	}
 
-	if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||
-				    (dig_port->port != PORT_A))) {
+	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
+	    ((dev_priv->vbt.psr.full_link) || (dig_port->port != PORT_A))) {
 		DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n");
 		return false;
 	}
@@ -650,7 +650,7 @@ void intel_psr_single_frame_update(struct drm_device *dev,
 	 * Single frame update is already supported on BDW+ but it requires
 	 * many W/A and it isn't really needed.
 	 */
-	if (!IS_VALLEYVIEW(dev))
+	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
 		return;
 
 	mutex_lock(&dev_priv->psr.lock);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 2b96f33..f8bf622 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -951,7 +951,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 	if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 		return -EINVAL;
 
-	if (IS_VALLEYVIEW(dev) &&
+	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 	    set->flags & I915_SET_COLORKEY_DESTINATION)
 		return -EINVAL;
 
@@ -1086,7 +1086,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
 			intel_plane->max_downscale = 1;
 		}
 
-		if (IS_VALLEYVIEW(dev)) {
+		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 			intel_plane->update_plane = vlv_update_plane;
 			intel_plane->disable_plane = vlv_disable_plane;
 
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index c2358ba..fcf04fe 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1115,7 +1115,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
 		d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
 	}
 
-	if (IS_VALLEYVIEW(dev_priv))
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		d->reg_post = FORCEWAKE_ACK_VLV;
 	else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
 		d->reg_post = ECOBUS;
@@ -1148,7 +1148,7 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
 			       FORCEWAKE_ACK_BLITTER_GEN9);
 		fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
 			       FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
-	} else if (IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
 		if (!IS_CHERRYVIEW(dev))
 			dev_priv->uncore.funcs.force_wake_put =
-- 
2.6.3

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/5] drm/i915: Separate cherryview from valleyview

[Ville Syrjälä]

On Wed, Dec 09, 2015 at 12:29:35PM -0800, Wayne Boyer wrote:
> The cherryview device shares many characteristics with the valleyview
> device.  When support was added to the driver for cherryview, the
> corresponding device info structure included .is_valleyview = 1.
> This is not correct and leads to some confusion.
> 
> This patch changes .is_valleyview to .is_cherryview in the cherryview
> device info structure and simplifies the IS_CHERRYVIEW macro.
> Then where appropriate, instances of IS_VALLEYVIEW are replaced with
> IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent.
> 
> v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro.
>     Also add followup patches to fix issues discovered during the first
>     review. (Ville)
> v3: Fix some style issues and one gen check. Remove CRT related changes
>     as CRT is not supported on CHV. (Imre, Ville)
> v4: Make a few more optimizations. (Ville)
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>

lgtm
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c     | 68 ++++++++++++++++-----------------
>  drivers/gpu/drm/i915/i915_dma.c         | 11 ++----
>  drivers/gpu/drm/i915/i915_drv.c         | 10 ++---
>  drivers/gpu/drm/i915/i915_drv.h         | 16 +++++---
>  drivers/gpu/drm/i915/i915_gem.c         |  4 +-
>  drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c     |  3 +-
>  drivers/gpu/drm/i915/i915_irq.c         |  8 ++--
>  drivers/gpu/drm/i915/i915_suspend.c     |  4 +-
>  drivers/gpu/drm/i915/i915_sysfs.c       | 10 ++---
>  drivers/gpu/drm/i915/intel_audio.c      |  7 ++--
>  drivers/gpu/drm/i915/intel_display.c    | 54 ++++++++++++++------------
>  drivers/gpu/drm/i915/intel_dp.c         | 40 +++++++++----------
>  drivers/gpu/drm/i915/intel_dsi.c        | 14 +++----
>  drivers/gpu/drm/i915/intel_dsi_pll.c    |  6 +--
>  drivers/gpu/drm/i915/intel_hdmi.c       |  4 +-
>  drivers/gpu/drm/i915/intel_hotplug.c    |  2 +-
>  drivers/gpu/drm/i915/intel_i2c.c        |  2 +-
>  drivers/gpu/drm/i915/intel_panel.c      |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c         |  8 ++--
>  drivers/gpu/drm/i915/intel_psr.c        |  6 +--
>  drivers/gpu/drm/i915/intel_sprite.c     |  4 +-
>  drivers/gpu/drm/i915/intel_uncore.c     |  4 +-
>  23 files changed, 147 insertions(+), 142 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index a8721fc..fff31253 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1142,8 +1142,34 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  			   MEMSTAT_VID_SHIFT);
>  		seq_printf(m, "Current P-state: %d\n",
>  			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
> -	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
> -		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> +		u32 freq_sts;
> +
> +		mutex_lock(&dev_priv->rps.hw_lock);
> +		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
> +		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
> +
> +		seq_printf(m, "actual GPU freq: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
> +
> +		seq_printf(m, "current GPU freq: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
> +
> +		seq_printf(m, "max GPU freq: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
> +
> +		seq_printf(m, "min GPU freq: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
> +
> +		seq_printf(m, "idle GPU freq: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
> +
> +		seq_printf(m,
> +			   "efficient (RPe) frequency: %d MHz\n",
> +			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +	} else if (INTEL_INFO(dev)->gen >= 6) {
>  		u32 rp_state_limits;
>  		u32 gt_perf_status;
>  		u32 rp_state_cap;
> @@ -1284,33 +1310,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		seq_printf(m,
>  			   "efficient (RPe) frequency: %d MHz\n",
>  			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
> -	} else if (IS_VALLEYVIEW(dev)) {
> -		u32 freq_sts;
> -
> -		mutex_lock(&dev_priv->rps.hw_lock);
> -		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> -		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
> -		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
> -
> -		seq_printf(m, "actual GPU freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
> -
> -		seq_printf(m, "current GPU freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
> -
> -		seq_printf(m, "max GPU freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
> -
> -		seq_printf(m, "min GPU freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
> -
> -		seq_printf(m, "idle GPU freq: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
> -
> -		seq_printf(m,
> -			   "efficient (RPe) frequency: %d MHz\n",
> -			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
> -		mutex_unlock(&dev_priv->rps.hw_lock);
>  	} else {
>  		seq_puts(m, "no P-state info available\n");
>  	}
> @@ -1602,7 +1601,7 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
>  	struct drm_info_node *node = m->private;
>  	struct drm_device *dev = node->minor->dev;
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		return vlv_drpc_info(m);
>  	else if (INTEL_INFO(dev)->gen >= 6)
>  		return gen6_drpc_info(m);
> @@ -1743,7 +1742,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>  		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
>  	else if (IS_PINEVIEW(dev))
>  		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
> -	else if (IS_VALLEYVIEW(dev))
> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>  
>  	intel_runtime_pm_put(dev_priv);
> @@ -3983,7 +3982,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
>  		ret = i8xx_pipe_crc_ctl_reg(&source, &val);
>  	else if (INTEL_INFO(dev)->gen < 5)
>  		ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
> -	else if (IS_VALLEYVIEW(dev))
> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
>  	else if (IS_GEN5(dev) || IS_GEN6(dev))
>  		ret = ilk_pipe_crc_ctl_reg(&source, &val);
> @@ -4052,7 +4051,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
>  
>  		if (IS_G4X(dev))
>  			g4x_undo_pipe_scramble_reset(dev, pipe);
> -		else if (IS_VALLEYVIEW(dev))
> +		else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  			vlv_undo_pipe_scramble_reset(dev, pipe);
>  		else if (IS_HASWELL(dev) && pipe == PIPE_A)
>  			hsw_trans_edp_pipe_A_crc_wa(dev, false);
> @@ -4442,7 +4441,8 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
>  		 * - WM1+ latency values in 0.5us units
>  		 * - latencies are in us on gen9/vlv/chv
>  		 */
> -		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
> +		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
> +		    IS_CHERRYVIEW(dev))
>  			latency *= 10;
>  		else if (level > 0)
>  			latency *= 5;
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index a81c766..083e2c0 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -256,7 +256,7 @@ intel_setup_mchbar(struct drm_device *dev)
>  	u32 temp;
>  	bool enabled;
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		return;
>  
>  	dev_priv->mchbar_need_disable = false;
> @@ -779,7 +779,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>  		info->num_sprites[PIPE_A] = 2;
>  		info->num_sprites[PIPE_B] = 2;
>  		info->num_sprites[PIPE_C] = 1;
> -	} else if (IS_VALLEYVIEW(dev))
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		for_each_pipe(dev_priv, pipe)
>  			info->num_sprites[pipe] = 2;
>  	else
> @@ -791,7 +791,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>  		info->num_pipes = 0;
>  	} else if (info->num_pipes > 0 &&
>  		   (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
> -		   !IS_VALLEYVIEW(dev)) {
> +		   !(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) {
>  		u32 fuse_strap = I915_READ(FUSE_STRAP);
>  		u32 sfuse_strap = I915_READ(SFUSE_STRAP);
>  
> @@ -836,9 +836,6 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>  
>  static void intel_init_dpio(struct drm_i915_private *dev_priv)
>  {
> -	if (!IS_VALLEYVIEW(dev_priv))
> -		return;
> -
>  	/*
>  	 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
>  	 * CHV x1 PHY (DP/HDMI D)
> @@ -847,7 +844,7 @@ static void intel_init_dpio(struct drm_i915_private *dev_priv)
>  	if (IS_CHERRYVIEW(dev_priv)) {
>  		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
>  		DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
> -	} else {
> +	} else if (IS_VALLEYVIEW(dev_priv)) {
>  		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index e6935f1..1fbbe8e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -311,7 +311,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.gen = 8, .num_pipes = 3,
>  	.need_gfx_hws = 1, .has_hotplug = 1,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> -	.is_valleyview = 1,
> +	.is_cherryview = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
>  	GEN_CHV_PIPEOFFSETS,
>  	CURSOR_OFFSETS,
> @@ -802,7 +802,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
>  
>  	pci_set_master(dev->pdev);
>  
> -	if (IS_VALLEYVIEW(dev_priv))
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		ret = vlv_resume_prepare(dev_priv, false);
>  	if (ret)
>  		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
> @@ -1532,7 +1532,7 @@ static int intel_runtime_resume(struct device *device)
>  		ret = bxt_resume_prepare(dev_priv);
>  	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		hsw_disable_pc8(dev_priv);
> -	else if (IS_VALLEYVIEW(dev_priv))
> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		ret = vlv_resume_prepare(dev_priv, true);
>  
>  	/*
> @@ -1549,7 +1549,7 @@ static int intel_runtime_resume(struct device *device)
>  	 * power well, so hpd is reinitialized from there. For
>  	 * everyone else do it here.
>  	 */
> -	if (!IS_VALLEYVIEW(dev_priv))
> +	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
>  		intel_hpd_init(dev_priv);
>  
>  	intel_enable_gt_powersave(dev);
> @@ -1574,7 +1574,7 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv)
>  		ret = bxt_suspend_complete(dev_priv);
>  	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		ret = hsw_suspend_complete(dev_priv);
> -	else if (IS_VALLEYVIEW(dev_priv))
> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		ret = vlv_suspend_complete(dev_priv);
>  	else
>  		ret = 0;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f1a8a53..3899f23 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -763,6 +763,7 @@ struct intel_csr {
>  	func(is_crestline) sep \
>  	func(is_ivybridge) sep \
>  	func(is_valleyview) sep \
> +	func(is_cherryview) sep \
>  	func(is_haswell) sep \
>  	func(is_skylake) sep \
>  	func(is_broxton) sep \
> @@ -2455,9 +2456,9 @@ struct drm_i915_cmd_table {
>  				 INTEL_DEVID(dev) == 0x0152 || \
>  				 INTEL_DEVID(dev) == 0x015a)
>  #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
> -#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
> +#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
>  #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
> -#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
> +#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
>  #define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
>  #define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
>  #define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
> @@ -2584,7 +2585,8 @@ struct drm_i915_cmd_table {
>  				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
>  #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
>  				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
> -				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
> +				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
> +				 IS_KABYLAKE(dev))
>  #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
>  #define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
>  
> @@ -2597,7 +2599,8 @@ struct drm_i915_cmd_table {
>  				    INTEL_INFO(dev)->gen >= 8)
>  
>  #define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
> -				 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
> +				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
> +				 !IS_BROXTON(dev))
>  
>  #define INTEL_PCH_DEVICE_ID_MASK		0xff00
>  #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
> @@ -2620,7 +2623,8 @@ struct drm_i915_cmd_table {
>  #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
>  #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
>  
> -#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
> +#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
> +			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  
>  /* DPF == dynamic parity feature */
>  #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
> @@ -3511,7 +3515,7 @@ __raw_write(64, q)
>  
>  static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
>  {
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		return VLV_VGACNTRL;
>  	else if (INTEL_INFO(dev)->gen >= 5)
>  		return CPU_VGACNTRL;
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index dfaf25b..e96e496 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4838,7 +4838,7 @@ int i915_gem_init(struct drm_device *dev)
>  
>  	mutex_lock(&dev->struct_mutex);
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		/* VLVA0 (potential hack), BIOS isn't actually waking us */
>  		I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
>  		if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
> @@ -4963,7 +4963,7 @@ i915_gem_load(struct drm_device *dev)
>  
>  	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
>  
> -	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
> +	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
>  		dev_priv->num_fence_regs = 32;
>  	else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
>  		dev_priv->num_fence_regs = 16;
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 43761c5..4b1161d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -190,7 +190,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
>  	 * would make the object snooped which might have a
>  	 * negative performance impact.
>  	 */
> -	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) {
> +	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>  		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
>  		/* Failure shouldn't ever happen this early */
>  		if (WARN_ON(ret)) {
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 1f7e6b9..963d9b6 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -140,8 +140,7 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
>  #endif
>  
>  	/* Early VLV doesn't have this */
> -	if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> -	    dev->pdev->revision < 0xb) {
> +	if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) {
>  		DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
>  		return 0;
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e88d692..86664d1 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -581,7 +581,7 @@ i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
>  {
>  	u32 enable_mask;
>  
> -	if (IS_VALLEYVIEW(dev_priv->dev))
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
>  							   status_mask);
>  	else
> @@ -595,7 +595,7 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
>  {
>  	u32 enable_mask;
>  
> -	if (IS_VALLEYVIEW(dev_priv->dev))
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
>  							   status_mask);
>  	else
> @@ -1723,7 +1723,7 @@ static void i9xx_hpd_irq_handler(struct drm_device *dev)
>  	 */
>  	POSTING_READ(PORT_HOTPLUG_STAT);
>  
> -	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
> +	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
>  
>  		if (hotplug_trigger) {
> @@ -4412,7 +4412,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
>  
>  	/* Let's track the enabled rps events */
> -	if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
> +	if (IS_VALLEYVIEW(dev_priv))
>  		/* WaGsvRC0ResidencyMethod:vlv */
>  		dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
>  	else
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 2d91821..a2aa09c 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -49,7 +49,7 @@ static void i915_save_display(struct drm_device *dev)
>  		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
>  		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
>  		dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
> -	} else if (!IS_VALLEYVIEW(dev)) {
> +	} else if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>  		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
>  		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
>  		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
> @@ -84,7 +84,7 @@ static void i915_restore_display(struct drm_device *dev)
>  		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
>  		I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
>  		I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
> -	} else if (!IS_VALLEYVIEW(dev)) {
> +	} else if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>  		I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
>  		I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
>  		I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index f929c61..37e3f0d 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -49,7 +49,7 @@ static u32 calc_residency(struct drm_device *dev,
>  	intel_runtime_pm_get(dev_priv);
>  
>  	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		units = 1;
>  		div = dev_priv->czclk_freq;
>  
> @@ -284,7 +284,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
>  	intel_runtime_pm_get(dev_priv);
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
> -	if (IS_VALLEYVIEW(dev_priv->dev)) {
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		u32 freq;
>  		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>  		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
> @@ -598,7 +598,7 @@ void i915_setup_sysfs(struct drm_device *dev)
>  		if (ret)
>  			DRM_ERROR("RC6p residency sysfs setup failed\n");
>  	}
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		ret = sysfs_merge_group(&dev->primary->kdev->kobj,
>  					&media_rc6_attr_group);
>  		if (ret)
> @@ -619,7 +619,7 @@ void i915_setup_sysfs(struct drm_device *dev)
>  	}
>  
>  	ret = 0;
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs);
>  	else if (INTEL_INFO(dev)->gen >= 6)
>  		ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs);
> @@ -635,7 +635,7 @@ void i915_setup_sysfs(struct drm_device *dev)
>  void i915_teardown_sysfs(struct drm_device *dev)
>  {
>  	sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr);
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs);
>  	else
>  		sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs);
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 9aa83e7..06fffae 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -375,7 +375,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder)
>  	if (HAS_PCH_IBX(dev_priv->dev)) {
>  		aud_config = IBX_AUD_CFG(pipe);
>  		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
> -	} else if (IS_VALLEYVIEW(dev_priv)) {
> +	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		aud_config = VLV_AUD_CFG(pipe);
>  		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
>  	} else {
> @@ -435,7 +435,8 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
>  		aud_config = IBX_AUD_CFG(pipe);
>  		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
>  		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
> -	} else if (IS_VALLEYVIEW(connector->dev)) {
> +	} else if (IS_VALLEYVIEW(connector->dev) ||
> +		   IS_CHERRYVIEW(connector->dev)) {
>  		hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
>  		aud_config = VLV_AUD_CFG(pipe);
>  		aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
> @@ -559,7 +560,7 @@ void intel_init_audio(struct drm_device *dev)
>  	if (IS_G4X(dev)) {
>  		dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
>  		dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
>  		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
>  	} else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b59a2d8..d3b643b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -187,7 +187,7 @@ int intel_hrawclk(struct drm_device *dev)
>  	uint32_t clkcfg;
>  
>  	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		return 200;
>  
>  	clkcfg = I915_READ(CLKCFG);
> @@ -215,7 +215,7 @@ int intel_hrawclk(struct drm_device *dev)
>  
>  static void intel_update_czclk(struct drm_i915_private *dev_priv)
>  {
> -	if (!IS_VALLEYVIEW(dev_priv))
> +	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
>  		return;
>  
>  	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
> @@ -716,11 +716,12 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
>  	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
>  		INTELPllInvalid("m1 out of range\n");
>  
> -	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
> +	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
> +	    !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
>  		if (clock->m1 <= clock->m2)
>  			INTELPllInvalid("m1 <= m2\n");
>  
> -	if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
>  		if (clock->p < limit->p.min || limit->p.max < clock->p)
>  			INTELPllInvalid("p out of range\n");
>  		if (clock->m < limit->m.min || limit->m.max < clock->m)
> @@ -1305,7 +1306,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv,
>  		    I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
>  			panel_pipe = PIPE_B;
>  		/* XXX: else fix for eDP */
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		/* presumably write lock depends on pipe, not port select */
>  		pp_reg = VLV_PIPE_PP_CONTROL(pipe);
>  		panel_pipe = pipe;
> @@ -1423,7 +1424,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
>  			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
>  			     sprite, pipe_name(pipe));
>  		}
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		for_each_sprite(dev_priv, pipe, sprite) {
>  			u32 val = I915_READ(SPCNTR(pipe, sprite));
>  			I915_STATE_WARN(val & SP_ENABLE,
> @@ -2319,7 +2320,7 @@ static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
>  	if (INTEL_INFO(dev_priv)->gen >= 9)
>  		return 256 * 1024;
>  	else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
> -		 IS_VALLEYVIEW(dev_priv))
> +		 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		return 128 * 1024;
>  	else if (INTEL_INFO(dev_priv)->gen >= 4)
>  		return 4 * 1024;
> @@ -5455,7 +5456,7 @@ static void intel_update_cdclk(struct drm_device *dev)
>  	 * BSpec erroneously claims we should aim for 4MHz, but
>  	 * in fact 1MHz is the correct frequency.
>  	 */
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		/*
>  		 * Program the gmbus_freq based on the cdclk frequency.
>  		 * BSpec erroneously claims we should aim for 4MHz, but
> @@ -7180,7 +7181,7 @@ static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
>  
>  	WARN_ON(!crtc_state->base.state);
>  
> -	if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
>  		refclk = 100000;
>  	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
>  	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
> @@ -7879,7 +7880,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
>  		pipeconf |= PIPECONF_DOUBLE_WIDE;
>  
>  	/* only g4x and later have fancy bpc/dither controls */
> -	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
> +	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		/* Bspec claims that we can't use dithering for 30bpp pipes. */
>  		if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
>  			pipeconf |= PIPECONF_DITHER_EN |
> @@ -7919,7 +7920,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
>  	} else
>  		pipeconf |= PIPECONF_PROGRESSIVE;
>  
> -	if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> +	     intel_crtc->config->limited_color_range)
>  		pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
>  
>  	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
> @@ -8166,7 +8168,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  	if (!(tmp & PIPECONF_ENABLE))
>  		return false;
>  
> -	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
> +	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		switch (tmp & PIPECONF_BPC_MASK) {
>  		case PIPECONF_6BPC:
>  			pipe_config->pipe_bpp = 18;
> @@ -8182,7 +8184,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  		}
>  	}
>  
> -	if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> +	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
>  		pipe_config->limited_color_range = true;
>  
>  	if (INTEL_INFO(dev)->gen < 4)
> @@ -8210,7 +8213,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  		pipe_config->pixel_multiplier = 1;
>  	}
>  	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
> -	if (!IS_VALLEYVIEW(dev)) {
> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>  		/*
>  		 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
>  		 * on 830. Filter it out here so that we don't
> @@ -11537,7 +11540,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>  	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
>  		work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		ring = &dev_priv->ring[BCS];
>  		if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
>  			/* vlv: DISPLAY_FLIP fails to change tiling */
> @@ -12016,7 +12019,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
>  	struct drm_connector_state *connector_state;
>  	int bpp, i;
>  
> -	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
> +	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
>  		bpp = 10*3;
>  	else if (INTEL_INFO(dev)->gen >= 5)
>  		bpp = 12*3;
> @@ -12626,7 +12629,7 @@ intel_pipe_config_compare(struct drm_device *dev,
>  	PIPE_CONF_CHECK_I(pixel_multiplier);
>  	PIPE_CONF_CHECK_I(has_hdmi_sink);
>  	if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
> -	    IS_VALLEYVIEW(dev))
> +	    IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		PIPE_CONF_CHECK_I(limited_color_range);
>  	PIPE_CONF_CHECK_I(has_infoframe);
>  
> @@ -14378,7 +14381,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>  
>  		if (I915_READ(PCH_DP_D) & DP_DETECTED)
>  			intel_dp_init(dev, PCH_DP_D, PORT_D);
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		/*
>  		 * The DP_DETECTED bit is the latched state of the DDC
>  		 * SDA pin at boot. However since eDP doesn't require DDC
> @@ -14527,7 +14530,7 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
>  		 *  pixels and 32K bytes."
>  		 */
>  		 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
> -	} else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
> +	} else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>  		return 32*1024;
>  	} else if (gen >= 4) {
>  		if (fb_modifier == I915_FORMAT_MOD_X_TILED)
> @@ -14631,7 +14634,8 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  		}
>  		break;
>  	case DRM_FORMAT_ABGR8888:
> -		if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
> +		if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> +		    INTEL_INFO(dev)->gen < 9) {
>  			DRM_DEBUG("unsupported pixel format: %s\n",
>  				  drm_get_format_name(mode_cmd->pixel_format));
>  			return -EINVAL;
> @@ -14647,7 +14651,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  		}
>  		break;
>  	case DRM_FORMAT_ABGR2101010:
> -		if (!IS_VALLEYVIEW(dev)) {
> +		if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>  			DRM_DEBUG("unsupported pixel format: %s\n",
>  				  drm_get_format_name(mode_cmd->pixel_format));
>  			return -EINVAL;
> @@ -14775,7 +14779,7 @@ static void intel_init_display(struct drm_device *dev)
>  		dev_priv->display.crtc_disable = ironlake_crtc_disable;
>  		dev_priv->display.update_primary_plane =
>  			ironlake_update_primary_plane;
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
>  		dev_priv->display.get_initial_plane_config =
>  			i9xx_get_initial_plane_config;
> @@ -14808,7 +14812,7 @@ static void intel_init_display(struct drm_device *dev)
>  	else if (IS_HASWELL(dev))
>  		dev_priv->display.get_display_clock_speed =
>  			haswell_get_display_clock_speed;
> -	else if (IS_VALLEYVIEW(dev))
> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		dev_priv->display.get_display_clock_speed =
>  			valleyview_get_display_clock_speed;
>  	else if (IS_GEN5(dev))
> @@ -14866,7 +14870,7 @@ static void intel_init_display(struct drm_device *dev)
>  			dev_priv->display.modeset_calc_cdclk =
>  				broadwell_modeset_calc_cdclk;
>  		}
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		dev_priv->display.modeset_commit_cdclk =
>  			valleyview_modeset_commit_cdclk;
>  		dev_priv->display.modeset_calc_cdclk =
> @@ -15640,7 +15644,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
>  		pll->on = false;
>  	}
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		vlv_wm_get_hw_state(dev);
>  	else if (IS_GEN9(dev))
>  		skl_wm_get_hw_state(dev);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f335c92..1edeb3e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -517,7 +517,7 @@ void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
>  	struct drm_device *dev = dev_priv->dev;
>  	struct intel_encoder *encoder;
>  
> -	if (WARN_ON(!IS_VALLEYVIEW(dev)))
> +	if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)))
>  		return;
>  
>  	/*
> @@ -582,7 +582,7 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
>  
>  	pps_lock(intel_dp);
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
>  		i915_reg_t pp_ctrl_reg, pp_div_reg;
>  		u32 pp_div;
> @@ -610,7 +610,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
>  
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
> -	if (IS_VALLEYVIEW(dev) &&
> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>  	    intel_dp->pps_pipe == INVALID_PIPE)
>  		return false;
>  
> @@ -624,7 +624,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>  
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
> -	if (IS_VALLEYVIEW(dev) &&
> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>  	    intel_dp->pps_pipe == INVALID_PIPE)
>  		return false;
>  
> @@ -1723,7 +1723,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
>  		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
>  	} else {
>  		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
> -		    crtc->config->limited_color_range)
> +		    !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
>  			intel_dp->DP |= DP_COLOR_RANGE_16_235;
>  
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> @@ -2418,7 +2418,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
>  	pipe_config->base.adjusted_mode.flags |= flags;
>  
>  	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
> -	    tmp & DP_COLOR_RANGE_16_235)
> +	    !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
>  		pipe_config->limited_color_range = true;
>  
>  	pipe_config->has_dp_encoder = true;
> @@ -2694,7 +2694,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
>  
>  	pps_lock(intel_dp);
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		vlv_init_panel_power_sequencer(intel_dp);
>  
>  	/*
> @@ -2728,7 +2728,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
>  
>  	pps_unlock(intel_dp);
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		unsigned int lane_mask = 0x0;
>  
>  		if (IS_CHERRYVIEW(dev))
> @@ -3218,7 +3218,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>  		if (dev_priv->edp_low_vswing && port == PORT_A)
>  			return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> -	} else if (IS_VALLEYVIEW(dev))
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  	else if (IS_GEN7(dev) && port == PORT_A)
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> @@ -3259,7 +3259,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  		default:
>  			return DP_TRAIN_PRE_EMPH_LEVEL_0;
>  		}
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>  		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>  			return DP_TRAIN_PRE_EMPH_LEVEL_3;
> @@ -4539,7 +4539,7 @@ bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
>  		return cpt_digital_port_connected(dev_priv, port);
>  	else if (IS_BROXTON(dev_priv))
>  		return bxt_digital_port_connected(dev_priv, port);
> -	else if (IS_VALLEYVIEW(dev_priv))
> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		return vlv_digital_port_connected(dev_priv, port);
>  	else
>  		return g4x_digital_port_connected(dev_priv, port);
> @@ -4933,7 +4933,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
>  	 * Read out the current power sequencer assignment,
>  	 * in case the BIOS did something with it.
>  	 */
> -	if (IS_VALLEYVIEW(encoder->dev))
> +	if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
>  		vlv_initial_power_sequencer_setup(intel_dp);
>  
>  	intel_edp_panel_vdd_sanitize(intel_dp);
> @@ -5293,7 +5293,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>  
>  	/* Haswell doesn't have any port selection bits for the panel
>  	 * power sequencer any more. */
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		port_sel = PANEL_PORT_SELECT_VLV(port);
>  	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
>  		if (port == PORT_A)
> @@ -5405,12 +5405,12 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>  
>  		val = I915_READ(reg);
>  		if (index > DRRS_HIGH_RR) {
> -			if (IS_VALLEYVIEW(dev))
> +			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
>  			else
>  				val |= PIPECONF_EDP_RR_MODE_SWITCH;
>  		} else {
> -			if (IS_VALLEYVIEW(dev))
> +			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
>  			else
>  				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
> @@ -5777,7 +5777,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
>  	}
>  	mutex_unlock(&dev->mode_config.mutex);
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
>  		register_reboot_notifier(&intel_dp->edp_notifier);
>  
> @@ -5825,7 +5825,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  	/* intel_dp vfuncs */
>  	if (INTEL_INFO(dev)->gen >= 9)
>  		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
> -	else if (IS_VALLEYVIEW(dev))
> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
>  	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
> @@ -5860,8 +5860,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  		intel_encoder->type = INTEL_OUTPUT_EDP;
>  
>  	/* eDP only on port B and/or C on vlv/chv */
> -	if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
> -		    port != PORT_B && port != PORT_C))
> +	if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> +		    is_edp(intel_dp) && port != PORT_B && port != PORT_C))
>  		return false;
>  
>  	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
> @@ -5912,7 +5912,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  	if (is_edp(intel_dp)) {
>  		pps_lock(intel_dp);
>  		intel_dp_init_panel_power_timestamps(intel_dp);
> -		if (IS_VALLEYVIEW(dev))
> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  			vlv_initial_power_sequencer_setup(intel_dp);
>  		else
>  			intel_dp_init_panel_power_sequencer(dev, intel_dp);
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 230957f..25bdf1c 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -369,7 +369,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
>  {
>  	struct drm_device *dev = encoder->base.dev;
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		vlv_dsi_device_ready(encoder);
>  	else if (IS_BROXTON(dev))
>  		bxt_dsi_device_ready(encoder);
> @@ -487,7 +487,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
>  
>  	msleep(intel_dsi->panel_on_delay);
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		/*
>  		 * Disable DPOunit clock gating, can stall pipe
>  		 * and we need DPLL REFA always enabled
> @@ -684,8 +684,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>  		 * Enable bit does not get set. To check whether DSI Port C
>  		 * was enabled in BIOS, check the Pipe B enable bit
>  		 */
> -		if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> -		    (port == PORT_C))
> +		if (IS_VALLEYVIEW(dev) && port == PORT_C)
>  			dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
>  							PIPECONF_ENABLE;
>  
> @@ -716,7 +715,8 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
>  
>  	if (IS_BROXTON(encoder->base.dev))
>  		pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
> -	else if (IS_VALLEYVIEW(encoder->base.dev))
> +	else if (IS_VALLEYVIEW(encoder->base.dev) ||
> +		 IS_CHERRYVIEW(encoder->base.dev))
>  		pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
>  
>  	if (!pclk)
> @@ -869,7 +869,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
>  	}
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {
> -		if (IS_VALLEYVIEW(dev)) {
> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  			/*
>  			 * escape clock divider, 20MHz, shared for A and C.
>  			 * device ready must be off when doing this! txclkesc?
> @@ -1129,7 +1129,7 @@ void intel_dsi_init(struct drm_device *dev)
>  	if (!dev_priv->vbt.has_mipi)
>  		return;
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
>  	} else {
>  		DRM_ERROR("Unsupported Mipi device to reg base");
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index cb3cf39..fbd2b51 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -561,7 +561,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder)
>  {
>  	struct drm_device *dev = encoder->base.dev;
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		vlv_enable_dsi_pll(encoder);
>  	else if (IS_BROXTON(dev))
>  		bxt_enable_dsi_pll(encoder);
> @@ -571,7 +571,7 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
>  {
>  	struct drm_device *dev = encoder->base.dev;
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		vlv_disable_dsi_pll(encoder);
>  	else if (IS_BROXTON(dev))
>  		bxt_disable_dsi_pll(encoder);
> @@ -599,6 +599,6 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>  
>  	if (IS_BROXTON(dev))
>  		bxt_dsi_reset_clocks(encoder, port);
> -	else if (IS_VALLEYVIEW(dev))
> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		vlv_dsi_reset_clocks(encoder, port);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index c3978ba..be7fab9 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -638,7 +638,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
>  
>  	if (HAS_DDI(dev_priv))
>  		reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
> -	else if (IS_VALLEYVIEW(dev_priv))
> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
>  	else if (HAS_PCH_SPLIT(dev_priv->dev))
>  		reg = TVIDEO_DIP_GCP(crtc->pipe);
> @@ -2100,7 +2100,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
>  		BUG();
>  	}
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		intel_hdmi->write_infoframe = vlv_write_infoframe;
>  		intel_hdmi->set_infoframes = vlv_set_infoframes;
>  		intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
> diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
> index b177857..a294a3c 100644
> --- a/drivers/gpu/drm/i915/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/intel_hotplug.c
> @@ -407,7 +407,7 @@ void intel_hpd_irq_handler(struct drm_device *dev,
>  			 * hotplug bits itself. So only WARN about unexpected
>  			 * interrupts on saner platforms.
>  			 */
> -			WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
> +			WARN_ONCE(!HAS_GMCH_DISPLAY(dev),
>  				  "Received HPD interrupt on pin %d although disabled\n", i);
>  			continue;
>  		}
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index e26e22a..25254b5 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -636,7 +636,7 @@ int intel_setup_gmbus(struct drm_device *dev)
>  	if (HAS_PCH_NOP(dev))
>  		return 0;
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
>  	else if (!HAS_GMCH_DISPLAY(dev_priv))
>  		dev_priv->gpio_mmio_base =
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index ae808b6..72183a0 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1784,7 +1784,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
>  		panel->backlight.set = pch_set_backlight;
>  		panel->backlight.get = pch_get_backlight;
>  		panel->backlight.hz_to_pwm = pch_hz_to_pwm;
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		if (dev_priv->vbt.has_mipi) {
>  			panel->backlight.setup = pwm_setup_backlight;
>  			panel->backlight.enable = pwm_enable_backlight;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ee05ce8..fe56181 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -291,7 +291,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
>  	struct drm_device *dev = dev_priv->dev;
>  	u32 val;
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
>  		POSTING_READ(FW_BLC_SELF_VLV);
>  		dev_priv->wm.vlv.cxsr = enable;
> @@ -4405,7 +4405,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  	if (dev_priv->rps.enabled) {
> -		if (IS_VALLEYVIEW(dev))
> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  			vlv_set_rps_idle(dev_priv);
>  		else
>  			gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
> @@ -4458,7 +4458,7 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
>  
>  void intel_set_rps(struct drm_device *dev, u8 val)
>  {
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		valleyview_set_rps(dev, val);
>  	else
>  		gen6_set_rps(dev, val);
> @@ -4502,7 +4502,7 @@ static void valleyview_disable_rps(struct drm_device *dev)
>  
>  static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
>  {
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
>  			mode = GEN6_RC_CTL_RC6_ENABLE;
>  		else
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index b6609e6..1778a7d 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -332,8 +332,8 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>  		return false;
>  	}
>  
> -	if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||
> -				    (dig_port->port != PORT_A))) {
> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> +	    ((dev_priv->vbt.psr.full_link) || (dig_port->port != PORT_A))) {
>  		DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n");
>  		return false;
>  	}
> @@ -650,7 +650,7 @@ void intel_psr_single_frame_update(struct drm_device *dev,
>  	 * Single frame update is already supported on BDW+ but it requires
>  	 * many W/A and it isn't really needed.
>  	 */
> -	if (!IS_VALLEYVIEW(dev))
> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
>  		return;
>  
>  	mutex_lock(&dev_priv->psr.lock);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 2b96f33..f8bf622 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -951,7 +951,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
>  	if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
>  		return -EINVAL;
>  
> -	if (IS_VALLEYVIEW(dev) &&
> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>  	    set->flags & I915_SET_COLORKEY_DESTINATION)
>  		return -EINVAL;
>  
> @@ -1086,7 +1086,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
>  			intel_plane->max_downscale = 1;
>  		}
>  
> -		if (IS_VALLEYVIEW(dev)) {
> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  			intel_plane->update_plane = vlv_update_plane;
>  			intel_plane->disable_plane = vlv_disable_plane;
>  
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index c2358ba..fcf04fe 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1115,7 +1115,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
>  		d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
>  	}
>  
> -	if (IS_VALLEYVIEW(dev_priv))
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		d->reg_post = FORCEWAKE_ACK_VLV;
>  	else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
>  		d->reg_post = ECOBUS;
> @@ -1148,7 +1148,7 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
>  			       FORCEWAKE_ACK_BLITTER_GEN9);
>  		fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
>  			       FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
> -	} else if (IS_VALLEYVIEW(dev)) {
> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
>  		if (!IS_CHERRYVIEW(dev))
>  			dev_priv->uncore.funcs.force_wake_put =
> -- 
> 2.6.3

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/5] drm/i915: Separate cherryview from valleyview

[Jani Nikula]

On Wed, 09 Dec 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Dec 09, 2015 at 12:29:35PM -0800, Wayne Boyer wrote:
>> The cherryview device shares many characteristics with the valleyview
>> device.  When support was added to the driver for cherryview, the
>> corresponding device info structure included .is_valleyview = 1.
>> This is not correct and leads to some confusion.
>> 
>> This patch changes .is_valleyview to .is_cherryview in the cherryview
>> device info structure and simplifies the IS_CHERRYVIEW macro.
>> Then where appropriate, instances of IS_VALLEYVIEW are replaced with
>> IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent.
>> 
>> v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro.
>>     Also add followup patches to fix issues discovered during the first
>>     review. (Ville)
>> v3: Fix some style issues and one gen check. Remove CRT related changes
>>     as CRT is not supported on CHV. (Imre, Ville)
>> v4: Make a few more optimizations. (Ville)
>> 
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
>
> lgtm
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Acked-by: Jani Nikula <jani.nikula@intel.com>

For this one I'll let Daniel do the honors to push.


>
>> ---
>>  drivers/gpu/drm/i915/i915_debugfs.c     | 68 ++++++++++++++++-----------------
>>  drivers/gpu/drm/i915/i915_dma.c         | 11 ++----
>>  drivers/gpu/drm/i915/i915_drv.c         | 10 ++---
>>  drivers/gpu/drm/i915/i915_drv.h         | 16 +++++---
>>  drivers/gpu/drm/i915/i915_gem.c         |  4 +-
>>  drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
>>  drivers/gpu/drm/i915/i915_gem_gtt.c     |  3 +-
>>  drivers/gpu/drm/i915/i915_irq.c         |  8 ++--
>>  drivers/gpu/drm/i915/i915_suspend.c     |  4 +-
>>  drivers/gpu/drm/i915/i915_sysfs.c       | 10 ++---
>>  drivers/gpu/drm/i915/intel_audio.c      |  7 ++--
>>  drivers/gpu/drm/i915/intel_display.c    | 54 ++++++++++++++------------
>>  drivers/gpu/drm/i915/intel_dp.c         | 40 +++++++++----------
>>  drivers/gpu/drm/i915/intel_dsi.c        | 14 +++----
>>  drivers/gpu/drm/i915/intel_dsi_pll.c    |  6 +--
>>  drivers/gpu/drm/i915/intel_hdmi.c       |  4 +-
>>  drivers/gpu/drm/i915/intel_hotplug.c    |  2 +-
>>  drivers/gpu/drm/i915/intel_i2c.c        |  2 +-
>>  drivers/gpu/drm/i915/intel_panel.c      |  2 +-
>>  drivers/gpu/drm/i915/intel_pm.c         |  8 ++--
>>  drivers/gpu/drm/i915/intel_psr.c        |  6 +--
>>  drivers/gpu/drm/i915/intel_sprite.c     |  4 +-
>>  drivers/gpu/drm/i915/intel_uncore.c     |  4 +-
>>  23 files changed, 147 insertions(+), 142 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index a8721fc..fff31253 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1142,8 +1142,34 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>>  			   MEMSTAT_VID_SHIFT);
>>  		seq_printf(m, "Current P-state: %d\n",
>>  			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
>> -	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
>> -		   IS_BROADWELL(dev) || IS_GEN9(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>> +		u32 freq_sts;
>> +
>> +		mutex_lock(&dev_priv->rps.hw_lock);
>> +		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>> +		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
>> +		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
>> +
>> +		seq_printf(m, "actual GPU freq: %d MHz\n",
>> +			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
>> +
>> +		seq_printf(m, "current GPU freq: %d MHz\n",
>> +			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
>> +
>> +		seq_printf(m, "max GPU freq: %d MHz\n",
>> +			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
>> +
>> +		seq_printf(m, "min GPU freq: %d MHz\n",
>> +			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
>> +
>> +		seq_printf(m, "idle GPU freq: %d MHz\n",
>> +			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
>> +
>> +		seq_printf(m,
>> +			   "efficient (RPe) frequency: %d MHz\n",
>> +			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
>> +		mutex_unlock(&dev_priv->rps.hw_lock);
>> +	} else if (INTEL_INFO(dev)->gen >= 6) {
>>  		u32 rp_state_limits;
>>  		u32 gt_perf_status;
>>  		u32 rp_state_cap;
>> @@ -1284,33 +1310,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>>  		seq_printf(m,
>>  			   "efficient (RPe) frequency: %d MHz\n",
>>  			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> -		u32 freq_sts;
>> -
>> -		mutex_lock(&dev_priv->rps.hw_lock);
>> -		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>> -		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
>> -		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
>> -
>> -		seq_printf(m, "actual GPU freq: %d MHz\n",
>> -			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
>> -
>> -		seq_printf(m, "current GPU freq: %d MHz\n",
>> -			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
>> -
>> -		seq_printf(m, "max GPU freq: %d MHz\n",
>> -			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
>> -
>> -		seq_printf(m, "min GPU freq: %d MHz\n",
>> -			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
>> -
>> -		seq_printf(m, "idle GPU freq: %d MHz\n",
>> -			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
>> -
>> -		seq_printf(m,
>> -			   "efficient (RPe) frequency: %d MHz\n",
>> -			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
>> -		mutex_unlock(&dev_priv->rps.hw_lock);
>>  	} else {
>>  		seq_puts(m, "no P-state info available\n");
>>  	}
>> @@ -1602,7 +1601,7 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
>>  	struct drm_info_node *node = m->private;
>>  	struct drm_device *dev = node->minor->dev;
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		return vlv_drpc_info(m);
>>  	else if (INTEL_INFO(dev)->gen >= 6)
>>  		return gen6_drpc_info(m);
>> @@ -1743,7 +1742,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>>  		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
>>  	else if (IS_PINEVIEW(dev))
>>  		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
>> -	else if (IS_VALLEYVIEW(dev))
>> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>>  
>>  	intel_runtime_pm_put(dev_priv);
>> @@ -3983,7 +3982,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
>>  		ret = i8xx_pipe_crc_ctl_reg(&source, &val);
>>  	else if (INTEL_INFO(dev)->gen < 5)
>>  		ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
>> -	else if (IS_VALLEYVIEW(dev))
>> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
>>  	else if (IS_GEN5(dev) || IS_GEN6(dev))
>>  		ret = ilk_pipe_crc_ctl_reg(&source, &val);
>> @@ -4052,7 +4051,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
>>  
>>  		if (IS_G4X(dev))
>>  			g4x_undo_pipe_scramble_reset(dev, pipe);
>> -		else if (IS_VALLEYVIEW(dev))
>> +		else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  			vlv_undo_pipe_scramble_reset(dev, pipe);
>>  		else if (IS_HASWELL(dev) && pipe == PIPE_A)
>>  			hsw_trans_edp_pipe_A_crc_wa(dev, false);
>> @@ -4442,7 +4441,8 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
>>  		 * - WM1+ latency values in 0.5us units
>>  		 * - latencies are in us on gen9/vlv/chv
>>  		 */
>> -		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
>> +		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
>> +		    IS_CHERRYVIEW(dev))
>>  			latency *= 10;
>>  		else if (level > 0)
>>  			latency *= 5;
>> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
>> index a81c766..083e2c0 100644
>> --- a/drivers/gpu/drm/i915/i915_dma.c
>> +++ b/drivers/gpu/drm/i915/i915_dma.c
>> @@ -256,7 +256,7 @@ intel_setup_mchbar(struct drm_device *dev)
>>  	u32 temp;
>>  	bool enabled;
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		return;
>>  
>>  	dev_priv->mchbar_need_disable = false;
>> @@ -779,7 +779,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>>  		info->num_sprites[PIPE_A] = 2;
>>  		info->num_sprites[PIPE_B] = 2;
>>  		info->num_sprites[PIPE_C] = 1;
>> -	} else if (IS_VALLEYVIEW(dev))
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		for_each_pipe(dev_priv, pipe)
>>  			info->num_sprites[pipe] = 2;
>>  	else
>> @@ -791,7 +791,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>>  		info->num_pipes = 0;
>>  	} else if (info->num_pipes > 0 &&
>>  		   (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
>> -		   !IS_VALLEYVIEW(dev)) {
>> +		   !(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) {
>>  		u32 fuse_strap = I915_READ(FUSE_STRAP);
>>  		u32 sfuse_strap = I915_READ(SFUSE_STRAP);
>>  
>> @@ -836,9 +836,6 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>>  
>>  static void intel_init_dpio(struct drm_i915_private *dev_priv)
>>  {
>> -	if (!IS_VALLEYVIEW(dev_priv))
>> -		return;
>> -
>>  	/*
>>  	 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
>>  	 * CHV x1 PHY (DP/HDMI D)
>> @@ -847,7 +844,7 @@ static void intel_init_dpio(struct drm_i915_private *dev_priv)
>>  	if (IS_CHERRYVIEW(dev_priv)) {
>>  		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
>>  		DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
>> -	} else {
>> +	} else if (IS_VALLEYVIEW(dev_priv)) {
>>  		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
>>  	}
>>  }
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index e6935f1..1fbbe8e 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -311,7 +311,7 @@ static const struct intel_device_info intel_cherryview_info = {
>>  	.gen = 8, .num_pipes = 3,
>>  	.need_gfx_hws = 1, .has_hotplug = 1,
>>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>> -	.is_valleyview = 1,
>> +	.is_cherryview = 1,
>>  	.display_mmio_offset = VLV_DISPLAY_BASE,
>>  	GEN_CHV_PIPEOFFSETS,
>>  	CURSOR_OFFSETS,
>> @@ -802,7 +802,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
>>  
>>  	pci_set_master(dev->pdev);
>>  
>> -	if (IS_VALLEYVIEW(dev_priv))
>> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		ret = vlv_resume_prepare(dev_priv, false);
>>  	if (ret)
>>  		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
>> @@ -1532,7 +1532,7 @@ static int intel_runtime_resume(struct device *device)
>>  		ret = bxt_resume_prepare(dev_priv);
>>  	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>>  		hsw_disable_pc8(dev_priv);
>> -	else if (IS_VALLEYVIEW(dev_priv))
>> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		ret = vlv_resume_prepare(dev_priv, true);
>>  
>>  	/*
>> @@ -1549,7 +1549,7 @@ static int intel_runtime_resume(struct device *device)
>>  	 * power well, so hpd is reinitialized from there. For
>>  	 * everyone else do it here.
>>  	 */
>> -	if (!IS_VALLEYVIEW(dev_priv))
>> +	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
>>  		intel_hpd_init(dev_priv);
>>  
>>  	intel_enable_gt_powersave(dev);
>> @@ -1574,7 +1574,7 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv)
>>  		ret = bxt_suspend_complete(dev_priv);
>>  	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>>  		ret = hsw_suspend_complete(dev_priv);
>> -	else if (IS_VALLEYVIEW(dev_priv))
>> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		ret = vlv_suspend_complete(dev_priv);
>>  	else
>>  		ret = 0;
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index f1a8a53..3899f23 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -763,6 +763,7 @@ struct intel_csr {
>>  	func(is_crestline) sep \
>>  	func(is_ivybridge) sep \
>>  	func(is_valleyview) sep \
>> +	func(is_cherryview) sep \
>>  	func(is_haswell) sep \
>>  	func(is_skylake) sep \
>>  	func(is_broxton) sep \
>> @@ -2455,9 +2456,9 @@ struct drm_i915_cmd_table {
>>  				 INTEL_DEVID(dev) == 0x0152 || \
>>  				 INTEL_DEVID(dev) == 0x015a)
>>  #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
>> -#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
>> +#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
>>  #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
>> -#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
>> +#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
>>  #define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
>>  #define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
>>  #define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
>> @@ -2584,7 +2585,8 @@ struct drm_i915_cmd_table {
>>  				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
>>  #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
>>  				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
>> -				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
>> +				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
>> +				 IS_KABYLAKE(dev))
>>  #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
>>  #define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
>>  
>> @@ -2597,7 +2599,8 @@ struct drm_i915_cmd_table {
>>  				    INTEL_INFO(dev)->gen >= 8)
>>  
>>  #define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
>> -				 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
>> +				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
>> +				 !IS_BROXTON(dev))
>>  
>>  #define INTEL_PCH_DEVICE_ID_MASK		0xff00
>>  #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
>> @@ -2620,7 +2623,8 @@ struct drm_i915_cmd_table {
>>  #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
>>  #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
>>  
>> -#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
>> +#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
>> +			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  
>>  /* DPF == dynamic parity feature */
>>  #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
>> @@ -3511,7 +3515,7 @@ __raw_write(64, q)
>>  
>>  static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
>>  {
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		return VLV_VGACNTRL;
>>  	else if (INTEL_INFO(dev)->gen >= 5)
>>  		return CPU_VGACNTRL;
>> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
>> index dfaf25b..e96e496 100644
>> --- a/drivers/gpu/drm/i915/i915_gem.c
>> +++ b/drivers/gpu/drm/i915/i915_gem.c
>> @@ -4838,7 +4838,7 @@ int i915_gem_init(struct drm_device *dev)
>>  
>>  	mutex_lock(&dev->struct_mutex);
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		/* VLVA0 (potential hack), BIOS isn't actually waking us */
>>  		I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
>>  		if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
>> @@ -4963,7 +4963,7 @@ i915_gem_load(struct drm_device *dev)
>>  
>>  	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
>>  
>> -	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
>> +	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
>>  		dev_priv->num_fence_regs = 32;
>>  	else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
>>  		dev_priv->num_fence_regs = 16;
>> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
>> index 43761c5..4b1161d 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
>> @@ -190,7 +190,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
>>  	 * would make the object snooped which might have a
>>  	 * negative performance impact.
>>  	 */
>> -	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) {
>> +	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>>  		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
>>  		/* Failure shouldn't ever happen this early */
>>  		if (WARN_ON(ret)) {
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index 1f7e6b9..963d9b6 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -140,8 +140,7 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
>>  #endif
>>  
>>  	/* Early VLV doesn't have this */
>> -	if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
>> -	    dev->pdev->revision < 0xb) {
>> +	if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) {
>>  		DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
>>  		return 0;
>>  	}
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index e88d692..86664d1 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -581,7 +581,7 @@ i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
>>  {
>>  	u32 enable_mask;
>>  
>> -	if (IS_VALLEYVIEW(dev_priv->dev))
>> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
>>  							   status_mask);
>>  	else
>> @@ -595,7 +595,7 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
>>  {
>>  	u32 enable_mask;
>>  
>> -	if (IS_VALLEYVIEW(dev_priv->dev))
>> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
>>  							   status_mask);
>>  	else
>> @@ -1723,7 +1723,7 @@ static void i9xx_hpd_irq_handler(struct drm_device *dev)
>>  	 */
>>  	POSTING_READ(PORT_HOTPLUG_STAT);
>>  
>> -	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
>> +	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
>>  
>>  		if (hotplug_trigger) {
>> @@ -4412,7 +4412,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>>  	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
>>  
>>  	/* Let's track the enabled rps events */
>> -	if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
>> +	if (IS_VALLEYVIEW(dev_priv))
>>  		/* WaGsvRC0ResidencyMethod:vlv */
>>  		dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
>>  	else
>> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
>> index 2d91821..a2aa09c 100644
>> --- a/drivers/gpu/drm/i915/i915_suspend.c
>> +++ b/drivers/gpu/drm/i915/i915_suspend.c
>> @@ -49,7 +49,7 @@ static void i915_save_display(struct drm_device *dev)
>>  		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
>>  		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
>>  		dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
>> -	} else if (!IS_VALLEYVIEW(dev)) {
>> +	} else if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>>  		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
>>  		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
>>  		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
>> @@ -84,7 +84,7 @@ static void i915_restore_display(struct drm_device *dev)
>>  		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
>>  		I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
>>  		I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
>> -	} else if (!IS_VALLEYVIEW(dev)) {
>> +	} else if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>>  		I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
>>  		I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
>>  		I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
>> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
>> index f929c61..37e3f0d 100644
>> --- a/drivers/gpu/drm/i915/i915_sysfs.c
>> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
>> @@ -49,7 +49,7 @@ static u32 calc_residency(struct drm_device *dev,
>>  	intel_runtime_pm_get(dev_priv);
>>  
>>  	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		units = 1;
>>  		div = dev_priv->czclk_freq;
>>  
>> @@ -284,7 +284,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
>>  	intel_runtime_pm_get(dev_priv);
>>  
>>  	mutex_lock(&dev_priv->rps.hw_lock);
>> -	if (IS_VALLEYVIEW(dev_priv->dev)) {
>> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>>  		u32 freq;
>>  		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>>  		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
>> @@ -598,7 +598,7 @@ void i915_setup_sysfs(struct drm_device *dev)
>>  		if (ret)
>>  			DRM_ERROR("RC6p residency sysfs setup failed\n");
>>  	}
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		ret = sysfs_merge_group(&dev->primary->kdev->kobj,
>>  					&media_rc6_attr_group);
>>  		if (ret)
>> @@ -619,7 +619,7 @@ void i915_setup_sysfs(struct drm_device *dev)
>>  	}
>>  
>>  	ret = 0;
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs);
>>  	else if (INTEL_INFO(dev)->gen >= 6)
>>  		ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs);
>> @@ -635,7 +635,7 @@ void i915_setup_sysfs(struct drm_device *dev)
>>  void i915_teardown_sysfs(struct drm_device *dev)
>>  {
>>  	sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr);
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs);
>>  	else
>>  		sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs);
>> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
>> index 9aa83e7..06fffae 100644
>> --- a/drivers/gpu/drm/i915/intel_audio.c
>> +++ b/drivers/gpu/drm/i915/intel_audio.c
>> @@ -375,7 +375,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder)
>>  	if (HAS_PCH_IBX(dev_priv->dev)) {
>>  		aud_config = IBX_AUD_CFG(pipe);
>>  		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
>> -	} else if (IS_VALLEYVIEW(dev_priv)) {
>> +	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>>  		aud_config = VLV_AUD_CFG(pipe);
>>  		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
>>  	} else {
>> @@ -435,7 +435,8 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
>>  		aud_config = IBX_AUD_CFG(pipe);
>>  		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
>>  		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
>> -	} else if (IS_VALLEYVIEW(connector->dev)) {
>> +	} else if (IS_VALLEYVIEW(connector->dev) ||
>> +		   IS_CHERRYVIEW(connector->dev)) {
>>  		hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
>>  		aud_config = VLV_AUD_CFG(pipe);
>>  		aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
>> @@ -559,7 +560,7 @@ void intel_init_audio(struct drm_device *dev)
>>  	if (IS_G4X(dev)) {
>>  		dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
>>  		dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
>>  		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
>>  	} else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index b59a2d8..d3b643b 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -187,7 +187,7 @@ int intel_hrawclk(struct drm_device *dev)
>>  	uint32_t clkcfg;
>>  
>>  	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		return 200;
>>  
>>  	clkcfg = I915_READ(CLKCFG);
>> @@ -215,7 +215,7 @@ int intel_hrawclk(struct drm_device *dev)
>>  
>>  static void intel_update_czclk(struct drm_i915_private *dev_priv)
>>  {
>> -	if (!IS_VALLEYVIEW(dev_priv))
>> +	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
>>  		return;
>>  
>>  	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
>> @@ -716,11 +716,12 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
>>  	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
>>  		INTELPllInvalid("m1 out of range\n");
>>  
>> -	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
>> +	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
>> +	    !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
>>  		if (clock->m1 <= clock->m2)
>>  			INTELPllInvalid("m1 <= m2\n");
>>  
>> -	if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
>> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
>>  		if (clock->p < limit->p.min || limit->p.max < clock->p)
>>  			INTELPllInvalid("p out of range\n");
>>  		if (clock->m < limit->m.min || limit->m.max < clock->m)
>> @@ -1305,7 +1306,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv,
>>  		    I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
>>  			panel_pipe = PIPE_B;
>>  		/* XXX: else fix for eDP */
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		/* presumably write lock depends on pipe, not port select */
>>  		pp_reg = VLV_PIPE_PP_CONTROL(pipe);
>>  		panel_pipe = pipe;
>> @@ -1423,7 +1424,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
>>  			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
>>  			     sprite, pipe_name(pipe));
>>  		}
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		for_each_sprite(dev_priv, pipe, sprite) {
>>  			u32 val = I915_READ(SPCNTR(pipe, sprite));
>>  			I915_STATE_WARN(val & SP_ENABLE,
>> @@ -2319,7 +2320,7 @@ static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
>>  	if (INTEL_INFO(dev_priv)->gen >= 9)
>>  		return 256 * 1024;
>>  	else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
>> -		 IS_VALLEYVIEW(dev_priv))
>> +		 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		return 128 * 1024;
>>  	else if (INTEL_INFO(dev_priv)->gen >= 4)
>>  		return 4 * 1024;
>> @@ -5455,7 +5456,7 @@ static void intel_update_cdclk(struct drm_device *dev)
>>  	 * BSpec erroneously claims we should aim for 4MHz, but
>>  	 * in fact 1MHz is the correct frequency.
>>  	 */
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		/*
>>  		 * Program the gmbus_freq based on the cdclk frequency.
>>  		 * BSpec erroneously claims we should aim for 4MHz, but
>> @@ -7180,7 +7181,7 @@ static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
>>  
>>  	WARN_ON(!crtc_state->base.state);
>>  
>> -	if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
>>  		refclk = 100000;
>>  	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
>>  	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
>> @@ -7879,7 +7880,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
>>  		pipeconf |= PIPECONF_DOUBLE_WIDE;
>>  
>>  	/* only g4x and later have fancy bpc/dither controls */
>> -	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
>> +	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		/* Bspec claims that we can't use dithering for 30bpp pipes. */
>>  		if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
>>  			pipeconf |= PIPECONF_DITHER_EN |
>> @@ -7919,7 +7920,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
>>  	} else
>>  		pipeconf |= PIPECONF_PROGRESSIVE;
>>  
>> -	if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
>> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>> +	     intel_crtc->config->limited_color_range)
>>  		pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
>>  
>>  	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
>> @@ -8166,7 +8168,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>>  	if (!(tmp & PIPECONF_ENABLE))
>>  		return false;
>>  
>> -	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
>> +	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		switch (tmp & PIPECONF_BPC_MASK) {
>>  		case PIPECONF_6BPC:
>>  			pipe_config->pipe_bpp = 18;
>> @@ -8182,7 +8184,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>>  		}
>>  	}
>>  
>> -	if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
>> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>> +	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
>>  		pipe_config->limited_color_range = true;
>>  
>>  	if (INTEL_INFO(dev)->gen < 4)
>> @@ -8210,7 +8213,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>>  		pipe_config->pixel_multiplier = 1;
>>  	}
>>  	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
>> -	if (!IS_VALLEYVIEW(dev)) {
>> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>>  		/*
>>  		 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
>>  		 * on 830. Filter it out here so that we don't
>> @@ -11537,7 +11540,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>>  	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
>>  		work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		ring = &dev_priv->ring[BCS];
>>  		if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
>>  			/* vlv: DISPLAY_FLIP fails to change tiling */
>> @@ -12016,7 +12019,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
>>  	struct drm_connector_state *connector_state;
>>  	int bpp, i;
>>  
>> -	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
>> +	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
>>  		bpp = 10*3;
>>  	else if (INTEL_INFO(dev)->gen >= 5)
>>  		bpp = 12*3;
>> @@ -12626,7 +12629,7 @@ intel_pipe_config_compare(struct drm_device *dev,
>>  	PIPE_CONF_CHECK_I(pixel_multiplier);
>>  	PIPE_CONF_CHECK_I(has_hdmi_sink);
>>  	if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
>> -	    IS_VALLEYVIEW(dev))
>> +	    IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		PIPE_CONF_CHECK_I(limited_color_range);
>>  	PIPE_CONF_CHECK_I(has_infoframe);
>>  
>> @@ -14378,7 +14381,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>>  
>>  		if (I915_READ(PCH_DP_D) & DP_DETECTED)
>>  			intel_dp_init(dev, PCH_DP_D, PORT_D);
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		/*
>>  		 * The DP_DETECTED bit is the latched state of the DDC
>>  		 * SDA pin at boot. However since eDP doesn't require DDC
>> @@ -14527,7 +14530,7 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
>>  		 *  pixels and 32K bytes."
>>  		 */
>>  		 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
>> -	} else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
>> +	} else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>>  		return 32*1024;
>>  	} else if (gen >= 4) {
>>  		if (fb_modifier == I915_FORMAT_MOD_X_TILED)
>> @@ -14631,7 +14634,8 @@ static int intel_framebuffer_init(struct drm_device *dev,
>>  		}
>>  		break;
>>  	case DRM_FORMAT_ABGR8888:
>> -		if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
>> +		if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
>> +		    INTEL_INFO(dev)->gen < 9) {
>>  			DRM_DEBUG("unsupported pixel format: %s\n",
>>  				  drm_get_format_name(mode_cmd->pixel_format));
>>  			return -EINVAL;
>> @@ -14647,7 +14651,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
>>  		}
>>  		break;
>>  	case DRM_FORMAT_ABGR2101010:
>> -		if (!IS_VALLEYVIEW(dev)) {
>> +		if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
>>  			DRM_DEBUG("unsupported pixel format: %s\n",
>>  				  drm_get_format_name(mode_cmd->pixel_format));
>>  			return -EINVAL;
>> @@ -14775,7 +14779,7 @@ static void intel_init_display(struct drm_device *dev)
>>  		dev_priv->display.crtc_disable = ironlake_crtc_disable;
>>  		dev_priv->display.update_primary_plane =
>>  			ironlake_update_primary_plane;
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
>>  		dev_priv->display.get_initial_plane_config =
>>  			i9xx_get_initial_plane_config;
>> @@ -14808,7 +14812,7 @@ static void intel_init_display(struct drm_device *dev)
>>  	else if (IS_HASWELL(dev))
>>  		dev_priv->display.get_display_clock_speed =
>>  			haswell_get_display_clock_speed;
>> -	else if (IS_VALLEYVIEW(dev))
>> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		dev_priv->display.get_display_clock_speed =
>>  			valleyview_get_display_clock_speed;
>>  	else if (IS_GEN5(dev))
>> @@ -14866,7 +14870,7 @@ static void intel_init_display(struct drm_device *dev)
>>  			dev_priv->display.modeset_calc_cdclk =
>>  				broadwell_modeset_calc_cdclk;
>>  		}
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		dev_priv->display.modeset_commit_cdclk =
>>  			valleyview_modeset_commit_cdclk;
>>  		dev_priv->display.modeset_calc_cdclk =
>> @@ -15640,7 +15644,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
>>  		pll->on = false;
>>  	}
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		vlv_wm_get_hw_state(dev);
>>  	else if (IS_GEN9(dev))
>>  		skl_wm_get_hw_state(dev);
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index f335c92..1edeb3e 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -517,7 +517,7 @@ void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
>>  	struct drm_device *dev = dev_priv->dev;
>>  	struct intel_encoder *encoder;
>>  
>> -	if (WARN_ON(!IS_VALLEYVIEW(dev)))
>> +	if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)))
>>  		return;
>>  
>>  	/*
>> @@ -582,7 +582,7 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
>>  
>>  	pps_lock(intel_dp);
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
>>  		i915_reg_t pp_ctrl_reg, pp_div_reg;
>>  		u32 pp_div;
>> @@ -610,7 +610,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
>>  
>>  	lockdep_assert_held(&dev_priv->pps_mutex);
>>  
>> -	if (IS_VALLEYVIEW(dev) &&
>> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>>  	    intel_dp->pps_pipe == INVALID_PIPE)
>>  		return false;
>>  
>> @@ -624,7 +624,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>>  
>>  	lockdep_assert_held(&dev_priv->pps_mutex);
>>  
>> -	if (IS_VALLEYVIEW(dev) &&
>> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>>  	    intel_dp->pps_pipe == INVALID_PIPE)
>>  		return false;
>>  
>> @@ -1723,7 +1723,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
>>  		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
>>  	} else {
>>  		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
>> -		    crtc->config->limited_color_range)
>> +		    !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
>>  			intel_dp->DP |= DP_COLOR_RANGE_16_235;
>>  
>>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
>> @@ -2418,7 +2418,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
>>  	pipe_config->base.adjusted_mode.flags |= flags;
>>  
>>  	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
>> -	    tmp & DP_COLOR_RANGE_16_235)
>> +	    !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
>>  		pipe_config->limited_color_range = true;
>>  
>>  	pipe_config->has_dp_encoder = true;
>> @@ -2694,7 +2694,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
>>  
>>  	pps_lock(intel_dp);
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		vlv_init_panel_power_sequencer(intel_dp);
>>  
>>  	/*
>> @@ -2728,7 +2728,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
>>  
>>  	pps_unlock(intel_dp);
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		unsigned int lane_mask = 0x0;
>>  
>>  		if (IS_CHERRYVIEW(dev))
>> @@ -3218,7 +3218,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>>  		if (dev_priv->edp_low_vswing && port == PORT_A)
>>  			return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
>> -	} else if (IS_VALLEYVIEW(dev))
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>>  	else if (IS_GEN7(dev) && port == PORT_A)
>>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
>> @@ -3259,7 +3259,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>>  		default:
>>  			return DP_TRAIN_PRE_EMPH_LEVEL_0;
>>  		}
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>>  		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>>  			return DP_TRAIN_PRE_EMPH_LEVEL_3;
>> @@ -4539,7 +4539,7 @@ bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
>>  		return cpt_digital_port_connected(dev_priv, port);
>>  	else if (IS_BROXTON(dev_priv))
>>  		return bxt_digital_port_connected(dev_priv, port);
>> -	else if (IS_VALLEYVIEW(dev_priv))
>> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		return vlv_digital_port_connected(dev_priv, port);
>>  	else
>>  		return g4x_digital_port_connected(dev_priv, port);
>> @@ -4933,7 +4933,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
>>  	 * Read out the current power sequencer assignment,
>>  	 * in case the BIOS did something with it.
>>  	 */
>> -	if (IS_VALLEYVIEW(encoder->dev))
>> +	if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
>>  		vlv_initial_power_sequencer_setup(intel_dp);
>>  
>>  	intel_edp_panel_vdd_sanitize(intel_dp);
>> @@ -5293,7 +5293,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>>  
>>  	/* Haswell doesn't have any port selection bits for the panel
>>  	 * power sequencer any more. */
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		port_sel = PANEL_PORT_SELECT_VLV(port);
>>  	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
>>  		if (port == PORT_A)
>> @@ -5405,12 +5405,12 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>>  
>>  		val = I915_READ(reg);
>>  		if (index > DRRS_HIGH_RR) {
>> -			if (IS_VALLEYVIEW(dev))
>> +			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
>>  			else
>>  				val |= PIPECONF_EDP_RR_MODE_SWITCH;
>>  		} else {
>> -			if (IS_VALLEYVIEW(dev))
>> +			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
>>  			else
>>  				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
>> @@ -5777,7 +5777,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
>>  	}
>>  	mutex_unlock(&dev->mode_config.mutex);
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
>>  		register_reboot_notifier(&intel_dp->edp_notifier);
>>  
>> @@ -5825,7 +5825,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>>  	/* intel_dp vfuncs */
>>  	if (INTEL_INFO(dev)->gen >= 9)
>>  		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
>> -	else if (IS_VALLEYVIEW(dev))
>> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
>>  	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>>  		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
>> @@ -5860,8 +5860,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>>  		intel_encoder->type = INTEL_OUTPUT_EDP;
>>  
>>  	/* eDP only on port B and/or C on vlv/chv */
>> -	if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
>> -		    port != PORT_B && port != PORT_C))
>> +	if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>> +		    is_edp(intel_dp) && port != PORT_B && port != PORT_C))
>>  		return false;
>>  
>>  	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
>> @@ -5912,7 +5912,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>>  	if (is_edp(intel_dp)) {
>>  		pps_lock(intel_dp);
>>  		intel_dp_init_panel_power_timestamps(intel_dp);
>> -		if (IS_VALLEYVIEW(dev))
>> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  			vlv_initial_power_sequencer_setup(intel_dp);
>>  		else
>>  			intel_dp_init_panel_power_sequencer(dev, intel_dp);
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index 230957f..25bdf1c 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -369,7 +369,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
>>  {
>>  	struct drm_device *dev = encoder->base.dev;
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		vlv_dsi_device_ready(encoder);
>>  	else if (IS_BROXTON(dev))
>>  		bxt_dsi_device_ready(encoder);
>> @@ -487,7 +487,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
>>  
>>  	msleep(intel_dsi->panel_on_delay);
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		/*
>>  		 * Disable DPOunit clock gating, can stall pipe
>>  		 * and we need DPLL REFA always enabled
>> @@ -684,8 +684,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>>  		 * Enable bit does not get set. To check whether DSI Port C
>>  		 * was enabled in BIOS, check the Pipe B enable bit
>>  		 */
>> -		if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
>> -		    (port == PORT_C))
>> +		if (IS_VALLEYVIEW(dev) && port == PORT_C)
>>  			dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
>>  							PIPECONF_ENABLE;
>>  
>> @@ -716,7 +715,8 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
>>  
>>  	if (IS_BROXTON(encoder->base.dev))
>>  		pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
>> -	else if (IS_VALLEYVIEW(encoder->base.dev))
>> +	else if (IS_VALLEYVIEW(encoder->base.dev) ||
>> +		 IS_CHERRYVIEW(encoder->base.dev))
>>  		pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
>>  
>>  	if (!pclk)
>> @@ -869,7 +869,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
>>  	}
>>  
>>  	for_each_dsi_port(port, intel_dsi->ports) {
>> -		if (IS_VALLEYVIEW(dev)) {
>> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  			/*
>>  			 * escape clock divider, 20MHz, shared for A and C.
>>  			 * device ready must be off when doing this! txclkesc?
>> @@ -1129,7 +1129,7 @@ void intel_dsi_init(struct drm_device *dev)
>>  	if (!dev_priv->vbt.has_mipi)
>>  		return;
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
>>  	} else {
>>  		DRM_ERROR("Unsupported Mipi device to reg base");
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> index cb3cf39..fbd2b51 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> @@ -561,7 +561,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder)
>>  {
>>  	struct drm_device *dev = encoder->base.dev;
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		vlv_enable_dsi_pll(encoder);
>>  	else if (IS_BROXTON(dev))
>>  		bxt_enable_dsi_pll(encoder);
>> @@ -571,7 +571,7 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
>>  {
>>  	struct drm_device *dev = encoder->base.dev;
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		vlv_disable_dsi_pll(encoder);
>>  	else if (IS_BROXTON(dev))
>>  		bxt_disable_dsi_pll(encoder);
>> @@ -599,6 +599,6 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>>  
>>  	if (IS_BROXTON(dev))
>>  		bxt_dsi_reset_clocks(encoder, port);
>> -	else if (IS_VALLEYVIEW(dev))
>> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		vlv_dsi_reset_clocks(encoder, port);
>>  }
>> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
>> index c3978ba..be7fab9 100644
>> --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> @@ -638,7 +638,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
>>  
>>  	if (HAS_DDI(dev_priv))
>>  		reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
>> -	else if (IS_VALLEYVIEW(dev_priv))
>> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
>>  	else if (HAS_PCH_SPLIT(dev_priv->dev))
>>  		reg = TVIDEO_DIP_GCP(crtc->pipe);
>> @@ -2100,7 +2100,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
>>  		BUG();
>>  	}
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		intel_hdmi->write_infoframe = vlv_write_infoframe;
>>  		intel_hdmi->set_infoframes = vlv_set_infoframes;
>>  		intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
>> diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
>> index b177857..a294a3c 100644
>> --- a/drivers/gpu/drm/i915/intel_hotplug.c
>> +++ b/drivers/gpu/drm/i915/intel_hotplug.c
>> @@ -407,7 +407,7 @@ void intel_hpd_irq_handler(struct drm_device *dev,
>>  			 * hotplug bits itself. So only WARN about unexpected
>>  			 * interrupts on saner platforms.
>>  			 */
>> -			WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
>> +			WARN_ONCE(!HAS_GMCH_DISPLAY(dev),
>>  				  "Received HPD interrupt on pin %d although disabled\n", i);
>>  			continue;
>>  		}
>> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
>> index e26e22a..25254b5 100644
>> --- a/drivers/gpu/drm/i915/intel_i2c.c
>> +++ b/drivers/gpu/drm/i915/intel_i2c.c
>> @@ -636,7 +636,7 @@ int intel_setup_gmbus(struct drm_device *dev)
>>  	if (HAS_PCH_NOP(dev))
>>  		return 0;
>>  
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
>>  	else if (!HAS_GMCH_DISPLAY(dev_priv))
>>  		dev_priv->gpio_mmio_base =
>> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
>> index ae808b6..72183a0 100644
>> --- a/drivers/gpu/drm/i915/intel_panel.c
>> +++ b/drivers/gpu/drm/i915/intel_panel.c
>> @@ -1784,7 +1784,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
>>  		panel->backlight.set = pch_set_backlight;
>>  		panel->backlight.get = pch_get_backlight;
>>  		panel->backlight.hz_to_pwm = pch_hz_to_pwm;
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		if (dev_priv->vbt.has_mipi) {
>>  			panel->backlight.setup = pwm_setup_backlight;
>>  			panel->backlight.enable = pwm_enable_backlight;
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index ee05ce8..fe56181 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -291,7 +291,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
>>  	struct drm_device *dev = dev_priv->dev;
>>  	u32 val;
>>  
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
>>  		POSTING_READ(FW_BLC_SELF_VLV);
>>  		dev_priv->wm.vlv.cxsr = enable;
>> @@ -4405,7 +4405,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
>>  
>>  	mutex_lock(&dev_priv->rps.hw_lock);
>>  	if (dev_priv->rps.enabled) {
>> -		if (IS_VALLEYVIEW(dev))
>> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  			vlv_set_rps_idle(dev_priv);
>>  		else
>>  			gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
>> @@ -4458,7 +4458,7 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
>>  
>>  void intel_set_rps(struct drm_device *dev, u8 val)
>>  {
>> -	if (IS_VALLEYVIEW(dev))
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  		valleyview_set_rps(dev, val);
>>  	else
>>  		gen6_set_rps(dev, val);
>> @@ -4502,7 +4502,7 @@ static void valleyview_disable_rps(struct drm_device *dev)
>>  
>>  static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
>>  {
>> -	if (IS_VALLEYVIEW(dev)) {
>> +	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
>>  			mode = GEN6_RC_CTL_RC6_ENABLE;
>>  		else
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index b6609e6..1778a7d 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -332,8 +332,8 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>>  		return false;
>>  	}
>>  
>> -	if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||
>> -				    (dig_port->port != PORT_A))) {
>> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
>> +	    ((dev_priv->vbt.psr.full_link) || (dig_port->port != PORT_A))) {
>>  		DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n");
>>  		return false;
>>  	}
>> @@ -650,7 +650,7 @@ void intel_psr_single_frame_update(struct drm_device *dev,
>>  	 * Single frame update is already supported on BDW+ but it requires
>>  	 * many W/A and it isn't really needed.
>>  	 */
>> -	if (!IS_VALLEYVIEW(dev))
>> +	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
>>  		return;
>>  
>>  	mutex_lock(&dev_priv->psr.lock);
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
>> index 2b96f33..f8bf622 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -951,7 +951,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
>>  	if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
>>  		return -EINVAL;
>>  
>> -	if (IS_VALLEYVIEW(dev) &&
>> +	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
>>  	    set->flags & I915_SET_COLORKEY_DESTINATION)
>>  		return -EINVAL;
>>  
>> @@ -1086,7 +1086,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
>>  			intel_plane->max_downscale = 1;
>>  		}
>>  
>> -		if (IS_VALLEYVIEW(dev)) {
>> +		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  			intel_plane->update_plane = vlv_update_plane;
>>  			intel_plane->disable_plane = vlv_disable_plane;
>>  
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>> index c2358ba..fcf04fe 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -1115,7 +1115,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
>>  		d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
>>  	}
>>  
>> -	if (IS_VALLEYVIEW(dev_priv))
>> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>  		d->reg_post = FORCEWAKE_ACK_VLV;
>>  	else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
>>  		d->reg_post = ECOBUS;
>> @@ -1148,7 +1148,7 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
>>  			       FORCEWAKE_ACK_BLITTER_GEN9);
>>  		fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
>>  			       FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
>> -	} else if (IS_VALLEYVIEW(dev)) {
>> +	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>>  		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
>>  		if (!IS_CHERRYVIEW(dev))
>>  			dev_priv->uncore.funcs.force_wake_put =
>> -- 
>> 2.6.3

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 5/5] drm/i915: Remove BUG_ON call in vlv_enable_pll

[Daniel Vetter]

On Tue, Dec 08, 2015 at 01:48:23PM +0200, Ville Syrjälä wrote:
> On Mon, Dec 07, 2015 at 03:02:42PM -0800, Wayne Boyer wrote:
> > Do some further clean up based on the initial review of
> > drm/i915: Separate cherryview from valleyview.
> > 
> > In this case remove the BUG_ON call in vlv_enable_pll().
> > 
> > v2: Also remove the BUG_ON call in chv_enable_pll(). (Ville)
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Death to BUG_ON!

Entire series merged to dinq, thanks for patches&review.
-Daniel

> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 5 -----
> >  1 file changed, 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 05458a6..3c86649 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1607,9 +1607,6 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
> >  
> >  	assert_pipe_disabled(dev_priv, crtc->pipe);
> >  
> > -	/* No really, not for ILK+ */
> > -	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
> > -
> >  	/* PLL is protected by panel, make sure we can write it */
> >  	if (IS_MOBILE(dev_priv->dev))
> >  		assert_panel_unlocked(dev_priv, crtc->pipe);
> > @@ -1647,8 +1644,6 @@ static void chv_enable_pll(struct intel_crtc *crtc,
> >  
> >  	assert_pipe_disabled(dev_priv, crtc->pipe);
> >  
> > -	BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
> > -
> >  	mutex_lock(&dev_priv->sb_lock);
> >  
> >  	/* Enable back the 10bit clock to display controller */
> > -- 
> > 2.6.3
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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