* [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
@ 2022-07-15 7:05 Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 01/15] ACPICA: MADT: Add LoongArch APICs support Jianmin Lv
` (15 more replies)
0 siblings, 16 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
boot protocol LoongArch-specific interrupt controllers (similar to APIC)
are already added in the ACPI Specification 6.5(which may be published in
early June this year and the board is reviewing the draft).
Currently, LoongArch based processors (e.g. Loongson-3A5000) can only
work together with LS7A chipsets. The irq chips in LoongArch computers
include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O
Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller),
HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main
Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are
per-package controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are all
controllers out of CPU (i.e., in chipsets). These controllers (in other
words, irqchips) are linked in a hierarchy, and there are two models of
hierarchy (legacy model and extended model).
Legacy IRQ model:
In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer
interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC,
while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and
gathered by HTVECINTC, and then go to LIOINTC, and then CPUINTC.
+---------------------------------------------+
| |
| +-----+ +---------+ +-------+ |
| | IPI | --> | CPUINTC | <-- | Timer | |
| +-----+ +---------+ +-------+ |
| ^ |
| | |
| +---------+ +-------+ |
| | LIOINTC | <-- | UARTs | |
| +---------+ +-------+ |
| ^ |
| | |
| +-----------+ |
| | HTVECINTC | |
| +-----------+ |
| ^ ^ |
| | | |
| +---------+ +---------+ |
| | PCH-PIC | | PCH-MSI | |
| +---------+ +---------+ |
| ^ ^ ^ |
| | | | |
| +---------+ +---------+ +---------+ |
| | PCH-LPC | | Devices | | Devices | |
| +---------+ +---------+ +---------+ |
| ^ |
| | |
| +---------+ |
| | Devices | |
| +---------+ |
| |
| |
+---------------------------------------------+
Extended IRQ model:
In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer
interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC,
while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and
gathered by EIOINTC, and then go to to CPUINTC directly.
+--------------------------------------------------------+
| |
| +-----+ +---------+ +-------+ |
| | IPI | --> | CPUINTC | <-- | Timer | |
| +-----+ +---------+ +-------+ |
| ^ ^ |
| | | |
| +---------+ +---------+ +-------+ |
| | EIOINTC | | LIOINTC | <-- | UARTs | |
| +---------+ +---------+ +-------+ |
| ^ ^ |
| | | |
| +---------+ +---------+ |
| | PCH-PIC | | PCH-MSI | |
| +---------+ +---------+ |
| ^ ^ ^ |
| | | | |
| +---------+ +---------+ +---------+ |
| | PCH-LPC | | Devices | | Devices | |
| +---------+ +---------+ +---------+ |
| ^ |
| | |
| +---------+ |
| | Devices | |
| +---------+ |
| |
| |
+--------------------------------------------------------+
The hierarchy model is constructed by parsing irq contronler structures
in MADT. Some controllers((e.g. LIOINTC, HTVECINTC, EIOINTC and PCH-LPC)
are hardcodingly connected to their parents, so their irqdomins are
separately routed to their parents in a fixed way. Some controllers
(e.g. PCH-PIC and PCH-MSI) could be routed to different parents for different
CPU. The firmware will config EIOINTC for the newer CPU and config HTVECINTC
for old CPU in MADT. By this way, PCH-PIC and PCH-MSI irqdomain can only be
routed one parent irqdomin: HTVECINTC or EIOINTC.
Example of irqchip topology in a system with two chipsets:
+------------------------------------------------------------+
| |
| +------------------+ |
| | CPUINTC | |
| +------------------+ |
| ^ ^ |
| | | |
| +----------+ +----------+ |
| | EIOINTC 0| | EIOINTC 1| |
| +----------+ +----------+ |
| ^ ^ ^ ^ |
| | | | | |
| +----------+ +----------+ +----------+ +----------+ |
| | PCH-PIC 0| | PCH-MSI 0| | PCH-PIC 1| | PCH-MSI 1| |
| +----------+ +----------+ +----------+ +----------+ |
| |
| |
+------------------------------------------------------------+
For systems with two chipsets, there are tow group(consists of EIOINTC, PCH-PIC and PCH-MSI) irqdomains,
and each group has same node id. So we defined a structure to mantain the relation of node and it's parent irqdomain.
struct acpi_vector_group {
int node;
int pci_segment;
struct irq_domain *parent;
};
The initialization and use of acpi_vector_group array are following:
1 Entry of struct acpi_vector_group array initialization:
By parsing MCFG, the node id（from bit44-47 of Base Address）and pci segment are extracted. And from MADT, we have the node id of each EIOINTC.
entry.node = node id of pci segment
entry.pci_segment = pci segment (only for msi irqdomain)
By matching node id of entry and EIOINTC to set parent.
entry.parent = EIOINTC irqdomain(node id of EIOINTC == node id of pci segment)
2 Get parent irqdomain for PCH-PIC:
From MADT, we have the node id of each PCH-PIC(from bit44-47 of Base Address).
if (node of entry i == node of PCH-PIC)
return entrys[i].parent;
3 Get parent irqdomain for PCH-MSI of pci segment:
return entrys[i].parent; (i is the index of msi irqdomain)
4 How to select a correct irqdomain to map irq for a device?
For devices using legacy irq behind PCH-PIC, GSI is used to select correct PCH-PIC irqdomain.
For devices using msi irq behind PCH-MSI, the pci segmen of the device is used to select correct PCH-MSI irqdomain.
V1 -> V2:
1, Remove queued patches;
2, Move common logic of DT/ACPI probing to common functions;
3, Split .suspend()/.resume() functions to separate patches.
V2 -> V3:
1, Fix a bug for loongson-pch-pic probe;
2, Some minor improvements for LPC controller.
V3 -> V4:
1, Rework the CPU interrupt controller driver;
2, Some minor improvements for other controllers.
V4 -> V5:
1, Add a description of LoonArch's IRQ model;
2, Support multiple EIOINTCs in one system;
3, Some minor improvements for other controllers.
V5 -> V6:
1, Attach a fwnode to CPUINTC irq domain;
2, Use raw spinlock instead of generic spinlock;
3, Improve the method of restoring EIOINTC state;
4, Update documentation, comments and commit messages.
V6 -> V7:
1, Fix build warnings reported by kernel test robot.
V7 -> V8:
1, Add arguments sanity checking for irqchip init functions;
2, Support Loongson-3C5000 (One NUMA Node includes 4 EIOINTC Node).
V8 -> V9:
1, Rebase on 5.17-rc5;
2, Update cover letter;
3, Some small improvements.
V9 -> V10:
1, Rebase on 5.17-rc6;
2, Fix build warnings reported by kernel test robot.
V10 -> V11:
1, Rebase on 5.18-rc4;
2, Fix irq affinity setting for EIOINTC;
3, Fix hwirq allocation failure for EIOINTC.
V11 -> RFC:
1, Refactored the way to build irqchip hierarchy topology.
RFC -> RFC V2:
1, Move all IO-interrupt related code to driver/irqchip from arch directory.
2. Add description for an example of two chipsets system.
RFC V2 -> RFC V3:
1, Add support for multiple GSI domains
2, Use ACPI_GENERIC_GSI for GSI handling
3, Drop suspend-resume stuff
4, Export fwnode handles instead of irq domain handles
RFC V3 -> V12:
1, Address patch attributions of the patch series
V12 -> V13
1 Based on 5.19-rc2
2 Remove arch specified gsi code
3 Split some 'common' code into the various drivers where they belong.
4 Allow acpi_gsi_to_irq() to have an arch-specific fallback
V13 -> V14
1 Add LoongArch-specified APICs definition
2 Use the way in CPUINTC driver to call pch-pic and pch-msi entry
3 Fix compiling and regression issue for OF path
V14 -> V15
1 Expose fwnode_handle of CPUINTC domain instead of using get_xxx_irq() for CPUINTC driver
2 Fix EIOINTC driver: delete parent_data referencing and fix set_affinity bug
3 Use acpi_disabled for DT and ACPI runtime code path
4 Fix return type of arch-specific acpi_gsi_to_irq fallback
5 Fix compile bug tested by kernel test robot
Huacai Chen (9):
ACPICA: MADT: Add LoongArch APICs support
irqchip: Add Loongson PCH LPC controller support
irqchip: remove COMPILE_TEST for pch-pic and pch-msi
irqchip/loongson-pch-pic: Add ACPI init support
irqchip/loongson-pch-msi: Add ACPI init support
irqchip/loongson-htvec: Add ACPI init support
irqchip/loongson-liointc: Add ACPI init support
irqchip: Add Loongson Extended I/O interrupt controller support
irqchip: Add LoongArch CPU interrupt controller support
Jianmin Lv (4):
genirq/generic_chip: export irq_unmap_generic_chip
LoongArch: Use ACPI_GENERIC_GSI for gsi handling
LoongArch: prepare to support multiple pch-pic and pch-msi irqdomain
irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch
Marc Zyngier (2):
APCI: irq: Add support for multiple GSI domains
ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
arch/loongarch/Kconfig | 1 +
arch/loongarch/include/asm/irq.h | 46 ++--
arch/loongarch/kernel/acpi.c | 65 -----
arch/loongarch/kernel/irq.c | 57 +++-
arch/loongarch/kernel/time.c | 14 +-
arch/mips/include/asm/mach-loongson64/irq.h | 2 +-
drivers/acpi/bus.c | 3 +
drivers/acpi/irq.c | 58 ++--
drivers/irqchip/Kconfig | 32 ++-
drivers/irqchip/Makefile | 3 +
drivers/irqchip/irq-gic-v3.c | 18 +-
drivers/irqchip/irq-gic.c | 18 +-
drivers/irqchip/irq-loongarch-cpu.c | 157 +++++++++++
drivers/irqchip/irq-loongson-eiointc.c | 395 ++++++++++++++++++++++++++++
drivers/irqchip/irq-loongson-htvec.c | 145 +++++++---
drivers/irqchip/irq-loongson-liointc.c | 226 ++++++++++------
drivers/irqchip/irq-loongson-pch-lpc.c | 208 +++++++++++++++
drivers/irqchip/irq-loongson-pch-msi.c | 131 ++++++---
drivers/irqchip/irq-loongson-pch-pic.c | 178 ++++++++++---
include/acpi/actbl2.h | 127 ++++++++-
include/linux/acpi.h | 4 +-
include/linux/cpuhotplug.h | 1 +
include/linux/irq.h | 1 +
kernel/irq/generic-chip.c | 2 +-
24 files changed, 1576 insertions(+), 316 deletions(-)
create mode 100644 drivers/irqchip/irq-loongarch-cpu.c
create mode 100644 drivers/irqchip/irq-loongson-eiointc.c
create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c
--
1.8.3.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH V15 01/15] ACPICA: MADT: Add LoongArch APICs support
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
@ 2022-07-15 7:05 ` Jianmin Lv
2022-07-16 18:10 ` Marc Zyngier
2022-07-15 7:05 ` [PATCH V15 02/15] APCI: irq: Add support for multiple GSI domains Jianmin Lv
` (14 subsequent siblings)
15 siblings, 1 reply; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
LoongArch-specific interrupt controllers (similar to APIC) are added
in the next revision of ACPI Specification (current revision is 6.4),
which including CORE_PIC (CPUINTC), LIO_PIC (LIOINTC), EIO_PIC (EIOINTC),
HT_PIC (HTVECINTC), BIO_PIC (PCHINTC), LPC_PIC (PCHLPC) and MSI_PIC
(PCHMSI). This patch add their definition.
ACPI changes of LoongArch-specific interrupt controllers have already
been approved in the ECRs, and will be public in the next revision of
ACPI Specification.
Reference: https://mantis.uefi.org/mantis/view.php?id=2203
Reference: https://mantis.uefi.org/mantis/view.php?id=2313
Above links needs login(available for ASWG), so the following link(
the ECR file for adding LoongArch APICs into ACPI spec) is provided
for public:
https://github.com/lvjianmin-loongson/acpica/blob/master/Add%20APIC%20Structures%20for%20Loongarch%20in%20MADT-rev3.pdf
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
include/acpi/actbl2.h | 127 +++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 125 insertions(+), 2 deletions(-)
diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
index 655102b..323bdd6 100644
--- a/include/acpi/actbl2.h
+++ b/include/acpi/actbl2.h
@@ -865,7 +865,14 @@ enum acpi_madt_type {
ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14,
ACPI_MADT_TYPE_GENERIC_TRANSLATOR = 15,
ACPI_MADT_TYPE_MULTIPROC_WAKEUP = 16,
- ACPI_MADT_TYPE_RESERVED = 17, /* 17 to 0x7F are reserved */
+ ACPI_MADT_TYPE_CORE_PIC = 17,
+ ACPI_MADT_TYPE_LIO_PIC = 18,
+ ACPI_MADT_TYPE_HT_PIC = 19,
+ ACPI_MADT_TYPE_EIO_PIC = 20,
+ ACPI_MADT_TYPE_MSI_PIC = 21,
+ ACPI_MADT_TYPE_BIO_PIC = 22,
+ ACPI_MADT_TYPE_LPC_PIC = 23,
+ ACPI_MADT_TYPE_RESERVED = 24, /* 24 to 0x7F are reserved */
ACPI_MADT_TYPE_OEM_RESERVED = 0x80 /* 0x80 to 0xFF are reserved for OEM use */
};
@@ -1096,7 +1103,123 @@ struct acpi_madt_multiproc_wakeup_mailbox {
#define ACPI_MP_WAKE_COMMAND_WAKEUP 1
-/* 17: OEM data */
+/* Values for Version field above */
+
+enum acpi_madt_core_pic_version {
+ ACPI_MADT_CORE_PIC_VERSION_NONE = 0,
+ ACPI_MADT_CORE_PIC_VERSION_V1 = 1,
+ ACPI_MADT_CORE_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
+};
+
+enum acpi_madt_lio_pic_version {
+ ACPI_MADT_LIO_PIC_VERSION_NONE = 0,
+ ACPI_MADT_LIO_PIC_VERSION_V1 = 1,
+ ACPI_MADT_LIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
+};
+
+enum acpi_madt_eio_pic_version {
+ ACPI_MADT_EIO_PIC_VERSION_NONE = 0,
+ ACPI_MADT_EIO_PIC_VERSION_V1 = 1,
+ ACPI_MADT_EIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
+};
+
+enum acpi_madt_ht_pic_version {
+ ACPI_MADT_HT_PIC_VERSION_NONE = 0,
+ ACPI_MADT_HT_PIC_VERSION_V1 = 1,
+ ACPI_MADT_HT_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
+};
+
+enum acpi_madt_bio_pic_version {
+ ACPI_MADT_BIO_PIC_VERSION_NONE = 0,
+ ACPI_MADT_BIO_PIC_VERSION_V1 = 1,
+ ACPI_MADT_BIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
+};
+
+enum acpi_madt_msi_pic_version {
+ ACPI_MADT_MSI_PIC_VERSION_NONE = 0,
+ ACPI_MADT_MSI_PIC_VERSION_V1 = 1,
+ ACPI_MADT_MSI_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
+};
+
+enum acpi_madt_lpc_pic_version {
+ ACPI_MADT_LPC_PIC_VERSION_NONE = 0,
+ ACPI_MADT_LPC_PIC_VERSION_V1 = 1,
+ ACPI_MADT_LPC_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
+};
+
+/* Core Interrupt Controller */
+
+struct acpi_madt_core_pic {
+ struct acpi_subtable_header header;
+ u8 version;
+ u32 processor_id;
+ u32 core_id;
+ u32 flags;
+};
+
+/* Legacy I/O Interrupt Controller */
+
+struct acpi_madt_lio_pic {
+ struct acpi_subtable_header header;
+ u8 version;
+ u64 address;
+ u16 size;
+ u8 cascade[2];
+ u32 cascade_map[2];
+};
+
+/* Extend I/O Interrupt Controller */
+
+struct acpi_madt_eio_pic {
+ struct acpi_subtable_header header;
+ u8 version;
+ u8 cascade;
+ u8 node;
+ u64 node_map;
+};
+
+/* HT Interrupt Controller */
+
+struct acpi_madt_ht_pic {
+ struct acpi_subtable_header header;
+ u8 version;
+ u64 address;
+ u16 size;
+ u8 cascade[8];
+};
+
+/* Bridge I/O Interrupt Controller */
+
+struct acpi_madt_bio_pic {
+ struct acpi_subtable_header header;
+ u8 version;
+ u64 address;
+ u16 size;
+ u16 id;
+ u16 gsi_base;
+};
+
+/* MSI Interrupt Controller */
+
+struct acpi_madt_msi_pic {
+ struct acpi_subtable_header header;
+ u8 version;
+ u64 msg_address;
+ u32 start;
+ u32 count;
+};
+
+/* LPC Interrupt Controller */
+
+struct acpi_madt_lpc_pic {
+ struct acpi_subtable_header header;
+ u8 version;
+ u64 address;
+ u16 size;
+ u8 cascade;
+};
+
+/* 80: OEM data */
struct acpi_madt_oem_data {
u8 oem_data[0];
--
1.8.3.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH V15 02/15] APCI: irq: Add support for multiple GSI domains
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 01/15] ACPICA: MADT: Add LoongArch APICs support Jianmin Lv
@ 2022-07-15 7:05 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 03/15] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback Jianmin Lv
` (13 subsequent siblings)
15 siblings, 0 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
From: Marc Zyngier <maz@kernel.org>
In an unfortunate departure from the ACPI spec, the LoongArch
architecture split its GSI space across multiple interrupt
controllers.
In order to be able to reuse the core code and prevent
architectures from reinventing an already square wheel, offer
the arch code the ability to register a dispatcher function
that will return the domain fwnode for a given GSI.
The ARM GIC drivers are updated to support this (with a single
domain, as intended).
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: Hanjun Guo <guohanjun@huawei.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Tested-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
---
drivers/acpi/irq.c | 40 +++++++++++++++++++++++++---------------
drivers/irqchip/irq-gic-v3.c | 18 ++++++++++++------
drivers/irqchip/irq-gic.c | 18 ++++++++++++------
include/linux/acpi.h | 2 +-
4 files changed, 50 insertions(+), 28 deletions(-)
diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c
index c68e694..f0de768 100644
--- a/drivers/acpi/irq.c
+++ b/drivers/acpi/irq.c
@@ -12,7 +12,7 @@
enum acpi_irq_model_id acpi_irq_model;
-static struct fwnode_handle *acpi_gsi_domain_id;
+static struct fwnode_handle *(*acpi_get_gsi_domain_id)(u32 gsi);
/**
* acpi_gsi_to_irq() - Retrieve the linux irq number for a given GSI
@@ -26,9 +26,10 @@
*/
int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
{
- struct irq_domain *d = irq_find_matching_fwnode(acpi_gsi_domain_id,
- DOMAIN_BUS_ANY);
+ struct irq_domain *d;
+ d = irq_find_matching_fwnode(acpi_get_gsi_domain_id(gsi),
+ DOMAIN_BUS_ANY);
*irq = irq_find_mapping(d, gsi);
/*
* *irq == 0 means no mapping, that should
@@ -53,12 +54,12 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger,
{
struct irq_fwspec fwspec;
- if (WARN_ON(!acpi_gsi_domain_id)) {
+ fwspec.fwnode = acpi_get_gsi_domain_id(gsi);
+ if (WARN_ON(!fwspec.fwnode)) {
pr_warn("GSI: No registered irqchip, giving up\n");
return -EINVAL;
}
- fwspec.fwnode = acpi_gsi_domain_id;
fwspec.param[0] = gsi;
fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity);
fwspec.param_count = 2;
@@ -73,13 +74,14 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger,
*/
void acpi_unregister_gsi(u32 gsi)
{
- struct irq_domain *d = irq_find_matching_fwnode(acpi_gsi_domain_id,
- DOMAIN_BUS_ANY);
+ struct irq_domain *d;
int irq;
if (WARN_ON(acpi_irq_model == ACPI_IRQ_MODEL_GIC && gsi < 16))
return;
+ d = irq_find_matching_fwnode(acpi_get_gsi_domain_id(gsi),
+ DOMAIN_BUS_ANY);
irq = irq_find_mapping(d, gsi);
irq_dispose_mapping(irq);
}
@@ -97,7 +99,8 @@ void acpi_unregister_gsi(u32 gsi)
* The referenced device fwhandle or NULL on failure
*/
static struct fwnode_handle *
-acpi_get_irq_source_fwhandle(const struct acpi_resource_source *source)
+acpi_get_irq_source_fwhandle(const struct acpi_resource_source *source,
+ u32 gsi)
{
struct fwnode_handle *result;
struct acpi_device *device;
@@ -105,7 +108,7 @@ void acpi_unregister_gsi(u32 gsi)
acpi_status status;
if (!source->string_length)
- return acpi_gsi_domain_id;
+ return acpi_get_gsi_domain_id(gsi);
status = acpi_get_handle(NULL, source->string_ptr, &handle);
if (WARN_ON(ACPI_FAILURE(status)))
@@ -194,7 +197,7 @@ static acpi_status acpi_irq_parse_one_cb(struct acpi_resource *ares,
ctx->index -= irq->interrupt_count;
return AE_OK;
}
- fwnode = acpi_gsi_domain_id;
+ fwnode = acpi_get_gsi_domain_id(irq->interrupts[ctx->index]);
acpi_irq_parse_one_match(fwnode, irq->interrupts[ctx->index],
irq->triggering, irq->polarity,
irq->shareable, ctx);
@@ -207,7 +210,8 @@ static acpi_status acpi_irq_parse_one_cb(struct acpi_resource *ares,
ctx->index -= eirq->interrupt_count;
return AE_OK;
}
- fwnode = acpi_get_irq_source_fwhandle(&eirq->resource_source);
+ fwnode = acpi_get_irq_source_fwhandle(&eirq->resource_source,
+ eirq->interrupts[ctx->index]);
acpi_irq_parse_one_match(fwnode, eirq->interrupts[ctx->index],
eirq->triggering, eirq->polarity,
eirq->shareable, ctx);
@@ -291,10 +295,10 @@ int acpi_irq_get(acpi_handle handle, unsigned int index, struct resource *res)
* GSI interrupts
*/
void __init acpi_set_irq_model(enum acpi_irq_model_id model,
- struct fwnode_handle *fwnode)
+ struct fwnode_handle *(*fn)(u32))
{
acpi_irq_model = model;
- acpi_gsi_domain_id = fwnode;
+ acpi_get_gsi_domain_id = fn;
}
/**
@@ -312,8 +316,14 @@ struct irq_domain *acpi_irq_create_hierarchy(unsigned int flags,
const struct irq_domain_ops *ops,
void *host_data)
{
- struct irq_domain *d = irq_find_matching_fwnode(acpi_gsi_domain_id,
- DOMAIN_BUS_ANY);
+ struct irq_domain *d;
+
+ /* This only works for the GIC model... */
+ if (acpi_irq_model != ACPI_IRQ_MODEL_GIC)
+ return NULL;
+
+ d = irq_find_matching_fwnode(acpi_get_gsi_domain_id(0),
+ DOMAIN_BUS_ANY);
if (!d)
return NULL;
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 5c1cf90..c664703 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -2360,11 +2360,17 @@ static void __init gic_acpi_setup_kvm_info(void)
vgic_set_kvm_info(&gic_v3_kvm_info);
}
+static struct fwnode_handle *gsi_domain_handle;
+
+static struct fwnode_handle *gic_v3_get_gsi_domain_id(u32 gsi)
+{
+ return gsi_domain_handle;
+}
+
static int __init
gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
{
struct acpi_madt_generic_distributor *dist;
- struct fwnode_handle *domain_handle;
size_t size;
int i, err;
@@ -2396,18 +2402,18 @@ static void __init gic_acpi_setup_kvm_info(void)
if (err)
goto out_redist_unmap;
- domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
- if (!domain_handle) {
+ gsi_domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
+ if (!gsi_domain_handle) {
err = -ENOMEM;
goto out_redist_unmap;
}
err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
- acpi_data.nr_redist_regions, 0, domain_handle);
+ acpi_data.nr_redist_regions, 0, gsi_domain_handle);
if (err)
goto out_fwhandle_free;
- acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
+ acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, gic_v3_get_gsi_domain_id);
if (static_branch_likely(&supports_deactivate_key))
gic_acpi_setup_kvm_info();
@@ -2415,7 +2421,7 @@ static void __init gic_acpi_setup_kvm_info(void)
return 0;
out_fwhandle_free:
- irq_domain_free_fwnode(domain_handle);
+ irq_domain_free_fwnode(gsi_domain_handle);
out_redist_unmap:
for (i = 0; i < acpi_data.nr_redist_regions; i++)
if (acpi_data.redist_regs[i].redist_base)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 820404c..4c7bae0 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -1682,11 +1682,17 @@ static void __init gic_acpi_setup_kvm_info(void)
vgic_set_kvm_info(&gic_v2_kvm_info);
}
+static struct fwnode_handle *gsi_domain_handle;
+
+static struct fwnode_handle *gic_v2_get_gsi_domain_id(u32 gsi)
+{
+ return gsi_domain_handle;
+}
+
static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
const unsigned long end)
{
struct acpi_madt_generic_distributor *dist;
- struct fwnode_handle *domain_handle;
struct gic_chip_data *gic = &gic_data[0];
int count, ret;
@@ -1724,22 +1730,22 @@ static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
/*
* Initialize GIC instance zero (no multi-GIC support).
*/
- domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
- if (!domain_handle) {
+ gsi_domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
+ if (!gsi_domain_handle) {
pr_err("Unable to allocate domain handle\n");
gic_teardown(gic);
return -ENOMEM;
}
- ret = __gic_init_bases(gic, domain_handle);
+ ret = __gic_init_bases(gic, gsi_domain_handle);
if (ret) {
pr_err("Failed to initialise GIC\n");
- irq_domain_free_fwnode(domain_handle);
+ irq_domain_free_fwnode(gsi_domain_handle);
gic_teardown(gic);
return ret;
}
- acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
+ acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, gic_v2_get_gsi_domain_id);
if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
gicv2m_init(NULL, gic_data[0].domain);
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 4f82a5b..957e23f 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -356,7 +356,7 @@ static inline bool acpi_sci_irq_valid(void)
int acpi_isa_irq_to_gsi (unsigned isa_irq, u32 *gsi);
void acpi_set_irq_model(enum acpi_irq_model_id model,
- struct fwnode_handle *fwnode);
+ struct fwnode_handle *(*)(u32));
struct irq_domain *acpi_irq_create_hierarchy(unsigned int flags,
unsigned int size,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH V15 03/15] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 01/15] ACPICA: MADT: Add LoongArch APICs support Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 02/15] APCI: irq: Add support for multiple GSI domains Jianmin Lv
@ 2022-07-15 7:05 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 04/15] genirq/generic_chip: export irq_unmap_generic_chip Jianmin Lv
` (12 subsequent siblings)
15 siblings, 0 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
From: Marc Zyngier <maz@kernel.org>
It appears that the generic version of acpi_gsi_to_irq() doesn't
fallback to establishing a mapping if there is no pre-existing
one while the x86 version does.
While arm64 seems unaffected by it, LoongArch is relying on the x86
behaviour. In an effort to prevent new architectures from reinventing
the proverbial wheel, provide an optional callback that the arch code
can set to restore the x86 behaviour.
Hopefully we can eventually get rid of this in the future once
the expected behaviour has been clarified.
Reported-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Tested-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
---
drivers/acpi/irq.c | 18 ++++++++++++++++--
include/linux/acpi.h | 1 +
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c
index f0de768..dabe45e 100644
--- a/drivers/acpi/irq.c
+++ b/drivers/acpi/irq.c
@@ -13,6 +13,7 @@
enum acpi_irq_model_id acpi_irq_model;
static struct fwnode_handle *(*acpi_get_gsi_domain_id)(u32 gsi);
+static u32 (*acpi_gsi_to_irq_fallback)(u32 gsi);
/**
* acpi_gsi_to_irq() - Retrieve the linux irq number for a given GSI
@@ -32,9 +33,12 @@ int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
DOMAIN_BUS_ANY);
*irq = irq_find_mapping(d, gsi);
/*
- * *irq == 0 means no mapping, that should
- * be reported as a failure
+ * *irq == 0 means no mapping, that should be reported as a
+ * failure, unless there is an arch-specific fallback handler.
*/
+ if (!*irq && acpi_gsi_to_irq_fallback)
+ *irq = acpi_gsi_to_irq_fallback(gsi);
+
return (*irq > 0) ? 0 : -EINVAL;
}
EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
@@ -302,6 +306,16 @@ void __init acpi_set_irq_model(enum acpi_irq_model_id model,
}
/**
+ * acpi_set_gsi_to_irq_fallback - Register a GSI transfer
+ * callback to fallback to arch specified implementation.
+ * @fn: arch-specific fallback handler
+ */
+void __init acpi_set_gsi_to_irq_fallback(u32 (*fn)(u32))
+{
+ acpi_gsi_to_irq_fallback = fn;
+}
+
+/**
* acpi_irq_create_hierarchy - Create a hierarchical IRQ domain with the default
* GSI domain as its parent.
* @flags: Irq domain flags associated with the domain
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 957e23f..e2b60d5 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -357,6 +357,7 @@ static inline bool acpi_sci_irq_valid(void)
void acpi_set_irq_model(enum acpi_irq_model_id model,
struct fwnode_handle *(*)(u32));
+void acpi_set_gsi_to_irq_fallback(u32 (*)(u32));
struct irq_domain *acpi_irq_create_hierarchy(unsigned int flags,
unsigned int size,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH V15 04/15] genirq/generic_chip: export irq_unmap_generic_chip
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (2 preceding siblings ...)
2022-07-15 7:05 ` [PATCH V15 03/15] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback Jianmin Lv
@ 2022-07-15 7:05 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 05/15] LoongArch: Use ACPI_GENERIC_GSI for gsi handling Jianmin Lv
` (11 subsequent siblings)
15 siblings, 0 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
Some irq controllers have to re-implement a private version for
irq_generic_chip_ops, because they have a different xlate to translate
hwirq. Export irq_unmap_generic_chip for reusing in user defined
ops.
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
include/linux/irq.h | 1 +
kernel/irq/generic-chip.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 5053082..83a4574 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -1121,6 +1121,7 @@ struct irq_domain_chip_generic {
/* Setup functions for irq_chip_generic */
int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hw_irq);
+void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq);
struct irq_chip_generic *
irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
void __iomem *reg_base, irq_flow_handler_t handler);
diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index f0862eb..c653cd3 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -431,7 +431,7 @@ int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
return 0;
}
-static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
+void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
{
struct irq_data *data = irq_domain_get_irq_data(d, virq);
struct irq_domain_chip_generic *dgc = d->gc;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH V15 05/15] LoongArch: Use ACPI_GENERIC_GSI for gsi handling
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (3 preceding siblings ...)
2022-07-15 7:05 ` [PATCH V15 04/15] genirq/generic_chip: export irq_unmap_generic_chip Jianmin Lv
@ 2022-07-15 7:05 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 06/15] irqchip: Add Loongson PCH LPC controller support Jianmin Lv
` (10 subsequent siblings)
15 siblings, 0 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
For LoongArch, generic gsi code(driver/acpi/irq.c) can be
reused after following patchs:
APCI: irq: Add support for multiple GSI domains
ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
So, config ACPI_GENERIC_GSI for LoongArch with removing the gsi code
in arch directory.
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
arch/loongarch/Kconfig | 1 +
arch/loongarch/kernel/acpi.c | 65 --------------------------------------------
2 files changed, 1 insertion(+), 65 deletions(-)
diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig
index 1920d52..7f98fc0 100644
--- a/arch/loongarch/Kconfig
+++ b/arch/loongarch/Kconfig
@@ -112,6 +112,7 @@ config LOONGARCH
select TRACE_IRQFLAGS_SUPPORT
select USE_PERCPU_NUMA_NODE_ID
select ZONE_DMA32
+ select ACPI_GENERIC_GSI if ACPI
config 32BIT
bool
diff --git a/arch/loongarch/kernel/acpi.c b/arch/loongarch/kernel/acpi.c
index bb729ee..03aa145 100644
--- a/arch/loongarch/kernel/acpi.c
+++ b/arch/loongarch/kernel/acpi.c
@@ -25,7 +25,6 @@
int acpi_strict = 1; /* We have no workarounds on LoongArch */
int num_processors;
int disabled_cpus;
-enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_PLATFORM;
u64 acpi_saved_sp;
@@ -33,70 +32,6 @@
#define PREFIX "ACPI: "
-int acpi_gsi_to_irq(u32 gsi, unsigned int *irqp)
-{
- if (irqp != NULL)
- *irqp = acpi_register_gsi(NULL, gsi, -1, -1);
- return (*irqp >= 0) ? 0 : -EINVAL;
-}
-EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
-
-int acpi_isa_irq_to_gsi(unsigned int isa_irq, u32 *gsi)
-{
- if (gsi)
- *gsi = isa_irq;
- return 0;
-}
-
-/*
- * success: return IRQ number (>=0)
- * failure: return < 0
- */
-int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
-{
- struct irq_fwspec fwspec;
-
- switch (gsi) {
- case GSI_MIN_CPU_IRQ ... GSI_MAX_CPU_IRQ:
- fwspec.fwnode = liointc_domain->fwnode;
- fwspec.param[0] = gsi - GSI_MIN_CPU_IRQ;
- fwspec.param_count = 1;
-
- return irq_create_fwspec_mapping(&fwspec);
-
- case GSI_MIN_LPC_IRQ ... GSI_MAX_LPC_IRQ:
- if (!pch_lpc_domain)
- return -EINVAL;
-
- fwspec.fwnode = pch_lpc_domain->fwnode;
- fwspec.param[0] = gsi - GSI_MIN_LPC_IRQ;
- fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity);
- fwspec.param_count = 2;
-
- return irq_create_fwspec_mapping(&fwspec);
-
- case GSI_MIN_PCH_IRQ ... GSI_MAX_PCH_IRQ:
- if (!pch_pic_domain[0])
- return -EINVAL;
-
- fwspec.fwnode = pch_pic_domain[0]->fwnode;
- fwspec.param[0] = gsi - GSI_MIN_PCH_IRQ;
- fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
- fwspec.param_count = 2;
-
- return irq_create_fwspec_mapping(&fwspec);
- }
-
- return -EINVAL;
-}
-EXPORT_SYMBOL_GPL(acpi_register_gsi);
-
-void acpi_unregister_gsi(u32 gsi)
-{
-
-}
-EXPORT_SYMBOL_GPL(acpi_unregister_gsi);
-
void __init __iomem * __acpi_map_table(unsigned long phys, unsigned long size)
{
--
1.8.3.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH V15 06/15] irqchip: Add Loongson PCH LPC controller support
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (4 preceding siblings ...)
2022-07-15 7:05 ` [PATCH V15 05/15] LoongArch: Use ACPI_GENERIC_GSI for gsi handling Jianmin Lv
@ 2022-07-15 7:05 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 07/15] irqchip: remove COMPILE_TEST for pch-pic and pch-msi Jianmin Lv
` (9 subsequent siblings)
15 siblings, 0 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
PCH-LPC stands for "LPC Interrupts" that described in Section 24.3 of
"Loongson 7A1000 Bridge User Manual". For more information please refer
Documentation/loongarch/irq-chip-model.rst.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/include/asm/irq.h | 4 +-
arch/loongarch/kernel/irq.c | 1 -
drivers/irqchip/Kconfig | 8 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-loongson-pch-lpc.c | 208 +++++++++++++++++++++++++++++++++
5 files changed, 219 insertions(+), 3 deletions(-)
create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index ace3ea6..48c0ce4 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -104,7 +104,7 @@ struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
struct acpi_madt_ht_pic *acpi_htvec);
-struct irq_domain *pch_lpc_acpi_init(struct irq_domain *parent,
+int pch_lpc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lpc_pic *acpi_pchlpc);
struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
struct acpi_madt_msi_pic *acpi_pchmsi);
@@ -121,7 +121,7 @@ struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
extern struct irq_domain *cpu_domain;
extern struct irq_domain *liointc_domain;
-extern struct irq_domain *pch_lpc_domain;
+extern struct fwnode_handle *pch_lpc_handle;
extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
extern struct irq_domain *pch_pic_domain[MAX_IO_PICS];
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index b34b8d7..07d6059 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -27,7 +27,6 @@
struct irq_domain *cpu_domain;
struct irq_domain *liointc_domain;
-struct irq_domain *pch_lpc_domain;
struct irq_domain *pch_msi_domain[MAX_IO_PICS];
struct irq_domain *pch_pic_domain[MAX_IO_PICS];
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 1f23a6b..c1d527f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -591,6 +591,14 @@ config LOONGSON_PCH_MSI
help
Support for the Loongson PCH MSI Controller.
+config LOONGSON_PCH_LPC
+ bool "Loongson PCH LPC Controller"
+ depends on MACH_LOONGSON64
+ default (MACH_LOONGSON64 && LOONGARCH)
+ select IRQ_DOMAIN_HIERARCHY
+ help
+ Support for the Loongson PCH LPC Controller.
+
config MST_IRQ
bool "MStar Interrupt Controller"
depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 5b67450..242b8b3 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -108,6 +108,7 @@ obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
obj-$(CONFIG_LOONGSON_HTVEC) += irq-loongson-htvec.o
obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-loongson-pch-pic.o
obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o
+obj-$(CONFIG_LOONGSON_PCH_LPC) += irq-loongson-pch-lpc.o
obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o
obj-$(CONFIG_SL28CPLD_INTC) += irq-sl28cpld.o
obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o
diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c
new file mode 100644
index 0000000..3f51184
--- /dev/null
+++ b/drivers/irqchip/irq-loongson-pch-lpc.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Loongson LPC Interrupt Controller support
+ *
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#define pr_fmt(fmt) "lpc: " fmt
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/kernel.h>
+
+/* Registers */
+#define LPC_INT_CTL 0x00
+#define LPC_INT_ENA 0x04
+#define LPC_INT_STS 0x08
+#define LPC_INT_CLR 0x0c
+#define LPC_INT_POL 0x10
+#define LPC_COUNT 16
+
+/* LPC_INT_CTL */
+#define LPC_INT_CTL_EN BIT(31)
+
+struct pch_lpc {
+ void __iomem *base;
+ struct irq_domain *lpc_domain;
+ raw_spinlock_t lpc_lock;
+ u32 saved_reg_ctl;
+ u32 saved_reg_ena;
+ u32 saved_reg_pol;
+};
+
+struct fwnode_handle *pch_lpc_handle;
+
+static void lpc_irq_ack(struct irq_data *d)
+{
+ unsigned long flags;
+ struct pch_lpc *priv = d->domain->host_data;
+
+ raw_spin_lock_irqsave(&priv->lpc_lock, flags);
+ writel(0x1 << d->hwirq, priv->base + LPC_INT_CLR);
+ raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
+}
+
+static void lpc_irq_mask(struct irq_data *d)
+{
+ unsigned long flags;
+ struct pch_lpc *priv = d->domain->host_data;
+
+ raw_spin_lock_irqsave(&priv->lpc_lock, flags);
+ writel(readl(priv->base + LPC_INT_ENA) & (~(0x1 << (d->hwirq))),
+ priv->base + LPC_INT_ENA);
+ raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
+}
+
+static void lpc_irq_unmask(struct irq_data *d)
+{
+ unsigned long flags;
+ struct pch_lpc *priv = d->domain->host_data;
+
+ raw_spin_lock_irqsave(&priv->lpc_lock, flags);
+ writel(readl(priv->base + LPC_INT_ENA) | (0x1 << (d->hwirq)),
+ priv->base + LPC_INT_ENA);
+ raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
+}
+
+static int lpc_irq_set_type(struct irq_data *d, unsigned int type)
+{
+ u32 val;
+ u32 mask = 0x1 << (d->hwirq);
+ struct pch_lpc *priv = d->domain->host_data;
+
+ if (!(type & IRQ_TYPE_LEVEL_MASK))
+ return 0;
+
+ val = readl(priv->base + LPC_INT_POL);
+
+ if (type == IRQ_TYPE_LEVEL_HIGH)
+ val |= mask;
+ else
+ val &= ~mask;
+
+ writel(val, priv->base + LPC_INT_POL);
+
+ return 0;
+}
+
+static const struct irq_chip pch_lpc_irq_chip = {
+ .name = "PCH LPC",
+ .irq_mask = lpc_irq_mask,
+ .irq_unmask = lpc_irq_unmask,
+ .irq_ack = lpc_irq_ack,
+ .irq_set_type = lpc_irq_set_type,
+ .flags = IRQCHIP_SKIP_SET_WAKE,
+};
+
+static void lpc_irq_dispatch(struct irq_desc *desc)
+{
+ u32 pending, bit;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct pch_lpc *priv = irq_desc_get_handler_data(desc);
+
+ chained_irq_enter(chip, desc);
+
+ pending = readl(priv->base + LPC_INT_ENA);
+ pending &= readl(priv->base + LPC_INT_STS);
+ if (!pending)
+ spurious_interrupt();
+
+ while (pending) {
+ bit = __ffs(pending);
+
+ generic_handle_domain_irq(priv->lpc_domain, bit);
+ pending &= ~BIT(bit);
+ }
+ chained_irq_exit(chip, desc);
+}
+
+static int pch_lpc_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hw)
+{
+ irq_set_chip_and_handler(irq, &pch_lpc_irq_chip, handle_level_irq);
+ return 0;
+}
+
+static const struct irq_domain_ops pch_lpc_domain_ops = {
+ .map = pch_lpc_map,
+ .translate = irq_domain_translate_twocell,
+};
+
+static void pch_lpc_reset(struct pch_lpc *priv)
+{
+ /* Enable the LPC interrupt, bit31: en bit30: edge */
+ writel(LPC_INT_CTL_EN, priv->base + LPC_INT_CTL);
+ writel(0, priv->base + LPC_INT_ENA);
+ /* Clear all 18-bit interrpt bit */
+ writel(GENMASK(17, 0), priv->base + LPC_INT_CLR);
+}
+
+static int pch_lpc_disabled(struct pch_lpc *priv)
+{
+ return (readl(priv->base + LPC_INT_ENA) == 0xffffffff) &&
+ (readl(priv->base + LPC_INT_STS) == 0xffffffff);
+}
+
+int __init pch_lpc_acpi_init(struct irq_domain *parent,
+ struct acpi_madt_lpc_pic *acpi_pchlpc)
+{
+ int parent_irq;
+ struct pch_lpc *priv;
+ struct irq_fwspec fwspec;
+ struct fwnode_handle *irq_handle;
+
+ if (!acpi_pchlpc)
+ return -EINVAL;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ raw_spin_lock_init(&priv->lpc_lock);
+
+ priv->base = ioremap(acpi_pchlpc->address, acpi_pchlpc->size);
+ if (!priv->base)
+ goto free_priv;
+
+ if (pch_lpc_disabled(priv)) {
+ pr_err("Failed to get LPC status\n");
+ goto iounmap_base;
+ }
+
+ irq_handle = irq_domain_alloc_named_fwnode("lpcintc");
+ if (!irq_handle) {
+ pr_err("Unable to allocate domain handle\n");
+ goto iounmap_base;
+ }
+
+ priv->lpc_domain = irq_domain_create_linear(irq_handle, LPC_COUNT,
+ &pch_lpc_domain_ops, priv);
+ if (!priv->lpc_domain) {
+ pr_err("Failed to create IRQ domain\n");
+ goto free_irq_handle;
+ }
+ pch_lpc_reset(priv);
+
+ fwspec.fwnode = parent->fwnode;
+ fwspec.param[0] = acpi_pchlpc->cascade + GSI_MIN_PCH_IRQ;
+ fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
+ fwspec.param_count = 2;
+ parent_irq = irq_create_fwspec_mapping(&fwspec);
+ irq_set_chained_handler_and_data(parent_irq, lpc_irq_dispatch, priv);
+
+ pch_lpc_handle = irq_handle;
+ return 0;
+
+free_irq_handle:
+ irq_domain_free_fwnode(irq_handle);
+iounmap_base:
+ iounmap(priv->base);
+free_priv:
+ kfree(priv);
+
+ return -ENOMEM;
+}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH V15 07/15] irqchip: remove COMPILE_TEST for pch-pic and pch-msi
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (5 preceding siblings ...)
2022-07-15 7:05 ` [PATCH V15 06/15] irqchip: Add Loongson PCH LPC controller support Jianmin Lv
@ 2022-07-15 7:05 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 08/15] irqchip/loongson-pch-pic: Add ACPI init support Jianmin Lv
` (8 subsequent siblings)
15 siblings, 0 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
Loongson's pch-pic and pch-msi will have some arch-specific
code, so we remove the COMPILE_TEST dependency to avoid build
warnings.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
drivers/irqchip/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index c1d527f..8844e6b 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -574,7 +574,7 @@ config LOONGSON_HTVEC
config LOONGSON_PCH_PIC
bool "Loongson PCH PIC Controller"
- depends on MACH_LOONGSON64 || COMPILE_TEST
+ depends on MACH_LOONGSON64
default MACH_LOONGSON64
select IRQ_DOMAIN_HIERARCHY
select IRQ_FASTEOI_HIERARCHY_HANDLERS
@@ -583,7 +583,7 @@ config LOONGSON_PCH_PIC
config LOONGSON_PCH_MSI
bool "Loongson PCH MSI Controller"
- depends on MACH_LOONGSON64 || COMPILE_TEST
+ depends on MACH_LOONGSON64
depends on PCI
default MACH_LOONGSON64
select IRQ_DOMAIN_HIERARCHY
--
1.8.3.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH V15 08/15] irqchip/loongson-pch-pic: Add ACPI init support
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (6 preceding siblings ...)
2022-07-15 7:05 ` [PATCH V15 07/15] irqchip: remove COMPILE_TEST for pch-pic and pch-msi Jianmin Lv
@ 2022-07-15 7:05 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 09/15] irqchip/loongson-pch-msi: " Jianmin Lv
` (7 subsequent siblings)
15 siblings, 0 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
PCH-PIC/PCH-MSI stands for "Interrupt Controller" that described in
Section 5 of "Loongson 7A1000 Bridge User Manual". For more information
please refer Documentation/loongarch/irq-chip-model.rst.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/include/asm/irq.h | 5 +-
arch/loongarch/kernel/irq.c | 1 -
arch/mips/include/asm/mach-loongson64/irq.h | 2 +-
drivers/irqchip/irq-loongson-pch-pic.c | 178 +++++++++++++++++++++++-----
4 files changed, 151 insertions(+), 35 deletions(-)
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index 48c0ce4..74fef60 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -108,8 +108,9 @@ int pch_lpc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lpc_pic *acpi_pchlpc);
struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
struct acpi_madt_msi_pic *acpi_pchmsi);
-struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
+int pch_pic_acpi_init(struct irq_domain *parent,
struct acpi_madt_bio_pic *acpi_pchpic);
+int find_pch_pic(u32 gsi);
extern struct acpi_madt_lio_pic *acpi_liointc;
extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS];
@@ -123,7 +124,7 @@ struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
extern struct irq_domain *liointc_domain;
extern struct fwnode_handle *pch_lpc_handle;
extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
-extern struct irq_domain *pch_pic_domain[MAX_IO_PICS];
+extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
extern irqreturn_t loongson3_ipi_interrupt(int irq, void *dev);
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index 07d6059..866b2ee 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -28,7 +28,6 @@
struct irq_domain *cpu_domain;
struct irq_domain *liointc_domain;
struct irq_domain *pch_msi_domain[MAX_IO_PICS];
-struct irq_domain *pch_pic_domain[MAX_IO_PICS];
/*
* 'what should we do if we get a hw irq event on an illegal vector'.
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index 98ea977..55e0dee 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -7,7 +7,7 @@
#define NR_MIPS_CPU_IRQS 8
#define NR_MAX_CHAINED_IRQS 40 /* Chained IRQs means those not directly used by devices */
#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256)
-
+#define MAX_IO_PICS 1
#define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
#include <asm/mach-generic/irq.h>
diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c
index a4eb8a2..b6a73c8 100644
--- a/drivers/irqchip/irq-loongson-pch-pic.c
+++ b/drivers/irqchip/irq-loongson-pch-pic.c
@@ -33,13 +33,40 @@
#define PIC_REG_IDX(irq_id) ((irq_id) / PIC_COUNT_PER_REG)
#define PIC_REG_BIT(irq_id) ((irq_id) % PIC_COUNT_PER_REG)
+static int nr_pics;
+
struct pch_pic {
void __iomem *base;
struct irq_domain *pic_domain;
u32 ht_vec_base;
raw_spinlock_t pic_lock;
+ u32 vec_count;
+ u32 gsi_base;
};
+static struct pch_pic *pch_pic_priv[MAX_IO_PICS];
+
+struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
+
+int find_pch_pic(u32 gsi)
+{
+ int i;
+
+ /* Find the PCH_PIC that manages this GSI. */
+ for (i = 0; i < MAX_IO_PICS; i++) {
+ struct pch_pic *priv = pch_pic_priv[i];
+
+ if (!priv)
+ return -1;
+
+ if (gsi >= priv->gsi_base && gsi < (priv->gsi_base + priv->vec_count))
+ return i;
+ }
+
+ pr_err("ERROR: Unable to locate PCH_PIC for GSI %d\n", gsi);
+ return -1;
+}
+
static void pch_pic_bitset(struct pch_pic *priv, int offset, int bit)
{
u32 reg;
@@ -139,6 +166,28 @@ static void pch_pic_ack_irq(struct irq_data *d)
.irq_set_type = pch_pic_set_type,
};
+static int pch_pic_domain_translate(struct irq_domain *d,
+ struct irq_fwspec *fwspec,
+ unsigned long *hwirq,
+ unsigned int *type)
+{
+ struct pch_pic *priv = d->host_data;
+ struct device_node *of_node = to_of_node(fwspec->fwnode);
+
+ if (fwspec->param_count < 1)
+ return -EINVAL;
+
+ if (of_node) {
+ *hwirq = fwspec->param[0] + priv->ht_vec_base;
+ *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
+ } else {
+ *hwirq = fwspec->param[0] - priv->gsi_base;
+ *type = IRQ_TYPE_NONE;
+ }
+
+ return 0;
+}
+
static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
@@ -149,13 +198,13 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
struct irq_fwspec parent_fwspec;
struct pch_pic *priv = domain->host_data;
- err = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
+ err = pch_pic_domain_translate(domain, fwspec, &hwirq, &type);
if (err)
return err;
parent_fwspec.fwnode = domain->parent->fwnode;
parent_fwspec.param_count = 1;
- parent_fwspec.param[0] = hwirq + priv->ht_vec_base;
+ parent_fwspec.param[0] = hwirq;
err = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
if (err)
@@ -170,7 +219,7 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
}
static const struct irq_domain_ops pch_pic_domain_ops = {
- .translate = irq_domain_translate_twocell,
+ .translate = pch_pic_domain_translate,
.alloc = pch_pic_alloc,
.free = irq_domain_free_irqs_parent,
};
@@ -180,7 +229,7 @@ static void pch_pic_reset(struct pch_pic *priv)
int i;
for (i = 0; i < PIC_COUNT; i++) {
- /* Write vectored ID */
+ /* Write vector ID */
writeb(priv->ht_vec_base + i, priv->base + PCH_INT_HTVEC(i));
/* Hardcode route to HT0 Lo */
writeb(1, priv->base + PCH_INT_ROUTE(i));
@@ -198,50 +247,37 @@ static void pch_pic_reset(struct pch_pic *priv)
}
}
-static int pch_pic_of_init(struct device_node *node,
- struct device_node *parent)
+static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base,
+ struct irq_domain *parent_domain, struct fwnode_handle *domain_handle,
+ u32 gsi_base)
{
struct pch_pic *priv;
- struct irq_domain *parent_domain;
- int err;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
raw_spin_lock_init(&priv->pic_lock);
- priv->base = of_iomap(node, 0);
- if (!priv->base) {
- err = -ENOMEM;
+ priv->base = ioremap(addr, size);
+ if (!priv->base)
goto free_priv;
- }
-
- parent_domain = irq_find_host(parent);
- if (!parent_domain) {
- pr_err("Failed to find the parent domain\n");
- err = -ENXIO;
- goto iounmap_base;
- }
- if (of_property_read_u32(node, "loongson,pic-base-vec",
- &priv->ht_vec_base)) {
- pr_err("Failed to determine pic-base-vec\n");
- err = -EINVAL;
- goto iounmap_base;
- }
+ priv->ht_vec_base = vec_base;
+ priv->vec_count = ((readq(priv->base) >> 48) & 0xff) + 1;
+ priv->gsi_base = gsi_base;
priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0,
- PIC_COUNT,
- of_node_to_fwnode(node),
- &pch_pic_domain_ops,
- priv);
+ priv->vec_count, domain_handle,
+ &pch_pic_domain_ops, priv);
+
if (!priv->pic_domain) {
pr_err("Failed to create IRQ domain\n");
- err = -ENOMEM;
goto iounmap_base;
}
pch_pic_reset(priv);
+ pch_pic_handle[nr_pics] = domain_handle;
+ pch_pic_priv[nr_pics++] = priv;
return 0;
@@ -250,7 +286,87 @@ static int pch_pic_of_init(struct device_node *node,
free_priv:
kfree(priv);
- return err;
+ return -EINVAL;
+}
+
+#ifdef CONFIG_OF
+
+static int pch_pic_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ int err, vec_base;
+ struct resource res;
+ struct irq_domain *parent_domain;
+
+ if (of_address_to_resource(node, 0, &res))
+ return -EINVAL;
+
+ parent_domain = irq_find_host(parent);
+ if (!parent_domain) {
+ pr_err("Failed to find the parent domain\n");
+ return -ENXIO;
+ }
+
+ if (of_property_read_u32(node, "loongson,pic-base-vec", &vec_base)) {
+ pr_err("Failed to determine pic-base-vec\n");
+ return -EINVAL;
+ }
+
+ err = pch_pic_init(res.start, resource_size(&res), vec_base,
+ parent_domain, of_node_to_fwnode(node), 0);
+ if (err < 0)
+ return err;
+
+ return 0;
}
IRQCHIP_DECLARE(pch_pic, "loongson,pch-pic-1.0", pch_pic_of_init);
+
+#endif
+
+#ifdef CONFIG_ACPI
+static int __init
+lpcintc_parse_madt(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_madt_lpc_pic *lpcintc_entry = (struct acpi_madt_lpc_pic *)header;
+
+ return pch_lpc_acpi_init(pch_pic_priv[0]->pic_domain, lpcintc_entry);
+}
+
+static int __init acpi_cascade_irqdomain_init(void)
+{
+ acpi_table_parse_madt(ACPI_MADT_TYPE_LPC_PIC,
+ lpcintc_parse_madt, 0);
+ return 0;
+}
+
+int __init pch_pic_acpi_init(struct irq_domain *parent,
+ struct acpi_madt_bio_pic *acpi_pchpic)
+{
+ int ret, vec_base;
+ struct fwnode_handle *domain_handle;
+
+ if (!acpi_pchpic)
+ return -EINVAL;
+
+ vec_base = acpi_pchpic->gsi_base - GSI_MIN_PCH_IRQ;
+
+ domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_pchpic);
+ if (!domain_handle) {
+ pr_err("Unable to allocate domain handle\n");
+ return -ENOMEM;
+ }
+
+ ret = pch_pic_init(acpi_pchpic->address, acpi_pchpic->size,
+ vec_base, parent, domain_handle, acpi_pchpic->gsi_base);
+
+ if (!ret) {
+ if (acpi_pchpic->id == 0)
+ acpi_cascade_irqdomain_init();
+ } else
+ irq_domain_free_fwnode(domain_handle);
+
+ return ret;
+}
+#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH V15 09/15] irqchip/loongson-pch-msi: Add ACPI init support
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (7 preceding siblings ...)
2022-07-15 7:05 ` [PATCH V15 08/15] irqchip/loongson-pch-pic: Add ACPI init support Jianmin Lv
@ 2022-07-15 7:05 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 10/15] irqchip/loongson-htvec: " Jianmin Lv
` (6 subsequent siblings)
15 siblings, 0 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
PCH-PIC/PCH-MSI stands for "Interrupt Controller" that described in
Section 5 of "Loongson 7A1000 Bridge User Manual". For more information
please refer Documentation/loongarch/irq-chip-model.rst.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/include/asm/irq.h | 4 +-
arch/loongarch/kernel/irq.c | 1 -
drivers/irqchip/irq-loongson-pch-msi.c | 131 ++++++++++++++++++++++-----------
3 files changed, 91 insertions(+), 45 deletions(-)
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index 74fef60..6022406 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -106,11 +106,12 @@ struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
struct acpi_madt_ht_pic *acpi_htvec);
int pch_lpc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lpc_pic *acpi_pchlpc);
-struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
+int pch_msi_acpi_init(struct irq_domain *parent,
struct acpi_madt_msi_pic *acpi_pchmsi);
int pch_pic_acpi_init(struct irq_domain *parent,
struct acpi_madt_bio_pic *acpi_pchpic);
int find_pch_pic(u32 gsi);
+struct fwnode_handle *get_pch_msi_handle(int pci_segment);
extern struct acpi_madt_lio_pic *acpi_liointc;
extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS];
@@ -123,7 +124,6 @@ int pch_pic_acpi_init(struct irq_domain *parent,
extern struct irq_domain *cpu_domain;
extern struct irq_domain *liointc_domain;
extern struct fwnode_handle *pch_lpc_handle;
-extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
extern irqreturn_t loongson3_ipi_interrupt(int irq, void *dev);
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index 866b2ee..ce21281 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -27,7 +27,6 @@
struct irq_domain *cpu_domain;
struct irq_domain *liointc_domain;
-struct irq_domain *pch_msi_domain[MAX_IO_PICS];
/*
* 'what should we do if we get a hw irq event on an illegal vector'.
diff --git a/drivers/irqchip/irq-loongson-pch-msi.c b/drivers/irqchip/irq-loongson-pch-msi.c
index e3801c4..b3f1f8e 100644
--- a/drivers/irqchip/irq-loongson-pch-msi.c
+++ b/drivers/irqchip/irq-loongson-pch-msi.c
@@ -15,6 +15,8 @@
#include <linux/pci.h>
#include <linux/slab.h>
+static int nr_pics;
+
struct pch_msi_data {
struct mutex msi_map_lock;
phys_addr_t doorbell;
@@ -23,6 +25,8 @@ struct pch_msi_data {
unsigned long *msi_map;
};
+static struct fwnode_handle *pch_msi_handle[MAX_IO_PICS];
+
static void pch_msi_mask_msi_irq(struct irq_data *d)
{
pci_msi_mask_irq(d);
@@ -154,12 +158,12 @@ static void pch_msi_middle_domain_free(struct irq_domain *domain,
};
static int pch_msi_init_domains(struct pch_msi_data *priv,
- struct device_node *node,
- struct irq_domain *parent)
+ struct irq_domain *parent,
+ struct fwnode_handle *domain_handle)
{
struct irq_domain *middle_domain, *msi_domain;
- middle_domain = irq_domain_create_linear(of_node_to_fwnode(node),
+ middle_domain = irq_domain_create_linear(domain_handle,
priv->num_irqs,
&pch_msi_middle_domain_ops,
priv);
@@ -171,7 +175,7 @@ static int pch_msi_init_domains(struct pch_msi_data *priv,
middle_domain->parent = parent;
irq_domain_update_bus_token(middle_domain, DOMAIN_BUS_NEXUS);
- msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
+ msi_domain = pci_msi_create_irq_domain(domain_handle,
&pch_msi_domain_info,
middle_domain);
if (!msi_domain) {
@@ -183,19 +187,11 @@ static int pch_msi_init_domains(struct pch_msi_data *priv,
return 0;
}
-static int pch_msi_init(struct device_node *node,
- struct device_node *parent)
+static int pch_msi_init(phys_addr_t msg_address, int irq_base, int irq_count,
+ struct irq_domain *parent_domain, struct fwnode_handle *domain_handle)
{
- struct pch_msi_data *priv;
- struct irq_domain *parent_domain;
- struct resource res;
int ret;
-
- parent_domain = irq_find_host(parent);
- if (!parent_domain) {
- pr_err("Failed to find the parent domain\n");
- return -ENXIO;
- }
+ struct pch_msi_data *priv;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -203,48 +199,99 @@ static int pch_msi_init(struct device_node *node,
mutex_init(&priv->msi_map_lock);
- ret = of_address_to_resource(node, 0, &res);
- if (ret) {
- pr_err("Failed to allocate resource\n");
- goto err_priv;
- }
-
- priv->doorbell = res.start;
-
- if (of_property_read_u32(node, "loongson,msi-base-vec",
- &priv->irq_first)) {
- pr_err("Unable to parse MSI vec base\n");
- ret = -EINVAL;
- goto err_priv;
- }
-
- if (of_property_read_u32(node, "loongson,msi-num-vecs",
- &priv->num_irqs)) {
- pr_err("Unable to parse MSI vec number\n");
- ret = -EINVAL;
- goto err_priv;
- }
+ priv->doorbell = msg_address;
+ priv->irq_first = irq_base;
+ priv->num_irqs = irq_count;
priv->msi_map = bitmap_zalloc(priv->num_irqs, GFP_KERNEL);
- if (!priv->msi_map) {
- ret = -ENOMEM;
+ if (!priv->msi_map)
goto err_priv;
- }
pr_debug("Registering %d MSIs, starting at %d\n",
priv->num_irqs, priv->irq_first);
- ret = pch_msi_init_domains(priv, node, parent_domain);
+ ret = pch_msi_init_domains(priv, parent_domain, domain_handle);
if (ret)
goto err_map;
+ pch_msi_handle[nr_pics++] = domain_handle;
return 0;
err_map:
bitmap_free(priv->msi_map);
err_priv:
kfree(priv);
- return ret;
+
+ return -EINVAL;
+}
+
+#ifdef CONFIG_OF
+static int pch_msi_of_init(struct device_node *node, struct device_node *parent)
+{
+ int err;
+ int irq_base, irq_count;
+ struct resource res;
+ struct irq_domain *parent_domain;
+
+ parent_domain = irq_find_host(parent);
+ if (!parent_domain) {
+ pr_err("Failed to find the parent domain\n");
+ return -ENXIO;
+ }
+
+ if (of_address_to_resource(node, 0, &res)) {
+ pr_err("Failed to allocate resource\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32(node, "loongson,msi-base-vec", &irq_base)) {
+ pr_err("Unable to parse MSI vec base\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32(node, "loongson,msi-num-vecs", &irq_count)) {
+ pr_err("Unable to parse MSI vec number\n");
+ return -EINVAL;
+ }
+
+ err = pch_msi_init(res.start, irq_base, irq_count, parent_domain, of_node_to_fwnode(node));
+ if (err < 0)
+ return err;
+
+ return 0;
+}
+
+IRQCHIP_DECLARE(pch_msi, "loongson,pch-msi-1.0", pch_msi_of_init);
+#endif
+
+#ifdef CONFIG_ACPI
+struct fwnode_handle *get_pch_msi_handle(int pci_segment)
+{
+ int i;
+
+ for (i = 0; i < MAX_IO_PICS; i++) {
+ if (msi_group[i].pci_segment == pci_segment)
+ return pch_msi_handle[i];
+ }
+ return NULL;
}
-IRQCHIP_DECLARE(pch_msi, "loongson,pch-msi-1.0", pch_msi_init);
+int __init pch_msi_acpi_init(struct irq_domain *parent,
+ struct acpi_madt_msi_pic *acpi_pchmsi)
+{
+ int ret;
+ struct fwnode_handle *domain_handle;
+
+ if (!acpi_pchmsi)
+ return -EINVAL;
+
+ domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_pchmsi);
+
+ ret = pch_msi_init(acpi_pchmsi->msg_address, acpi_pchmsi->start,
+ acpi_pchmsi->count, parent, domain_handle);
+ if (ret < 0)
+ irq_domain_free_fwnode(domain_handle);
+
+ return ret;
+}
+#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH V15 10/15] irqchip/loongson-htvec: Add ACPI init support
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (8 preceding siblings ...)
2022-07-15 7:05 ` [PATCH V15 09/15] irqchip/loongson-pch-msi: " Jianmin Lv
@ 2022-07-15 7:05 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 11/15] irqchip/loongson-liointc: " Jianmin Lv
` (5 subsequent siblings)
15 siblings, 0 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
HTVECINTC stands for "HyperTransport Interrupts" that described in
Section 14.3 of "Loongson 3A5000 Processor Reference Manual". For more
information please refer Documentation/loongarch/irq-chip-model.rst.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/include/asm/irq.h | 2 +-
drivers/irqchip/irq-loongson-htvec.c | 145 +++++++++++++++++++++++++++--------
2 files changed, 112 insertions(+), 35 deletions(-)
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index 6022406..8775dc6 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -102,7 +102,7 @@ struct irq_domain *liointc_acpi_init(struct irq_domain *parent,
struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
struct acpi_madt_eio_pic *acpi_eiointc);
-struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
+int htvec_acpi_init(struct irq_domain *parent,
struct acpi_madt_ht_pic *acpi_htvec);
int pch_lpc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lpc_pic *acpi_pchlpc);
diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loongson-htvec.c
index 60a335d..65f4938 100644
--- a/drivers/irqchip/irq-loongson-htvec.c
+++ b/drivers/irqchip/irq-loongson-htvec.c
@@ -20,7 +20,6 @@
/* Registers */
#define HTVEC_EN_OFF 0x20
#define HTVEC_MAX_PARENT_IRQ 8
-
#define VEC_COUNT_PER_REG 32
#define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG)
#define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG)
@@ -32,6 +31,8 @@ struct htvec {
raw_spinlock_t htvec_lock;
};
+static struct htvec *htvec_priv;
+
static void htvec_irq_dispatch(struct irq_desc *desc)
{
int i;
@@ -155,64 +156,140 @@ static void htvec_reset(struct htvec *priv)
}
}
-static int htvec_of_init(struct device_node *node,
- struct device_node *parent)
+static int htvec_init(phys_addr_t addr, unsigned long size,
+ int num_parents, int parent_irq[], struct fwnode_handle *domain_handle)
{
+ int i;
struct htvec *priv;
- int err, parent_irq[8], i;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
+ priv->num_parents = num_parents;
+ priv->base = ioremap(addr, size);
raw_spin_lock_init(&priv->htvec_lock);
- priv->base = of_iomap(node, 0);
- if (!priv->base) {
- err = -ENOMEM;
- goto free_priv;
- }
-
- /* Interrupt may come from any of the 8 interrupt lines */
- for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) {
- parent_irq[i] = irq_of_parse_and_map(node, i);
- if (parent_irq[i] <= 0)
- break;
-
- priv->num_parents++;
- }
-
- if (!priv->num_parents) {
- pr_err("Failed to get parent irqs\n");
- err = -ENODEV;
- goto iounmap_base;
- }
- priv->htvec_domain = irq_domain_create_linear(of_node_to_fwnode(node),
+ /* Setup IRQ domain */
+ priv->htvec_domain = irq_domain_create_linear(domain_handle,
(VEC_COUNT_PER_REG * priv->num_parents),
&htvec_domain_ops, priv);
if (!priv->htvec_domain) {
- pr_err("Failed to create IRQ domain\n");
- err = -ENOMEM;
- goto irq_dispose;
+ pr_err("loongson-htvec: cannot add IRQ domain\n");
+ goto iounmap_base;
}
htvec_reset(priv);
- for (i = 0; i < priv->num_parents; i++)
+ for (i = 0; i < priv->num_parents; i++) {
irq_set_chained_handler_and_data(parent_irq[i],
htvec_irq_dispatch, priv);
+ }
+
+ htvec_priv = priv;
return 0;
-irq_dispose:
- for (; i > 0; i--)
- irq_dispose_mapping(parent_irq[i - 1]);
iounmap_base:
iounmap(priv->base);
-free_priv:
kfree(priv);
- return err;
+ return -EINVAL;
+}
+
+#ifdef CONFIG_OF
+
+static int htvec_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ int i, err;
+ int parent_irq[8];
+ int num_parents = 0;
+ struct resource res;
+
+ if (of_address_to_resource(node, 0, &res))
+ return -EINVAL;
+
+ /* Interrupt may come from any of the 8 interrupt lines */
+ for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) {
+ parent_irq[i] = irq_of_parse_and_map(node, i);
+ if (parent_irq[i] <= 0)
+ break;
+
+ num_parents++;
+ }
+
+ err = htvec_init(res.start, resource_size(&res),
+ num_parents, parent_irq, of_node_to_fwnode(node));
+ if (err < 0)
+ return err;
+
+ return 0;
}
IRQCHIP_DECLARE(htvec, "loongson,htvec-1.0", htvec_of_init);
+
+#endif
+
+#ifdef CONFIG_ACPI
+static int __init
+pch_pic_parse_madt(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header;
+
+ return pch_pic_acpi_init(htvec_priv->htvec_domain, pchpic_entry);
+}
+
+static int __init
+pch_msi_parse_madt(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header;
+
+ return pch_msi_acpi_init(htvec_priv->htvec_domain, pchmsi_entry);
+}
+
+static int __init acpi_cascade_irqdomain_init(void)
+{
+ acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC,
+ pch_pic_parse_madt, 0);
+ acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC,
+ pch_msi_parse_madt, 0);
+ return 0;
+}
+
+int __init htvec_acpi_init(struct irq_domain *parent,
+ struct acpi_madt_ht_pic *acpi_htvec)
+{
+ int i, ret;
+ int num_parents, parent_irq[8];
+ struct fwnode_handle *domain_handle;
+
+ if (!acpi_htvec)
+ return -EINVAL;
+
+ num_parents = HTVEC_MAX_PARENT_IRQ;
+
+ domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_htvec);
+ if (!domain_handle) {
+ pr_err("Unable to allocate domain handle\n");
+ return -ENOMEM;
+ }
+
+ /* Interrupt may come from any of the 8 interrupt lines */
+ for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++)
+ parent_irq[i] = irq_create_mapping(parent, acpi_htvec->cascade[i]);
+
+ ret = htvec_init(acpi_htvec->address, acpi_htvec->size,
+ num_parents, parent_irq, domain_handle);
+
+ if (!ret)
+ acpi_cascade_irqdomain_init();
+ else
+ irq_domain_free_fwnode(domain_handle);
+
+ return ret;
+}
+
+#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH V15 11/15] irqchip/loongson-liointc: Add ACPI init support
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (9 preceding siblings ...)
2022-07-15 7:05 ` [PATCH V15 10/15] irqchip/loongson-htvec: " Jianmin Lv
@ 2022-07-15 7:05 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 12/15] LoongArch: prepare to support multiple pch-pic and pch-msi irqdomain Jianmin Lv
` (4 subsequent siblings)
15 siblings, 0 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
LIOINTC stands for "Legacy I/O Interrupts" that described in Section
11.1 of "Loongson 3A5000 Processor Reference Manual". For more
information please refer Documentation/loongarch/irq-chip-model.rst.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/include/asm/irq.h | 4 +-
arch/loongarch/kernel/irq.c | 1 -
drivers/irqchip/irq-loongson-liointc.c | 225 ++++++++++++++++++++++-----------
3 files changed, 152 insertions(+), 78 deletions(-)
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index 8775dc6..b4c7956 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -97,7 +97,7 @@ static inline void eiointc_enable(void)
struct irq_domain *loongarch_cpu_irq_init(void);
-struct irq_domain *liointc_acpi_init(struct irq_domain *parent,
+int liointc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lio_pic *acpi_liointc);
struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
struct acpi_madt_eio_pic *acpi_eiointc);
@@ -122,7 +122,7 @@ int pch_pic_acpi_init(struct irq_domain *parent,
extern struct acpi_madt_bio_pic *acpi_pchpic[MAX_IO_PICS];
extern struct irq_domain *cpu_domain;
-extern struct irq_domain *liointc_domain;
+extern struct fwnode_handle *liointc_handle;
extern struct fwnode_handle *pch_lpc_handle;
extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index ce21281..b04201c 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -26,7 +26,6 @@
EXPORT_PER_CPU_SYMBOL(irq_stat);
struct irq_domain *cpu_domain;
-struct irq_domain *liointc_domain;
/*
* 'what should we do if we get a hw irq event on an illegal vector'.
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 8d05d8b..93eb01b 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -23,7 +23,7 @@
#endif
#define LIOINTC_CHIP_IRQ 32
-#define LIOINTC_NUM_PARENT 4
+#define LIOINTC_NUM_PARENT 4
#define LIOINTC_NUM_CORES 4
#define LIOINTC_INTC_CHIP_START 0x20
@@ -41,6 +41,7 @@
#if defined(CONFIG_MIPS)
#define liointc_core_id get_ebase_cpunum()
+#define GSI_MIN_CPU_IRQ 0
#else
#define liointc_core_id get_csr_cpuid()
#endif
@@ -58,6 +59,8 @@ struct liointc_priv {
bool has_lpc_irq_errata;
};
+struct fwnode_handle *liointc_handle;
+
static void liointc_chained_handle_irq(struct irq_desc *desc)
{
struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
@@ -153,97 +156,79 @@ static void liointc_resume(struct irq_chip_generic *gc)
irq_gc_unlock_irqrestore(gc, flags);
}
-static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
-static const char * const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
+static int parent_irq[LIOINTC_NUM_PARENT];
+static u32 parent_int_map[LIOINTC_NUM_PARENT];
+static const char *const parent_names[] = {"int0", "int1", "int2", "int3"};
+static const char *const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
-static void __iomem *liointc_get_reg_byname(struct device_node *node,
- const char *name)
+static int liointc_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
+ const u32 *intspec, unsigned int intsize,
+ unsigned long *out_hwirq, unsigned int *out_type)
{
- int index = of_property_match_string(node, "reg-names", name);
-
- if (index < 0)
- return NULL;
-
- return of_iomap(node, index);
+ if (WARN_ON(intsize < 1))
+ return -EINVAL;
+ *out_hwirq = intspec[0] - GSI_MIN_CPU_IRQ;
+ *out_type = IRQ_TYPE_NONE;
+ return 0;
}
-static int __init liointc_of_init(struct device_node *node,
- struct device_node *parent)
+static const struct irq_domain_ops acpi_irq_gc_ops = {
+ .map = irq_map_generic_chip,
+ .unmap = irq_unmap_generic_chip,
+ .xlate = liointc_domain_xlate,
+};
+
+static int liointc_init(phys_addr_t addr, unsigned long size, int revision,
+ struct fwnode_handle *domain_handle, struct device_node *node)
{
+ int i, err;
+ void __iomem *base;
+ struct irq_chip_type *ct;
struct irq_chip_generic *gc;
struct irq_domain *domain;
- struct irq_chip_type *ct;
struct liointc_priv *priv;
- void __iomem *base;
- u32 of_parent_int_map[LIOINTC_NUM_PARENT];
- int parent_irq[LIOINTC_NUM_PARENT];
- bool have_parent = FALSE;
- int sz, i, err = 0;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
- if (of_device_is_compatible(node, "loongson,liointc-2.0")) {
- base = liointc_get_reg_byname(node, "main");
- if (!base) {
- err = -ENODEV;
- goto out_free_priv;
- }
+ base = ioremap(addr, size);
+ if (!base)
+ goto out_free_priv;
- for (i = 0; i < LIOINTC_NUM_CORES; i++)
- priv->core_isr[i] = liointc_get_reg_byname(node, core_reg_names[i]);
- if (!priv->core_isr[0]) {
- err = -ENODEV;
- goto out_iounmap_base;
- }
- } else {
- base = of_iomap(node, 0);
- if (!base) {
- err = -ENODEV;
- goto out_free_priv;
- }
+ for (i = 0; i < LIOINTC_NUM_CORES; i++)
+ priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
- for (i = 0; i < LIOINTC_NUM_CORES; i++)
- priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
- }
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++)
+ priv->handler[i].parent_int_map = parent_int_map[i];
- for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
- parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
- if (parent_irq[i] > 0)
- have_parent = TRUE;
- }
- if (!have_parent) {
- err = -ENODEV;
- goto out_iounmap_isr;
- }
+ if (revision > 1) {
+ for (i = 0; i < LIOINTC_NUM_CORES; i++) {
+ int index = of_property_match_string(node,
+ "reg-names", core_reg_names[i]);
- sz = of_property_read_variable_u32_array(node,
- "loongson,parent_int_map",
- &of_parent_int_map[0],
- LIOINTC_NUM_PARENT,
- LIOINTC_NUM_PARENT);
- if (sz < 4) {
- pr_err("loongson-liointc: No parent_int_map\n");
- err = -ENODEV;
- goto out_iounmap_isr;
- }
+ if (index < 0)
+ return -EINVAL;
- for (i = 0; i < LIOINTC_NUM_PARENT; i++)
- priv->handler[i].parent_int_map = of_parent_int_map[i];
+ priv->core_isr[i] = of_iomap(node, index);
+ }
+ }
/* Setup IRQ domain */
- domain = irq_domain_add_linear(node, 32,
+ if (!acpi_disabled)
+ domain = irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IRQ,
+ &acpi_irq_gc_ops, priv);
+ else
+ domain = irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IRQ,
&irq_generic_chip_ops, priv);
if (!domain) {
pr_err("loongson-liointc: cannot add IRQ domain\n");
- err = -EINVAL;
- goto out_iounmap_isr;
+ goto out_iounmap;
}
- err = irq_alloc_domain_generic_chips(domain, 32, 1,
- node->full_name, handle_level_irq,
- IRQ_NOPROBE, 0, 0);
+ err = irq_alloc_domain_generic_chips(domain, LIOINTC_CHIP_IRQ, 1,
+ (node ? node->full_name : "LIOINTC"),
+ handle_level_irq, 0, IRQ_NOPROBE, 0);
if (err) {
pr_err("loongson-liointc: unable to register IRQ domain\n");
goto out_free_domain;
@@ -299,24 +284,114 @@ static int __init liointc_of_init(struct device_node *node,
liointc_chained_handle_irq, &priv->handler[i]);
}
+ liointc_handle = domain_handle;
return 0;
out_free_domain:
irq_domain_remove(domain);
-out_iounmap_isr:
- for (i = 0; i < LIOINTC_NUM_CORES; i++) {
- if (!priv->core_isr[i])
- continue;
- iounmap(priv->core_isr[i]);
- }
-out_iounmap_base:
+out_iounmap:
iounmap(base);
out_free_priv:
kfree(priv);
- return err;
+ return -EINVAL;
+}
+
+#ifdef CONFIG_OF
+
+static int __init liointc_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ bool have_parent = FALSE;
+ int sz, i, index, revision, err = 0;
+ struct resource res;
+
+ if (!of_device_is_compatible(node, "loongson,liointc-2.0")) {
+ index = 0;
+ revision = 1;
+ } else {
+ index = of_property_match_string(node, "reg-names", "main");
+ revision = 2;
+ }
+
+ if (of_address_to_resource(node, index, &res))
+ return -EINVAL;
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
+ if (parent_irq[i] > 0)
+ have_parent = TRUE;
+ }
+ if (!have_parent)
+ return -ENODEV;
+
+ sz = of_property_read_variable_u32_array(node,
+ "loongson,parent_int_map",
+ &parent_int_map[0],
+ LIOINTC_NUM_PARENT,
+ LIOINTC_NUM_PARENT);
+ if (sz < 4) {
+ pr_err("loongson-liointc: No parent_int_map\n");
+ return -ENODEV;
+ }
+
+ err = liointc_init(res.start, resource_size(&res),
+ revision, of_node_to_fwnode(node), node);
+ if (err < 0)
+ return err;
+
+ return 0;
}
IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
IRQCHIP_DECLARE(loongson_liointc_2_0, "loongson,liointc-2.0", liointc_of_init);
+
+#endif
+
+#ifdef CONFIG_ACPI
+static int __init htintc_parse_madt(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_madt_ht_pic *htintc_entry = (struct acpi_madt_ht_pic *)header;
+ struct irq_domain *parent = irq_find_matching_fwnode(liointc_handle, DOMAIN_BUS_ANY);
+
+ return htvec_acpi_init(parent, htintc_entry);
+}
+
+static int __init acpi_cascade_irqdomain_init(void)
+{
+ acpi_table_parse_madt(ACPI_MADT_TYPE_HT_PIC,
+ htintc_parse_madt, 0);
+ return 0;
+}
+
+int __init liointc_acpi_init(struct irq_domain *parent, struct acpi_madt_lio_pic *acpi_liointc)
+{
+ int ret;
+ struct fwnode_handle *domain_handle;
+
+ if (!acpi_liointc)
+ return -EINVAL;
+
+ parent_int_map[0] = acpi_liointc->cascade_map[0];
+ parent_int_map[1] = acpi_liointc->cascade_map[1];
+
+ parent_irq[0] = irq_create_mapping(parent, acpi_liointc->cascade[0]);
+ parent_irq[1] = irq_create_mapping(parent, acpi_liointc->cascade[1]);
+
+ domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_liointc);
+ if (!domain_handle) {
+ pr_err("Unable to allocate domain handle\n");
+ return -ENOMEM;
+ }
+ ret = liointc_init(acpi_liointc->address, acpi_liointc->size,
+ 1, domain_handle, NULL);
+ if (ret == 0)
+ acpi_cascade_irqdomain_init();
+ else
+ irq_domain_free_fwnode(domain_handle);
+
+ return ret;
+}
+#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH V15 12/15] LoongArch: prepare to support multiple pch-pic and pch-msi irqdomain
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (10 preceding siblings ...)
2022-07-15 7:05 ` [PATCH V15 11/15] irqchip/loongson-liointc: " Jianmin Lv
@ 2022-07-15 7:05 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 13/15] irqchip: Add Loongson Extended I/O interrupt controller support Jianmin Lv
` (3 subsequent siblings)
15 siblings, 0 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
For systems with two chipsets, there are two related pch-pic and
pch-msi irqdomains, each of which has the same node id as its
parent irqdomain. So we use a structure to mantain the relation
of node and it's parent irqdomain as pch irqdomin, the 'pci_segment'
field is only used to match the pci segment of a pci device when
setting msi irqdomain for the device.
struct acpi_vector_group {
int node;
int pci_segment;
struct irq_domain *parent;
};
The field 'pci_segment' and 'node' are initialized from MCFG, and
the parent irqdomain driver will set field 'parent' by matching same
'node'.
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
arch/loongarch/include/asm/irq.h | 8 ++++++++
arch/loongarch/kernel/irq.c | 38 ++++++++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index b4c7956..a07315a 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -48,6 +48,14 @@ static inline bool on_irq_stack(int cpu, unsigned long sp)
#define MAX_IO_PICS 2
#define NR_IRQS (64 + (256 * MAX_IO_PICS))
+struct acpi_vector_group {
+ int node;
+ int pci_segment;
+ struct irq_domain *parent;
+};
+extern struct acpi_vector_group pch_group[MAX_IO_PICS];
+extern struct acpi_vector_group msi_group[MAX_IO_PICS];
+
#define CORES_PER_EIO_NODE 4
#define LOONGSON_CPU_UART0_VEC 10 /* CPU UART0 */
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index b04201c..06f2a15 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -26,6 +26,8 @@
EXPORT_PER_CPU_SYMBOL(irq_stat);
struct irq_domain *cpu_domain;
+struct acpi_vector_group pch_group[MAX_IO_PICS];
+struct acpi_vector_group msi_group[MAX_IO_PICS];
/*
* 'what should we do if we get a hw irq event on an illegal vector'.
@@ -52,6 +54,41 @@ int arch_show_interrupts(struct seq_file *p, int prec)
return 0;
}
+static int __init early_pci_mcfg_parse(struct acpi_table_header *header)
+{
+ struct acpi_table_mcfg *mcfg;
+ struct acpi_mcfg_allocation *mptr;
+ int i, n;
+
+ if (header->length < sizeof(struct acpi_table_mcfg))
+ return -EINVAL;
+
+ n = (header->length - sizeof(struct acpi_table_mcfg)) /
+ sizeof(struct acpi_mcfg_allocation);
+ mcfg = (struct acpi_table_mcfg *)header;
+ mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
+
+ for (i = 0; i < n; i++, mptr++) {
+ msi_group[i].pci_segment = mptr->pci_segment;
+ pch_group[i].node = msi_group[i].node = (mptr->address >> 44) & 0xf;
+ }
+
+ return 0;
+}
+
+static void __init init_vec_parent_group(void)
+{
+ int i;
+
+ for (i = 0; i < MAX_IO_PICS; i++) {
+ msi_group[i].pci_segment = -1;
+ msi_group[i].node = -1;
+ pch_group[i].node = -1;
+ }
+
+ acpi_table_parse(ACPI_SIG_MCFG, early_pci_mcfg_parse);
+}
+
void __init init_IRQ(void)
{
int i;
@@ -65,6 +102,7 @@ void __init init_IRQ(void)
clear_csr_ecfg(ECFG0_IM);
clear_csr_estat(ESTATF_IP);
+ init_vec_parent_group();
irqchip_init();
#ifdef CONFIG_SMP
ipi_irq = EXCCODE_IPI - EXCCODE_INT_START;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH V15 13/15] irqchip: Add Loongson Extended I/O interrupt controller support
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (11 preceding siblings ...)
2022-07-15 7:05 ` [PATCH V15 12/15] LoongArch: prepare to support multiple pch-pic and pch-msi irqdomain Jianmin Lv
@ 2022-07-15 7:05 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 14/15] irqchip: Add LoongArch CPU " Jianmin Lv
` (2 subsequent siblings)
15 siblings, 0 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
EIOINTC stands for "Extended I/O Interrupts" that described in Section
11.2 of "Loongson 3A5000 Processor Reference Manual". For more
information please refer Documentation/loongarch/irq-chip-model.rst.
Loongson-3A5000 has 4 cores per NUMA node, and each NUMA node has an
EIOINTC; while Loongson-3C5000 has 16 cores per NUMA node, and each NUMA
node has 4 EIOINTCs. In other words, 16 cores of one NUMA node in
Loongson-3C5000 are organized in 4 groups, each group connects to an
EIOINTC. We call the "group" here as an EIOINTC node, so each EIOINTC
node always includes 4 cores (both in Loongson-3A5000 and Loongson-
3C5000).
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/include/asm/irq.h | 11 +-
drivers/irqchip/Kconfig | 10 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-loongson-eiointc.c | 395 +++++++++++++++++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
5 files changed, 408 insertions(+), 10 deletions(-)
create mode 100644 drivers/irqchip/irq-loongson-eiointc.c
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index a07315a..a826ac4 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -87,15 +87,6 @@ struct acpi_vector_group {
extern int find_pch_pic(u32 gsi);
extern int eiointc_get_node(int id);
-static inline void eiointc_enable(void)
-{
- uint64_t misc;
-
- misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
- misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
- iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
-}
-
struct acpi_madt_lio_pic;
struct acpi_madt_eio_pic;
struct acpi_madt_ht_pic;
@@ -107,7 +98,7 @@ static inline void eiointc_enable(void)
int liointc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lio_pic *acpi_liointc);
-struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
+int eiointc_acpi_init(struct irq_domain *parent,
struct acpi_madt_eio_pic *acpi_eiointc);
int htvec_acpi_init(struct irq_domain *parent,
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 8844e6b..8f077d3 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -555,6 +555,16 @@ config LOONGSON_LIOINTC
help
Support for the Loongson Local I/O Interrupt Controller.
+config LOONGSON_EIOINTC
+ bool "Loongson Extend I/O Interrupt Controller"
+ depends on LOONGARCH
+ depends on MACH_LOONGSON64
+ default MACH_LOONGSON64
+ select IRQ_DOMAIN_HIERARCHY
+ select GENERIC_IRQ_CHIP
+ help
+ Support for the Loongson3 Extend I/O Interrupt Vector Controller.
+
config LOONGSON_HTPIC
bool "Loongson3 HyperTransport PIC Controller"
depends on MACH_LOONGSON64 && MIPS
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 242b8b3..0cfd4f0 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -104,6 +104,7 @@ obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
obj-$(CONFIG_TI_PRUSS_INTC) += irq-pruss-intc.o
obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
+obj-$(CONFIG_LOONGSON_EIOINTC) += irq-loongson-eiointc.o
obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
obj-$(CONFIG_LOONGSON_HTVEC) += irq-loongson-htvec.o
obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-loongson-pch-pic.o
diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c
new file mode 100644
index 0000000..80d8ca6
--- /dev/null
+++ b/drivers/irqchip/irq-loongson-eiointc.c
@@ -0,0 +1,395 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Loongson Extend I/O Interrupt Controller support
+ *
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#define pr_fmt(fmt) "eiointc: " fmt
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#define EIOINTC_REG_NODEMAP 0x14a0
+#define EIOINTC_REG_IPMAP 0x14c0
+#define EIOINTC_REG_ENABLE 0x1600
+#define EIOINTC_REG_BOUNCE 0x1680
+#define EIOINTC_REG_ISR 0x1800
+#define EIOINTC_REG_ROUTE 0x1c00
+
+#define VEC_REG_COUNT 4
+#define VEC_COUNT_PER_REG 64
+#define VEC_COUNT (VEC_REG_COUNT * VEC_COUNT_PER_REG)
+#define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG)
+#define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG)
+#define EIOINTC_ALL_ENABLE 0xffffffff
+
+#define MAX_EIO_NODES (NR_CPUS / CORES_PER_EIO_NODE)
+
+static int nr_pics;
+
+struct eiointc_priv {
+ u32 node;
+ nodemask_t node_map;
+ cpumask_t cpuspan_map;
+ struct fwnode_handle *domain_handle;
+ struct irq_domain *eiointc_domain;
+};
+
+static struct eiointc_priv *eiointc_priv[MAX_IO_PICS];
+
+static void eiointc_enable(void)
+{
+ uint64_t misc;
+
+ misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
+ misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
+ iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
+}
+
+static int cpu_to_eio_node(int cpu)
+{
+ return cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
+}
+
+static void eiointc_set_irq_route(int pos, unsigned int cpu, unsigned int mnode, nodemask_t *node_map)
+{
+ int i, node, cpu_node, route_node;
+ unsigned char coremap;
+ uint32_t pos_off, data, data_byte, data_mask;
+
+ pos_off = pos & ~3;
+ data_byte = pos & 3;
+ data_mask = ~BIT_MASK(data_byte) & 0xf;
+
+ /* Calculate node and coremap of target irq */
+ cpu_node = cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
+ coremap = BIT(cpu_logical_map(cpu) % CORES_PER_EIO_NODE);
+
+ for_each_online_cpu(i) {
+ node = cpu_to_eio_node(i);
+ if (!node_isset(node, *node_map))
+ continue;
+
+ /* EIO node 0 is in charge of inter-node interrupt dispatch */
+ route_node = (node == mnode) ? cpu_node : node;
+ data = ((coremap | (route_node << 4)) << (data_byte * 8));
+ csr_any_send(EIOINTC_REG_ROUTE + pos_off, data, data_mask, node * CORES_PER_EIO_NODE);
+ }
+}
+
+static DEFINE_RAW_SPINLOCK(affinity_lock);
+
+static int eiointc_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, bool force)
+{
+ unsigned int cpu;
+ unsigned long flags;
+ uint32_t vector, regaddr;
+ struct cpumask intersect_affinity;
+ struct eiointc_priv *priv = d->domain->host_data;
+
+ raw_spin_lock_irqsave(&affinity_lock, flags);
+
+ cpumask_and(&intersect_affinity, affinity, cpu_online_mask);
+ cpumask_and(&intersect_affinity, &intersect_affinity, &priv->cpuspan_map);
+
+ if (cpumask_empty(&intersect_affinity)) {
+ raw_spin_unlock_irqrestore(&affinity_lock, flags);
+ return -EINVAL;
+ }
+ cpu = cpumask_first(&intersect_affinity);
+
+ vector = d->hwirq;
+ regaddr = EIOINTC_REG_ENABLE + ((vector >> 5) << 2);
+
+ /* Mask target vector */
+ csr_any_send(regaddr, EIOINTC_ALL_ENABLE & (~BIT(vector & 0x1F)), 0x0, 0);
+ /* Set route for target vector */
+ eiointc_set_irq_route(vector, cpu, priv->node, &priv->node_map);
+ /* Unmask target vector */
+ csr_any_send(regaddr, EIOINTC_ALL_ENABLE, 0x0, 0);
+
+ irq_data_update_effective_affinity(d, cpumask_of(cpu));
+
+ raw_spin_unlock_irqrestore(&affinity_lock, flags);
+
+ return IRQ_SET_MASK_OK;
+}
+
+static int eiointc_index(int node)
+{
+ int i;
+
+ for (i = 0; i < nr_pics; i++) {
+ if (node_isset(node, eiointc_priv[i]->node_map))
+ return i;
+ }
+
+ return -1;
+}
+
+static int eiointc_router_init(unsigned int cpu)
+{
+ int i, bit;
+ uint32_t data;
+ uint32_t node = cpu_to_eio_node(cpu);
+ uint32_t index = eiointc_index(node);
+
+ if (index < 0) {
+ pr_err("Error: invalid nodemap!\n");
+ return -1;
+ }
+
+ if ((cpu_logical_map(cpu) % CORES_PER_EIO_NODE) == 0) {
+ eiointc_enable();
+
+ for (i = 0; i < VEC_COUNT / 32; i++) {
+ data = (((1 << (i * 2 + 1)) << 16) | (1 << (i * 2)));
+ iocsr_write32(data, EIOINTC_REG_NODEMAP + i * 4);
+ }
+
+ for (i = 0; i < VEC_COUNT / 32 / 4; i++) {
+ bit = BIT(1 + index); /* Route to IP[1 + index] */
+ data = bit | (bit << 8) | (bit << 16) | (bit << 24);
+ iocsr_write32(data, EIOINTC_REG_IPMAP + i * 4);
+ }
+
+ for (i = 0; i < VEC_COUNT / 4; i++) {
+ /* Route to Node-0 Core-0 */
+ if (index == 0)
+ bit = BIT(cpu_logical_map(0));
+ else
+ bit = (eiointc_priv[index]->node << 4) | 1;
+
+ data = bit | (bit << 8) | (bit << 16) | (bit << 24);
+ iocsr_write32(data, EIOINTC_REG_ROUTE + i * 4);
+ }
+
+ for (i = 0; i < VEC_COUNT / 32; i++) {
+ data = 0xffffffff;
+ iocsr_write32(data, EIOINTC_REG_ENABLE + i * 4);
+ iocsr_write32(data, EIOINTC_REG_BOUNCE + i * 4);
+ }
+ }
+
+ return 0;
+}
+
+static void eiointc_irq_dispatch(struct irq_desc *desc)
+{
+ int i;
+ u64 pending;
+ bool handled = false;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct eiointc_priv *priv = irq_desc_get_handler_data(desc);
+
+ chained_irq_enter(chip, desc);
+
+ for (i = 0; i < VEC_REG_COUNT; i++) {
+ pending = iocsr_read64(EIOINTC_REG_ISR + (i << 3));
+ iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3));
+ while (pending) {
+ int bit = __ffs(pending);
+ int irq = bit + VEC_COUNT_PER_REG * i;
+
+ generic_handle_domain_irq(priv->eiointc_domain, irq);
+ pending &= ~BIT(bit);
+ handled = true;
+ }
+ }
+
+ if (!handled)
+ spurious_interrupt();
+
+ chained_irq_exit(chip, desc);
+}
+
+static void eiointc_ack_irq(struct irq_data *d)
+{
+}
+
+static void eiointc_mask_irq(struct irq_data *d)
+{
+}
+
+static void eiointc_unmask_irq(struct irq_data *d)
+{
+}
+
+static struct irq_chip eiointc_irq_chip = {
+ .name = "EIOINTC",
+ .irq_ack = eiointc_ack_irq,
+ .irq_mask = eiointc_mask_irq,
+ .irq_unmask = eiointc_unmask_irq,
+ .irq_set_affinity = eiointc_set_irq_affinity,
+};
+
+static int eiointc_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *arg)
+{
+ int ret;
+ unsigned int i, type;
+ unsigned long hwirq = 0;
+ struct eiointc *priv = domain->host_data;
+
+ ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < nr_irqs; i++) {
+ irq_domain_set_info(domain, virq + i, hwirq + i, &eiointc_irq_chip,
+ priv, handle_edge_irq, NULL, NULL);
+ }
+
+ return 0;
+}
+
+static void eiointc_domain_free(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs)
+{
+ int i;
+
+ for (i = 0; i < nr_irqs; i++) {
+ struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
+
+ irq_set_handler(virq + i, NULL);
+ irq_domain_reset_irq_data(d);
+ }
+}
+
+static const struct irq_domain_ops eiointc_domain_ops = {
+ .translate = irq_domain_translate_onecell,
+ .alloc = eiointc_domain_alloc,
+ .free = eiointc_domain_free,
+};
+
+static void acpi_set_vec_parent(int node, struct irq_domain *parent, struct acpi_vector_group *vec_group)
+{
+ int i;
+
+ if (cpu_has_flatmode)
+ node = cpu_to_node(node * CORES_PER_EIO_NODE);
+
+ for (i = 0; i < MAX_IO_PICS; i++) {
+ if (node == vec_group[i].node) {
+ vec_group[i].parent = parent;
+ return;
+ }
+ }
+}
+
+struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector_group *vec_group)
+{
+ int i;
+
+ for (i = 0; i < MAX_IO_PICS; i++) {
+ if (node == vec_group[i].node)
+ return vec_group[i].parent;
+ }
+ return NULL;
+}
+
+static int __init
+pch_pic_parse_madt(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header;
+ unsigned int node = (pchpic_entry->address >> 44) & 0xf;
+ struct irq_domain *parent = acpi_get_vec_parent(node, pch_group);
+
+ if (parent)
+ return pch_pic_acpi_init(parent, pchpic_entry);
+
+ return -EINVAL;
+}
+
+static int __init
+pch_msi_parse_madt(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header;
+ struct irq_domain *parent = acpi_get_vec_parent(eiointc_priv[nr_pics - 1]->node, msi_group);
+
+ if (parent)
+ return pch_msi_acpi_init(parent, pchmsi_entry);
+
+ return -EINVAL;
+}
+
+static int __init acpi_cascade_irqdomain_init(void)
+{
+ acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC,
+ pch_pic_parse_madt, 0);
+ acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC,
+ pch_msi_parse_madt, 1);
+ return 0;
+}
+
+int __init eiointc_acpi_init(struct irq_domain *parent,
+ struct acpi_madt_eio_pic *acpi_eiointc)
+{
+ int i, parent_irq;
+ unsigned long node_map;
+ struct eiointc_priv *priv;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_eiointc);
+ if (!priv->domain_handle) {
+ pr_err("Unable to allocate domain handle\n");
+ goto out_free_priv;
+ }
+
+ priv->node = acpi_eiointc->node;
+ node_map = acpi_eiointc->node_map ? : -1ULL;
+
+ for_each_possible_cpu(i) {
+ if (node_map & (1ULL << cpu_to_eio_node(i))) {
+ node_set(cpu_to_eio_node(i), priv->node_map);
+ cpumask_or(&priv->cpuspan_map, &priv->cpuspan_map, cpumask_of(i));
+ }
+ }
+
+ /* Setup IRQ domain */
+ priv->eiointc_domain = irq_domain_create_linear(priv->domain_handle, VEC_COUNT,
+ &eiointc_domain_ops, priv);
+ if (!priv->eiointc_domain) {
+ pr_err("loongson-eiointc: cannot add IRQ domain\n");
+ goto out_free_handle;
+ }
+
+ eiointc_priv[nr_pics++] = priv;
+
+ eiointc_router_init(0);
+
+ parent_irq = irq_create_mapping(parent, acpi_eiointc->cascade);
+ irq_set_chained_handler_and_data(parent_irq, eiointc_irq_dispatch, priv);
+
+ cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_LOONGARCH_STARTING,
+ "irqchip/loongarch/intc:starting",
+ eiointc_router_init, NULL);
+
+ acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, pch_group);
+ acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, msi_group);
+ acpi_cascade_irqdomain_init();
+
+ return 0;
+
+out_free_handle:
+ irq_domain_free_fwnode(priv->domain_handle);
+ priv->domain_handle = NULL;
+out_free_priv:
+ kfree(priv);
+
+ return -ENOMEM;
+}
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 19f0dbf..de662f3 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -151,6 +151,7 @@ enum cpuhp_state {
CPUHP_AP_IRQ_BCM2836_STARTING,
CPUHP_AP_IRQ_MIPS_GIC_STARTING,
CPUHP_AP_IRQ_RISCV_STARTING,
+ CPUHP_AP_IRQ_LOONGARCH_STARTING,
CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
CPUHP_AP_ARM_MVEBU_COHERENCY,
CPUHP_AP_MICROCODE_LOADER,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH V15 14/15] irqchip: Add LoongArch CPU interrupt controller support
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (12 preceding siblings ...)
2022-07-15 7:05 ` [PATCH V15 13/15] irqchip: Add Loongson Extended I/O interrupt controller support Jianmin Lv
@ 2022-07-15 7:05 ` Jianmin Lv
2022-07-15 15:11 ` Huacai Chen
2022-07-15 7:05 ` [PATCH V15 15/15] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch Jianmin Lv
2022-07-16 18:39 ` [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Marc Zyngier
15 siblings, 1 reply; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
From: Huacai Chen <chenhuacai@loongson.cn>
LoongArch CPUINTC stands for CSR.ECFG/CSR.ESTAT and related interrupt
controller that described in Section 7.4 of "LoongArch Reference Manual,
Vol 1". For more information please refer Documentation/loongarch/irq-
chip-model.rst.
LoongArch CPUINTC has 13 interrupt sources: SWI0~1, HWI0~7, IPI, TI
(Timer) and PCOV (PMC). IRQ mappings of HWI0~7 are configurable (can be
created from DT/ACPI), but IPI, TI (Timer) and PCOV (PMC) are hardcoded
bits, so we expose the fwnode_handle to map them, and get mapped irq
by irq_create_mapping when using them.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/include/asm/irq.h | 8 +--
arch/loongarch/kernel/irq.c | 15 ++++-
arch/loongarch/kernel/time.c | 14 ++++-
drivers/irqchip/Kconfig | 10 +++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-loongarch-cpu.c | 119 ++++++++++++++++++++++++++++++++++++
6 files changed, 157 insertions(+), 10 deletions(-)
create mode 100644 drivers/irqchip/irq-loongarch-cpu.c
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index a826ac4..ca46856 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -35,9 +35,6 @@ static inline bool on_irq_stack(int cpu, unsigned long sp)
return (low <= sp && sp <= high);
}
-int get_ipi_irq(void);
-int get_pmc_irq(void);
-int get_timer_irq(void);
void spurious_interrupt(void);
#define NR_IRQS_LEGACY 16
@@ -94,13 +91,10 @@ struct acpi_vector_group {
struct acpi_madt_msi_pic;
struct acpi_madt_lpc_pic;
-struct irq_domain *loongarch_cpu_irq_init(void);
-
int liointc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lio_pic *acpi_liointc);
int eiointc_acpi_init(struct irq_domain *parent,
struct acpi_madt_eio_pic *acpi_eiointc);
-
int htvec_acpi_init(struct irq_domain *parent,
struct acpi_madt_ht_pic *acpi_htvec);
int pch_lpc_acpi_init(struct irq_domain *parent,
@@ -120,7 +114,7 @@ int pch_pic_acpi_init(struct irq_domain *parent,
extern struct acpi_madt_msi_pic *acpi_pchmsi[MAX_IO_PICS];
extern struct acpi_madt_bio_pic *acpi_pchpic[MAX_IO_PICS];
-extern struct irq_domain *cpu_domain;
+extern struct fwnode_handle *cpuintc_handle;
extern struct fwnode_handle *liointc_handle;
extern struct fwnode_handle *pch_lpc_handle;
extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index 06f2a15..99924d8 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -25,7 +25,6 @@
DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
EXPORT_PER_CPU_SYMBOL(irq_stat);
-struct irq_domain *cpu_domain;
struct acpi_vector_group pch_group[MAX_IO_PICS];
struct acpi_vector_group msi_group[MAX_IO_PICS];
@@ -89,6 +88,16 @@ static void __init init_vec_parent_group(void)
acpi_table_parse(ACPI_SIG_MCFG, early_pci_mcfg_parse);
}
+static int __init get_ipi_irq(void)
+{
+ struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
+
+ if (d)
+ return irq_create_mapping(d, EXCCODE_IPI - EXCCODE_INT_START);
+
+ return -EINVAL;
+}
+
void __init init_IRQ(void)
{
int i;
@@ -105,7 +114,9 @@ void __init init_IRQ(void)
init_vec_parent_group();
irqchip_init();
#ifdef CONFIG_SMP
- ipi_irq = EXCCODE_IPI - EXCCODE_INT_START;
+ ipi_irq = get_ipi_irq();
+ if (ipi_irq < 0)
+ panic("IPI IRQ mapping failed\n");
irq_set_percpu_devid(ipi_irq);
r = request_percpu_irq(ipi_irq, loongson3_ipi_interrupt, "IPI", &ipi_dummy_dev);
if (r < 0)
diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c
index fe68238..79dc5ed 100644
--- a/arch/loongarch/kernel/time.c
+++ b/arch/loongarch/kernel/time.c
@@ -123,6 +123,16 @@ void sync_counter(void)
csr_write64(-init_timeval, LOONGARCH_CSR_CNTC);
}
+static int get_timer_irq(void)
+{
+ struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
+
+ if (d)
+ return irq_create_mapping(d, EXCCODE_TIMER - EXCCODE_INT_START);
+
+ return -EINVAL;
+}
+
int constant_clockevent_init(void)
{
unsigned int irq;
@@ -132,7 +142,9 @@ int constant_clockevent_init(void)
struct clock_event_device *cd;
static int timer_irq_installed = 0;
- irq = EXCCODE_TIMER - EXCCODE_INT_START;
+ irq = get_timer_irq();
+ if (irq < 0)
+ pr_err("Failed to map irq %d (timer)\n", irq);
cd = &per_cpu(constant_clockevent_device, cpu);
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 8f077d3..f53164c 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -546,6 +546,16 @@ config EXYNOS_IRQ_COMBINER
Say yes here to add support for the IRQ combiner devices embedded
in Samsung Exynos chips.
+config IRQ_LOONGARCH_CPU
+ bool
+ select GENERIC_IRQ_CHIP
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_EFFECTIVE_AFF_MASK
+ help
+ Support for the LoongArch CPU Interrupt Controller. For details of
+ irq chip hierarchy on LoongArch platforms please read the document
+ Documentation/loongarch/irq-chip-model.rst.
+
config LOONGSON_LIOINTC
bool "Loongson Local I/O Interrupt Controller"
depends on MACH_LOONGSON64
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 0cfd4f0..e559007 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -103,6 +103,7 @@ obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
obj-$(CONFIG_TI_PRUSS_INTC) += irq-pruss-intc.o
+obj-$(CONFIG_IRQ_LOONGARCH_CPU) += irq-loongarch-cpu.o
obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
obj-$(CONFIG_LOONGSON_EIOINTC) += irq-loongson-eiointc.o
obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loongarch-cpu.c
new file mode 100644
index 0000000..476f407
--- /dev/null
+++ b/drivers/irqchip/irq-loongarch-cpu.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+
+#include <asm/loongarch.h>
+#include <asm/setup.h>
+
+static struct irq_domain *irq_domain;
+struct fwnode_handle *cpuintc_handle;
+
+static void mask_loongarch_irq(struct irq_data *d)
+{
+ clear_csr_ecfg(ECFGF(d->hwirq));
+}
+
+static void unmask_loongarch_irq(struct irq_data *d)
+{
+ set_csr_ecfg(ECFGF(d->hwirq));
+}
+
+static struct irq_chip cpu_irq_controller = {
+ .name = "CPUINTC",
+ .irq_mask = mask_loongarch_irq,
+ .irq_unmask = unmask_loongarch_irq,
+};
+
+static void handle_cpu_irq(struct pt_regs *regs)
+{
+ int hwirq;
+ unsigned int estat = read_csr_estat() & CSR_ESTAT_IS;
+
+ while ((hwirq = ffs(estat))) {
+ estat &= ~BIT(hwirq - 1);
+ generic_handle_domain_irq(irq_domain, hwirq - 1);
+ }
+}
+
+static int loongarch_cpu_intc_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ irq_set_noprobe(irq);
+ irq_set_chip_and_handler(irq, &cpu_irq_controller, handle_percpu_irq);
+
+ return 0;
+}
+
+static const struct irq_domain_ops loongarch_cpu_intc_irq_domain_ops = {
+ .map = loongarch_cpu_intc_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static int __init loongarch_cpu_irq_init(void)
+{
+ /* Mask interrupts. */
+ clear_csr_ecfg(ECFG0_IM);
+ clear_csr_estat(ESTATF_IP);
+
+ cpuintc_handle = irq_domain_alloc_fwnode(NULL);
+ irq_domain = irq_domain_create_linear(cpuintc_handle, EXCCODE_INT_NUM,
+ &loongarch_cpu_intc_irq_domain_ops, NULL);
+
+ if (!irq_domain)
+ panic("Failed to add irqdomain for LoongArch CPU");
+
+ set_handle_irq(&handle_cpu_irq);
+
+ return 0;
+}
+
+static int __init
+liointc_parse_madt(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_madt_lio_pic *liointc_entry = (struct acpi_madt_lio_pic *)header;
+
+ return liointc_acpi_init(irq_domain, liointc_entry);
+}
+
+static int __init
+eiointc_parse_madt(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_madt_eio_pic *eiointc_entry = (struct acpi_madt_eio_pic *)header;
+
+ return eiointc_acpi_init(irq_domain, eiointc_entry);
+}
+
+static int __init acpi_cascade_irqdomain_init(void)
+{
+ acpi_table_parse_madt(ACPI_MADT_TYPE_LIO_PIC,
+ liointc_parse_madt, 0);
+ acpi_table_parse_madt(ACPI_MADT_TYPE_EIO_PIC,
+ eiointc_parse_madt, 0);
+ return 0;
+}
+
+static int __init coreintc_acpi_init_v1(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ if (irq_domain)
+ return 0;
+
+ loongarch_cpu_irq_init();
+ acpi_cascade_irqdomain_init();
+
+ return 0;
+}
+
+IRQCHIP_ACPI_DECLARE(coreintc_v1, ACPI_MADT_TYPE_CORE_PIC,
+ NULL, ACPI_MADT_CORE_PIC_VERSION_V1,
+ coreintc_acpi_init_v1);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH V15 15/15] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (13 preceding siblings ...)
2022-07-15 7:05 ` [PATCH V15 14/15] irqchip: Add LoongArch CPU " Jianmin Lv
@ 2022-07-15 7:05 ` Jianmin Lv
2022-07-16 18:39 ` [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Marc Zyngier
15 siblings, 0 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-15 7:05 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, loongarch, Hanjun Guo, Lorenzo Pieralisi,
Jiaxun Yang, Huacai Chen
For LoongArch, ACPI_IRQ_MODEL_LPIC is introduced, and then the
callback acpi_get_gsi_domain_id and acpi_gsi_to_irq_fallback are
implemented.
The acpi_get_gsi_domain_id callback returns related fwnode handle
of irqdomain for different GSI range.
The acpi_gsi_to_irq_fallback will create new mapping for gsi when
the mapping of it is not found.
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
drivers/acpi/bus.c | 3 +++
drivers/irqchip/irq-loongarch-cpu.c | 38 +++++++++++++++++++++++++++++++++++++
include/linux/acpi.h | 1 +
3 files changed, 42 insertions(+)
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 86fa61a..63fbf00 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -1145,6 +1145,9 @@ static int __init acpi_bus_init_irq(void)
case ACPI_IRQ_MODEL_PLATFORM:
message = "platform specific model";
break;
+ case ACPI_IRQ_MODEL_LPIC:
+ message = "LPIC";
+ break;
default:
pr_info("Unknown interrupt routing model\n");
return -ENODEV;
diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loongarch-cpu.c
index 476f407..93a4b15 100644
--- a/drivers/irqchip/irq-loongarch-cpu.c
+++ b/drivers/irqchip/irq-loongarch-cpu.c
@@ -16,6 +16,42 @@
static struct irq_domain *irq_domain;
struct fwnode_handle *cpuintc_handle;
+static u32 lpic_gsi_to_irq(u32 gsi)
+{
+ /* Only pch irqdomain transferring is required for LoongArch. */
+ if (gsi >= GSI_MIN_PCH_IRQ && gsi <= GSI_MAX_PCH_IRQ)
+ return acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH);
+
+ return 0;
+}
+
+static struct fwnode_handle *lpic_get_gsi_domain_id(u32 gsi)
+{
+ int id;
+ struct fwnode_handle *domain_handle = NULL;
+
+ switch (gsi) {
+ case GSI_MIN_CPU_IRQ ... GSI_MAX_CPU_IRQ:
+ if (liointc_handle)
+ domain_handle = liointc_handle;
+ break;
+
+ case GSI_MIN_LPC_IRQ ... GSI_MAX_LPC_IRQ:
+ if (pch_lpc_handle)
+ domain_handle = pch_lpc_handle;
+ break;
+
+ case GSI_MIN_PCH_IRQ ... GSI_MAX_PCH_IRQ:
+ id = find_pch_pic(gsi);
+ if (id >= 0 && pch_pic_handle[id])
+ domain_handle = pch_pic_handle[id];
+
+ break;
+ }
+
+ return domain_handle;
+}
+
static void mask_loongarch_irq(struct irq_data *d)
{
clear_csr_ecfg(ECFGF(d->hwirq));
@@ -71,6 +107,8 @@ static int __init loongarch_cpu_irq_init(void)
panic("Failed to add irqdomain for LoongArch CPU");
set_handle_irq(&handle_cpu_irq);
+ acpi_set_irq_model(ACPI_IRQ_MODEL_LPIC, lpic_get_gsi_domain_id);
+ acpi_set_gsi_to_irq_fallback(lpic_gsi_to_irq);
return 0;
}
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index e2b60d5..76520f3 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -105,6 +105,7 @@ enum acpi_irq_model_id {
ACPI_IRQ_MODEL_IOSAPIC,
ACPI_IRQ_MODEL_PLATFORM,
ACPI_IRQ_MODEL_GIC,
+ ACPI_IRQ_MODEL_LPIC,
ACPI_IRQ_MODEL_COUNT
};
--
1.8.3.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH V15 14/15] irqchip: Add LoongArch CPU interrupt controller support
2022-07-15 7:05 ` [PATCH V15 14/15] irqchip: Add LoongArch CPU " Jianmin Lv
@ 2022-07-15 15:11 ` Huacai Chen
2022-07-17 12:02 ` Jianmin Lv
0 siblings, 1 reply; 36+ messages in thread
From: Huacai Chen @ 2022-07-15 15:11 UTC (permalink / raw)
To: Jianmin Lv
Cc: Thomas Gleixner, Marc Zyngier, LKML, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
Hi, Jianmin,
On Fri, Jul 15, 2022 at 3:11 PM Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
> From: Huacai Chen <chenhuacai@loongson.cn>
>
> LoongArch CPUINTC stands for CSR.ECFG/CSR.ESTAT and related interrupt
> controller that described in Section 7.4 of "LoongArch Reference Manual,
> Vol 1". For more information please refer Documentation/loongarch/irq-
> chip-model.rst.
>
> LoongArch CPUINTC has 13 interrupt sources: SWI0~1, HWI0~7, IPI, TI
> (Timer) and PCOV (PMC). IRQ mappings of HWI0~7 are configurable (can be
> created from DT/ACPI), but IPI, TI (Timer) and PCOV (PMC) are hardcoded
> bits, so we expose the fwnode_handle to map them, and get mapped irq
> by irq_create_mapping when using them.
>
> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> ---
> arch/loongarch/include/asm/irq.h | 8 +--
> arch/loongarch/kernel/irq.c | 15 ++++-
> arch/loongarch/kernel/time.c | 14 ++++-
> drivers/irqchip/Kconfig | 10 +++
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-loongarch-cpu.c | 119 ++++++++++++++++++++++++++++++++++++
> 6 files changed, 157 insertions(+), 10 deletions(-)
> create mode 100644 drivers/irqchip/irq-loongarch-cpu.c
>
> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
> index a826ac4..ca46856 100644
> --- a/arch/loongarch/include/asm/irq.h
> +++ b/arch/loongarch/include/asm/irq.h
> @@ -35,9 +35,6 @@ static inline bool on_irq_stack(int cpu, unsigned long sp)
> return (low <= sp && sp <= high);
> }
>
> -int get_ipi_irq(void);
> -int get_pmc_irq(void);
> -int get_timer_irq(void);
> void spurious_interrupt(void);
>
> #define NR_IRQS_LEGACY 16
> @@ -94,13 +91,10 @@ struct acpi_vector_group {
> struct acpi_madt_msi_pic;
> struct acpi_madt_lpc_pic;
>
> -struct irq_domain *loongarch_cpu_irq_init(void);
> -
> int liointc_acpi_init(struct irq_domain *parent,
> struct acpi_madt_lio_pic *acpi_liointc);
> int eiointc_acpi_init(struct irq_domain *parent,
> struct acpi_madt_eio_pic *acpi_eiointc);
> -
> int htvec_acpi_init(struct irq_domain *parent,
> struct acpi_madt_ht_pic *acpi_htvec);
> int pch_lpc_acpi_init(struct irq_domain *parent,
> @@ -120,7 +114,7 @@ int pch_pic_acpi_init(struct irq_domain *parent,
> extern struct acpi_madt_msi_pic *acpi_pchmsi[MAX_IO_PICS];
> extern struct acpi_madt_bio_pic *acpi_pchpic[MAX_IO_PICS];
>
> -extern struct irq_domain *cpu_domain;
> +extern struct fwnode_handle *cpuintc_handle;
> extern struct fwnode_handle *liointc_handle;
> extern struct fwnode_handle *pch_lpc_handle;
> extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
> diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
> index 06f2a15..99924d8 100644
> --- a/arch/loongarch/kernel/irq.c
> +++ b/arch/loongarch/kernel/irq.c
> @@ -25,7 +25,6 @@
> DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
> EXPORT_PER_CPU_SYMBOL(irq_stat);
>
> -struct irq_domain *cpu_domain;
> struct acpi_vector_group pch_group[MAX_IO_PICS];
> struct acpi_vector_group msi_group[MAX_IO_PICS];
>
> @@ -89,6 +88,16 @@ static void __init init_vec_parent_group(void)
> acpi_table_parse(ACPI_SIG_MCFG, early_pci_mcfg_parse);
> }
>
> +static int __init get_ipi_irq(void)
> +{
> + struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
> +
> + if (d)
> + return irq_create_mapping(d, EXCCODE_IPI - EXCCODE_INT_START);
> +
> + return -EINVAL;
> +}
> +
> void __init init_IRQ(void)
> {
> int i;
> @@ -105,7 +114,9 @@ void __init init_IRQ(void)
> init_vec_parent_group();
> irqchip_init();
> #ifdef CONFIG_SMP
> - ipi_irq = EXCCODE_IPI - EXCCODE_INT_START;
> + ipi_irq = get_ipi_irq();
> + if (ipi_irq < 0)
> + panic("IPI IRQ mapping failed\n");
> irq_set_percpu_devid(ipi_irq);
> r = request_percpu_irq(ipi_irq, loongson3_ipi_interrupt, "IPI", &ipi_dummy_dev);
> if (r < 0)
> diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c
> index fe68238..79dc5ed 100644
> --- a/arch/loongarch/kernel/time.c
> +++ b/arch/loongarch/kernel/time.c
> @@ -123,6 +123,16 @@ void sync_counter(void)
> csr_write64(-init_timeval, LOONGARCH_CSR_CNTC);
> }
>
> +static int get_timer_irq(void)
> +{
> + struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
> +
> + if (d)
> + return irq_create_mapping(d, EXCCODE_TIMER - EXCCODE_INT_START);
> +
> + return -EINVAL;
> +}
> +
> int constant_clockevent_init(void)
> {
> unsigned int irq;
> @@ -132,7 +142,9 @@ int constant_clockevent_init(void)
> struct clock_event_device *cd;
> static int timer_irq_installed = 0;
>
> - irq = EXCCODE_TIMER - EXCCODE_INT_START;
> + irq = get_timer_irq();
> + if (irq < 0)
> + pr_err("Failed to map irq %d (timer)\n", irq);
>
> cd = &per_cpu(constant_clockevent_device, cpu);
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 8f077d3..f53164c 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -546,6 +546,16 @@ config EXYNOS_IRQ_COMBINER
> Say yes here to add support for the IRQ combiner devices embedded
> in Samsung Exynos chips.
>
> +config IRQ_LOONGARCH_CPU
> + bool
> + select GENERIC_IRQ_CHIP
> + select IRQ_DOMAIN
> + select GENERIC_IRQ_EFFECTIVE_AFF_MASK
> + help
> + Support for the LoongArch CPU Interrupt Controller. For details of
> + irq chip hierarchy on LoongArch platforms please read the document
> + Documentation/loongarch/irq-chip-model.rst.
> +
> config LOONGSON_LIOINTC
> bool "Loongson Local I/O Interrupt Controller"
> depends on MACH_LOONGSON64
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 0cfd4f0..e559007 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -103,6 +103,7 @@ obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
> obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
> obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
> obj-$(CONFIG_TI_PRUSS_INTC) += irq-pruss-intc.o
> +obj-$(CONFIG_IRQ_LOONGARCH_CPU) += irq-loongarch-cpu.o
> obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
> obj-$(CONFIG_LOONGSON_EIOINTC) += irq-loongson-eiointc.o
> obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
> diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loongarch-cpu.c
> new file mode 100644
> index 0000000..476f407
> --- /dev/null
> +++ b/drivers/irqchip/irq-loongarch-cpu.c
> @@ -0,0 +1,119 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
> + */
> +
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqdomain.h>
> +
> +#include <asm/loongarch.h>
> +#include <asm/setup.h>
> +
> +static struct irq_domain *irq_domain;
> +struct fwnode_handle *cpuintc_handle;
> +
> +static void mask_loongarch_irq(struct irq_data *d)
> +{
> + clear_csr_ecfg(ECFGF(d->hwirq));
> +}
> +
> +static void unmask_loongarch_irq(struct irq_data *d)
> +{
> + set_csr_ecfg(ECFGF(d->hwirq));
> +}
> +
> +static struct irq_chip cpu_irq_controller = {
> + .name = "CPUINTC",
> + .irq_mask = mask_loongarch_irq,
> + .irq_unmask = unmask_loongarch_irq,
> +};
> +
> +static void handle_cpu_irq(struct pt_regs *regs)
> +{
> + int hwirq;
> + unsigned int estat = read_csr_estat() & CSR_ESTAT_IS;
> +
> + while ((hwirq = ffs(estat))) {
> + estat &= ~BIT(hwirq - 1);
> + generic_handle_domain_irq(irq_domain, hwirq - 1);
> + }
> +}
> +
> +static int loongarch_cpu_intc_map(struct irq_domain *d, unsigned int irq,
> + irq_hw_number_t hwirq)
> +{
> + irq_set_noprobe(irq);
> + irq_set_chip_and_handler(irq, &cpu_irq_controller, handle_percpu_irq);
> +
> + return 0;
> +}
> +
> +static const struct irq_domain_ops loongarch_cpu_intc_irq_domain_ops = {
> + .map = loongarch_cpu_intc_map,
> + .xlate = irq_domain_xlate_onecell,
> +};
> +
> +static int __init loongarch_cpu_irq_init(void)
> +{
> + /* Mask interrupts. */
> + clear_csr_ecfg(ECFG0_IM);
> + clear_csr_estat(ESTATF_IP);
> +
> + cpuintc_handle = irq_domain_alloc_fwnode(NULL);
> + irq_domain = irq_domain_create_linear(cpuintc_handle, EXCCODE_INT_NUM,
> + &loongarch_cpu_intc_irq_domain_ops, NULL);
> +
> + if (!irq_domain)
> + panic("Failed to add irqdomain for LoongArch CPU");
> +
> + set_handle_irq(&handle_cpu_irq);
> +
> + return 0;
> +}
> +
> +static int __init
> +liointc_parse_madt(union acpi_subtable_headers *header,
> + const unsigned long end)
> +{
> + struct acpi_madt_lio_pic *liointc_entry = (struct acpi_madt_lio_pic *)header;
> +
> + return liointc_acpi_init(irq_domain, liointc_entry);
> +}
> +
> +static int __init
> +eiointc_parse_madt(union acpi_subtable_headers *header,
> + const unsigned long end)
> +{
> + struct acpi_madt_eio_pic *eiointc_entry = (struct acpi_madt_eio_pic *)header;
> +
> + return eiointc_acpi_init(irq_domain, eiointc_entry);
> +}
> +
> +static int __init acpi_cascade_irqdomain_init(void)
> +{
> + acpi_table_parse_madt(ACPI_MADT_TYPE_LIO_PIC,
> + liointc_parse_madt, 0);
> + acpi_table_parse_madt(ACPI_MADT_TYPE_EIO_PIC,
> + eiointc_parse_madt, 0);
> + return 0;
> +}
> +
> +static int __init coreintc_acpi_init_v1(union acpi_subtable_headers *header,
> + const unsigned long end)
> +{
> + if (irq_domain)
> + return 0;
> +
> + loongarch_cpu_irq_init();
> + acpi_cascade_irqdomain_init();
> +
> + return 0;
> +}
> +
> +IRQCHIP_ACPI_DECLARE(coreintc_v1, ACPI_MADT_TYPE_CORE_PIC,
> + NULL, ACPI_MADT_CORE_PIC_VERSION_V1,
> + coreintc_acpi_init_v1);
I think loongarch_cpu_irq_init() and coreintc_acpi_init_v1() can be
merged like below, which makes code simpler.
static int __init loongarch_cpu_irq_init(union acpi_subtable_headers
*header, const unsigned long end)
{
struct fwnode_handle *domain_handle;
if (irq_domain)
return 0;
/* Mask interrupts. */
clear_csr_ecfg(ECFG0_IM);
clear_csr_estat(ESTATF_IP);
domain_handle = irq_domain_alloc_fwnode(NULL);
irq_domain = irq_domain_create_linear(domain_handle, EXCCODE_INT_NUM,
&loongarch_cpu_intc_irq_domain_ops, NULL);
if (!irq_domain)
panic("Failed to add irqdomain for LoongArch CPU");
acpi_cascade_irqdomain_init();
set_handle_irq(&handle_cpu_irq);
return 0;
}
IRQCHIP_ACPI_DECLARE(cpuintc_v1, ACPI_MADT_TYPE_CORE_PIC,
NULL, ACPI_MADT_CORE_PIC_VERSION_V1, loongarch_cpu_irq_init);
Thanks,
Huacai
> --
> 1.8.3.1
>
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 01/15] ACPICA: MADT: Add LoongArch APICs support
2022-07-15 7:05 ` [PATCH V15 01/15] ACPICA: MADT: Add LoongArch APICs support Jianmin Lv
@ 2022-07-16 18:10 ` Marc Zyngier
2022-07-17 1:05 ` Jianmin Lv
2022-07-18 12:28 ` Jianmin Lv
0 siblings, 2 replies; 36+ messages in thread
From: Marc Zyngier @ 2022-07-16 18:10 UTC (permalink / raw)
To: Jianmin Lv, Robert Moore
Cc: Thomas Gleixner, linux-kernel, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
[+ Robert Moore]
On Fri, 15 Jul 2022 08:05:37 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
> From: Huacai Chen <chenhuacai@loongson.cn>
>
> LoongArch-specific interrupt controllers (similar to APIC) are added
> in the next revision of ACPI Specification (current revision is 6.4),
> which including CORE_PIC (CPUINTC), LIO_PIC (LIOINTC), EIO_PIC (EIOINTC),
> HT_PIC (HTVECINTC), BIO_PIC (PCHINTC), LPC_PIC (PCHLPC) and MSI_PIC
> (PCHMSI). This patch add their definition.
>
> ACPI changes of LoongArch-specific interrupt controllers have already
> been approved in the ECRs, and will be public in the next revision of
> ACPI Specification.
>
> Reference: https://mantis.uefi.org/mantis/view.php?id=2203
> Reference: https://mantis.uefi.org/mantis/view.php?id=2313
>
> Above links needs login(available for ASWG), so the following link(
> the ECR file for adding LoongArch APICs into ACPI spec) is provided
> for public:
>
> https://github.com/lvjianmin-loongson/acpica/blob/master/Add%20APIC%20Structures%20for%20Loongarch%20in%20MADT-rev3.pdf
>
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Since the ACPI maintainers are unwilling to take this patch (for
undisclosed reasons), we need something to unblock this sorry
situation, as I don't think it is fair on the LoongArch folks to be
blocked for another cycle on this ground only.
I'm proposing to replace this patch with the following, which will
allow the patches to be merged without breaking anything. Once the
ACPI support is updated, we'll be able to simply revert this patch.
Thanks,
M.
From 43ec25d2dbde3c422cce430c9d5ec32fbe7b255c Mon Sep 17 00:00:00 2001
From: Marc Zyngier <maz@kernel.org>
Date: Sat, 16 Jul 2022 18:56:10 +0100
Subject: [PATCH] LoongArch: Provisionally add ACPICA data structures
The LoongArch architecture is using ACPI, but the spec containing
the required updates still is in an unreleased state.
Instead of preventing the inclusion of the IRQ support into the
kernel, add the missing bits to the arch-specific parts of
the ACPICA support.
Once the ACPICA bits are updated to the version that supports
LoongArch, these bits can eventually be removed.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/loongarch/include/asm/acpi.h | 138 ++++++++++++++++++++++++++++++
1 file changed, 138 insertions(+)
diff --git a/arch/loongarch/include/asm/acpi.h b/arch/loongarch/include/asm/acpi.h
index 62044cd5b7bc..6155e46098af 100644
--- a/arch/loongarch/include/asm/acpi.h
+++ b/arch/loongarch/include/asm/acpi.h
@@ -31,6 +31,144 @@ static inline bool acpi_has_cpu_in_madt(void)
extern struct list_head acpi_wakeup_device_list;
+/*
+ * Temporary definitions until the core ACPICA code gets updated (see
+ * 1656837932-18257-1-git-send-email-lvjianmin@loongson.cn and its
+ * follow-ups for the "rationale").
+ *
+ * Once the "legal reasons" are cleared and that the code is merged,
+ * this can be dropped entierely.
+ */
+#if (ACPI_CA_VERSION == 0x20220331 && !defined(LOONGARCH_ACPICA_EXT))
+
+#define LOONGARCH_ACPICA_EXT 1
+
+#define ACPI_MADT_TYPE_CORE_PIC 17
+#define ACPI_MADT_TYPE_LIO_PIC 18
+#define ACPI_MADT_TYPE_HT_PIC 19
+#define ACPI_MADT_TYPE_EIO_PIC 20
+#define ACPI_MADT_TYPE_MSI_PIC 21
+#define ACPI_MADT_TYPE_BIO_PIC 22
+#define ACPI_MADT_TYPE_LPC_PIC 23
+
+/* Values for Version field above */
+
+enum acpi_madt_core_pic_version {
+ ACPI_MADT_CORE_PIC_VERSION_NONE = 0,
+ ACPI_MADT_CORE_PIC_VERSION_V1 = 1,
+ ACPI_MADT_CORE_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
+};
+
+enum acpi_madt_lio_pic_version {
+ ACPI_MADT_LIO_PIC_VERSION_NONE = 0,
+ ACPI_MADT_LIO_PIC_VERSION_V1 = 1,
+ ACPI_MADT_LIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
+};
+
+enum acpi_madt_eio_pic_version {
+ ACPI_MADT_EIO_PIC_VERSION_NONE = 0,
+ ACPI_MADT_EIO_PIC_VERSION_V1 = 1,
+ ACPI_MADT_EIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
+};
+
+enum acpi_madt_ht_pic_version {
+ ACPI_MADT_HT_PIC_VERSION_NONE = 0,
+ ACPI_MADT_HT_PIC_VERSION_V1 = 1,
+ ACPI_MADT_HT_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
+};
+
+enum acpi_madt_bio_pic_version {
+ ACPI_MADT_BIO_PIC_VERSION_NONE = 0,
+ ACPI_MADT_BIO_PIC_VERSION_V1 = 1,
+ ACPI_MADT_BIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
+};
+
+enum acpi_madt_msi_pic_version {
+ ACPI_MADT_MSI_PIC_VERSION_NONE = 0,
+ ACPI_MADT_MSI_PIC_VERSION_V1 = 1,
+ ACPI_MADT_MSI_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
+};
+
+enum acpi_madt_lpc_pic_version {
+ ACPI_MADT_LPC_PIC_VERSION_NONE = 0,
+ ACPI_MADT_LPC_PIC_VERSION_V1 = 1,
+ ACPI_MADT_LPC_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
+};
+
+/* Core Interrupt Controller */
+
+struct acpi_madt_core_pic {
+ struct acpi_subtable_header header;
+ u8 version;
+ u32 processor_id;
+ u32 core_id;
+ u32 flags;
+};
+
+/* Legacy I/O Interrupt Controller */
+
+struct acpi_madt_lio_pic {
+ struct acpi_subtable_header header;
+ u8 version;
+ u64 address;
+ u16 size;
+ u8 cascade[2];
+ u32 cascade_map[2];
+};
+
+/* Extend I/O Interrupt Controller */
+
+struct acpi_madt_eio_pic {
+ struct acpi_subtable_header header;
+ u8 version;
+ u8 cascade;
+ u8 node;
+ u64 node_map;
+};
+
+/* HT Interrupt Controller */
+
+struct acpi_madt_ht_pic {
+ struct acpi_subtable_header header;
+ u8 version;
+ u64 address;
+ u16 size;
+ u8 cascade[8];
+};
+
+/* Bridge I/O Interrupt Controller */
+
+struct acpi_madt_bio_pic {
+ struct acpi_subtable_header header;
+ u8 version;
+ u64 address;
+ u16 size;
+ u16 id;
+ u16 gsi_base;
+};
+
+/* MSI Interrupt Controller */
+
+struct acpi_madt_msi_pic {
+ struct acpi_subtable_header header;
+ u8 version;
+ u64 msg_address;
+ u32 start;
+ u32 count;
+};
+
+/* LPC Interrupt Controller */
+
+struct acpi_madt_lpc_pic {
+ struct acpi_subtable_header header;
+ u8 version;
+ u64 address;
+ u16 size;
+ u8 cascade;
+};
+
+#endif
+
#endif /* !CONFIG_ACPI */
#define ACPI_TABLE_UPGRADE_MAX_PHYS ARCH_LOW_ADDRESS_LIMIT
--
2.34.1
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
` (14 preceding siblings ...)
2022-07-15 7:05 ` [PATCH V15 15/15] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch Jianmin Lv
@ 2022-07-16 18:39 ` Marc Zyngier
2022-07-17 1:06 ` Jianmin Lv
15 siblings, 1 reply; 36+ messages in thread
From: Marc Zyngier @ 2022-07-16 18:39 UTC (permalink / raw)
To: Jianmin Lv
Cc: Thomas Gleixner, linux-kernel, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On Fri, 15 Jul 2022 08:05:36 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
> LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
> LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
> version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
> boot protocol LoongArch-specific interrupt controllers (similar to APIC)
> are already added in the ACPI Specification 6.5(which may be published in
> early June this year and the board is reviewing the draft).
>
> Currently, LoongArch based processors (e.g. Loongson-3A5000) can only
> work together with LS7A chipsets. The irq chips in LoongArch computers
> include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O
> Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller),
> HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main
> Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
> in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
[...]
Compiling this series for loongarch with loongson3_defconfig on top of
5.19-rc3 results in the following:
loongarch64-linux-ld: drivers/irqchip/irq-loongson-eiointc.o: in function `.L60':
irq-loongson-eiointc.c:(.init.text+0x4c): undefined reference to `pch_msi_acpi_init'
loongarch64-linux-ld: drivers/irqchip/irq-loongson-htvec.o: in function `pch_msi_parse_madt':
irq-loongson-htvec.c:(.init.text+0x14): undefined reference to `pch_msi_acpi_init'
make: *** [Makefile:1164: vmlinux] Error 1
I *really* would have expected this series to be in a better shape
after over 15 rounds, but it looks like I'm expecting too much. I
haven't investigated the breakage, but this should (at the very least)
pass the defconfig test and optional drivers not being selected.
The corresponding MIPS configuration seems to build fine.
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 01/15] ACPICA: MADT: Add LoongArch APICs support
2022-07-16 18:10 ` Marc Zyngier
@ 2022-07-17 1:05 ` Jianmin Lv
2022-07-18 12:28 ` Jianmin Lv
1 sibling, 0 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-17 1:05 UTC (permalink / raw)
To: Marc Zyngier, Robert Moore
Cc: Thomas Gleixner, linux-kernel, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On 2022/7/17 上午2:10, Marc Zyngier wrote:
> [+ Robert Moore]
>
> On Fri, 15 Jul 2022 08:05:37 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> From: Huacai Chen <chenhuacai@loongson.cn>
>>
>> LoongArch-specific interrupt controllers (similar to APIC) are added
>> in the next revision of ACPI Specification (current revision is 6.4),
>> which including CORE_PIC (CPUINTC), LIO_PIC (LIOINTC), EIO_PIC (EIOINTC),
>> HT_PIC (HTVECINTC), BIO_PIC (PCHINTC), LPC_PIC (PCHLPC) and MSI_PIC
>> (PCHMSI). This patch add their definition.
>>
>> ACPI changes of LoongArch-specific interrupt controllers have already
>> been approved in the ECRs, and will be public in the next revision of
>> ACPI Specification.
>>
>> Reference: https://mantis.uefi.org/mantis/view.php?id=2203
>> Reference: https://mantis.uefi.org/mantis/view.php?id=2313
>>
>> Above links needs login(available for ASWG), so the following link(
>> the ECR file for adding LoongArch APICs into ACPI spec) is provided
>> for public:
>>
>> https://github.com/lvjianmin-loongson/acpica/blob/master/Add%20APIC%20Structures%20for%20Loongarch%20in%20MADT-rev3.pdf
>>
>> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
>
> Since the ACPI maintainers are unwilling to take this patch (for
> undisclosed reasons), we need something to unblock this sorry
> situation, as I don't think it is fair on the LoongArch folks to be
> blocked for another cycle on this ground only.
>
> I'm proposing to replace this patch with the following, which will
> allow the patches to be merged without breaking anything. Once the
> ACPI support is updated, we'll be able to simply revert this patch.
>
> Thanks,
>
> M.
>
Ok, Marc, thanks very much really, I'll add the patch in the patch series.
> From 43ec25d2dbde3c422cce430c9d5ec32fbe7b255c Mon Sep 17 00:00:00 2001
> From: Marc Zyngier <maz@kernel.org>
> Date: Sat, 16 Jul 2022 18:56:10 +0100
> Subject: [PATCH] LoongArch: Provisionally add ACPICA data structures
>
> The LoongArch architecture is using ACPI, but the spec containing
> the required updates still is in an unreleased state.
>
> Instead of preventing the inclusion of the IRQ support into the
> kernel, add the missing bits to the arch-specific parts of
> the ACPICA support.
>
> Once the ACPICA bits are updated to the version that supports
> LoongArch, these bits can eventually be removed.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/loongarch/include/asm/acpi.h | 138 ++++++++++++++++++++++++++++++
> 1 file changed, 138 insertions(+)
>
> diff --git a/arch/loongarch/include/asm/acpi.h b/arch/loongarch/include/asm/acpi.h
> index 62044cd5b7bc..6155e46098af 100644
> --- a/arch/loongarch/include/asm/acpi.h
> +++ b/arch/loongarch/include/asm/acpi.h
> @@ -31,6 +31,144 @@ static inline bool acpi_has_cpu_in_madt(void)
>
> extern struct list_head acpi_wakeup_device_list;
>
> +/*
> + * Temporary definitions until the core ACPICA code gets updated (see
> + * 1656837932-18257-1-git-send-email-lvjianmin@loongson.cn and its
> + * follow-ups for the "rationale").
> + *
> + * Once the "legal reasons" are cleared and that the code is merged,
> + * this can be dropped entierely.
> + */
> +#if (ACPI_CA_VERSION == 0x20220331 && !defined(LOONGARCH_ACPICA_EXT))
> +
> +#define LOONGARCH_ACPICA_EXT 1
> +
> +#define ACPI_MADT_TYPE_CORE_PIC 17
> +#define ACPI_MADT_TYPE_LIO_PIC 18
> +#define ACPI_MADT_TYPE_HT_PIC 19
> +#define ACPI_MADT_TYPE_EIO_PIC 20
> +#define ACPI_MADT_TYPE_MSI_PIC 21
> +#define ACPI_MADT_TYPE_BIO_PIC 22
> +#define ACPI_MADT_TYPE_LPC_PIC 23
> +
> +/* Values for Version field above */
> +
> +enum acpi_madt_core_pic_version {
> + ACPI_MADT_CORE_PIC_VERSION_NONE = 0,
> + ACPI_MADT_CORE_PIC_VERSION_V1 = 1,
> + ACPI_MADT_CORE_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> +};
> +
> +enum acpi_madt_lio_pic_version {
> + ACPI_MADT_LIO_PIC_VERSION_NONE = 0,
> + ACPI_MADT_LIO_PIC_VERSION_V1 = 1,
> + ACPI_MADT_LIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> +};
> +
> +enum acpi_madt_eio_pic_version {
> + ACPI_MADT_EIO_PIC_VERSION_NONE = 0,
> + ACPI_MADT_EIO_PIC_VERSION_V1 = 1,
> + ACPI_MADT_EIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> +};
> +
> +enum acpi_madt_ht_pic_version {
> + ACPI_MADT_HT_PIC_VERSION_NONE = 0,
> + ACPI_MADT_HT_PIC_VERSION_V1 = 1,
> + ACPI_MADT_HT_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> +};
> +
> +enum acpi_madt_bio_pic_version {
> + ACPI_MADT_BIO_PIC_VERSION_NONE = 0,
> + ACPI_MADT_BIO_PIC_VERSION_V1 = 1,
> + ACPI_MADT_BIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> +};
> +
> +enum acpi_madt_msi_pic_version {
> + ACPI_MADT_MSI_PIC_VERSION_NONE = 0,
> + ACPI_MADT_MSI_PIC_VERSION_V1 = 1,
> + ACPI_MADT_MSI_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> +};
> +
> +enum acpi_madt_lpc_pic_version {
> + ACPI_MADT_LPC_PIC_VERSION_NONE = 0,
> + ACPI_MADT_LPC_PIC_VERSION_V1 = 1,
> + ACPI_MADT_LPC_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> +};
> +
> +/* Core Interrupt Controller */
> +
> +struct acpi_madt_core_pic {
> + struct acpi_subtable_header header;
> + u8 version;
> + u32 processor_id;
> + u32 core_id;
> + u32 flags;
> +};
> +
> +/* Legacy I/O Interrupt Controller */
> +
> +struct acpi_madt_lio_pic {
> + struct acpi_subtable_header header;
> + u8 version;
> + u64 address;
> + u16 size;
> + u8 cascade[2];
> + u32 cascade_map[2];
> +};
> +
> +/* Extend I/O Interrupt Controller */
> +
> +struct acpi_madt_eio_pic {
> + struct acpi_subtable_header header;
> + u8 version;
> + u8 cascade;
> + u8 node;
> + u64 node_map;
> +};
> +
> +/* HT Interrupt Controller */
> +
> +struct acpi_madt_ht_pic {
> + struct acpi_subtable_header header;
> + u8 version;
> + u64 address;
> + u16 size;
> + u8 cascade[8];
> +};
> +
> +/* Bridge I/O Interrupt Controller */
> +
> +struct acpi_madt_bio_pic {
> + struct acpi_subtable_header header;
> + u8 version;
> + u64 address;
> + u16 size;
> + u16 id;
> + u16 gsi_base;
> +};
> +
> +/* MSI Interrupt Controller */
> +
> +struct acpi_madt_msi_pic {
> + struct acpi_subtable_header header;
> + u8 version;
> + u64 msg_address;
> + u32 start;
> + u32 count;
> +};
> +
> +/* LPC Interrupt Controller */
> +
> +struct acpi_madt_lpc_pic {
> + struct acpi_subtable_header header;
> + u8 version;
> + u64 address;
> + u16 size;
> + u8 cascade;
> +};
> +
> +#endif
> +
> #endif /* !CONFIG_ACPI */
>
> #define ACPI_TABLE_UPGRADE_MAX_PHYS ARCH_LOW_ADDRESS_LIMIT
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
2022-07-16 18:39 ` [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Marc Zyngier
@ 2022-07-17 1:06 ` Jianmin Lv
2022-07-17 10:02 ` Marc Zyngier
0 siblings, 1 reply; 36+ messages in thread
From: Jianmin Lv @ 2022-07-17 1:06 UTC (permalink / raw)
To: Marc Zyngier
Cc: Thomas Gleixner, linux-kernel, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On 2022/7/17 上午2:39, Marc Zyngier wrote:
> On Fri, 15 Jul 2022 08:05:36 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
>> LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
>> version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
>> boot protocol LoongArch-specific interrupt controllers (similar to APIC)
>> are already added in the ACPI Specification 6.5(which may be published in
>> early June this year and the board is reviewing the draft).
>>
>> Currently, LoongArch based processors (e.g. Loongson-3A5000) can only
>> work together with LS7A chipsets. The irq chips in LoongArch computers
>> include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O
>> Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller),
>> HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main
>> Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
>> in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
>
> [...]
>
> Compiling this series for loongarch with loongson3_defconfig on top of
> 5.19-rc3 results in the following:
>
> loongarch64-linux-ld: drivers/irqchip/irq-loongson-eiointc.o: in function `.L60':
> irq-loongson-eiointc.c:(.init.text+0x4c): undefined reference to `pch_msi_acpi_init'
> loongarch64-linux-ld: drivers/irqchip/irq-loongson-htvec.o: in function `pch_msi_parse_madt':
> irq-loongson-htvec.c:(.init.text+0x14): undefined reference to `pch_msi_acpi_init'
> make: *** [Makefile:1164: vmlinux] Error 1
>
> I *really* would have expected this series to be in a better shape
> after over 15 rounds, but it looks like I'm expecting too much. I
> haven't investigated the breakage, but this should (at the very least)
> pass the defconfig test and optional drivers not being selected.
>
> The corresponding MIPS configuration seems to build fine.
>
> M.
>
Hi, Marc
Sorry for that first, pch_msi_acpi_init is defined in pch_msi driver
which is compiled depend on CONFIG_PCI, and I test the patches each time
with PCI patches and other(or else, kernel can not be boot), so I'm ok
for testing the patches. The PCI patches has been accepted by PCI
maintainers and will be merged in this merge window.
I don't know how to deal with this situation. Should I add *#ifdef
CONFIG_PCI* at position of calling pch_msi_acpi_init or some other way?
Thanks sincerely.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
2022-07-17 1:06 ` Jianmin Lv
@ 2022-07-17 10:02 ` Marc Zyngier
2022-07-17 11:29 ` Jianmin Lv
0 siblings, 1 reply; 36+ messages in thread
From: Marc Zyngier @ 2022-07-17 10:02 UTC (permalink / raw)
To: Jianmin Lv
Cc: Thomas Gleixner, linux-kernel, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On Sun, 17 Jul 2022 02:06:12 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
>
>
> On 2022/7/17 上午2:39, Marc Zyngier wrote:
> > On Fri, 15 Jul 2022 08:05:36 +0100,
> > Jianmin Lv <lvjianmin@loongson.cn> wrote:
> >>
> >> LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
> >> LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
> >> version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
> >> boot protocol LoongArch-specific interrupt controllers (similar to APIC)
> >> are already added in the ACPI Specification 6.5(which may be published in
> >> early June this year and the board is reviewing the draft).
> >>
> >> Currently, LoongArch based processors (e.g. Loongson-3A5000) can only
> >> work together with LS7A chipsets. The irq chips in LoongArch computers
> >> include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O
> >> Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller),
> >> HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main
> >> Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
> >> in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
> >
> > [...]
> >
> > Compiling this series for loongarch with loongson3_defconfig on top of
> > 5.19-rc3 results in the following:
> >
> > loongarch64-linux-ld: drivers/irqchip/irq-loongson-eiointc.o: in function `.L60':
> > irq-loongson-eiointc.c:(.init.text+0x4c): undefined reference to `pch_msi_acpi_init'
> > loongarch64-linux-ld: drivers/irqchip/irq-loongson-htvec.o: in function `pch_msi_parse_madt':
> > irq-loongson-htvec.c:(.init.text+0x14): undefined reference to `pch_msi_acpi_init'
> > make: *** [Makefile:1164: vmlinux] Error 1
> >
> > I *really* would have expected this series to be in a better shape
> > after over 15 rounds, but it looks like I'm expecting too much. I
> > haven't investigated the breakage, but this should (at the very least)
> > pass the defconfig test and optional drivers not being selected.
> >
> > The corresponding MIPS configuration seems to build fine.
> >
> > M.
> >
>
> Hi, Marc
>
> Sorry for that first, pch_msi_acpi_init is defined in pch_msi driver
> which is compiled depend on CONFIG_PCI, and I test the patches each
> time with PCI patches and other(or else, kernel can not be boot), so
> I'm ok for testing the patches. The PCI patches has been accepted by
> PCI maintainers and will be merged in this merge window.
But each series *must* at the very least compile in isolation.
>
> I don't know how to deal with this situation. Should I add *#ifdef
> CONFIG_PCI* at position of calling pch_msi_acpi_init or some other
> way?
You could try something like this, which results in a kernel that
fully links with defconfig and no additional patch:
diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index ca468564fc85..4479d95867ec 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -99,8 +99,17 @@ int htvec_acpi_init(struct irq_domain *parent,
struct acpi_madt_ht_pic *acpi_htvec);
int pch_lpc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lpc_pic *acpi_pchlpc);
+#if IS_ENABLED(CONFIG_LOONGSON_PCH_MSI)
int pch_msi_acpi_init(struct irq_domain *parent,
- struct acpi_madt_msi_pic *acpi_pchmsi);
+ struct acpi_madt_msi_pic *acpi_pchmsi);
+#else
+static inline int pch_msi_acpi_init(struct irq_domain *parent,
+ struct acpi_madt_msi_pic *acpi_pchmsi)
+{
+ return 0;
+
+}
+#endif
int pch_pic_acpi_init(struct irq_domain *parent,
struct acpi_madt_bio_pic *acpi_pchpic);
int find_pch_pic(u32 gsi);
But the other issue is that you seem to call this function from two
different locations. This cannot be right, as there should be only one
probe order, and not multiple.
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
2022-07-17 10:02 ` Marc Zyngier
@ 2022-07-17 11:29 ` Jianmin Lv
2022-07-17 14:08 ` Huacai Chen
2022-07-17 14:49 ` Marc Zyngier
0 siblings, 2 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-17 11:29 UTC (permalink / raw)
To: Marc Zyngier
Cc: Thomas Gleixner, linux-kernel, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On 2022/7/17 下午6:02, Marc Zyngier wrote:
> On Sun, 17 Jul 2022 02:06:12 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>>
>>
>> On 2022/7/17 上午2:39, Marc Zyngier wrote:
>>> On Fri, 15 Jul 2022 08:05:36 +0100,
>>> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>>>
>>>> LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
>>>> LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
>>>> version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
>>>> boot protocol LoongArch-specific interrupt controllers (similar to APIC)
>>>> are already added in the ACPI Specification 6.5(which may be published in
>>>> early June this year and the board is reviewing the draft).
>>>>
>>>> Currently, LoongArch based processors (e.g. Loongson-3A5000) can only
>>>> work together with LS7A chipsets. The irq chips in LoongArch computers
>>>> include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O
>>>> Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller),
>>>> HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main
>>>> Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
>>>> in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
>>>
>>> [...]
>>>
>>> Compiling this series for loongarch with loongson3_defconfig on top of
>>> 5.19-rc3 results in the following:
>>>
>>> loongarch64-linux-ld: drivers/irqchip/irq-loongson-eiointc.o: in function `.L60':
>>> irq-loongson-eiointc.c:(.init.text+0x4c): undefined reference to `pch_msi_acpi_init'
>>> loongarch64-linux-ld: drivers/irqchip/irq-loongson-htvec.o: in function `pch_msi_parse_madt':
>>> irq-loongson-htvec.c:(.init.text+0x14): undefined reference to `pch_msi_acpi_init'
>>> make: *** [Makefile:1164: vmlinux] Error 1
>>>
>>> I *really* would have expected this series to be in a better shape
>>> after over 15 rounds, but it looks like I'm expecting too much. I
>>> haven't investigated the breakage, but this should (at the very least)
>>> pass the defconfig test and optional drivers not being selected.
>>>
>>> The corresponding MIPS configuration seems to build fine.
>>>
>>> M.
>>>
>>
>> Hi, Marc
>>
>> Sorry for that first, pch_msi_acpi_init is defined in pch_msi driver
>> which is compiled depend on CONFIG_PCI, and I test the patches each
>> time with PCI patches and other(or else, kernel can not be boot), so
>> I'm ok for testing the patches. The PCI patches has been accepted by
>> PCI maintainers and will be merged in this merge window.
>
> But each series *must* at the very least compile in isolation.
>
>>
>> I don't know how to deal with this situation. Should I add *#ifdef
>> CONFIG_PCI* at position of calling pch_msi_acpi_init or some other
>> way?
>
> You could try something like this, which results in a kernel that
> fully links with defconfig and no additional patch:
>
> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
> index ca468564fc85..4479d95867ec 100644
> --- a/arch/loongarch/include/asm/irq.h
> +++ b/arch/loongarch/include/asm/irq.h
> @@ -99,8 +99,17 @@ int htvec_acpi_init(struct irq_domain *parent,
> struct acpi_madt_ht_pic *acpi_htvec);
> int pch_lpc_acpi_init(struct irq_domain *parent,
> struct acpi_madt_lpc_pic *acpi_pchlpc);
> +#if IS_ENABLED(CONFIG_LOONGSON_PCH_MSI)
> int pch_msi_acpi_init(struct irq_domain *parent,
> - struct acpi_madt_msi_pic *acpi_pchmsi);
> + struct acpi_madt_msi_pic *acpi_pchmsi);
> +#else
> +static inline int pch_msi_acpi_init(struct irq_domain *parent,
> + struct acpi_madt_msi_pic *acpi_pchmsi)
> +{
> + return 0;
> +
> +}
> +#endif
> int pch_pic_acpi_init(struct irq_domain *parent,
> struct acpi_madt_bio_pic *acpi_pchpic);
> int find_pch_pic(u32 gsi);
>
Ok, thanks, I'll add this into that patch.
> But the other issue is that you seem to call this function from two
> different locations. This cannot be right, as there should be only one
> probe order, and not multiple.
>
As we described two IRQ models(Legacy and Extended) in this cover
letter, the parent domain of MSI domain can be htvec domain(Legacy) or
eiointc domain(Extended). In MADT, only one APIC(HTPIC for htvec or
EIOPIC for eiointc) is allowed to pass into kernel, and then in the
irqchip driver, only one kind APIC of them can be parsed from MADT, so
we have to support two probe order for them.
> M.
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 14/15] irqchip: Add LoongArch CPU interrupt controller support
2022-07-15 15:11 ` Huacai Chen
@ 2022-07-17 12:02 ` Jianmin Lv
0 siblings, 0 replies; 36+ messages in thread
From: Jianmin Lv @ 2022-07-17 12:02 UTC (permalink / raw)
To: Huacai Chen
Cc: Thomas Gleixner, Marc Zyngier, LKML, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On 2022/7/15 下午11:11, Huacai Chen wrote:
> Hi, Jianmin,
>
> On Fri, Jul 15, 2022 at 3:11 PM Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> From: Huacai Chen <chenhuacai@loongson.cn>
>>
>> LoongArch CPUINTC stands for CSR.ECFG/CSR.ESTAT and related interrupt
>> controller that described in Section 7.4 of "LoongArch Reference Manual,
>> Vol 1". For more information please refer Documentation/loongarch/irq-
>> chip-model.rst.
>>
>> LoongArch CPUINTC has 13 interrupt sources: SWI0~1, HWI0~7, IPI, TI
>> (Timer) and PCOV (PMC). IRQ mappings of HWI0~7 are configurable (can be
>> created from DT/ACPI), but IPI, TI (Timer) and PCOV (PMC) are hardcoded
>> bits, so we expose the fwnode_handle to map them, and get mapped irq
>> by irq_create_mapping when using them.
>>
>> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
>> ---
>> arch/loongarch/include/asm/irq.h | 8 +--
>> arch/loongarch/kernel/irq.c | 15 ++++-
>> arch/loongarch/kernel/time.c | 14 ++++-
>> drivers/irqchip/Kconfig | 10 +++
>> drivers/irqchip/Makefile | 1 +
>> drivers/irqchip/irq-loongarch-cpu.c | 119 ++++++++++++++++++++++++++++++++++++
>> 6 files changed, 157 insertions(+), 10 deletions(-)
>> create mode 100644 drivers/irqchip/irq-loongarch-cpu.c
>>
>> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
>> index a826ac4..ca46856 100644
>> --- a/arch/loongarch/include/asm/irq.h
>> +++ b/arch/loongarch/include/asm/irq.h
>> @@ -35,9 +35,6 @@ static inline bool on_irq_stack(int cpu, unsigned long sp)
>> return (low <= sp && sp <= high);
>> }
>>
>> -int get_ipi_irq(void);
>> -int get_pmc_irq(void);
>> -int get_timer_irq(void);
>> void spurious_interrupt(void);
>>
>> #define NR_IRQS_LEGACY 16
>> @@ -94,13 +91,10 @@ struct acpi_vector_group {
>> struct acpi_madt_msi_pic;
>> struct acpi_madt_lpc_pic;
>>
>> -struct irq_domain *loongarch_cpu_irq_init(void);
>> -
>> int liointc_acpi_init(struct irq_domain *parent,
>> struct acpi_madt_lio_pic *acpi_liointc);
>> int eiointc_acpi_init(struct irq_domain *parent,
>> struct acpi_madt_eio_pic *acpi_eiointc);
>> -
>> int htvec_acpi_init(struct irq_domain *parent,
>> struct acpi_madt_ht_pic *acpi_htvec);
>> int pch_lpc_acpi_init(struct irq_domain *parent,
>> @@ -120,7 +114,7 @@ int pch_pic_acpi_init(struct irq_domain *parent,
>> extern struct acpi_madt_msi_pic *acpi_pchmsi[MAX_IO_PICS];
>> extern struct acpi_madt_bio_pic *acpi_pchpic[MAX_IO_PICS];
>>
>> -extern struct irq_domain *cpu_domain;
>> +extern struct fwnode_handle *cpuintc_handle;
>> extern struct fwnode_handle *liointc_handle;
>> extern struct fwnode_handle *pch_lpc_handle;
>> extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
>> diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
>> index 06f2a15..99924d8 100644
>> --- a/arch/loongarch/kernel/irq.c
>> +++ b/arch/loongarch/kernel/irq.c
>> @@ -25,7 +25,6 @@
>> DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
>> EXPORT_PER_CPU_SYMBOL(irq_stat);
>>
>> -struct irq_domain *cpu_domain;
>> struct acpi_vector_group pch_group[MAX_IO_PICS];
>> struct acpi_vector_group msi_group[MAX_IO_PICS];
>>
>> @@ -89,6 +88,16 @@ static void __init init_vec_parent_group(void)
>> acpi_table_parse(ACPI_SIG_MCFG, early_pci_mcfg_parse);
>> }
>>
>> +static int __init get_ipi_irq(void)
>> +{
>> + struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
>> +
>> + if (d)
>> + return irq_create_mapping(d, EXCCODE_IPI - EXCCODE_INT_START);
>> +
>> + return -EINVAL;
>> +}
>> +
>> void __init init_IRQ(void)
>> {
>> int i;
>> @@ -105,7 +114,9 @@ void __init init_IRQ(void)
>> init_vec_parent_group();
>> irqchip_init();
>> #ifdef CONFIG_SMP
>> - ipi_irq = EXCCODE_IPI - EXCCODE_INT_START;
>> + ipi_irq = get_ipi_irq();
>> + if (ipi_irq < 0)
>> + panic("IPI IRQ mapping failed\n");
>> irq_set_percpu_devid(ipi_irq);
>> r = request_percpu_irq(ipi_irq, loongson3_ipi_interrupt, "IPI", &ipi_dummy_dev);
>> if (r < 0)
>> diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c
>> index fe68238..79dc5ed 100644
>> --- a/arch/loongarch/kernel/time.c
>> +++ b/arch/loongarch/kernel/time.c
>> @@ -123,6 +123,16 @@ void sync_counter(void)
>> csr_write64(-init_timeval, LOONGARCH_CSR_CNTC);
>> }
>>
>> +static int get_timer_irq(void)
>> +{
>> + struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
>> +
>> + if (d)
>> + return irq_create_mapping(d, EXCCODE_TIMER - EXCCODE_INT_START);
>> +
>> + return -EINVAL;
>> +}
>> +
>> int constant_clockevent_init(void)
>> {
>> unsigned int irq;
>> @@ -132,7 +142,9 @@ int constant_clockevent_init(void)
>> struct clock_event_device *cd;
>> static int timer_irq_installed = 0;
>>
>> - irq = EXCCODE_TIMER - EXCCODE_INT_START;
>> + irq = get_timer_irq();
>> + if (irq < 0)
>> + pr_err("Failed to map irq %d (timer)\n", irq);
>>
>> cd = &per_cpu(constant_clockevent_device, cpu);
>>
>> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
>> index 8f077d3..f53164c 100644
>> --- a/drivers/irqchip/Kconfig
>> +++ b/drivers/irqchip/Kconfig
>> @@ -546,6 +546,16 @@ config EXYNOS_IRQ_COMBINER
>> Say yes here to add support for the IRQ combiner devices embedded
>> in Samsung Exynos chips.
>>
>> +config IRQ_LOONGARCH_CPU
>> + bool
>> + select GENERIC_IRQ_CHIP
>> + select IRQ_DOMAIN
>> + select GENERIC_IRQ_EFFECTIVE_AFF_MASK
>> + help
>> + Support for the LoongArch CPU Interrupt Controller. For details of
>> + irq chip hierarchy on LoongArch platforms please read the document
>> + Documentation/loongarch/irq-chip-model.rst.
>> +
>> config LOONGSON_LIOINTC
>> bool "Loongson Local I/O Interrupt Controller"
>> depends on MACH_LOONGSON64
>> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
>> index 0cfd4f0..e559007 100644
>> --- a/drivers/irqchip/Makefile
>> +++ b/drivers/irqchip/Makefile
>> @@ -103,6 +103,7 @@ obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
>> obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
>> obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
>> obj-$(CONFIG_TI_PRUSS_INTC) += irq-pruss-intc.o
>> +obj-$(CONFIG_IRQ_LOONGARCH_CPU) += irq-loongarch-cpu.o
>> obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
>> obj-$(CONFIG_LOONGSON_EIOINTC) += irq-loongson-eiointc.o
>> obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
>> diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loongarch-cpu.c
>> new file mode 100644
>> index 0000000..476f407
>> --- /dev/null
>> +++ b/drivers/irqchip/irq-loongarch-cpu.c
>> @@ -0,0 +1,119 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
>> + */
>> +
>> +#include <linux/init.h>
>> +#include <linux/kernel.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/irq.h>
>> +#include <linux/irqchip.h>
>> +#include <linux/irqdomain.h>
>> +
>> +#include <asm/loongarch.h>
>> +#include <asm/setup.h>
>> +
>> +static struct irq_domain *irq_domain;
>> +struct fwnode_handle *cpuintc_handle;
>> +
>> +static void mask_loongarch_irq(struct irq_data *d)
>> +{
>> + clear_csr_ecfg(ECFGF(d->hwirq));
>> +}
>> +
>> +static void unmask_loongarch_irq(struct irq_data *d)
>> +{
>> + set_csr_ecfg(ECFGF(d->hwirq));
>> +}
>> +
>> +static struct irq_chip cpu_irq_controller = {
>> + .name = "CPUINTC",
>> + .irq_mask = mask_loongarch_irq,
>> + .irq_unmask = unmask_loongarch_irq,
>> +};
>> +
>> +static void handle_cpu_irq(struct pt_regs *regs)
>> +{
>> + int hwirq;
>> + unsigned int estat = read_csr_estat() & CSR_ESTAT_IS;
>> +
>> + while ((hwirq = ffs(estat))) {
>> + estat &= ~BIT(hwirq - 1);
>> + generic_handle_domain_irq(irq_domain, hwirq - 1);
>> + }
>> +}
>> +
>> +static int loongarch_cpu_intc_map(struct irq_domain *d, unsigned int irq,
>> + irq_hw_number_t hwirq)
>> +{
>> + irq_set_noprobe(irq);
>> + irq_set_chip_and_handler(irq, &cpu_irq_controller, handle_percpu_irq);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct irq_domain_ops loongarch_cpu_intc_irq_domain_ops = {
>> + .map = loongarch_cpu_intc_map,
>> + .xlate = irq_domain_xlate_onecell,
>> +};
>> +
>> +static int __init loongarch_cpu_irq_init(void)
>> +{
>> + /* Mask interrupts. */
>> + clear_csr_ecfg(ECFG0_IM);
>> + clear_csr_estat(ESTATF_IP);
>> +
>> + cpuintc_handle = irq_domain_alloc_fwnode(NULL);
>> + irq_domain = irq_domain_create_linear(cpuintc_handle, EXCCODE_INT_NUM,
>> + &loongarch_cpu_intc_irq_domain_ops, NULL);
>> +
>> + if (!irq_domain)
>> + panic("Failed to add irqdomain for LoongArch CPU");
>> +
>> + set_handle_irq(&handle_cpu_irq);
>> +
>> + return 0;
>> +}
>> +
>> +static int __init
>> +liointc_parse_madt(union acpi_subtable_headers *header,
>> + const unsigned long end)
>> +{
>> + struct acpi_madt_lio_pic *liointc_entry = (struct acpi_madt_lio_pic *)header;
>> +
>> + return liointc_acpi_init(irq_domain, liointc_entry);
>> +}
>> +
>> +static int __init
>> +eiointc_parse_madt(union acpi_subtable_headers *header,
>> + const unsigned long end)
>> +{
>> + struct acpi_madt_eio_pic *eiointc_entry = (struct acpi_madt_eio_pic *)header;
>> +
>> + return eiointc_acpi_init(irq_domain, eiointc_entry);
>> +}
>> +
>> +static int __init acpi_cascade_irqdomain_init(void)
>> +{
>> + acpi_table_parse_madt(ACPI_MADT_TYPE_LIO_PIC,
>> + liointc_parse_madt, 0);
>> + acpi_table_parse_madt(ACPI_MADT_TYPE_EIO_PIC,
>> + eiointc_parse_madt, 0);
>> + return 0;
>> +}
>> +
>> +static int __init coreintc_acpi_init_v1(union acpi_subtable_headers *header,
>> + const unsigned long end)
>> +{
>> + if (irq_domain)
>> + return 0;
>> +
>> + loongarch_cpu_irq_init();
>> + acpi_cascade_irqdomain_init();
>> +
>> + return 0;
>> +}
>> +
>> +IRQCHIP_ACPI_DECLARE(coreintc_v1, ACPI_MADT_TYPE_CORE_PIC,
>> + NULL, ACPI_MADT_CORE_PIC_VERSION_V1,
>> + coreintc_acpi_init_v1);
>
> I think loongarch_cpu_irq_init() and coreintc_acpi_init_v1() can be
> merged like below, which makes code simpler.
>
> static int __init loongarch_cpu_irq_init(union acpi_subtable_headers
> *header, const unsigned long end)
> {
> struct fwnode_handle *domain_handle;
>
> if (irq_domain)
> return 0;
>
> /* Mask interrupts. */
> clear_csr_ecfg(ECFG0_IM);
> clear_csr_estat(ESTATF_IP);
>
> domain_handle = irq_domain_alloc_fwnode(NULL);
> irq_domain = irq_domain_create_linear(domain_handle, EXCCODE_INT_NUM,
>
> &loongarch_cpu_intc_irq_domain_ops, NULL);
>
> if (!irq_domain)
> panic("Failed to add irqdomain for LoongArch CPU");
>
> acpi_cascade_irqdomain_init();
> set_handle_irq(&handle_cpu_irq);
>
> return 0;
> }
> IRQCHIP_ACPI_DECLARE(cpuintc_v1, ACPI_MADT_TYPE_CORE_PIC,
> NULL, ACPI_MADT_CORE_PIC_VERSION_V1, loongarch_cpu_irq_init);
>
> Thanks,
> Huacai
Yes, thanks, it seems more simpler, I'll change it in next version.
>> --
>> 1.8.3.1
>>
>>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
2022-07-17 11:29 ` Jianmin Lv
@ 2022-07-17 14:08 ` Huacai Chen
2022-07-17 14:43 ` Marc Zyngier
2022-07-17 14:49 ` Marc Zyngier
1 sibling, 1 reply; 36+ messages in thread
From: Huacai Chen @ 2022-07-17 14:08 UTC (permalink / raw)
To: Jianmin Lv
Cc: Marc Zyngier, Thomas Gleixner, linux-kernel, loongarch,
Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
Hi, Marc, Jianmin,
On Sun, Jul 17, 2022 at 7:29 PM Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
>
>
> On 2022/7/17 下午6:02, Marc Zyngier wrote:
> > On Sun, 17 Jul 2022 02:06:12 +0100,
> > Jianmin Lv <lvjianmin@loongson.cn> wrote:
> >>
> >>
> >>
> >> On 2022/7/17 上午2:39, Marc Zyngier wrote:
> >>> On Fri, 15 Jul 2022 08:05:36 +0100,
> >>> Jianmin Lv <lvjianmin@loongson.cn> wrote:
> >>>>
> >>>> LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
> >>>> LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
> >>>> version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
> >>>> boot protocol LoongArch-specific interrupt controllers (similar to APIC)
> >>>> are already added in the ACPI Specification 6.5(which may be published in
> >>>> early June this year and the board is reviewing the draft).
> >>>>
> >>>> Currently, LoongArch based processors (e.g. Loongson-3A5000) can only
> >>>> work together with LS7A chipsets. The irq chips in LoongArch computers
> >>>> include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O
> >>>> Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller),
> >>>> HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main
> >>>> Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
> >>>> in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
> >>>
> >>> [...]
> >>>
> >>> Compiling this series for loongarch with loongson3_defconfig on top of
> >>> 5.19-rc3 results in the following:
> >>>
> >>> loongarch64-linux-ld: drivers/irqchip/irq-loongson-eiointc.o: in function `.L60':
> >>> irq-loongson-eiointc.c:(.init.text+0x4c): undefined reference to `pch_msi_acpi_init'
> >>> loongarch64-linux-ld: drivers/irqchip/irq-loongson-htvec.o: in function `pch_msi_parse_madt':
> >>> irq-loongson-htvec.c:(.init.text+0x14): undefined reference to `pch_msi_acpi_init'
> >>> make: *** [Makefile:1164: vmlinux] Error 1
> >>>
> >>> I *really* would have expected this series to be in a better shape
> >>> after over 15 rounds, but it looks like I'm expecting too much. I
> >>> haven't investigated the breakage, but this should (at the very least)
> >>> pass the defconfig test and optional drivers not being selected.
> >>>
> >>> The corresponding MIPS configuration seems to build fine.
> >>>
> >>> M.
> >>>
> >>
> >> Hi, Marc
> >>
> >> Sorry for that first, pch_msi_acpi_init is defined in pch_msi driver
> >> which is compiled depend on CONFIG_PCI, and I test the patches each
> >> time with PCI patches and other(or else, kernel can not be boot), so
> >> I'm ok for testing the patches. The PCI patches has been accepted by
> >> PCI maintainers and will be merged in this merge window.
> >
> > But each series *must* at the very least compile in isolation.
> >
> >>
> >> I don't know how to deal with this situation. Should I add *#ifdef
> >> CONFIG_PCI* at position of calling pch_msi_acpi_init or some other
> >> way?
> >
> > You could try something like this, which results in a kernel that
> > fully links with defconfig and no additional patch:
> >
> > diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
> > index ca468564fc85..4479d95867ec 100644
> > --- a/arch/loongarch/include/asm/irq.h
> > +++ b/arch/loongarch/include/asm/irq.h
> > @@ -99,8 +99,17 @@ int htvec_acpi_init(struct irq_domain *parent,
> > struct acpi_madt_ht_pic *acpi_htvec);
> > int pch_lpc_acpi_init(struct irq_domain *parent,
> > struct acpi_madt_lpc_pic *acpi_pchlpc);
> > +#if IS_ENABLED(CONFIG_LOONGSON_PCH_MSI)
> > int pch_msi_acpi_init(struct irq_domain *parent,
> > - struct acpi_madt_msi_pic *acpi_pchmsi);
> > + struct acpi_madt_msi_pic *acpi_pchmsi);
> > +#else
> > +static inline int pch_msi_acpi_init(struct irq_domain *parent,
> > + struct acpi_madt_msi_pic *acpi_pchmsi)
> > +{
> > + return 0;
> > +
> > +}
> > +#endif
> > int pch_pic_acpi_init(struct irq_domain *parent,
> > struct acpi_madt_bio_pic *acpi_pchpic);
> > int find_pch_pic(u32 gsi);
> >
>
> Ok, thanks, I'll add this into that patch.
>
>
> > But the other issue is that you seem to call this function from two
> > different locations. This cannot be right, as there should be only one
> > probe order, and not multiple.
> >
>
> As we described two IRQ models(Legacy and Extended) in this cover
> letter, the parent domain of MSI domain can be htvec domain(Legacy) or
> eiointc domain(Extended). In MADT, only one APIC(HTPIC for htvec or
> EIOPIC for eiointc) is allowed to pass into kernel, and then in the
> irqchip driver, only one kind APIC of them can be parsed from MADT, so
> we have to support two probe order for them.
I have an idea but I don't know whether it is acceptable: Marc gives
an Acked-by for the whole series, then this irqchip series goes
through the loongarch tree together with the PCI patches, then we
don't need other hacks except the ACPI definitions.
Huacai
>
> > M.
> >
>
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
2022-07-17 14:08 ` Huacai Chen
@ 2022-07-17 14:43 ` Marc Zyngier
2022-07-18 2:38 ` Huacai Chen
0 siblings, 1 reply; 36+ messages in thread
From: Marc Zyngier @ 2022-07-17 14:43 UTC (permalink / raw)
To: Huacai Chen
Cc: Jianmin Lv, Thomas Gleixner, linux-kernel, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On Sun, 17 Jul 2022 15:08:14 +0100,
Huacai Chen <chenhuacai@kernel.org> wrote:
>
> Hi, Marc, Jianmin,
>
> I have an idea but I don't know whether it is acceptable: Marc gives
> an Acked-by for the whole series, then this irqchip series goes
> through the loongarch tree together with the PCI patches, then we
> don't need other hacks except the ACPI definitions.
Not sure how this solves the original problem. PCI should never be
mandatory (it is actually super useful to be able to build a very
small kernel without too many drivers), and there shouldn't be
configurations where the kernel doesn't build.
It is also my own responsibility to merge these things, and I'd rather
not delegate this, specially as it touches a bunch of other
subsystems.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
2022-07-17 11:29 ` Jianmin Lv
2022-07-17 14:08 ` Huacai Chen
@ 2022-07-17 14:49 ` Marc Zyngier
2022-07-18 1:07 ` Jianmin Lv
1 sibling, 1 reply; 36+ messages in thread
From: Marc Zyngier @ 2022-07-17 14:49 UTC (permalink / raw)
To: Jianmin Lv
Cc: Thomas Gleixner, linux-kernel, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On Sun, 17 Jul 2022 12:29:05 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
>
>
> On 2022/7/17 下午6:02, Marc Zyngier wrote:
> > But the other issue is that you seem to call this function from two
> > different locations. This cannot be right, as there should be only one
> > probe order, and not multiple.
> >
>
> As we described two IRQ models(Legacy and Extended) in this cover
> letter, the parent domain of MSI domain can be htvec domain(Legacy) or
> eiointc domain(Extended). In MADT, only one APIC(HTPIC for htvec or
> EIOPIC for eiointc) is allowed to pass into kernel, and then in the
> irqchip driver, only one kind APIC of them can be parsed from MADT, so
> we have to support two probe order for them.
Do you really have the two variants in the wild? Or is this just
because this is a possibility?
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
2022-07-17 14:49 ` Marc Zyngier
@ 2022-07-18 1:07 ` Jianmin Lv
2022-07-18 6:39 ` Marc Zyngier
0 siblings, 1 reply; 36+ messages in thread
From: Jianmin Lv @ 2022-07-18 1:07 UTC (permalink / raw)
To: Marc Zyngier
Cc: Thomas Gleixner, linux-kernel, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On 2022/7/17 下午10:49, Marc Zyngier wrote:
> On Sun, 17 Jul 2022 12:29:05 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>>
>>
>> On 2022/7/17 下午6:02, Marc Zyngier wrote:
>>> But the other issue is that you seem to call this function from two
>>> different locations. This cannot be right, as there should be only one
>>> probe order, and not multiple.
>>>
>>
>> As we described two IRQ models(Legacy and Extended) in this cover
>> letter, the parent domain of MSI domain can be htvec domain(Legacy) or
>> eiointc domain(Extended). In MADT, only one APIC(HTPIC for htvec or
>> EIOPIC for eiointc) is allowed to pass into kernel, and then in the
>> irqchip driver, only one kind APIC of them can be parsed from MADT, so
>> we have to support two probe order for them.
>
> Do you really have the two variants in the wild? Or is this just
> because this is a possibility?
>
Currently, there are not CPUs(used for PC and server) based on LoongArch
shipped with only HTPIC, but with both HTPIC and EIOPIC, we just want to
provide two choices for designers(but obviously, EIOPIC may be enough
currently). Do you think we don't have to do like this, yes? If so,
maybe we don't have to support ACPI-way entry for htvec currently, and
do the work in future if required.
> M.
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
2022-07-17 14:43 ` Marc Zyngier
@ 2022-07-18 2:38 ` Huacai Chen
2022-07-18 6:43 ` Marc Zyngier
0 siblings, 1 reply; 36+ messages in thread
From: Huacai Chen @ 2022-07-18 2:38 UTC (permalink / raw)
To: Marc Zyngier
Cc: Jianmin Lv, Thomas Gleixner, LKML, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
Hi, Marc,
On Sun, Jul 17, 2022 at 10:43 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On Sun, 17 Jul 2022 15:08:14 +0100,
> Huacai Chen <chenhuacai@kernel.org> wrote:
> >
> > Hi, Marc, Jianmin,
> >
> > I have an idea but I don't know whether it is acceptable: Marc gives
> > an Acked-by for the whole series, then this irqchip series goes
> > through the loongarch tree together with the PCI patches, then we
> > don't need other hacks except the ACPI definitions.
>
> Not sure how this solves the original problem. PCI should never be
> mandatory (it is actually super useful to be able to build a very
> small kernel without too many drivers), and there shouldn't be
> configurations where the kernel doesn't build.
Now, the pci-loongson controller code (A) is in the PCI tree, the pci
enablement code (B) is in the LoongArch tree, and the irqchip code (C)
is in the irqchip tree. If the order for upstream is (A) --> (B) -->
(C), there will be no build error. My above idea is to make sure the
order of (B) and (C) is controlled in the same tree. PCI/MSI is a
mandatory requirement for LoongArch, so I want to avoid some
unnecessary #ifdefs.
>
> It is also my own responsibility to merge these things, and I'd rather
> not delegate this, specially as it touches a bunch of other
> subsystems.
I know, this is reasonable. Then if we can control the order of
(A)(B)(C) in three trees, the build error can be avoided in the
linux-next tree.
Huacai
>
> Thanks,
>
> M.
>
> --
> Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
2022-07-18 1:07 ` Jianmin Lv
@ 2022-07-18 6:39 ` Marc Zyngier
2022-07-18 8:29 ` Jianmin Lv
0 siblings, 1 reply; 36+ messages in thread
From: Marc Zyngier @ 2022-07-18 6:39 UTC (permalink / raw)
To: Jianmin Lv
Cc: Thomas Gleixner, linux-kernel, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On Mon, 18 Jul 2022 02:07:21 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
>
>
> On 2022/7/17 下午10:49, Marc Zyngier wrote:
> > On Sun, 17 Jul 2022 12:29:05 +0100,
> > Jianmin Lv <lvjianmin@loongson.cn> wrote:
> >>
> >>
> >>
> >> On 2022/7/17 下午6:02, Marc Zyngier wrote:
> >>> But the other issue is that you seem to call this function from two
> >>> different locations. This cannot be right, as there should be only one
> >>> probe order, and not multiple.
> >>>
> >>
> >> As we described two IRQ models(Legacy and Extended) in this cover
> >> letter, the parent domain of MSI domain can be htvec domain(Legacy) or
> >> eiointc domain(Extended). In MADT, only one APIC(HTPIC for htvec or
> >> EIOPIC for eiointc) is allowed to pass into kernel, and then in the
> >> irqchip driver, only one kind APIC of them can be parsed from MADT, so
> >> we have to support two probe order for them.
> >
> > Do you really have the two variants in the wild? Or is this just
> > because this is a possibility?
> >
>
> Currently, there are not CPUs(used for PC and server) based on
> LoongArch shipped with only HTPIC, but with both HTPIC and EIOPIC, we
> just want to provide two choices for designers(but obviously, EIOPIC
> may be enough currently). Do you think we don't have to do like this,
> yes? If so, maybe we don't have to support ACPI-way entry for htvec
> currently, and do the work in future if required.
If the existing HW is only following the 'Extended' model, then I'd
suggest you only support this for now. It has two effects:
- it simplifies the current code, making it more maintainable and
easier to reason about
- it sends the message to integrators that 'Extended' is the correct
model, and that it is what they should support
Now, we don't have much time left to get this series into -next (I
will be closing the tree to new features this week, and only queue
fixes).
So whatever you need to do, please do it quickly so that we can have
at least some of this in 5.20.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
2022-07-18 2:38 ` Huacai Chen
@ 2022-07-18 6:43 ` Marc Zyngier
2022-07-18 8:35 ` Huacai Chen
0 siblings, 1 reply; 36+ messages in thread
From: Marc Zyngier @ 2022-07-18 6:43 UTC (permalink / raw)
To: Huacai Chen
Cc: Jianmin Lv, Thomas Gleixner, LKML, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On Mon, 18 Jul 2022 03:38:09 +0100,
Huacai Chen <chenhuacai@kernel.org> wrote:
>
> Hi, Marc,
>
> On Sun, Jul 17, 2022 at 10:43 PM Marc Zyngier <maz@kernel.org> wrote:
> >
> > On Sun, 17 Jul 2022 15:08:14 +0100,
> > Huacai Chen <chenhuacai@kernel.org> wrote:
> > >
> > > Hi, Marc, Jianmin,
> > >
> > > I have an idea but I don't know whether it is acceptable: Marc gives
> > > an Acked-by for the whole series, then this irqchip series goes
> > > through the loongarch tree together with the PCI patches, then we
> > > don't need other hacks except the ACPI definitions.
> >
> > Not sure how this solves the original problem. PCI should never be
> > mandatory (it is actually super useful to be able to build a very
> > small kernel without too many drivers), and there shouldn't be
> > configurations where the kernel doesn't build.
> Now, the pci-loongson controller code (A) is in the PCI tree, the pci
> enablement code (B) is in the LoongArch tree, and the irqchip code (C)
> is in the irqchip tree. If the order for upstream is (A) --> (B) -->
> (C), there will be no build error. My above idea is to make sure the
> order of (B) and (C) is controlled in the same tree. PCI/MSI is a
> mandatory requirement for LoongArch, so I want to avoid some
> unnecessary #ifdefs.
>
> >
> > It is also my own responsibility to merge these things, and I'd rather
> > not delegate this, specially as it touches a bunch of other
> > subsystems.
> I know, this is reasonable. Then if we can control the order of
> (A)(B)(C) in three trees, the build error can be avoided in the
> linux-next tree.
This would require stable branches between all three trees, as we
don't control the *order* of the merges. I'd have to carry (A) and (B)
as part of (C), which is really over the top.
Just queue a patch to remove the #ifdef once we're at -rc1 and that
things have settled down. This will be simpler for everyone, and will
allow everyone to have a clean tree without dragging tons of extra
patches.
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
2022-07-18 6:39 ` Marc Zyngier
@ 2022-07-18 8:29 ` Jianmin Lv
2022-07-18 8:39 ` Huacai Chen
0 siblings, 1 reply; 36+ messages in thread
From: Jianmin Lv @ 2022-07-18 8:29 UTC (permalink / raw)
To: Marc Zyngier
Cc: Thomas Gleixner, linux-kernel, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On 2022/7/18 下午2:39, Marc Zyngier wrote:
> On Mon, 18 Jul 2022 02:07:21 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>>
>>
>> On 2022/7/17 下午10:49, Marc Zyngier wrote:
>>> On Sun, 17 Jul 2022 12:29:05 +0100,
>>> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>>>
>>>>
>>>>
>>>> On 2022/7/17 下午6:02, Marc Zyngier wrote:
>>>>> But the other issue is that you seem to call this function from two
>>>>> different locations. This cannot be right, as there should be only one
>>>>> probe order, and not multiple.
>>>>>
>>>>
>>>> As we described two IRQ models(Legacy and Extended) in this cover
>>>> letter, the parent domain of MSI domain can be htvec domain(Legacy) or
>>>> eiointc domain(Extended). In MADT, only one APIC(HTPIC for htvec or
>>>> EIOPIC for eiointc) is allowed to pass into kernel, and then in the
>>>> irqchip driver, only one kind APIC of them can be parsed from MADT, so
>>>> we have to support two probe order for them.
>>>
>>> Do you really have the two variants in the wild? Or is this just
>>> because this is a possibility?
>>>
>>
>> Currently, there are not CPUs(used for PC and server) based on
>> LoongArch shipped with only HTPIC, but with both HTPIC and EIOPIC, we
>> just want to provide two choices for designers(but obviously, EIOPIC
>> may be enough currently). Do you think we don't have to do like this,
>> yes? If so, maybe we don't have to support ACPI-way entry for htvec
>> currently, and do the work in future if required.
>
> If the existing HW is only following the 'Extended' model, then I'd
> suggest you only support this for now. It has two effects:
>
> - it simplifies the current code, making it more maintainable and
> easier to reason about
>
> - it sends the message to integrators that 'Extended' is the correct
> model, and that it is what they should support
>
> Now, we don't have much time left to get this series into -next (I
> will be closing the tree to new features this week, and only queue
> fixes).
>
> So whatever you need to do, please do it quickly so that we can have
> at least some of this in 5.20.
>
> Thanks,
>
> M.
>
Ok, Marc, thanks for your suggestion, got it, I'll remove 'Legacy' mode
support and send next version as soon as possible.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
2022-07-18 6:43 ` Marc Zyngier
@ 2022-07-18 8:35 ` Huacai Chen
0 siblings, 0 replies; 36+ messages in thread
From: Huacai Chen @ 2022-07-18 8:35 UTC (permalink / raw)
To: Marc Zyngier
Cc: Jianmin Lv, Thomas Gleixner, LKML, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
Hi, Marc,
On Mon, Jul 18, 2022 at 2:43 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On Mon, 18 Jul 2022 03:38:09 +0100,
> Huacai Chen <chenhuacai@kernel.org> wrote:
> >
> > Hi, Marc,
> >
> > On Sun, Jul 17, 2022 at 10:43 PM Marc Zyngier <maz@kernel.org> wrote:
> > >
> > > On Sun, 17 Jul 2022 15:08:14 +0100,
> > > Huacai Chen <chenhuacai@kernel.org> wrote:
> > > >
> > > > Hi, Marc, Jianmin,
> > > >
> > > > I have an idea but I don't know whether it is acceptable: Marc gives
> > > > an Acked-by for the whole series, then this irqchip series goes
> > > > through the loongarch tree together with the PCI patches, then we
> > > > don't need other hacks except the ACPI definitions.
> > >
> > > Not sure how this solves the original problem. PCI should never be
> > > mandatory (it is actually super useful to be able to build a very
> > > small kernel without too many drivers), and there shouldn't be
> > > configurations where the kernel doesn't build.
> > Now, the pci-loongson controller code (A) is in the PCI tree, the pci
> > enablement code (B) is in the LoongArch tree, and the irqchip code (C)
> > is in the irqchip tree. If the order for upstream is (A) --> (B) -->
> > (C), there will be no build error. My above idea is to make sure the
> > order of (B) and (C) is controlled in the same tree. PCI/MSI is a
> > mandatory requirement for LoongArch, so I want to avoid some
> > unnecessary #ifdefs.
> >
> > >
> > > It is also my own responsibility to merge these things, and I'd rather
> > > not delegate this, specially as it touches a bunch of other
> > > subsystems.
> > I know, this is reasonable. Then if we can control the order of
> > (A)(B)(C) in three trees, the build error can be avoided in the
> > linux-next tree.
>
> This would require stable branches between all three trees, as we
> don't control the *order* of the merges. I'd have to carry (A) and (B)
> as part of (C), which is really over the top.
>
> Just queue a patch to remove the #ifdef once we're at -rc1 and that
> things have settled down. This will be simpler for everyone, and will
> allow everyone to have a clean tree without dragging tons of extra
> patches.
OK, I agree with your decision.
Huacai
>
> M.
>
> --
> Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
2022-07-18 8:29 ` Jianmin Lv
@ 2022-07-18 8:39 ` Huacai Chen
0 siblings, 0 replies; 36+ messages in thread
From: Huacai Chen @ 2022-07-18 8:39 UTC (permalink / raw)
To: Jianmin Lv
Cc: Marc Zyngier, Thomas Gleixner, LKML, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
Hi, Jianmin and Marc,
On Mon, Jul 18, 2022 at 4:29 PM Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
>
>
> On 2022/7/18 下午2:39, Marc Zyngier wrote:
> > On Mon, 18 Jul 2022 02:07:21 +0100,
> > Jianmin Lv <lvjianmin@loongson.cn> wrote:
> >>
> >>
> >>
> >> On 2022/7/17 下午10:49, Marc Zyngier wrote:
> >>> On Sun, 17 Jul 2022 12:29:05 +0100,
> >>> Jianmin Lv <lvjianmin@loongson.cn> wrote:
> >>>>
> >>>>
> >>>>
> >>>> On 2022/7/17 下午6:02, Marc Zyngier wrote:
> >>>>> But the other issue is that you seem to call this function from two
> >>>>> different locations. This cannot be right, as there should be only one
> >>>>> probe order, and not multiple.
> >>>>>
> >>>>
> >>>> As we described two IRQ models(Legacy and Extended) in this cover
> >>>> letter, the parent domain of MSI domain can be htvec domain(Legacy) or
> >>>> eiointc domain(Extended). In MADT, only one APIC(HTPIC for htvec or
> >>>> EIOPIC for eiointc) is allowed to pass into kernel, and then in the
> >>>> irqchip driver, only one kind APIC of them can be parsed from MADT, so
> >>>> we have to support two probe order for them.
> >>>
> >>> Do you really have the two variants in the wild? Or is this just
> >>> because this is a possibility?
> >>>
> >>
> >> Currently, there are not CPUs(used for PC and server) based on
> >> LoongArch shipped with only HTPIC, but with both HTPIC and EIOPIC, we
> >> just want to provide two choices for designers(but obviously, EIOPIC
> >> may be enough currently). Do you think we don't have to do like this,
> >> yes? If so, maybe we don't have to support ACPI-way entry for htvec
> >> currently, and do the work in future if required.
> >
> > If the existing HW is only following the 'Extended' model, then I'd
> > suggest you only support this for now. It has two effects:
> >
> > - it simplifies the current code, making it more maintainable and
> > easier to reason about
> >
> > - it sends the message to integrators that 'Extended' is the correct
> > model, and that it is what they should support
> >
> > Now, we don't have much time left to get this series into -next (I
> > will be closing the tree to new features this week, and only queue
> > fixes).
> >
> > So whatever you need to do, please do it quickly so that we can have
> > at least some of this in 5.20.
> >
> > Thanks,
> >
> > M.
> >
>
> Ok, Marc, thanks for your suggestion, got it, I'll remove 'Legacy' mode
> support and send next version as soon as possible.
I think keeping the "Legacy" mode is faster than removing it for now
to keep up with the merge window, since it is already here and doesn't
need to modify.
Huacai
>
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 01/15] ACPICA: MADT: Add LoongArch APICs support
2022-07-16 18:10 ` Marc Zyngier
2022-07-17 1:05 ` Jianmin Lv
@ 2022-07-18 12:28 ` Jianmin Lv
2022-07-18 13:26 ` Marc Zyngier
1 sibling, 1 reply; 36+ messages in thread
From: Jianmin Lv @ 2022-07-18 12:28 UTC (permalink / raw)
To: Marc Zyngier, Robert Moore
Cc: Thomas Gleixner, linux-kernel, loongarch, Hanjun Guo,
Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On 2022/7/17 上午2:10, Marc Zyngier wrote:
> [+ Robert Moore]
>
> On Fri, 15 Jul 2022 08:05:37 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> From: Huacai Chen <chenhuacai@loongson.cn>
>>
>> LoongArch-specific interrupt controllers (similar to APIC) are added
>> in the next revision of ACPI Specification (current revision is 6.4),
>> which including CORE_PIC (CPUINTC), LIO_PIC (LIOINTC), EIO_PIC (EIOINTC),
>> HT_PIC (HTVECINTC), BIO_PIC (PCHINTC), LPC_PIC (PCHLPC) and MSI_PIC
>> (PCHMSI). This patch add their definition.
>>
>> ACPI changes of LoongArch-specific interrupt controllers have already
>> been approved in the ECRs, and will be public in the next revision of
>> ACPI Specification.
>>
>> Reference: https://mantis.uefi.org/mantis/view.php?id=2203
>> Reference: https://mantis.uefi.org/mantis/view.php?id=2313
>>
>> Above links needs login(available for ASWG), so the following link(
>> the ECR file for adding LoongArch APICs into ACPI spec) is provided
>> for public:
>>
>> https://github.com/lvjianmin-loongson/acpica/blob/master/Add%20APIC%20Structures%20for%20Loongarch%20in%20MADT-rev3.pdf
>>
>> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
>
> Since the ACPI maintainers are unwilling to take this patch (for
> undisclosed reasons), we need something to unblock this sorry
> situation, as I don't think it is fair on the LoongArch folks to be
> blocked for another cycle on this ground only.
>
> I'm proposing to replace this patch with the following, which will
> allow the patches to be merged without breaking anything. Once the
> ACPI support is updated, we'll be able to simply revert this patch.
>
> Thanks,
>
> M.
>
> From 43ec25d2dbde3c422cce430c9d5ec32fbe7b255c Mon Sep 17 00:00:00 2001
> From: Marc Zyngier <maz@kernel.org>
> Date: Sat, 16 Jul 2022 18:56:10 +0100
> Subject: [PATCH] LoongArch: Provisionally add ACPICA data structures
>
> The LoongArch architecture is using ACPI, but the spec containing
> the required updates still is in an unreleased state.
>
> Instead of preventing the inclusion of the IRQ support into the
> kernel, add the missing bits to the arch-specific parts of
> the ACPICA support.
>
> Once the ACPICA bits are updated to the version that supports
> LoongArch, these bits can eventually be removed.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/loongarch/include/asm/acpi.h | 138 ++++++++++++++++++++++++++++++
> 1 file changed, 138 insertions(+)
>
> diff --git a/arch/loongarch/include/asm/acpi.h b/arch/loongarch/include/asm/acpi.h
> index 62044cd5b7bc..6155e46098af 100644
> --- a/arch/loongarch/include/asm/acpi.h
> +++ b/arch/loongarch/include/asm/acpi.h
> @@ -31,6 +31,144 @@ static inline bool acpi_has_cpu_in_madt(void)
>
> extern struct list_head acpi_wakeup_device_list;
>
> +/*
> + * Temporary definitions until the core ACPICA code gets updated (see
> + * 1656837932-18257-1-git-send-email-lvjianmin@loongson.cn and its
> + * follow-ups for the "rationale").
> + *
> + * Once the "legal reasons" are cleared and that the code is merged,
> + * this can be dropped entierely.
> + */
> +#if (ACPI_CA_VERSION == 0x20220331 && !defined(LOONGARCH_ACPICA_EXT))
> +
> +#define LOONGARCH_ACPICA_EXT 1
> +
> +#define ACPI_MADT_TYPE_CORE_PIC 17
> +#define ACPI_MADT_TYPE_LIO_PIC 18
> +#define ACPI_MADT_TYPE_HT_PIC 19
> +#define ACPI_MADT_TYPE_EIO_PIC 20
> +#define ACPI_MADT_TYPE_MSI_PIC 21
> +#define ACPI_MADT_TYPE_BIO_PIC 22
> +#define ACPI_MADT_TYPE_LPC_PIC 23
> +
> +/* Values for Version field above */
> +
> +enum acpi_madt_core_pic_version {
> + ACPI_MADT_CORE_PIC_VERSION_NONE = 0,
> + ACPI_MADT_CORE_PIC_VERSION_V1 = 1,
> + ACPI_MADT_CORE_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> +};
> +
> +enum acpi_madt_lio_pic_version {
> + ACPI_MADT_LIO_PIC_VERSION_NONE = 0,
> + ACPI_MADT_LIO_PIC_VERSION_V1 = 1,
> + ACPI_MADT_LIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> +};
> +
> +enum acpi_madt_eio_pic_version {
> + ACPI_MADT_EIO_PIC_VERSION_NONE = 0,
> + ACPI_MADT_EIO_PIC_VERSION_V1 = 1,
> + ACPI_MADT_EIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> +};
> +
> +enum acpi_madt_ht_pic_version {
> + ACPI_MADT_HT_PIC_VERSION_NONE = 0,
> + ACPI_MADT_HT_PIC_VERSION_V1 = 1,
> + ACPI_MADT_HT_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> +};
> +
> +enum acpi_madt_bio_pic_version {
> + ACPI_MADT_BIO_PIC_VERSION_NONE = 0,
> + ACPI_MADT_BIO_PIC_VERSION_V1 = 1,
> + ACPI_MADT_BIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> +};
> +
> +enum acpi_madt_msi_pic_version {
> + ACPI_MADT_MSI_PIC_VERSION_NONE = 0,
> + ACPI_MADT_MSI_PIC_VERSION_V1 = 1,
> + ACPI_MADT_MSI_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> +};
> +
> +enum acpi_madt_lpc_pic_version {
> + ACPI_MADT_LPC_PIC_VERSION_NONE = 0,
> + ACPI_MADT_LPC_PIC_VERSION_V1 = 1,
> + ACPI_MADT_LPC_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> +};
> +
Hi, Marc, I add #pragma here to make following structures align to 1
byte as include/acpi/actbl2.h, or else, the MADT will not be parsed
correctly.
#pragma pack(1)
> +/* Core Interrupt Controller */
> +
> +struct acpi_madt_core_pic {
> + struct acpi_subtable_header header;
> + u8 version;
> + u32 processor_id;
> + u32 core_id;
> + u32 flags;
> +};
> +
> +/* Legacy I/O Interrupt Controller */
> +
> +struct acpi_madt_lio_pic {
> + struct acpi_subtable_header header;
> + u8 version;
> + u64 address;
> + u16 size;
> + u8 cascade[2];
> + u32 cascade_map[2];
> +};
> +
> +/* Extend I/O Interrupt Controller */
> +
> +struct acpi_madt_eio_pic {
> + struct acpi_subtable_header header;
> + u8 version;
> + u8 cascade;
> + u8 node;
> + u64 node_map;
> +};
> +
> +/* HT Interrupt Controller */
> +
> +struct acpi_madt_ht_pic {
> + struct acpi_subtable_header header;
> + u8 version;
> + u64 address;
> + u16 size;
> + u8 cascade[8];
> +};
> +
> +/* Bridge I/O Interrupt Controller */
> +
> +struct acpi_madt_bio_pic {
> + struct acpi_subtable_header header;
> + u8 version;
> + u64 address;
> + u16 size;
> + u16 id;
> + u16 gsi_base;
> +};
> +
> +/* MSI Interrupt Controller */
> +
> +struct acpi_madt_msi_pic {
> + struct acpi_subtable_header header;
> + u8 version;
> + u64 msg_address;
> + u32 start;
> + u32 count;
> +};
> +
> +/* LPC Interrupt Controller */
> +
> +struct acpi_madt_lpc_pic {
> + struct acpi_subtable_header header;
> + u8 version;
> + u64 address;
> + u16 size;
> + u8 cascade;
> +};
> +
#pragma pack()
> +#endif
> +
> #endif /* !CONFIG_ACPI */
>
> #define ACPI_TABLE_UPGRADE_MAX_PHYS ARCH_LOW_ADDRESS_LIMIT
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH V15 01/15] ACPICA: MADT: Add LoongArch APICs support
2022-07-18 12:28 ` Jianmin Lv
@ 2022-07-18 13:26 ` Marc Zyngier
0 siblings, 0 replies; 36+ messages in thread
From: Marc Zyngier @ 2022-07-18 13:26 UTC (permalink / raw)
To: Jianmin Lv
Cc: Robert Moore, Thomas Gleixner, linux-kernel, loongarch,
Hanjun Guo, Lorenzo Pieralisi, Jiaxun Yang, Huacai Chen
On Mon, 18 Jul 2022 13:28:11 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
>
>
> On 2022/7/17 上午2:10, Marc Zyngier wrote:
> > [+ Robert Moore]
> >
> > On Fri, 15 Jul 2022 08:05:37 +0100,
> > Jianmin Lv <lvjianmin@loongson.cn> wrote:
> >>
> >> From: Huacai Chen <chenhuacai@loongson.cn>
> >>
> >> LoongArch-specific interrupt controllers (similar to APIC) are added
> >> in the next revision of ACPI Specification (current revision is 6.4),
> >> which including CORE_PIC (CPUINTC), LIO_PIC (LIOINTC), EIO_PIC (EIOINTC),
> >> HT_PIC (HTVECINTC), BIO_PIC (PCHINTC), LPC_PIC (PCHLPC) and MSI_PIC
> >> (PCHMSI). This patch add their definition.
> >>
> >> ACPI changes of LoongArch-specific interrupt controllers have already
> >> been approved in the ECRs, and will be public in the next revision of
> >> ACPI Specification.
> >>
> >> Reference: https://mantis.uefi.org/mantis/view.php?id=2203
> >> Reference: https://mantis.uefi.org/mantis/view.php?id=2313
> >>
> >> Above links needs login(available for ASWG), so the following link(
> >> the ECR file for adding LoongArch APICs into ACPI spec) is provided
> >> for public:
> >>
> >> https://github.com/lvjianmin-loongson/acpica/blob/master/Add%20APIC%20Structures%20for%20Loongarch%20in%20MADT-rev3.pdf
> >>
> >> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> >> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> >
> > Since the ACPI maintainers are unwilling to take this patch (for
> > undisclosed reasons), we need something to unblock this sorry
> > situation, as I don't think it is fair on the LoongArch folks to be
> > blocked for another cycle on this ground only.
> >
> > I'm proposing to replace this patch with the following, which will
> > allow the patches to be merged without breaking anything. Once the
> > ACPI support is updated, we'll be able to simply revert this patch.
> >
> > Thanks,
> >
> > M.
> >
> > From 43ec25d2dbde3c422cce430c9d5ec32fbe7b255c Mon Sep 17 00:00:00 2001
> > From: Marc Zyngier <maz@kernel.org>
> > Date: Sat, 16 Jul 2022 18:56:10 +0100
> > Subject: [PATCH] LoongArch: Provisionally add ACPICA data structures
> >
> > The LoongArch architecture is using ACPI, but the spec containing
> > the required updates still is in an unreleased state.
> >
> > Instead of preventing the inclusion of the IRQ support into the
> > kernel, add the missing bits to the arch-specific parts of
> > the ACPICA support.
> >
> > Once the ACPICA bits are updated to the version that supports
> > LoongArch, these bits can eventually be removed.
> >
> > Signed-off-by: Marc Zyngier <maz@kernel.org>
> > ---
> > arch/loongarch/include/asm/acpi.h | 138 ++++++++++++++++++++++++++++++
> > 1 file changed, 138 insertions(+)
> >
> > diff --git a/arch/loongarch/include/asm/acpi.h b/arch/loongarch/include/asm/acpi.h
> > index 62044cd5b7bc..6155e46098af 100644
> > --- a/arch/loongarch/include/asm/acpi.h
> > +++ b/arch/loongarch/include/asm/acpi.h
> > @@ -31,6 +31,144 @@ static inline bool acpi_has_cpu_in_madt(void)
> > extern struct list_head acpi_wakeup_device_list;
> > +/*
> > + * Temporary definitions until the core ACPICA code gets updated (see
> > + * 1656837932-18257-1-git-send-email-lvjianmin@loongson.cn and its
> > + * follow-ups for the "rationale").
> > + *
> > + * Once the "legal reasons" are cleared and that the code is merged,
> > + * this can be dropped entierely.
> > + */
> > +#if (ACPI_CA_VERSION == 0x20220331 && !defined(LOONGARCH_ACPICA_EXT))
> > +
> > +#define LOONGARCH_ACPICA_EXT 1
> > +
> > +#define ACPI_MADT_TYPE_CORE_PIC 17
> > +#define ACPI_MADT_TYPE_LIO_PIC 18
> > +#define ACPI_MADT_TYPE_HT_PIC 19
> > +#define ACPI_MADT_TYPE_EIO_PIC 20
> > +#define ACPI_MADT_TYPE_MSI_PIC 21
> > +#define ACPI_MADT_TYPE_BIO_PIC 22
> > +#define ACPI_MADT_TYPE_LPC_PIC 23
> > +
> > +/* Values for Version field above */
> > +
> > +enum acpi_madt_core_pic_version {
> > + ACPI_MADT_CORE_PIC_VERSION_NONE = 0,
> > + ACPI_MADT_CORE_PIC_VERSION_V1 = 1,
> > + ACPI_MADT_CORE_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> > +};
> > +
> > +enum acpi_madt_lio_pic_version {
> > + ACPI_MADT_LIO_PIC_VERSION_NONE = 0,
> > + ACPI_MADT_LIO_PIC_VERSION_V1 = 1,
> > + ACPI_MADT_LIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> > +};
> > +
> > +enum acpi_madt_eio_pic_version {
> > + ACPI_MADT_EIO_PIC_VERSION_NONE = 0,
> > + ACPI_MADT_EIO_PIC_VERSION_V1 = 1,
> > + ACPI_MADT_EIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> > +};
> > +
> > +enum acpi_madt_ht_pic_version {
> > + ACPI_MADT_HT_PIC_VERSION_NONE = 0,
> > + ACPI_MADT_HT_PIC_VERSION_V1 = 1,
> > + ACPI_MADT_HT_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> > +};
> > +
> > +enum acpi_madt_bio_pic_version {
> > + ACPI_MADT_BIO_PIC_VERSION_NONE = 0,
> > + ACPI_MADT_BIO_PIC_VERSION_V1 = 1,
> > + ACPI_MADT_BIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> > +};
> > +
> > +enum acpi_madt_msi_pic_version {
> > + ACPI_MADT_MSI_PIC_VERSION_NONE = 0,
> > + ACPI_MADT_MSI_PIC_VERSION_V1 = 1,
> > + ACPI_MADT_MSI_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> > +};
> > +
> > +enum acpi_madt_lpc_pic_version {
> > + ACPI_MADT_LPC_PIC_VERSION_NONE = 0,
> > + ACPI_MADT_LPC_PIC_VERSION_V1 = 1,
> > + ACPI_MADT_LPC_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> > +};
> > +
>
> Hi, Marc, I add #pragma here to make following structures align to 1
> byte as include/acpi/actbl2.h, or else, the MADT will not be parsed
> correctly.
If that's required, please add it.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2022-07-18 13:26 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 01/15] ACPICA: MADT: Add LoongArch APICs support Jianmin Lv
2022-07-16 18:10 ` Marc Zyngier
2022-07-17 1:05 ` Jianmin Lv
2022-07-18 12:28 ` Jianmin Lv
2022-07-18 13:26 ` Marc Zyngier
2022-07-15 7:05 ` [PATCH V15 02/15] APCI: irq: Add support for multiple GSI domains Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 03/15] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 04/15] genirq/generic_chip: export irq_unmap_generic_chip Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 05/15] LoongArch: Use ACPI_GENERIC_GSI for gsi handling Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 06/15] irqchip: Add Loongson PCH LPC controller support Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 07/15] irqchip: remove COMPILE_TEST for pch-pic and pch-msi Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 08/15] irqchip/loongson-pch-pic: Add ACPI init support Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 09/15] irqchip/loongson-pch-msi: " Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 10/15] irqchip/loongson-htvec: " Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 11/15] irqchip/loongson-liointc: " Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 12/15] LoongArch: prepare to support multiple pch-pic and pch-msi irqdomain Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 13/15] irqchip: Add Loongson Extended I/O interrupt controller support Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 14/15] irqchip: Add LoongArch CPU " Jianmin Lv
2022-07-15 15:11 ` Huacai Chen
2022-07-17 12:02 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 15/15] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch Jianmin Lv
2022-07-16 18:39 ` [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Marc Zyngier
2022-07-17 1:06 ` Jianmin Lv
2022-07-17 10:02 ` Marc Zyngier
2022-07-17 11:29 ` Jianmin Lv
2022-07-17 14:08 ` Huacai Chen
2022-07-17 14:43 ` Marc Zyngier
2022-07-18 2:38 ` Huacai Chen
2022-07-18 6:43 ` Marc Zyngier
2022-07-18 8:35 ` Huacai Chen
2022-07-17 14:49 ` Marc Zyngier
2022-07-18 1:07 ` Jianmin Lv
2022-07-18 6:39 ` Marc Zyngier
2022-07-18 8:29 ` Jianmin Lv
2022-07-18 8:39 ` Huacai Chen
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