From: Lars Povlsen <lars.povlsen@microchip.com> To: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Lars Povlsen <lars.povlsen@microchip.com>, Serge Semin <fancer.lancer@gmail.com>, Mark Brown <broonie@kernel.org>, SoC Team <soc@kernel.org>, Rob Herring <robh+dt@kernel.org>, <devicetree@vger.kernel.org>, Alexandre Belloni <alexandre.belloni@bootlin.com>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>, Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>, <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH 04/10] dt-bindings: spi: Add bindings for spi-dw-mchp Date: Tue, 9 Jun 2020 12:27:44 +0200 [thread overview] Message-ID: <87img0ilen.fsf@soft-dev15.microsemi.net> (raw) In-Reply-To: <20200602194925.qbevttzz3ghvmd2d@mobilestation> Serge Semin writes: > On Wed, May 13, 2020 at 04:00:25PM +0200, Lars Povlsen wrote: >> This add DT bindings for the Microsemi/Microchip SPI controller used >> in various SoC's. It describes the "mscc,ocelot-spi" and >> "mscc,jaguar2-spi" bindings. > > As I see it, there is no need in this patch at all. Current DT binding file > describes the MSCC version of the DW APB SSI IP pretty well. You can add an > example to the DT schema though with "mscc,ocelot-spi" or "mscc,jaguar2-spi" > compatible string and additional registers range. > Fine by me. I just had the understanding that a YAML binding had to be given for a new driver. I will add the bindings to the existing YAML with proper guards. ---Lars > -Sergey > >> >> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> >> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> >> --- >> .../bindings/spi/mscc,ocelot-spi.yaml | 60 +++++++++++++++++++ >> .../bindings/spi/snps,dw-apb-ssi.txt | 7 +-- >> MAINTAINERS | 1 + >> 3 files changed, 63 insertions(+), 5 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml >> >> diff --git a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml >> new file mode 100644 >> index 0000000000000..a3ac0fa576553 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml >> @@ -0,0 +1,60 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: "http://devicetree.org/schemas/spi/mscc,ocelot-spi.yaml#" >> +$schema: "http://devicetree.org/meta-schemas/core.yaml#" >> + >> +title: Microsemi Vcore-III SPI Communication Controller >> + >> +maintainers: >> + - Alexandre Belloni <alexandre.belloni@bootlin.com> >> + - Lars Povlsen <lars.povlsen@microchip.com> >> + >> +allOf: >> + - $ref: "spi-controller.yaml#" >> + >> +description: | >> + The Microsemi Vcore-III SPI controller is a general purpose SPI >> + controller based upon the Designware SPI controller. It uses an 8 >> + byte rx/tx fifo. >> + >> +properties: >> + compatible: >> + enum: >> + - mscc,ocelot-spi >> + - mscc,jaguar2-spi >> + >> + interrupts: >> + maxItems: 1 >> + >> + reg: >> + minItems: 2 >> + items: >> + - description: Designware SPI registers >> + - description: CS override registers >> + >> + clocks: >> + maxItems: 1 >> + >> + reg-io-width: >> + description: | >> + The I/O register width (in bytes) implemented by this device. >> + items: >> + enum: [ 2, 4 ] >> + maxItems: 1 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + >> +examples: >> + - | >> + spi0: spi@101000 { >> + compatible = "mscc,ocelot-spi"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + reg = <0x101000 0x100>, <0x3c 0x18>; >> + interrupts = <9>; >> + clocks = <&ahb_clk>; >> + }; >> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt >> index 3ed08ee9feba4..5e1849be7bae5 100644 >> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt >> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt >> @@ -1,10 +1,8 @@ >> Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. >> >> Required properties: >> -- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or >> - "jaguar2", or "amazon,alpine-dw-apb-ssi" >> -- reg : The register base for the controller. For "mscc,<soc>-spi", a second >> - register set is required (named ICPU_CFG:SPI_MST) >> +- compatible : "snps,dw-apb-ssi" or "amazon,alpine-dw-apb-ssi" >> +- reg : The register base for the controller. >> - interrupts : One interrupt, used by the controller. >> - #address-cells : <1>, as required by generic SPI binding. >> - #size-cells : <0>, also as required by generic SPI binding. >> @@ -38,4 +36,3 @@ Example: >> cs-gpios = <&gpio0 13 0>, >> <&gpio0 14 0>; >> }; >> - >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 1db598723a1d8..6472240b8391b 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -11231,6 +11231,7 @@ L: linux-mips@vger.kernel.org >> S: Supported >> F: Documentation/devicetree/bindings/mips/mscc.txt >> F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt >> +F: Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml >> F: arch/mips/boot/dts/mscc/ >> F: arch/mips/configs/generic/board-ocelot.config >> F: arch/mips/generic/board-ocelot.c >> -- >> 2.26.2 >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Lars Povlsen, Microchip
WARNING: multiple messages have this Message-ID (diff)
From: Lars Povlsen <lars.povlsen@microchip.com> To: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: devicetree@vger.kernel.org, Alexandre Belloni <alexandre.belloni@bootlin.com>, Mark Brown <broonie@kernel.org>, linux-kernel@vger.kernel.org, Serge Semin <fancer.lancer@gmail.com>, linux-spi@vger.kernel.org, SoC Team <soc@kernel.org>, Rob Herring <robh+dt@kernel.org>, linux-arm-kernel@lists.infradead.org, Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>, Lars Povlsen <lars.povlsen@microchip.com> Subject: Re: [PATCH 04/10] dt-bindings: spi: Add bindings for spi-dw-mchp Date: Tue, 9 Jun 2020 12:27:44 +0200 [thread overview] Message-ID: <87img0ilen.fsf@soft-dev15.microsemi.net> (raw) In-Reply-To: <20200602194925.qbevttzz3ghvmd2d@mobilestation> Serge Semin writes: > On Wed, May 13, 2020 at 04:00:25PM +0200, Lars Povlsen wrote: >> This add DT bindings for the Microsemi/Microchip SPI controller used >> in various SoC's. It describes the "mscc,ocelot-spi" and >> "mscc,jaguar2-spi" bindings. > > As I see it, there is no need in this patch at all. Current DT binding file > describes the MSCC version of the DW APB SSI IP pretty well. You can add an > example to the DT schema though with "mscc,ocelot-spi" or "mscc,jaguar2-spi" > compatible string and additional registers range. > Fine by me. I just had the understanding that a YAML binding had to be given for a new driver. I will add the bindings to the existing YAML with proper guards. ---Lars > -Sergey > >> >> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> >> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> >> --- >> .../bindings/spi/mscc,ocelot-spi.yaml | 60 +++++++++++++++++++ >> .../bindings/spi/snps,dw-apb-ssi.txt | 7 +-- >> MAINTAINERS | 1 + >> 3 files changed, 63 insertions(+), 5 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml >> >> diff --git a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml >> new file mode 100644 >> index 0000000000000..a3ac0fa576553 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml >> @@ -0,0 +1,60 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: "http://devicetree.org/schemas/spi/mscc,ocelot-spi.yaml#" >> +$schema: "http://devicetree.org/meta-schemas/core.yaml#" >> + >> +title: Microsemi Vcore-III SPI Communication Controller >> + >> +maintainers: >> + - Alexandre Belloni <alexandre.belloni@bootlin.com> >> + - Lars Povlsen <lars.povlsen@microchip.com> >> + >> +allOf: >> + - $ref: "spi-controller.yaml#" >> + >> +description: | >> + The Microsemi Vcore-III SPI controller is a general purpose SPI >> + controller based upon the Designware SPI controller. It uses an 8 >> + byte rx/tx fifo. >> + >> +properties: >> + compatible: >> + enum: >> + - mscc,ocelot-spi >> + - mscc,jaguar2-spi >> + >> + interrupts: >> + maxItems: 1 >> + >> + reg: >> + minItems: 2 >> + items: >> + - description: Designware SPI registers >> + - description: CS override registers >> + >> + clocks: >> + maxItems: 1 >> + >> + reg-io-width: >> + description: | >> + The I/O register width (in bytes) implemented by this device. >> + items: >> + enum: [ 2, 4 ] >> + maxItems: 1 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + >> +examples: >> + - | >> + spi0: spi@101000 { >> + compatible = "mscc,ocelot-spi"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + reg = <0x101000 0x100>, <0x3c 0x18>; >> + interrupts = <9>; >> + clocks = <&ahb_clk>; >> + }; >> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt >> index 3ed08ee9feba4..5e1849be7bae5 100644 >> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt >> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt >> @@ -1,10 +1,8 @@ >> Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. >> >> Required properties: >> -- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or >> - "jaguar2", or "amazon,alpine-dw-apb-ssi" >> -- reg : The register base for the controller. For "mscc,<soc>-spi", a second >> - register set is required (named ICPU_CFG:SPI_MST) >> +- compatible : "snps,dw-apb-ssi" or "amazon,alpine-dw-apb-ssi" >> +- reg : The register base for the controller. >> - interrupts : One interrupt, used by the controller. >> - #address-cells : <1>, as required by generic SPI binding. >> - #size-cells : <0>, also as required by generic SPI binding. >> @@ -38,4 +36,3 @@ Example: >> cs-gpios = <&gpio0 13 0>, >> <&gpio0 14 0>; >> }; >> - >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 1db598723a1d8..6472240b8391b 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -11231,6 +11231,7 @@ L: linux-mips@vger.kernel.org >> S: Supported >> F: Documentation/devicetree/bindings/mips/mscc.txt >> F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt >> +F: Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml >> F: arch/mips/boot/dts/mscc/ >> F: arch/mips/configs/generic/board-ocelot.config >> F: arch/mips/generic/board-ocelot.c >> -- >> 2.26.2 >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Lars Povlsen, Microchip _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-06-09 10:27 UTC|newest] Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-13 14:00 [PATCH 00/10] spi: Adding support for Microchip Sparx5 SoC Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 01/10] spi: dw: Add support for polled operation via no IRQ specified in DT Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-13 14:20 ` Mark Brown 2020-05-14 13:04 ` Serge Semin 2020-05-14 13:04 ` Serge Semin 2020-05-15 9:11 ` Lars Povlsen 2020-05-15 9:11 ` Lars Povlsen 2020-05-13 14:37 ` Mark Brown 2020-05-19 10:21 ` Lars Povlsen 2020-05-19 10:21 ` Lars Povlsen 2020-05-13 14:55 ` Andy Shevchenko 2020-05-13 14:55 ` Andy Shevchenko 2020-05-19 10:25 ` Lars Povlsen 2020-05-19 10:25 ` Lars Povlsen 2020-06-02 19:10 ` Serge Semin 2020-06-02 19:10 ` Serge Semin 2020-06-09 9:13 ` Lars Povlsen 2020-06-09 9:13 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 02/10] spi: dw: Add support for RX sample delay register Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-06-02 19:39 ` Serge Semin 2020-06-02 19:39 ` Serge Semin 2020-06-09 10:04 ` Lars Povlsen 2020-06-09 10:04 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 03/10] spi: dw: Add support for client driver memory operations Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 04/10] dt-bindings: spi: Add bindings for spi-dw-mchp Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-13 14:52 ` Mark Brown 2020-05-19 11:47 ` Lars Povlsen 2020-05-19 11:47 ` Lars Povlsen 2020-05-19 11:58 ` Mark Brown 2020-05-19 12:10 ` Lars Povlsen 2020-05-19 12:10 ` Lars Povlsen 2020-06-02 19:49 ` Serge Semin 2020-06-02 19:49 ` Serge Semin 2020-06-09 10:27 ` Lars Povlsen [this message] 2020-06-09 10:27 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 05/10] spi: spi-dw-mmio: Spin off MSCC platforms into spi-dw-mchp Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-13 15:18 ` Mark Brown 2020-05-19 12:05 ` Lars Povlsen 2020-05-19 12:05 ` Lars Povlsen 2020-06-02 21:12 ` Serge Semin 2020-06-02 21:12 ` Serge Semin 2020-06-10 14:28 ` Lars Povlsen 2020-06-10 14:28 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 06/10] dt-bindings: spi: spi-dw-mchp: Add Sparx5 support Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-13 15:25 ` Mark Brown 2020-06-02 23:07 ` Serge Semin 2020-06-02 23:07 ` Serge Semin 2020-06-10 12:27 ` Lars Povlsen 2020-06-10 12:27 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 07/10] " Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-14 10:25 ` Mark Brown 2020-05-19 9:29 ` Lars Povlsen 2020-05-19 9:29 ` Lars Povlsen 2020-06-02 23:22 ` Serge Semin 2020-06-02 23:22 ` Serge Semin 2020-05-13 14:00 ` [PATCH 08/10] arm64: dts: sparx5: Add SPI controller Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 09/10] arm64: dts: sparx5: Add spi-nor support Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-13 14:00 ` [PATCH 10/10] arm64: dts: sparx5: Add spi-nand devices Lars Povlsen 2020-05-13 14:00 ` Lars Povlsen 2020-05-29 16:21 ` [PATCH 00/10] spi: Adding support for Microchip Sparx5 SoC Serge Semin 2020-05-29 16:21 ` Serge Semin 2020-06-02 8:18 ` Lars Povlsen 2020-06-02 8:18 ` Lars Povlsen 2020-06-02 8:21 ` Serge Semin 2020-06-02 8:21 ` Serge Semin 2020-06-02 9:56 ` Mark Brown 2020-06-02 23:44 ` Serge Semin 2020-06-02 23:44 ` Serge Semin
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