* [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
@ 2019-03-15 20:05 Alistair Francis
2019-03-18 8:39 ` Paolo Bonzini
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Alistair Francis @ 2019-03-15 20:05 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, Alistair Francis, alistair23, david.abdurachmanov,
rjones, abologna, pbonzini
Set msi_nonbroken as true for the PLIC.
According to the comment located here:
https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38
the msi_nonbroken variable should be set to true even if they don't
support MSI. In this case that is what we are doing as we don't support
MSI.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Andrea Bolognani <abologna@redhat.com>
Reported-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
---
This should allow working pcie-root-ports in QEMU and allow libvirt
to start using PCIe by default for RISC-V guests.
hw/riscv/sifive_plic.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index d12ec3fc9a..4b0537c912 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -22,6 +22,7 @@
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "hw/sysbus.h"
+#include "hw/pci/msi.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/sifive_plic.h"
@@ -443,6 +444,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
+
+ msi_nonbroken = true;
}
static void sifive_plic_class_init(ObjectClass *klass, void *data)
--
2.21.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
2019-03-15 20:05 [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true Alistair Francis
@ 2019-03-18 8:39 ` Paolo Bonzini
2019-03-18 9:22 ` Andrea Bolognani
2019-03-18 9:31 ` Palmer Dabbelt
2019-03-18 8:58 ` [Qemu-riscv] [Qemu-devel] " Markus Armbruster
2019-03-18 9:31 ` [Qemu-riscv] " Andrea Bolognani
2 siblings, 2 replies; 11+ messages in thread
From: Paolo Bonzini @ 2019-03-18 8:39 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: palmer, alistair23, david.abdurachmanov, rjones, abologna
On 15/03/19 21:05, Alistair Francis wrote:
> Set msi_nonbroken as true for the PLIC.
>
> According to the comment located here:
> https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38
> the msi_nonbroken variable should be set to true even if they don't
> support MSI. In this case that is what we are doing as we don't support
> MSI.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reported-by: Andrea Bolognani <abologna@redhat.com>
> Reported-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
> ---
> This should allow working pcie-root-ports in QEMU and allow libvirt
> to start using PCIe by default for RISC-V guests.
>
> hw/riscv/sifive_plic.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
> index d12ec3fc9a..4b0537c912 100644
> --- a/hw/riscv/sifive_plic.c
> +++ b/hw/riscv/sifive_plic.c
> @@ -22,6 +22,7 @@
> #include "qemu/log.h"
> #include "qemu/error-report.h"
> #include "hw/sysbus.h"
> +#include "hw/pci/msi.h"
> #include "target/riscv/cpu.h"
> #include "hw/riscv/sifive_plic.h"
>
> @@ -443,6 +444,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
> plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
> qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
> +
> + msi_nonbroken = true;
> }
>
> static void sifive_plic_class_init(ObjectClass *klass, void *data)
>
I can queue this patch, and add the "select MSI" to CONFIG_SIFIVE.
Paolo
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
2019-03-18 8:39 ` Paolo Bonzini
@ 2019-03-18 9:22 ` Andrea Bolognani
2019-03-18 9:37 ` David Abdurachmanov
2019-03-18 9:31 ` Palmer Dabbelt
1 sibling, 1 reply; 11+ messages in thread
From: Andrea Bolognani @ 2019-03-18 9:22 UTC (permalink / raw)
To: Paolo Bonzini, Alistair Francis, qemu-devel, qemu-riscv
Cc: palmer, alistair23, david.abdurachmanov, rjones
On Mon, 2019-03-18 at 09:39 +0100, Paolo Bonzini wrote:
> On 15/03/19 21:05, Alistair Francis wrote:
> > Set msi_nonbroken as true for the PLIC.
> >
> > According to the comment located here:
> > https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38
> > the msi_nonbroken variable should be set to true even if they don't
> > support MSI. In this case that is what we are doing as we don't support
> > MSI.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > Reported-by: Andrea Bolognani <abologna@redhat.com>
> > Reported-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
> > ---
> > This should allow working pcie-root-ports in QEMU and allow libvirt
> > to start using PCIe by default for RISC-V guests.
> >
> > hw/riscv/sifive_plic.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
> > index d12ec3fc9a..4b0537c912 100644
> > --- a/hw/riscv/sifive_plic.c
> > +++ b/hw/riscv/sifive_plic.c
> > @@ -22,6 +22,7 @@
> > #include "qemu/log.h"
> > #include "qemu/error-report.h"
> > #include "hw/sysbus.h"
> > +#include "hw/pci/msi.h"
> > #include "target/riscv/cpu.h"
> > #include "hw/riscv/sifive_plic.h"
> >
> > @@ -443,6 +444,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
> > plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
> > sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
> > qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
> > +
> > + msi_nonbroken = true;
> > }
> >
> > static void sifive_plic_class_init(ObjectClass *klass, void *data)
>
> I can queue this patch, and add the "select MSI" to CONFIG_SIFIVE.
The interrupt controller is used by the virt machine type too IIUC,
so the same should be added to CONFIG_RISCV_VIRT I think.
--
Andrea Bolognani / Red Hat / Virtualization
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
2019-03-18 9:22 ` Andrea Bolognani
@ 2019-03-18 9:37 ` David Abdurachmanov
0 siblings, 0 replies; 11+ messages in thread
From: David Abdurachmanov @ 2019-03-18 9:37 UTC (permalink / raw)
To: Andrea Bolognani
Cc: Paolo Bonzini, Alistair Francis, qemu-devel, qemu-riscv, palmer,
alistair23, rjones
On Mon, Mar 18, 2019 at 10:22 AM Andrea Bolognani <abologna@redhat.com> wrote:
>
> On Mon, 2019-03-18 at 09:39 +0100, Paolo Bonzini wrote:
> > On 15/03/19 21:05, Alistair Francis wrote:
> > > Set msi_nonbroken as true for the PLIC.
> > >
> > > According to the comment located here:
> > > https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38
> > > the msi_nonbroken variable should be set to true even if they don't
> > > support MSI. In this case that is what we are doing as we don't support
> > > MSI.
> > >
> > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > > Reported-by: Andrea Bolognani <abologna@redhat.com>
> > > Reported-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
> > > ---
> > > This should allow working pcie-root-ports in QEMU and allow libvirt
> > > to start using PCIe by default for RISC-V guests.
> > >
> > > hw/riscv/sifive_plic.c | 3 +++
> > > 1 file changed, 3 insertions(+)
> > >
> > > diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
> > > index d12ec3fc9a..4b0537c912 100644
> > > --- a/hw/riscv/sifive_plic.c
> > > +++ b/hw/riscv/sifive_plic.c
> > > @@ -22,6 +22,7 @@
> > > #include "qemu/log.h"
> > > #include "qemu/error-report.h"
> > > #include "hw/sysbus.h"
> > > +#include "hw/pci/msi.h"
> > > #include "target/riscv/cpu.h"
> > > #include "hw/riscv/sifive_plic.h"
> > >
> > > @@ -443,6 +444,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
> > > plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
> > > sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
> > > qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
> > > +
> > > + msi_nonbroken = true;
> > > }
> > >
> > > static void sifive_plic_class_init(ObjectClass *klass, void *data)
> >
> > I can queue this patch, and add the "select MSI" to CONFIG_SIFIVE.
>
> The interrupt controller is used by the virt machine type too IIUC,
> so the same should be added to CONFIG_RISCV_VIRT I think.
CONFIG_SIFIVE is selected by CONFIG_RISCV_VIRT thus we should be good.
>
> --
> Andrea Bolognani / Red Hat / Virtualization
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
2019-03-18 8:39 ` Paolo Bonzini
2019-03-18 9:22 ` Andrea Bolognani
@ 2019-03-18 9:31 ` Palmer Dabbelt
2019-03-21 11:56 ` Andrea Bolognani
1 sibling, 1 reply; 11+ messages in thread
From: Palmer Dabbelt @ 2019-03-18 9:31 UTC (permalink / raw)
To: pbonzini
Cc: Alistair Francis, qemu-devel, qemu-riscv, alistair23,
David Abdurachmanov, rjones, abologna
On Mon, 18 Mar 2019 01:39:46 PDT (-0700), pbonzini@redhat.com wrote:
> On 15/03/19 21:05, Alistair Francis wrote:
>> Set msi_nonbroken as true for the PLIC.
>>
>> According to the comment located here:
>> https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38
>> the msi_nonbroken variable should be set to true even if they don't
>> support MSI. In this case that is what we are doing as we don't support
>> MSI.
>>
>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> Reported-by: Andrea Bolognani <abologna@redhat.com>
>> Reported-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
>> ---
>> This should allow working pcie-root-ports in QEMU and allow libvirt
>> to start using PCIe by default for RISC-V guests.
>>
>> hw/riscv/sifive_plic.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
>> index d12ec3fc9a..4b0537c912 100644
>> --- a/hw/riscv/sifive_plic.c
>> +++ b/hw/riscv/sifive_plic.c
>> @@ -22,6 +22,7 @@
>> #include "qemu/log.h"
>> #include "qemu/error-report.h"
>> #include "hw/sysbus.h"
>> +#include "hw/pci/msi.h"
>> #include "target/riscv/cpu.h"
>> #include "hw/riscv/sifive_plic.h"
>>
>> @@ -443,6 +444,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
>> plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
>> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
>> qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
>> +
>> + msi_nonbroken = true;
>> }
>>
>> static void sifive_plic_class_init(ObjectClass *klass, void *data)
>>
>
> I can queue this patch, and add the "select MSI" to CONFIG_SIFIVE.
Works for me. Thanks!
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
2019-03-18 9:31 ` Palmer Dabbelt
@ 2019-03-21 11:56 ` Andrea Bolognani
2019-03-21 12:21 ` Paolo Bonzini
0 siblings, 1 reply; 11+ messages in thread
From: Andrea Bolognani @ 2019-03-21 11:56 UTC (permalink / raw)
To: Palmer Dabbelt, pbonzini
Cc: qemu-riscv, David Abdurachmanov, rjones, qemu-devel,
Alistair Francis, alistair23
On Mon, 2019-03-18 at 02:31 -0700, Palmer Dabbelt wrote:
> On Mon, 18 Mar 2019 01:39:46 PDT (-0700), pbonzini@redhat.com wrote:
> > On 15/03/19 21:05, Alistair Francis wrote:
> > > Set msi_nonbroken as true for the PLIC.
> > >
> > > According to the comment located here:
> > > https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38
> > > the msi_nonbroken variable should be set to true even if they don't
> > > support MSI. In this case that is what we are doing as we don't support
> > > MSI.
> >
> > I can queue this patch, and add the "select MSI" to CONFIG_SIFIVE.
>
> Works for me. Thanks!
Just so we're on the same page, are you targeting this at 4.0.0?
If it gets merged in the next few days I can probably get the
corresponding libvirt patches in before our own freeze starts.
It would be great if we could make it so guests created with
QEMU 4.0.0 + libvirt 5.2.0 get PCI by default :)
--
Andrea Bolognani / Red Hat / Virtualization
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
2019-03-21 11:56 ` Andrea Bolognani
@ 2019-03-21 12:21 ` Paolo Bonzini
0 siblings, 0 replies; 11+ messages in thread
From: Paolo Bonzini @ 2019-03-21 12:21 UTC (permalink / raw)
To: Andrea Bolognani, Palmer Dabbelt
Cc: qemu-riscv, David Abdurachmanov, rjones, qemu-devel,
Alistair Francis, alistair23
On 21/03/19 12:56, Andrea Bolognani wrote:
> Just so we're on the same page, are you targeting this at 4.0.0?
> If it gets merged in the next few days I can probably get the
> corresponding libvirt patches in before our own freeze starts.
>
> It would be great if we could make it so guests created with
> QEMU 4.0.0 + libvirt 5.2.0 get PCI by default :)
Yes, I'll send the pull request tomorrow.
Paolo
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
2019-03-15 20:05 [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true Alistair Francis
2019-03-18 8:39 ` Paolo Bonzini
@ 2019-03-18 8:58 ` Markus Armbruster
2019-03-18 9:55 ` Peter Maydell
2019-03-18 9:31 ` [Qemu-riscv] " Andrea Bolognani
2 siblings, 1 reply; 11+ messages in thread
From: Markus Armbruster @ 2019-03-18 8:58 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel, qemu-riscv, david.abdurachmanov, palmer, rjones,
abologna, pbonzini, alistair23
Alistair Francis <Alistair.Francis@wdc.com> writes:
> Set msi_nonbroken as true for the PLIC.
>
> According to the comment located here:
> https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38
> the msi_nonbroken variable should be set to true even if they don't
> support MSI. In this case that is what we are doing as we don't support
> MSI.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reported-by: Andrea Bolognani <abologna@redhat.com>
> Reported-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
> ---
> This should allow working pcie-root-ports in QEMU and allow libvirt
> to start using PCIe by default for RISC-V guests.
Lovely! If more people reviewed and updated their interrupt controllers
this way, we'd be in better shape.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
2019-03-18 8:58 ` [Qemu-riscv] [Qemu-devel] " Markus Armbruster
@ 2019-03-18 9:55 ` Peter Maydell
2019-03-18 12:31 ` Markus Armbruster
0 siblings, 1 reply; 11+ messages in thread
From: Peter Maydell @ 2019-03-18 9:55 UTC (permalink / raw)
To: Markus Armbruster
Cc: Alistair Francis, qemu-riscv, david.abdurachmanov, palmer,
rjones, qemu-devel, abologna, alistair23, pbonzini
On Mon, 18 Mar 2019 at 08:59, Markus Armbruster <armbru@redhat.com> wrote:
>
> Alistair Francis <Alistair.Francis@wdc.com> writes:
>
> > Set msi_nonbroken as true for the PLIC.
> >
> > According to the comment located here:
> > https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38
> > the msi_nonbroken variable should be set to true even if they don't
> > support MSI. In this case that is what we are doing as we don't support
> > MSI.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > Reported-by: Andrea Bolognani <abologna@redhat.com>
> > Reported-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
> > ---
> > This should allow working pcie-root-ports in QEMU and allow libvirt
> > to start using PCIe by default for RISC-V guests.
>
> Lovely! If more people reviewed and updated their interrupt controllers
> this way, we'd be in better shape.
Why do we have a flag which each interrupt controller
has to set rather than just making the right thing the
default (and having the one or two interrupt controllers
that need the wrong thing for backwards compatibility reasons
be the ones that have to set the flag) ? This way round makes
it way to easy to add a new interrupt controller with this
bug without noticing it, I think.
thanks
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
2019-03-18 9:55 ` Peter Maydell
@ 2019-03-18 12:31 ` Markus Armbruster
0 siblings, 0 replies; 11+ messages in thread
From: Markus Armbruster @ 2019-03-18 12:31 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-riscv, david.abdurachmanov, palmer, qemu-devel, rjones,
Alistair Francis, abologna, pbonzini, alistair23,
Michael S. Tsirkin
Peter Maydell <peter.maydell@linaro.org> writes:
> On Mon, 18 Mar 2019 at 08:59, Markus Armbruster <armbru@redhat.com> wrote:
>>
>> Alistair Francis <Alistair.Francis@wdc.com> writes:
>>
>> > Set msi_nonbroken as true for the PLIC.
>> >
>> > According to the comment located here:
>> > https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38
>> > the msi_nonbroken variable should be set to true even if they don't
>> > support MSI. In this case that is what we are doing as we don't support
>> > MSI.
>> >
>> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> > Reported-by: Andrea Bolognani <abologna@redhat.com>
>> > Reported-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
>> > ---
>> > This should allow working pcie-root-ports in QEMU and allow libvirt
>> > to start using PCIe by default for RISC-V guests.
>>
>> Lovely! If more people reviewed and updated their interrupt controllers
>> this way, we'd be in better shape.
>
> Why do we have a flag which each interrupt controller
> has to set rather than just making the right thing the
> default (and having the one or two interrupt controllers
> that need the wrong thing for backwards compatibility reasons
> be the ones that have to set the flag) ? This way round makes
> it way to easy to add a new interrupt controller with this
> bug without noticing it, I think.
This is ultimately a question for Michael (cc'ed). However, I can
provide a bit of context right away.
The problem is virtual interrupt controllers that claim to support MSI
when they don't. The OS's probe returns "go ahead and use MSI", and the
system falls apart.
So we put in a lame work-around to masks these interrupt controller
bugs: if MSI is broken, mangle all PCI devices to make them deny MSI
capability.
The next problem is that we don't even know which of our interrupt
controllers have MSI working. So we summarily declare them all broken,
then have the few we actually know declare themselves non-broken.
The next problem is having multiple interrupt controllers, some broken,
some not. The work-around falls apart there. We currently use the
ostrich algorithm to deal with that.
More information in the thread around
Message-ID: <87wppi1vol.fsf@blackfin.pond.sub.org>
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg00983.html
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
2019-03-15 20:05 [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true Alistair Francis
2019-03-18 8:39 ` Paolo Bonzini
2019-03-18 8:58 ` [Qemu-riscv] [Qemu-devel] " Markus Armbruster
@ 2019-03-18 9:31 ` Andrea Bolognani
2 siblings, 0 replies; 11+ messages in thread
From: Andrea Bolognani @ 2019-03-18 9:31 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: palmer, alistair23, david.abdurachmanov, rjones, pbonzini
On Fri, 2019-03-15 at 20:05 +0000, Alistair Francis wrote:
> Set msi_nonbroken as true for the PLIC.
>
> According to the comment located here:
> https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38
> the msi_nonbroken variable should be set to true even if they don't
> support MSI. In this case that is what we are doing as we don't support
> MSI.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reported-by: Andrea Bolognani <abologna@redhat.com>
> Reported-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
> ---
> This should allow working pcie-root-ports in QEMU and allow libvirt
> to start using PCIe by default for RISC-V guests.
>
> hw/riscv/sifive_plic.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
> index d12ec3fc9a..4b0537c912 100644
> --- a/hw/riscv/sifive_plic.c
> +++ b/hw/riscv/sifive_plic.c
> @@ -22,6 +22,7 @@
> #include "qemu/log.h"
> #include "qemu/error-report.h"
> #include "hw/sysbus.h"
> +#include "hw/pci/msi.h"
> #include "target/riscv/cpu.h"
> #include "hw/riscv/sifive_plic.h"
>
> @@ -443,6 +444,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
> plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
> qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
> +
> + msi_nonbroken = true;
> }
>
> static void sifive_plic_class_init(ObjectClass *klass, void *data)
With this patch applied, I was able to bring up a riscv64/virt guest
with graphics, using PCIe devices only:
https://imgur.com/a/taN06hE
Tested-by: Andrea Bolognani <abologna@redhat.com>
--
Andrea Bolognani / Red Hat / Virtualization
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-03-21 12:24 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-15 20:05 [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true Alistair Francis
2019-03-18 8:39 ` Paolo Bonzini
2019-03-18 9:22 ` Andrea Bolognani
2019-03-18 9:37 ` David Abdurachmanov
2019-03-18 9:31 ` Palmer Dabbelt
2019-03-21 11:56 ` Andrea Bolognani
2019-03-21 12:21 ` Paolo Bonzini
2019-03-18 8:58 ` [Qemu-riscv] [Qemu-devel] " Markus Armbruster
2019-03-18 9:55 ` Peter Maydell
2019-03-18 12:31 ` Markus Armbruster
2019-03-18 9:31 ` [Qemu-riscv] " Andrea Bolognani
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