Re: [PATCH 1/2] drm/i915: Move engine reset preparation to i915_gem_reset_prepare()

[Mika Kuoppala <mika.kuoppala@linux.intel.com>]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Now that we have prepare/finish routines for the GEM reset, move the
> disabling of the engine->irq_tasklet into them to reduce repetition. The
> device irq enable/disable is split out to ensure it is run first and
> last always (even if the GPU reset fails).
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>

As discussed briefly in irc, the disabling could be part of
reset and enabling part of init_hw, that way we could wedge
also with irq's off, even if it breaks the symmetry.

Regardless, this is an improvement.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 21 ++-------------------
>  drivers/gpu/drm/i915/i915_gem.c |  7 +++++++
>  2 files changed, 9 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 4e5ea5898e06..bb747aeb29aa 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1728,22 +1728,6 @@ static int i915_resume_switcheroo(struct drm_device *dev)
>  	return i915_drm_resume(dev);
>  }
>  
> -static void disable_engines_irq(struct drm_i915_private *dev_priv)
> -{
> -	struct intel_engine_cs *engine;
> -	enum intel_engine_id id;
> -
> -	/* Ensure irq handler finishes, and not run again. */
> -	disable_irq(dev_priv->drm.irq);
> -	for_each_engine(engine, dev_priv, id)
> -		tasklet_kill(&engine->irq_tasklet);
> -}
> -
> -static void enable_engines_irq(struct drm_i915_private *dev_priv)
> -{
> -	enable_irq(dev_priv->drm.irq);
> -}
> -
>  /**
>   * i915_reset - reset chip after a hang
>   * @dev_priv: device private to reset
> @@ -1776,12 +1760,10 @@ void i915_reset(struct drm_i915_private *dev_priv)
>  	error->reset_count++;
>  
>  	pr_notice("drm/i915: Resetting chip after gpu hang\n");
> +	disable_irq(dev_priv->drm.irq);
>  	i915_gem_reset_prepare(dev_priv);
>  
> -	disable_engines_irq(dev_priv);
>  	ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
> -	enable_engines_irq(dev_priv);
> -
>  	if (ret) {
>  		if (ret != -ENODEV)
>  			DRM_ERROR("Failed to reset chip: %i\n", ret);
> @@ -1816,6 +1798,7 @@ void i915_reset(struct drm_i915_private *dev_priv)
>  	i915_queue_hangcheck(dev_priv);
>  
>  wakeup:
> +	enable_irq(dev_priv->drm.irq);
>  	wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
>  	return;
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index d4c59b53532e..94450621e6cb 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2631,6 +2631,13 @@ static void reset_request(struct drm_i915_gem_request *request)
>  
>  void i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
>  {
> +	struct intel_engine_cs *engine;
> +	enum intel_engine_id id;
> +
> +	/* Ensure irq handler finishes, and not run again. */
> +	for_each_engine(engine, dev_priv, id)
> +		tasklet_kill(&engine->irq_tasklet);
> +
>  	i915_gem_revoke_fences(dev_priv);
>  }
>  
> -- 
> 2.11.0
>
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