From: Kevin Hilman <khilman@ti.com> To: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: linux-omap@vger.kernel.org, paul@pwsan.com, b-cousson@ti.com, rnayak@ti.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 2/6] omap4: prcm: Fix the CPUx clockdomain offsets Date: Tue, 01 Feb 2011 17:20:36 -0800 [thread overview] Message-ID: <87ipx3mduj.fsf@ti.com> (raw) In-Reply-To: <1296212688-21951-3-git-send-email-santosh.shilimkar@ti.com> (Santosh Shilimkar's message of "Fri, 28 Jan 2011 16:34:44 +0530") Santosh Shilimkar <santosh.shilimkar@ti.com> writes: > CPU0 and CPU1 clockdomain is at the offset of 0x18 from the LPRM base. > The header file has set it wrongly to 0x0. Offset 0x0 is for CPUx power > domain control register > > Fix the same. Has this also been updated in the autogen scripts? Benoit? Kevin > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > Cc: Paul Walmsley <paul@pwsan.com> > --- > arch/arm/mach-omap2/prcm_mpu44xx.h | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h > index 729a644..3300ff6 100644 > --- a/arch/arm/mach-omap2/prcm_mpu44xx.h > +++ b/arch/arm/mach-omap2/prcm_mpu44xx.h > @@ -38,8 +38,8 @@ > #define OMAP4430_PRCM_MPU_CPU1_INST 0x0800 > > /* PRCM_MPU clockdomain register offsets (from instance start) */ > -#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0000 > -#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0000 > +#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0018 > +#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0018 > > > /*
WARNING: multiple messages have this Message-ID (diff)
From: khilman@ti.com (Kevin Hilman) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/6] omap4: prcm: Fix the CPUx clockdomain offsets Date: Tue, 01 Feb 2011 17:20:36 -0800 [thread overview] Message-ID: <87ipx3mduj.fsf@ti.com> (raw) In-Reply-To: <1296212688-21951-3-git-send-email-santosh.shilimkar@ti.com> (Santosh Shilimkar's message of "Fri, 28 Jan 2011 16:34:44 +0530") Santosh Shilimkar <santosh.shilimkar@ti.com> writes: > CPU0 and CPU1 clockdomain is at the offset of 0x18 from the LPRM base. > The header file has set it wrongly to 0x0. Offset 0x0 is for CPUx power > domain control register > > Fix the same. Has this also been updated in the autogen scripts? Benoit? Kevin > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > Cc: Paul Walmsley <paul@pwsan.com> > --- > arch/arm/mach-omap2/prcm_mpu44xx.h | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h > index 729a644..3300ff6 100644 > --- a/arch/arm/mach-omap2/prcm_mpu44xx.h > +++ b/arch/arm/mach-omap2/prcm_mpu44xx.h > @@ -38,8 +38,8 @@ > #define OMAP4430_PRCM_MPU_CPU1_INST 0x0800 > > /* PRCM_MPU clockdomain register offsets (from instance start) */ > -#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0000 > -#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0000 > +#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0018 > +#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0018 > > > /*
next prev parent reply other threads:[~2011-02-02 1:20 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2011-01-28 11:04 [PATCH 0/6] omap4: prcm: Few dpll, clockdomain and powerdomain updates Santosh Shilimkar 2011-01-28 11:04 ` Santosh Shilimkar 2011-01-28 11:04 ` [PATCH 1/6] omap4: powerdomain: Add supported INACTIVE power state Santosh Shilimkar 2011-01-28 11:04 ` Santosh Shilimkar 2011-01-31 23:14 ` Paul Walmsley 2011-01-31 23:14 ` Paul Walmsley 2011-02-01 6:29 ` Santosh Shilimkar 2011-02-01 6:29 ` Santosh Shilimkar 2011-02-01 12:39 ` Cousson, Benoit 2011-02-01 12:39 ` Cousson, Benoit 2011-02-02 21:40 ` Paul Walmsley 2011-02-02 21:40 ` Paul Walmsley 2011-02-03 8:55 ` Santosh Shilimkar 2011-02-03 8:55 ` Santosh Shilimkar 2011-02-02 1:19 ` Kevin Hilman 2011-02-02 1:19 ` Kevin Hilman 2011-02-02 4:19 ` Rajendra Nayak 2011-02-02 4:19 ` Rajendra Nayak 2011-02-02 21:28 ` Kevin Hilman 2011-02-02 21:28 ` Kevin Hilman 2011-02-03 9:00 ` Santosh Shilimkar 2011-02-03 9:00 ` Santosh Shilimkar 2011-01-28 11:04 ` [PATCH 2/6] omap4: prcm: Fix the CPUx clockdomain offsets Santosh Shilimkar 2011-01-28 11:04 ` Santosh Shilimkar 2011-02-02 1:20 ` Kevin Hilman [this message] 2011-02-02 1:20 ` Kevin Hilman 2011-02-02 9:24 ` Cousson, Benoit 2011-02-02 9:24 ` Cousson, Benoit 2011-02-03 12:51 ` Cousson, Benoit 2011-02-03 12:51 ` Cousson, Benoit 2011-01-28 11:04 ` [PATCH 3/6] omap4: powerdomain: Use intended PWRSTS_* flags instead of values Santosh Shilimkar 2011-01-28 11:04 ` Santosh Shilimkar 2011-02-02 1:21 ` Kevin Hilman 2011-02-02 1:21 ` Kevin Hilman 2011-02-02 6:15 ` Santosh Shilimkar 2011-02-02 6:15 ` Santosh Shilimkar 2011-01-28 11:04 ` [PATCH 4/6] omap4: dpll: Enable all DPLL autoidle at boot Santosh Shilimkar 2011-01-28 11:04 ` Santosh Shilimkar 2011-01-31 23:17 ` Paul Walmsley 2011-01-31 23:17 ` Paul Walmsley 2011-02-01 5:24 ` Rajendra Nayak 2011-02-01 5:24 ` Rajendra Nayak 2011-01-28 11:04 ` [PATCH 5/6] omap4: dpll: Add dpll api to control GATE_CTRL Santosh Shilimkar 2011-01-28 11:04 ` Santosh Shilimkar 2011-01-28 11:04 ` [PATCH 6/6] omap4: dpll: Enable auto gate control for all MX postdividers Santosh Shilimkar 2011-01-28 11:04 ` Santosh Shilimkar 2011-01-28 12:37 ` [PATCH 0/6] omap4: prcm: Few dpll, clockdomain and powerdomain updates Santosh Shilimkar 2011-01-28 12:37 ` Santosh Shilimkar
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