From: Thomas Gleixner <tglx@linutronix.de>
To: Marcelo Tosatti <mtosatti@redhat.com>,
Nitesh Narayan Lal <nitesh@redhat.com>
Cc: Jacob Keller <jacob.e.keller@intel.com>,
Peter Zijlstra <peterz@infradead.org>,
helgaas@kernel.org, linux-kernel@vger.kernel.org,
netdev@vger.kernel.org, linux-pci@vger.kernel.org,
intel-wired-lan@lists.osuosl.org, frederic@kernel.org,
sassmann@redhat.com, jesse.brandeburg@intel.com,
lihong.yang@intel.com, jeffrey.t.kirsher@intel.com,
jlelli@redhat.com, hch@infradead.org, bhelgaas@google.com,
mike.marciniszyn@intel.com, dennis.dalessandro@intel.com,
thomas.lendacky@amd.com, jiri@nvidia.com, mingo@redhat.com,
juri.lelli@redhat.com, vincent.guittot@linaro.org,
lgoncalv@redhat.com, Jakub Kicinski <kuba@kernel.org>
Subject: Re: [PATCH v4 4/4] PCI: Limit pci_alloc_irq_vectors() to housekeeping CPUs
Date: Tue, 27 Oct 2020 15:43:56 +0100 [thread overview]
Message-ID: <87k0vb20gj.fsf@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20201027114739.GA11336@fuller.cnet>
On Tue, Oct 27 2020 at 08:47, Marcelo Tosatti wrote:
> On Mon, Oct 26, 2020 at 06:22:29PM -0400, Nitesh Narayan Lal wrote:
> However, if per-CPU interrupts are not disabled, then the (for example)
> network device is free to include the CPU in its list of destinations.
> Which would require one to say, configure RPS (or whatever mechanism
> is distributing interrupts).
And why is that a problem? If that's possible then you can prevent
getting RX interrupts already today.
> Hum, it would feel safer (rather than trust the #1 rule to be valid
> in all cases) to ask the driver to disable the interrupt (after shutting
> down queue) for that particular CPU.
>
> BTW, Thomas, software is free to configure a particular MSI-X interrupt
> to point to any CPU:
>
> 10.11 MESSAGE SIGNALLED INTERRUPTS
I know how MSI works :)
> So taking the example where computation happens while isolated and later
> stored via block interface, aren't we restricting the usage scenarios
> by enforcing the "per-CPU queue has interrupt pointing to owner CPU"
> rule?
No. For block this is the ideal configuration (think locality) and it
prevents vector exhaustion. If you make these interrupts freely routable
then you bring back the vector exhaustion problem right away.
Now we already established that networking has different requirements,
so you have to come up with a different solution for it which allows to
work for all use cases.
Thanks,
tglx
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de>
To: intel-wired-lan@osuosl.org
Subject: [Intel-wired-lan] [PATCH v4 4/4] PCI: Limit pci_alloc_irq_vectors() to housekeeping CPUs
Date: Tue, 27 Oct 2020 15:43:56 +0100 [thread overview]
Message-ID: <87k0vb20gj.fsf@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20201027114739.GA11336@fuller.cnet>
On Tue, Oct 27 2020 at 08:47, Marcelo Tosatti wrote:
> On Mon, Oct 26, 2020 at 06:22:29PM -0400, Nitesh Narayan Lal wrote:
> However, if per-CPU interrupts are not disabled, then the (for example)
> network device is free to include the CPU in its list of destinations.
> Which would require one to say, configure RPS (or whatever mechanism
> is distributing interrupts).
And why is that a problem? If that's possible then you can prevent
getting RX interrupts already today.
> Hum, it would feel safer (rather than trust the #1 rule to be valid
> in all cases) to ask the driver to disable the interrupt (after shutting
> down queue) for that particular CPU.
>
> BTW, Thomas, software is free to configure a particular MSI-X interrupt
> to point to any CPU:
>
> 10.11 MESSAGE SIGNALLED INTERRUPTS
I know how MSI works :)
> So taking the example where computation happens while isolated and later
> stored via block interface, aren't we restricting the usage scenarios
> by enforcing the "per-CPU queue has interrupt pointing to owner CPU"
> rule?
No. For block this is the ideal configuration (think locality) and it
prevents vector exhaustion. If you make these interrupts freely routable
then you bring back the vector exhaustion problem right away.
Now we already established that networking has different requirements,
so you have to come up with a different solution for it which allows to
work for all use cases.
Thanks,
tglx
next prev parent reply other threads:[~2020-10-27 15:00 UTC|newest]
Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-28 18:35 [PATCH v4 0/4] isolation: limit msix vectors to housekeeping CPUs Nitesh Narayan Lal
2020-09-28 18:35 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-09-28 18:35 ` [PATCH v4 1/4] sched/isolation: API to get number of " Nitesh Narayan Lal
2020-09-28 18:35 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-09-28 18:35 ` [PATCH v4 2/4] sched/isolation: Extend nohz_full to isolate managed IRQs Nitesh Narayan Lal
2020-09-28 18:35 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-10-23 13:25 ` Peter Zijlstra
2020-10-23 13:25 ` [Intel-wired-lan] " Peter Zijlstra
2020-10-23 13:29 ` Frederic Weisbecker
2020-10-23 13:29 ` [Intel-wired-lan] " Frederic Weisbecker
2020-10-23 13:57 ` Nitesh Narayan Lal
2020-10-23 13:57 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-10-23 13:45 ` Nitesh Narayan Lal
2020-10-23 13:45 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-09-28 18:35 ` [PATCH v4 3/4] i40e: Limit msix vectors to housekeeping CPUs Nitesh Narayan Lal
2020-09-28 18:35 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-09-28 18:35 ` [PATCH v4 4/4] PCI: Limit pci_alloc_irq_vectors() " Nitesh Narayan Lal
2020-09-28 18:35 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-09-28 21:59 ` Bjorn Helgaas
2020-09-28 21:59 ` [Intel-wired-lan] " Bjorn Helgaas
2020-09-29 17:46 ` Christoph Hellwig
2020-09-29 17:46 ` [Intel-wired-lan] " Christoph Hellwig
2020-10-16 12:20 ` Peter Zijlstra
2020-10-16 12:20 ` [Intel-wired-lan] " Peter Zijlstra
2020-10-18 18:14 ` Nitesh Narayan Lal
2020-10-18 18:14 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-10-19 11:11 ` Peter Zijlstra
2020-10-19 11:11 ` [Intel-wired-lan] " Peter Zijlstra
2020-10-19 14:00 ` Marcelo Tosatti
2020-10-19 14:00 ` [Intel-wired-lan] " Marcelo Tosatti
2020-10-19 14:25 ` Nitesh Narayan Lal
2020-10-19 14:25 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-10-20 7:30 ` Peter Zijlstra
2020-10-20 7:30 ` [Intel-wired-lan] " Peter Zijlstra
2020-10-20 13:00 ` Nitesh Narayan Lal
2020-10-20 13:00 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-10-20 13:41 ` Peter Zijlstra
2020-10-20 13:41 ` [Intel-wired-lan] " Peter Zijlstra
2020-10-20 14:39 ` Nitesh Narayan Lal
2020-10-20 14:39 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-10-22 17:47 ` Nitesh Narayan Lal
2020-10-22 17:47 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-10-23 8:58 ` Peter Zijlstra
2020-10-23 8:58 ` [Intel-wired-lan] " Peter Zijlstra
2020-10-23 13:10 ` Nitesh Narayan Lal
2020-10-23 13:10 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-10-23 21:00 ` Thomas Gleixner
2020-10-23 21:00 ` [Intel-wired-lan] " Thomas Gleixner
2020-10-26 13:35 ` Nitesh Narayan Lal
2020-10-26 13:35 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-10-26 13:57 ` Thomas Gleixner
2020-10-26 13:57 ` [Intel-wired-lan] " Thomas Gleixner
2020-10-26 17:30 ` Marcelo Tosatti
2020-10-26 17:30 ` [Intel-wired-lan] " Marcelo Tosatti
2020-10-26 19:00 ` Thomas Gleixner
2020-10-26 19:00 ` [Intel-wired-lan] " Thomas Gleixner
2020-10-26 19:11 ` Marcelo Tosatti
2020-10-26 19:11 ` [Intel-wired-lan] " Marcelo Tosatti
2020-10-26 19:21 ` Jacob Keller
2020-10-26 19:21 ` [Intel-wired-lan] " Jacob Keller
2020-10-26 20:11 ` Thomas Gleixner
2020-10-26 20:11 ` [Intel-wired-lan] " Thomas Gleixner
2020-10-26 21:11 ` Jacob Keller
2020-10-26 21:11 ` [Intel-wired-lan] " Jacob Keller
2020-10-26 21:50 ` Thomas Gleixner
2020-10-26 21:50 ` [Intel-wired-lan] " Thomas Gleixner
2020-10-26 22:13 ` Jakub Kicinski
2020-10-26 22:13 ` [Intel-wired-lan] " Jakub Kicinski
2020-10-26 22:46 ` Thomas Gleixner
2020-10-26 22:46 ` [Intel-wired-lan] " Thomas Gleixner
2020-10-26 22:52 ` Jacob Keller
2020-10-26 22:52 ` [Intel-wired-lan] " Jacob Keller
2020-10-26 22:22 ` Nitesh Narayan Lal
2020-10-26 22:22 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-10-26 22:49 ` Thomas Gleixner
2020-10-26 22:49 ` [Intel-wired-lan] " Thomas Gleixner
2020-10-26 23:08 ` Jacob Keller
2020-10-26 23:08 ` [Intel-wired-lan] " Jacob Keller
2020-10-27 14:28 ` Thomas Gleixner
2020-10-27 14:28 ` [Intel-wired-lan] " Thomas Gleixner
2020-10-27 11:47 ` Marcelo Tosatti
2020-10-27 11:47 ` [Intel-wired-lan] " Marcelo Tosatti
2020-10-27 14:43 ` Thomas Gleixner [this message]
2020-10-27 14:43 ` Thomas Gleixner
2020-10-19 14:21 ` Frederic Weisbecker
2020-10-19 14:21 ` [Intel-wired-lan] " Frederic Weisbecker
2020-10-20 14:16 ` Thomas Gleixner
2020-10-20 14:16 ` [Intel-wired-lan] " Thomas Gleixner
2020-10-20 16:18 ` Nitesh Narayan Lal
2020-10-20 16:18 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-10-20 18:07 ` Thomas Gleixner
2020-10-20 18:07 ` [Intel-wired-lan] " Thomas Gleixner
2020-10-21 20:25 ` Thomas Gleixner
2020-10-21 20:25 ` [Intel-wired-lan] " Thomas Gleixner
2020-10-21 21:04 ` Nitesh Narayan Lal
2020-10-21 21:04 ` [Intel-wired-lan] " Nitesh Narayan Lal
2020-10-22 0:02 ` Jakub Kicinski
2020-10-22 0:02 ` [Intel-wired-lan] " Jakub Kicinski
2020-10-22 0:27 ` Jacob Keller
2020-10-22 0:27 ` [Intel-wired-lan] " Jacob Keller
2020-10-22 8:28 ` Thomas Gleixner
2020-10-22 8:28 ` [Intel-wired-lan] " Thomas Gleixner
2020-10-22 12:28 ` Marcelo Tosatti
2020-10-22 12:28 ` [Intel-wired-lan] " Marcelo Tosatti
2020-10-22 22:39 ` Thomas Gleixner
2020-10-22 22:39 ` [Intel-wired-lan] " Thomas Gleixner
2020-10-01 15:49 ` [PATCH v4 0/4] isolation: limit msix vectors " Frederic Weisbecker
2020-10-01 15:49 ` [Intel-wired-lan] " Frederic Weisbecker
2020-10-08 21:40 ` Nitesh Narayan Lal
2020-10-08 21:40 ` [Intel-wired-lan] " Nitesh Narayan Lal
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