* [PATCH] drm/915: Parsing the missed out DTD fields from the VBT
@ 2016-12-22 18:07 Madhav Chauhan
2016-12-22 18:29 ` Ville Syrjälä
0 siblings, 1 reply; 5+ messages in thread
From: Madhav Chauhan @ 2016-12-22 18:07 UTC (permalink / raw)
To: intel-gfx
Cc: ander.conselvan.de.oliveira, jani.nikula, shobhit.kumar, Vincente Tsou
From: Vincente Tsou <vincente.tsou@intel.com>
The upper bits of the vsync width, vsync offset and hsync width
were not parsed form the VBT. Parse these fields in this patch.
V2: Renamed lvds dvo timing structure members and code identation
fix (Jani's review comments)
Signed-off-by: Vincente Tsou <vincente.tsou@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/intel_bios.c | 8 +++++---
drivers/gpu/drm/i915/intel_vbt_defs.h | 12 +++++++-----
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index a359def..f6d3755 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -114,16 +114,18 @@ static u32 get_blocksize(const void *block_data)
panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
- dvo_timing->hsync_pulse_width;
+ ((dvo_timing->hsync_pulse_width_hi << 8) |
+ dvo_timing->hsync_pulse_width_lo);
panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
dvo_timing->vactive_lo;
panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
- dvo_timing->vsync_off;
+ ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo);
panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
- dvo_timing->vsync_pulse_width;
+ ((dvo_timing->vsync_pulse_width_hi << 4) |
+ dvo_timing->vsync_pulse_width_lo);
panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
panel_fixed_mode->clock = dvo_timing->clock * 10;
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
index 8886cab1..a92e776 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -399,10 +399,12 @@ struct lvds_dvo_timing {
u8 vblank_hi:4;
u8 vactive_hi:4;
u8 hsync_off_lo;
- u8 hsync_pulse_width;
- u8 vsync_pulse_width:4;
- u8 vsync_off:4;
- u8 rsvd0:6;
+ u8 hsync_pulse_width_lo;
+ u8 vsync_pulse_width_lo:4;
+ u8 vsync_off_lo:4;
+ u8 vsync_pulse_width_hi:2;
+ u8 vsync_off_hi:2;
+ u8 hsync_pulse_width_hi:2;
u8 hsync_off_hi:2;
u8 himage_lo;
u8 vimage_lo;
@@ -414,7 +416,7 @@ struct lvds_dvo_timing {
u8 digital:2;
u8 vsync_positive:1;
u8 hsync_positive:1;
- u8 rsvd2:1;
+ u8 non_interlaced:1;
} __packed;
struct lvds_pnp_id {
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/915: Parsing the missed out DTD fields from the VBT
2016-12-22 18:07 [PATCH] drm/915: Parsing the missed out DTD fields from the VBT Madhav Chauhan
@ 2016-12-22 18:29 ` Ville Syrjälä
2016-12-23 7:03 ` Jani Nikula
0 siblings, 1 reply; 5+ messages in thread
From: Ville Syrjälä @ 2016-12-22 18:29 UTC (permalink / raw)
To: Madhav Chauhan
Cc: jani.nikula, ander.conselvan.de.oliveira, intel-gfx,
Vincente Tsou, shobhit.kumar
On Thu, Dec 22, 2016 at 01:07:44PM -0500, Madhav Chauhan wrote:
> From: Vincente Tsou <vincente.tsou@intel.com>
>
> The upper bits of the vsync width, vsync offset and hsync width
> were not parsed form the VBT. Parse these fields in this patch.
>
> V2: Renamed lvds dvo timing structure members and code identation
> fix (Jani's review comments)
>
> Signed-off-by: Vincente Tsou <vincente.tsou@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_bios.c | 8 +++++---
> drivers/gpu/drm/i915/intel_vbt_defs.h | 12 +++++++-----
> 2 files changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index a359def..f6d3755 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -114,16 +114,18 @@ static u32 get_blocksize(const void *block_data)
> panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
> ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
> panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
> - dvo_timing->hsync_pulse_width;
> + ((dvo_timing->hsync_pulse_width_hi << 8) |
> + dvo_timing->hsync_pulse_width_lo);
> panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
> ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
>
> panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
> dvo_timing->vactive_lo;
> panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
> - dvo_timing->vsync_off;
> + ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo);
> panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
> - dvo_timing->vsync_pulse_width;
> + ((dvo_timing->vsync_pulse_width_hi << 4) |
> + dvo_timing->vsync_pulse_width_lo);
> panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
> ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
> panel_fixed_mode->clock = dvo_timing->clock * 10;
> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
> index 8886cab1..a92e776 100644
> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
> @@ -399,10 +399,12 @@ struct lvds_dvo_timing {
> u8 vblank_hi:4;
> u8 vactive_hi:4;
> u8 hsync_off_lo;
> - u8 hsync_pulse_width;
> - u8 vsync_pulse_width:4;
> - u8 vsync_off:4;
> - u8 rsvd0:6;
> + u8 hsync_pulse_width_lo;
> + u8 vsync_pulse_width_lo:4;
> + u8 vsync_off_lo:4;
> + u8 vsync_pulse_width_hi:2;
> + u8 vsync_off_hi:2;
> + u8 hsync_pulse_width_hi:2;
Last time I looked at this I decided that we had at least two
definitions for this thing in our code. But maybe that was just on the
igt side because I can't find it in the kernel right now.
Oh, and in igt someone has also realized that this stuff matches the
EDID DTD as well, and so we sometimes parse it using some EDIDy macros
instead. So three ways to do it in igt, at least one in the kernel (and
a second one if you count the EDID parser). It might make sense to
clean it all up somehow.
> u8 hsync_off_hi:2;
> u8 himage_lo;
> u8 vimage_lo;
> @@ -414,7 +416,7 @@ struct lvds_dvo_timing {
> u8 digital:2;
> u8 vsync_positive:1;
> u8 hsync_positive:1;
> - u8 rsvd2:1;
> + u8 non_interlaced:1;
> } __packed;
>
> struct lvds_pnp_id {
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/915: Parsing the missed out DTD fields from the VBT
2016-12-22 18:29 ` Ville Syrjälä
@ 2016-12-23 7:03 ` Jani Nikula
0 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2016-12-23 7:03 UTC (permalink / raw)
To: Ville Syrjälä, Madhav Chauhan
Cc: ander.conselvan.de.oliveira, intel-gfx, Vincente Tsou, shobhit.kumar
On Thu, 22 Dec 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Dec 22, 2016 at 01:07:44PM -0500, Madhav Chauhan wrote:
>> From: Vincente Tsou <vincente.tsou@intel.com>
>>
>> The upper bits of the vsync width, vsync offset and hsync width
>> were not parsed form the VBT. Parse these fields in this patch.
>>
>> V2: Renamed lvds dvo timing structure members and code identation
>> fix (Jani's review comments)
>>
>> Signed-off-by: Vincente Tsou <vincente.tsou@intel.com>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_bios.c | 8 +++++---
>> drivers/gpu/drm/i915/intel_vbt_defs.h | 12 +++++++-----
>> 2 files changed, 12 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>> index a359def..f6d3755 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -114,16 +114,18 @@ static u32 get_blocksize(const void *block_data)
>> panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
>> ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
>> panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
>> - dvo_timing->hsync_pulse_width;
>> + ((dvo_timing->hsync_pulse_width_hi << 8) |
>> + dvo_timing->hsync_pulse_width_lo);
>> panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
>> ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
>>
>> panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
>> dvo_timing->vactive_lo;
>> panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
>> - dvo_timing->vsync_off;
>> + ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo);
>> panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
>> - dvo_timing->vsync_pulse_width;
>> + ((dvo_timing->vsync_pulse_width_hi << 4) |
>> + dvo_timing->vsync_pulse_width_lo);
>> panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
>> ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
>> panel_fixed_mode->clock = dvo_timing->clock * 10;
>> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
>> index 8886cab1..a92e776 100644
>> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
>> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
>> @@ -399,10 +399,12 @@ struct lvds_dvo_timing {
>> u8 vblank_hi:4;
>> u8 vactive_hi:4;
>> u8 hsync_off_lo;
>> - u8 hsync_pulse_width;
>> - u8 vsync_pulse_width:4;
>> - u8 vsync_off:4;
>> - u8 rsvd0:6;
>> + u8 hsync_pulse_width_lo;
>> + u8 vsync_pulse_width_lo:4;
>> + u8 vsync_off_lo:4;
>> + u8 vsync_pulse_width_hi:2;
>> + u8 vsync_off_hi:2;
>> + u8 hsync_pulse_width_hi:2;
>
> Last time I looked at this I decided that we had at least two
> definitions for this thing in our code. But maybe that was just on the
> igt side because I can't find it in the kernel right now.
>
> Oh, and in igt someone has also realized that this stuff matches the
> EDID DTD as well, and so we sometimes parse it using some EDIDy macros
> instead. So three ways to do it in igt, at least one in the kernel (and
> a second one if you count the EDID parser). It might make sense to
> clean it all up somehow.
Agreed, but this is a worthwhile addition to the kernel right now.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>> u8 hsync_off_hi:2;
>> u8 himage_lo;
>> u8 vimage_lo;
>> @@ -414,7 +416,7 @@ struct lvds_dvo_timing {
>> u8 digital:2;
>> u8 vsync_positive:1;
>> u8 hsync_positive:1;
>> - u8 rsvd2:1;
>> + u8 non_interlaced:1;
>> } __packed;
>>
>> struct lvds_pnp_id {
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/915: Parsing the missed out DTD fields from the VBT
2016-12-22 18:23 Madhav Chauhan
@ 2016-12-23 13:16 ` Jani Nikula
0 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2016-12-23 13:16 UTC (permalink / raw)
To: Madhav Chauhan, intel-gfx
Cc: ander.conselvan.de.oliveira, Vincente Tsou, shobhit.kumar
On Thu, 22 Dec 2016, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Vincente Tsou <vincente.tsou@intel.com>
>
> The upper bits of the vsync width, vsync offset and hsync width
> were not parsed from the VBT. Parse these fields in this patch.
>
> V2: Renamed lvds dvo timing structure members and code identation
> fix (Jani's review comments)
> V3: Corrected commit message, used "from the VBT"
>
> Signed-off-by: Vincente Tsou <vincente.tsou@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Pushed to dinq, thanks for the patch.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_bios.c | 8 +++++---
> drivers/gpu/drm/i915/intel_vbt_defs.h | 12 +++++++-----
> 2 files changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index a359def..f6d3755 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -114,16 +114,18 @@ static u32 get_blocksize(const void *block_data)
> panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
> ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
> panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
> - dvo_timing->hsync_pulse_width;
> + ((dvo_timing->hsync_pulse_width_hi << 8) |
> + dvo_timing->hsync_pulse_width_lo);
> panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
> ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
>
> panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
> dvo_timing->vactive_lo;
> panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
> - dvo_timing->vsync_off;
> + ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo);
> panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
> - dvo_timing->vsync_pulse_width;
> + ((dvo_timing->vsync_pulse_width_hi << 4) |
> + dvo_timing->vsync_pulse_width_lo);
> panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
> ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
> panel_fixed_mode->clock = dvo_timing->clock * 10;
> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
> index 8886cab1..a92e776 100644
> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
> @@ -399,10 +399,12 @@ struct lvds_dvo_timing {
> u8 vblank_hi:4;
> u8 vactive_hi:4;
> u8 hsync_off_lo;
> - u8 hsync_pulse_width;
> - u8 vsync_pulse_width:4;
> - u8 vsync_off:4;
> - u8 rsvd0:6;
> + u8 hsync_pulse_width_lo;
> + u8 vsync_pulse_width_lo:4;
> + u8 vsync_off_lo:4;
> + u8 vsync_pulse_width_hi:2;
> + u8 vsync_off_hi:2;
> + u8 hsync_pulse_width_hi:2;
> u8 hsync_off_hi:2;
> u8 himage_lo;
> u8 vimage_lo;
> @@ -414,7 +416,7 @@ struct lvds_dvo_timing {
> u8 digital:2;
> u8 vsync_positive:1;
> u8 hsync_positive:1;
> - u8 rsvd2:1;
> + u8 non_interlaced:1;
> } __packed;
>
> struct lvds_pnp_id {
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] drm/915: Parsing the missed out DTD fields from the VBT
@ 2016-12-22 18:23 Madhav Chauhan
2016-12-23 13:16 ` Jani Nikula
0 siblings, 1 reply; 5+ messages in thread
From: Madhav Chauhan @ 2016-12-22 18:23 UTC (permalink / raw)
To: intel-gfx
Cc: ander.conselvan.de.oliveira, jani.nikula, shobhit.kumar, Vincente Tsou
From: Vincente Tsou <vincente.tsou@intel.com>
The upper bits of the vsync width, vsync offset and hsync width
were not parsed from the VBT. Parse these fields in this patch.
V2: Renamed lvds dvo timing structure members and code identation
fix (Jani's review comments)
V3: Corrected commit message, used "from the VBT"
Signed-off-by: Vincente Tsou <vincente.tsou@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/intel_bios.c | 8 +++++---
drivers/gpu/drm/i915/intel_vbt_defs.h | 12 +++++++-----
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index a359def..f6d3755 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -114,16 +114,18 @@ static u32 get_blocksize(const void *block_data)
panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
- dvo_timing->hsync_pulse_width;
+ ((dvo_timing->hsync_pulse_width_hi << 8) |
+ dvo_timing->hsync_pulse_width_lo);
panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
dvo_timing->vactive_lo;
panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
- dvo_timing->vsync_off;
+ ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo);
panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
- dvo_timing->vsync_pulse_width;
+ ((dvo_timing->vsync_pulse_width_hi << 4) |
+ dvo_timing->vsync_pulse_width_lo);
panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
panel_fixed_mode->clock = dvo_timing->clock * 10;
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
index 8886cab1..a92e776 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -399,10 +399,12 @@ struct lvds_dvo_timing {
u8 vblank_hi:4;
u8 vactive_hi:4;
u8 hsync_off_lo;
- u8 hsync_pulse_width;
- u8 vsync_pulse_width:4;
- u8 vsync_off:4;
- u8 rsvd0:6;
+ u8 hsync_pulse_width_lo;
+ u8 vsync_pulse_width_lo:4;
+ u8 vsync_off_lo:4;
+ u8 vsync_pulse_width_hi:2;
+ u8 vsync_off_hi:2;
+ u8 hsync_pulse_width_hi:2;
u8 hsync_off_hi:2;
u8 himage_lo;
u8 vimage_lo;
@@ -414,7 +416,7 @@ struct lvds_dvo_timing {
u8 digital:2;
u8 vsync_positive:1;
u8 hsync_positive:1;
- u8 rsvd2:1;
+ u8 non_interlaced:1;
} __packed;
struct lvds_pnp_id {
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-12-23 13:16 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-12-22 18:07 [PATCH] drm/915: Parsing the missed out DTD fields from the VBT Madhav Chauhan
2016-12-22 18:29 ` Ville Syrjälä
2016-12-23 7:03 ` Jani Nikula
2016-12-22 18:23 Madhav Chauhan
2016-12-23 13:16 ` Jani Nikula
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