From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 4/7] target-arm: Update arm_generate_debug_exceptions() to handle EL2/EL3
Date: Fri, 05 Feb 2016 14:09:03 +0000 [thread overview]
Message-ID: <87k2mjnta8.fsf@linaro.org> (raw)
In-Reply-To: <1454506721-11843-5-git-send-email-peter.maydell@linaro.org>
Peter Maydell <peter.maydell@linaro.org> writes:
> The arm_generate_debug_exceptions() function as originally implemented
> assumes no EL2 or EL3. Since we now have much more of an implementation
> of those now, fix this assumption.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/cpu.h | 48 +++++++++++++++++++++++++++++++++++++++++++-----
> 1 file changed, 43 insertions(+), 5 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index cf2df50..0fb79d0 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -1742,9 +1742,7 @@ typedef enum ARMASIdx {
> ARMASIdx_S = 1,
> } ARMASIdx;
>
> -/* Return the Exception Level targeted by debug exceptions;
> - * currently always EL1 since we don't implement EL2 or EL3.
> - */
> +/* Return the Exception Level targeted by debug exceptions. */
> static inline int arm_debug_target_el(CPUARMState *env)
> {
> bool secure = arm_is_secure(env);
> @@ -1767,6 +1765,14 @@ static inline int arm_debug_target_el(CPUARMState *env)
>
> static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
> {
> + if (arm_is_secure(env)) {
> + /* MDCR_EL3.SDD disables debug events from Secure state */
Is it worth commenting that BRK still works?
> + if (extract32(env->cp15.mdcr_el3,ctct 16, 1) != 0
The != 0 is superfluous here.
> + || arm_current_el(env) == 3) {
> + return false;
> + }
> + }
> +
> if (arm_current_el(env) == arm_debug_target_el(env)) {
> if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
> || (env->daif & PSTATE_D)) {
> @@ -1778,10 +1784,42 @@ static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
>
> static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
> {
> - if (arm_current_el(env) == 0 && arm_el_is_aa64(env, 1)) {
> + int el = arm_current_el(env);
> +
> + if (el == 0 && arm_el_is_aa64(env, 1)) {
> return aa64_generate_debug_exceptions(env);
> }
> - return arm_current_el(env) != 2;
> +
> + if (arm_is_secure(env)) {
> + int spd;
> +
> + if (el == 0 && (env->cp15.sder & 1)) {
> + /* SDER.SUIDEN means debug exceptions from Secure EL0
> + * are always enabled. Otherwise they are controlled by
> + * SDCR.SPD like those from other Secure ELs.
> + */
> + return true;
> + }
> +
> + spd = extract32(env->cp15.mdcr_el3, 14, 2);
> + switch (spd) {
> + case 1:
> + /* SPD == 0b01 is reserved, but behaves as 0b00. */
> + case 0:
> + /* For 0b00 we return true if external secure invasive debug
> + * is enabled. On real hardware this is controlled by external
> + * signals to the core. QEMU always permits debug, and behaves
> + * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
> + */
> + return true;
> + case 2:
> + return false;
> + case 3:
> + return true;
> + }
> + }
> +
> + return el != 2;
> }
>
> /* Return true if debugging exceptions are currently enabled.
Otherwise:
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
next prev parent reply other threads:[~2016-02-05 14:09 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-03 13:38 [Qemu-devel] [PATCH 0/7] Fix some more EL3 things and enable EL3 for AArch64 Peter Maydell
2016-02-03 13:38 ` [Qemu-devel] [PATCH 1/7] target-arm: Fix typo in comment in arm_is_secure_below_el3() Peter Maydell
2016-02-05 9:52 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2016-02-06 11:49 ` [Qemu-devel] " Edgar E. Iglesias
2016-02-06 18:24 ` [Qemu-devel] [Qemu-arm] " Sergey Fedorov
2016-02-03 13:38 ` [Qemu-devel] [PATCH 2/7] target-arm: Implement MDCR_EL3 and SDCR Peter Maydell
2016-02-05 11:13 ` Alex Bennée
2016-02-05 11:28 ` Peter Maydell
2016-02-06 12:04 ` Edgar E. Iglesias
2016-02-06 18:42 ` Sergey Fedorov
2016-02-08 13:11 ` Peter Maydell
2016-02-03 13:38 ` [Qemu-devel] [PATCH 3/7] target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR Peter Maydell
2016-02-05 13:43 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2016-02-06 12:17 ` [Qemu-devel] " Edgar E. Iglesias
2016-02-06 13:48 ` Peter Maydell
2016-02-06 16:03 ` Edgar E. Iglesias
2016-02-06 16:10 ` Edgar E. Iglesias
2016-02-03 13:38 ` [Qemu-devel] [PATCH 4/7] target-arm: Update arm_generate_debug_exceptions() to handle EL2/EL3 Peter Maydell
2016-02-05 14:09 ` Alex Bennée [this message]
2016-02-05 15:55 ` Peter Maydell
2016-02-06 18:43 ` Sergey Fedorov
2016-02-03 13:38 ` [Qemu-devel] [PATCH 5/7] target-arm: Add isread parameter to CPAccessFns Peter Maydell
2016-02-05 14:20 ` Alex Bennée
2016-02-05 14:29 ` Peter Maydell
2016-02-05 16:17 ` Alex Bennée
2016-02-05 16:27 ` Peter Maydell
2016-02-05 16:43 ` Alex Bennée
2016-02-06 16:16 ` Edgar E. Iglesias
2016-02-06 18:52 ` Sergey Fedorov
2016-02-03 13:38 ` [Qemu-devel] [PATCH 6/7] target-arm: Implement NSACR trapping behaviour Peter Maydell
2016-02-05 16:07 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2016-02-05 16:22 ` Peter Maydell
2016-02-06 16:42 ` [Qemu-devel] " Edgar E. Iglesias
2016-02-03 13:38 ` [Qemu-devel] [PATCH 7/7] target-arm: Enable EL3 for Cortex-A53 and Cortex-A57 Peter Maydell
2016-02-05 16:08 ` Alex Bennée
2016-02-06 16:43 ` Edgar E. Iglesias
2016-02-06 18:55 ` Sergey Fedorov
2016-02-08 13:18 ` [Qemu-devel] [Qemu-arm] [PATCH 0/7] Fix some more EL3 things and enable EL3 for AArch64 Peter Maydell
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