* [PATCH 1/2] drm/i915/skl: Don't skip mst encoders in skl_ddi_pll_select()
@ 2016-02-02 14:35 ` Lyude
0 siblings, 0 replies; 10+ messages in thread
From: Lyude @ 2016-02-02 14:35 UTC (permalink / raw)
To: Daniel Vetter, Jani Nikula, intel-gfx, dri-devel, linux-kernel,
David Airlie
Cc: Rob Clark, Adam Jackson, Lyude
We don't actually check for INTEL_OUTPUT_DP_MST at all in here, as a
result we skip assigning a DPLL to any DP MST ports, which makes link
training fail, after which things just keep going downhill from there.
Consequently, this fixes DisplayPort MST causing kernel panics, machine
check errors, etc. on Skylake.
Signed-off-by: Lyude <cpaul@redhat.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e6408e5..54a165b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1589,7 +1589,8 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
wrpll_params.central_freq;
- } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
+ } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
+ intel_encoder->type == INTEL_OUTPUT_DP_MST) {
switch (crtc_state->port_clock / 2) {
case 81000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
--
2.5.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 1/2] drm/i915/skl: Don't skip mst encoders in skl_ddi_pll_select()
@ 2016-02-02 14:35 ` Lyude
0 siblings, 0 replies; 10+ messages in thread
From: Lyude @ 2016-02-02 14:35 UTC (permalink / raw)
To: Daniel Vetter, Jani Nikula, intel-gfx, dri-devel, linux-kernel,
David Airlie
Cc: Lyude, Rob Clark, Adam Jackson
We don't actually check for INTEL_OUTPUT_DP_MST at all in here, as a
result we skip assigning a DPLL to any DP MST ports, which makes link
training fail, after which things just keep going downhill from there.
Consequently, this fixes DisplayPort MST causing kernel panics, machine
check errors, etc. on Skylake.
Signed-off-by: Lyude <cpaul@redhat.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e6408e5..54a165b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1589,7 +1589,8 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
wrpll_params.central_freq;
- } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
+ } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
+ intel_encoder->type == INTEL_OUTPUT_DP_MST) {
switch (crtc_state->port_clock / 2) {
case 81000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] drm/i915/skl: Explicitly check for eDP in skl_ddi_pll_select()
2016-02-02 14:35 ` Lyude
@ 2016-02-02 14:35 ` Lyude
-1 siblings, 0 replies; 10+ messages in thread
From: Lyude @ 2016-02-02 14:35 UTC (permalink / raw)
To: Daniel Vetter, Jani Nikula, intel-gfx, dri-devel, linux-kernel,
David Airlie
Cc: Rob Clark, Adam Jackson, Lyude
Assuming any connector that isn't DP, MST, or HDMI is eDP definitely
seems likely to cover up other bugs in the future.
Signed-off-by: Lyude <cpaul@redhat.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 54a165b..e2adc380 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1604,8 +1604,10 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
}
cfgcr1 = cfgcr2 = 0;
- } else /* eDP */
+ } else if (intel_encoder->type == INTEL_OUTPUT_EDP) {
return true;
+ } else
+ return false;
memset(&crtc_state->dpll_hw_state, 0,
sizeof(crtc_state->dpll_hw_state));
--
2.5.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] drm/i915/skl: Explicitly check for eDP in skl_ddi_pll_select()
@ 2016-02-02 14:35 ` Lyude
0 siblings, 0 replies; 10+ messages in thread
From: Lyude @ 2016-02-02 14:35 UTC (permalink / raw)
To: Daniel Vetter, Jani Nikula, intel-gfx, dri-devel, linux-kernel,
David Airlie
Cc: Lyude, Rob Clark, Adam Jackson
Assuming any connector that isn't DP, MST, or HDMI is eDP definitely
seems likely to cover up other bugs in the future.
Signed-off-by: Lyude <cpaul@redhat.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 54a165b..e2adc380 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1604,8 +1604,10 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
}
cfgcr1 = cfgcr2 = 0;
- } else /* eDP */
+ } else if (intel_encoder->type == INTEL_OUTPUT_EDP) {
return true;
+ } else
+ return false;
memset(&crtc_state->dpll_hw_state, 0,
sizeof(crtc_state->dpll_hw_state));
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915/skl: Don't skip mst encoders in skl_ddi_pll_select()
2016-02-02 14:35 ` Lyude
@ 2016-02-02 15:15 ` Jani Nikula
-1 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2016-02-02 15:15 UTC (permalink / raw)
To: Lyude, Daniel Vetter, intel-gfx, dri-devel, linux-kernel, David Airlie
Cc: Rob Clark, Adam Jackson, Lyude
On Tue, 02 Feb 2016, Lyude <cpaul@redhat.com> wrote:
> We don't actually check for INTEL_OUTPUT_DP_MST at all in here, as a
> result we skip assigning a DPLL to any DP MST ports, which makes link
> training fail, after which things just keep going downhill from there.
Apparently broken since
commit 82d35437018950c25200051733fb2fbf63cca86c
Author: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Date: Thu Nov 13 14:55:20 2014 +0000
drm/i915/skl: Implementation of SKL DPLL programming
> Consequently, this fixes DisplayPort MST causing kernel panics, machine
> check errors, etc. on Skylake.
Please copy-paste some traces for the commit message so it'll be easier
to match bug reports and fixes later on.
BR,
Jani.
>
> Signed-off-by: Lyude <cpaul@redhat.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index e6408e5..54a165b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1589,7 +1589,8 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
> DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
> DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
> wrpll_params.central_freq;
> - } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
> + } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
> + intel_encoder->type == INTEL_OUTPUT_DP_MST) {
> switch (crtc_state->port_clock / 2) {
> case 81000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915/skl: Don't skip mst encoders in skl_ddi_pll_select()
@ 2016-02-02 15:15 ` Jani Nikula
0 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2016-02-02 15:15 UTC (permalink / raw)
To: Daniel Vetter, intel-gfx, dri-devel, linux-kernel, David Airlie
Cc: Lyude, Rob Clark
On Tue, 02 Feb 2016, Lyude <cpaul@redhat.com> wrote:
> We don't actually check for INTEL_OUTPUT_DP_MST at all in here, as a
> result we skip assigning a DPLL to any DP MST ports, which makes link
> training fail, after which things just keep going downhill from there.
Apparently broken since
commit 82d35437018950c25200051733fb2fbf63cca86c
Author: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Date: Thu Nov 13 14:55:20 2014 +0000
drm/i915/skl: Implementation of SKL DPLL programming
> Consequently, this fixes DisplayPort MST causing kernel panics, machine
> check errors, etc. on Skylake.
Please copy-paste some traces for the commit message so it'll be easier
to match bug reports and fixes later on.
BR,
Jani.
>
> Signed-off-by: Lyude <cpaul@redhat.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index e6408e5..54a165b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1589,7 +1589,8 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
> DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
> DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
> wrpll_params.central_freq;
> - } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
> + } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
> + intel_encoder->type == INTEL_OUTPUT_DP_MST) {
> switch (crtc_state->port_clock / 2) {
> case 81000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 1/2] drm/i915/skl: Don't skip mst encoders in skl_ddi_pll_select()
2016-02-02 15:15 ` Jani Nikula
@ 2016-02-02 15:49 ` Lyude
-1 siblings, 0 replies; 10+ messages in thread
From: Lyude @ 2016-02-02 15:49 UTC (permalink / raw)
To: Daniel Vetter, Jani Nikula, intel-gfx, dri-devel, linux-kernel,
David Airlie
Cc: Rob Clark, Adam Jackson, Lyude
We don't actually check for INTEL_OUTPUT_DP_MST at all in here, as a
result we skip assigning a DPLL to any DP MST ports, which makes link
training fail:
[ 1442.933896] [drm:intel_power_well_enable] enabling DDI D power well
[ 1442.933905] [drm:skl_set_power_well] Enabling DDI D power well
[ 1442.933957] [drm:intel_mst_pre_enable_dp] 0
[ 1442.935474] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
[ 1442.935477] [drm:intel_dp_set_signal_levels] Using vswing level 0
[ 1442.935480] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
[ 1442.936190] [drm:intel_dp_set_signal_levels] Using signal levels 05000000
[ 1442.936193] [drm:intel_dp_set_signal_levels] Using vswing level 1
[ 1442.936195] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
[ 1442.936858] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
[ 1442.936862] [drm:intel_dp_set_signal_levels] Using vswing level 2
…
[ 1442.998253] [drm:intel_dp_link_training_clock_recovery [i915]] *ERROR* too many full retries, give up
[ 1442.998512] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to train DP, aborting
After which the pipe state goes completely out of sync:
[ 70.075596] [drm:check_crtc_state] [CRTC:25]
[ 70.075696] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in ddi_pll_sel (expected 0x00000000, found 0x00000001)
[ 70.075747] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in shared_dpll (expected -1, found 0)
[ 70.075798] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.ctrl1 (expected 0x00000000, found 0x00000021)
[ 70.075840] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr1 (expected 0x00000000, found 0x80400173)
[ 70.075884] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr2 (expected 0x00000000, found 0x000003a5)
[ 70.075954] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 262750, found 72256)
[ 70.075999] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in port_clock (expected 540000, found 148500)
And if you're especially lucky, it keeps going downhill:
[ 83.309256] Kernel panic - not syncing: Timeout: Not all CPUs entered broadcast exception handler
[ 83.309265]
[ 83.309265] =================================
[ 83.309266] [ INFO: inconsistent lock state ]
[ 83.309267] 4.5.0-rc1Lyude-Test #265 Not tainted
[ 83.309267] ---------------------------------
[ 83.309268] inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage.
[ 83.309270] Xorg/1194 [HC0[1]:SC0[0]:HE1:SE1] takes:
[ 83.309293] (&(&dev_priv->uncore.lock)->rlock){?.-...}, at: [<ffffffffa02a6073>] gen9_write32+0x63/0x400 [i915]
[ 83.309293] {IN-HARDIRQ-W} state was registered at:
[ 83.309297] [<ffffffff810e84f4>] __lock_acquire+0x9c4/0x1d00
[ 83.309299] [<ffffffff810ea1be>] lock_acquire+0xce/0x1c0
[ 83.309302] [<ffffffff8177d936>] _raw_spin_lock_irqsave+0x56/0x90
[ 83.309321] [<ffffffffa02a5492>] gen9_read32+0x52/0x3d0 [i915]
[ 83.309332] [<ffffffffa024beea>] gen8_irq_handler+0x27a/0x6a0 [i915]
[ 83.309337] [<ffffffff810fdbc1>] handle_irq_event_percpu+0x41/0x300
[ 83.309339] [<ffffffff810fdeb9>] handle_irq_event+0x39/0x60
[ 83.309341] [<ffffffff811010b4>] handle_edge_irq+0x74/0x130
[ 83.309344] [<ffffffff81009073>] handle_irq+0x73/0x120
[ 83.309346] [<ffffffff817805f1>] do_IRQ+0x61/0x120
[ 83.309348] [<ffffffff8177e6d6>] ret_from_intr+0x0/0x20
[ 83.309351] [<ffffffff815f5105>] cpuidle_enter_state+0x105/0x330
[ 83.309353] [<ffffffff815f5367>] cpuidle_enter+0x17/0x20
[ 83.309356] [<ffffffff810dbe1a>] call_cpuidle+0x2a/0x50
[ 83.309358] [<ffffffff810dc1dd>] cpu_startup_entry+0x26d/0x3a0
[ 83.309360] [<ffffffff817701da>] rest_init+0x13a/0x140
[ 83.309363] [<ffffffff81f2af8e>] start_kernel+0x475/0x482
[ 83.309365] [<ffffffff81f2a315>] x86_64_start_reservations+0x2a/0x2c
[ 83.309367] [<ffffffff81f2a452>] x86_64_start_kernel+0x13b/0x14a
Fixes: 82d354370189 ("drm/i915/skl: Implementation of SKL DPLL programming")
Signed-off-by: Lyude <cpaul@redhat.com>
---
Changes
* Add "Fixes" line with link to commit that introduced this problem
* Add some stack traces to aid in future debugging and fixes
drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e6408e5..54a165b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1589,7 +1589,8 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
wrpll_params.central_freq;
- } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
+ } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
+ intel_encoder->type == INTEL_OUTPUT_DP_MST) {
switch (crtc_state->port_clock / 2) {
case 81000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
--
2.5.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 1/2] drm/i915/skl: Don't skip mst encoders in skl_ddi_pll_select()
@ 2016-02-02 15:49 ` Lyude
0 siblings, 0 replies; 10+ messages in thread
From: Lyude @ 2016-02-02 15:49 UTC (permalink / raw)
To: Daniel Vetter, Jani Nikula, intel-gfx, dri-devel, linux-kernel,
David Airlie
Cc: Lyude, Rob Clark
We don't actually check for INTEL_OUTPUT_DP_MST at all in here, as a
result we skip assigning a DPLL to any DP MST ports, which makes link
training fail:
[ 1442.933896] [drm:intel_power_well_enable] enabling DDI D power well
[ 1442.933905] [drm:skl_set_power_well] Enabling DDI D power well
[ 1442.933957] [drm:intel_mst_pre_enable_dp] 0
[ 1442.935474] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
[ 1442.935477] [drm:intel_dp_set_signal_levels] Using vswing level 0
[ 1442.935480] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
[ 1442.936190] [drm:intel_dp_set_signal_levels] Using signal levels 05000000
[ 1442.936193] [drm:intel_dp_set_signal_levels] Using vswing level 1
[ 1442.936195] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
[ 1442.936858] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
[ 1442.936862] [drm:intel_dp_set_signal_levels] Using vswing level 2
…
[ 1442.998253] [drm:intel_dp_link_training_clock_recovery [i915]] *ERROR* too many full retries, give up
[ 1442.998512] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to train DP, aborting
After which the pipe state goes completely out of sync:
[ 70.075596] [drm:check_crtc_state] [CRTC:25]
[ 70.075696] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in ddi_pll_sel (expected 0x00000000, found 0x00000001)
[ 70.075747] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in shared_dpll (expected -1, found 0)
[ 70.075798] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.ctrl1 (expected 0x00000000, found 0x00000021)
[ 70.075840] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr1 (expected 0x00000000, found 0x80400173)
[ 70.075884] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr2 (expected 0x00000000, found 0x000003a5)
[ 70.075954] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 262750, found 72256)
[ 70.075999] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in port_clock (expected 540000, found 148500)
And if you're especially lucky, it keeps going downhill:
[ 83.309256] Kernel panic - not syncing: Timeout: Not all CPUs entered broadcast exception handler
[ 83.309265]
[ 83.309265] =================================
[ 83.309266] [ INFO: inconsistent lock state ]
[ 83.309267] 4.5.0-rc1Lyude-Test #265 Not tainted
[ 83.309267] ---------------------------------
[ 83.309268] inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage.
[ 83.309270] Xorg/1194 [HC0[1]:SC0[0]:HE1:SE1] takes:
[ 83.309293] (&(&dev_priv->uncore.lock)->rlock){?.-...}, at: [<ffffffffa02a6073>] gen9_write32+0x63/0x400 [i915]
[ 83.309293] {IN-HARDIRQ-W} state was registered at:
[ 83.309297] [<ffffffff810e84f4>] __lock_acquire+0x9c4/0x1d00
[ 83.309299] [<ffffffff810ea1be>] lock_acquire+0xce/0x1c0
[ 83.309302] [<ffffffff8177d936>] _raw_spin_lock_irqsave+0x56/0x90
[ 83.309321] [<ffffffffa02a5492>] gen9_read32+0x52/0x3d0 [i915]
[ 83.309332] [<ffffffffa024beea>] gen8_irq_handler+0x27a/0x6a0 [i915]
[ 83.309337] [<ffffffff810fdbc1>] handle_irq_event_percpu+0x41/0x300
[ 83.309339] [<ffffffff810fdeb9>] handle_irq_event+0x39/0x60
[ 83.309341] [<ffffffff811010b4>] handle_edge_irq+0x74/0x130
[ 83.309344] [<ffffffff81009073>] handle_irq+0x73/0x120
[ 83.309346] [<ffffffff817805f1>] do_IRQ+0x61/0x120
[ 83.309348] [<ffffffff8177e6d6>] ret_from_intr+0x0/0x20
[ 83.309351] [<ffffffff815f5105>] cpuidle_enter_state+0x105/0x330
[ 83.309353] [<ffffffff815f5367>] cpuidle_enter+0x17/0x20
[ 83.309356] [<ffffffff810dbe1a>] call_cpuidle+0x2a/0x50
[ 83.309358] [<ffffffff810dc1dd>] cpu_startup_entry+0x26d/0x3a0
[ 83.309360] [<ffffffff817701da>] rest_init+0x13a/0x140
[ 83.309363] [<ffffffff81f2af8e>] start_kernel+0x475/0x482
[ 83.309365] [<ffffffff81f2a315>] x86_64_start_reservations+0x2a/0x2c
[ 83.309367] [<ffffffff81f2a452>] x86_64_start_kernel+0x13b/0x14a
Fixes: 82d354370189 ("drm/i915/skl: Implementation of SKL DPLL programming")
Signed-off-by: Lyude <cpaul@redhat.com>
---
Changes
* Add "Fixes" line with link to commit that introduced this problem
* Add some stack traces to aid in future debugging and fixes
drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e6408e5..54a165b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1589,7 +1589,8 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
wrpll_params.central_freq;
- } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
+ } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
+ intel_encoder->type == INTEL_OUTPUT_DP_MST) {
switch (crtc_state->port_clock / 2) {
case 81000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
--
2.5.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/skl: Don't skip mst encoders in skl_ddi_pll_select()
2016-02-02 15:49 ` Lyude
@ 2016-02-09 9:35 ` Daniel Vetter
-1 siblings, 0 replies; 10+ messages in thread
From: Daniel Vetter @ 2016-02-09 9:35 UTC (permalink / raw)
To: Lyude
Cc: Daniel Vetter, Jani Nikula, intel-gfx, dri-devel, linux-kernel,
David Airlie, Rob Clark, Adam Jackson
On Tue, Feb 02, 2016 at 10:49:43AM -0500, Lyude wrote:
> We don't actually check for INTEL_OUTPUT_DP_MST at all in here, as a
> result we skip assigning a DPLL to any DP MST ports, which makes link
> training fail:
>
> [ 1442.933896] [drm:intel_power_well_enable] enabling DDI D power well
> [ 1442.933905] [drm:skl_set_power_well] Enabling DDI D power well
> [ 1442.933957] [drm:intel_mst_pre_enable_dp] 0
> [ 1442.935474] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
> [ 1442.935477] [drm:intel_dp_set_signal_levels] Using vswing level 0
> [ 1442.935480] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
> [ 1442.936190] [drm:intel_dp_set_signal_levels] Using signal levels 05000000
> [ 1442.936193] [drm:intel_dp_set_signal_levels] Using vswing level 1
> [ 1442.936195] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
> [ 1442.936858] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
> [ 1442.936862] [drm:intel_dp_set_signal_levels] Using vswing level 2
> …
> [ 1442.998253] [drm:intel_dp_link_training_clock_recovery [i915]] *ERROR* too many full retries, give up
> [ 1442.998512] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to train DP, aborting
>
> After which the pipe state goes completely out of sync:
>
> [ 70.075596] [drm:check_crtc_state] [CRTC:25]
> [ 70.075696] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in ddi_pll_sel (expected 0x00000000, found 0x00000001)
> [ 70.075747] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in shared_dpll (expected -1, found 0)
> [ 70.075798] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.ctrl1 (expected 0x00000000, found 0x00000021)
> [ 70.075840] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr1 (expected 0x00000000, found 0x80400173)
> [ 70.075884] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr2 (expected 0x00000000, found 0x000003a5)
> [ 70.075954] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 262750, found 72256)
> [ 70.075999] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in port_clock (expected 540000, found 148500)
>
> And if you're especially lucky, it keeps going downhill:
>
> [ 83.309256] Kernel panic - not syncing: Timeout: Not all CPUs entered broadcast exception handler
> [ 83.309265]
> [ 83.309265] =================================
> [ 83.309266] [ INFO: inconsistent lock state ]
> [ 83.309267] 4.5.0-rc1Lyude-Test #265 Not tainted
> [ 83.309267] ---------------------------------
> [ 83.309268] inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage.
> [ 83.309270] Xorg/1194 [HC0[1]:SC0[0]:HE1:SE1] takes:
> [ 83.309293] (&(&dev_priv->uncore.lock)->rlock){?.-...}, at: [<ffffffffa02a6073>] gen9_write32+0x63/0x400 [i915]
> [ 83.309293] {IN-HARDIRQ-W} state was registered at:
> [ 83.309297] [<ffffffff810e84f4>] __lock_acquire+0x9c4/0x1d00
> [ 83.309299] [<ffffffff810ea1be>] lock_acquire+0xce/0x1c0
> [ 83.309302] [<ffffffff8177d936>] _raw_spin_lock_irqsave+0x56/0x90
> [ 83.309321] [<ffffffffa02a5492>] gen9_read32+0x52/0x3d0 [i915]
> [ 83.309332] [<ffffffffa024beea>] gen8_irq_handler+0x27a/0x6a0 [i915]
> [ 83.309337] [<ffffffff810fdbc1>] handle_irq_event_percpu+0x41/0x300
> [ 83.309339] [<ffffffff810fdeb9>] handle_irq_event+0x39/0x60
> [ 83.309341] [<ffffffff811010b4>] handle_edge_irq+0x74/0x130
> [ 83.309344] [<ffffffff81009073>] handle_irq+0x73/0x120
> [ 83.309346] [<ffffffff817805f1>] do_IRQ+0x61/0x120
> [ 83.309348] [<ffffffff8177e6d6>] ret_from_intr+0x0/0x20
> [ 83.309351] [<ffffffff815f5105>] cpuidle_enter_state+0x105/0x330
> [ 83.309353] [<ffffffff815f5367>] cpuidle_enter+0x17/0x20
> [ 83.309356] [<ffffffff810dbe1a>] call_cpuidle+0x2a/0x50
> [ 83.309358] [<ffffffff810dc1dd>] cpu_startup_entry+0x26d/0x3a0
> [ 83.309360] [<ffffffff817701da>] rest_init+0x13a/0x140
> [ 83.309363] [<ffffffff81f2af8e>] start_kernel+0x475/0x482
> [ 83.309365] [<ffffffff81f2a315>] x86_64_start_reservations+0x2a/0x2c
> [ 83.309367] [<ffffffff81f2a452>] x86_64_start_kernel+0x13b/0x14a
>
> Fixes: 82d354370189 ("drm/i915/skl: Implementation of SKL DPLL programming")
> Signed-off-by: Lyude <cpaul@redhat.com>
Somehow CI is ignoring your patch, but then we don't have any dp mst skl
machines in CI anyway yet (would be obvious we'd have noticed this too).
So applied both, with cc: stable for patch 1.
Thanks, Daniel
> ---
> Changes
> * Add "Fixes" line with link to commit that introduced this problem
> * Add some stack traces to aid in future debugging and fixes
>
> drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index e6408e5..54a165b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1589,7 +1589,8 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
> DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
> DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
> wrpll_params.central_freq;
> - } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
> + } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
> + intel_encoder->type == INTEL_OUTPUT_DP_MST) {
> switch (crtc_state->port_clock / 2) {
> case 81000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
> --
> 2.5.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/skl: Don't skip mst encoders in skl_ddi_pll_select()
@ 2016-02-09 9:35 ` Daniel Vetter
0 siblings, 0 replies; 10+ messages in thread
From: Daniel Vetter @ 2016-02-09 9:35 UTC (permalink / raw)
To: Lyude
Cc: Rob Clark, intel-gfx, linux-kernel, dri-devel, David Airlie,
Daniel Vetter
On Tue, Feb 02, 2016 at 10:49:43AM -0500, Lyude wrote:
> We don't actually check for INTEL_OUTPUT_DP_MST at all in here, as a
> result we skip assigning a DPLL to any DP MST ports, which makes link
> training fail:
>
> [ 1442.933896] [drm:intel_power_well_enable] enabling DDI D power well
> [ 1442.933905] [drm:skl_set_power_well] Enabling DDI D power well
> [ 1442.933957] [drm:intel_mst_pre_enable_dp] 0
> [ 1442.935474] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
> [ 1442.935477] [drm:intel_dp_set_signal_levels] Using vswing level 0
> [ 1442.935480] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
> [ 1442.936190] [drm:intel_dp_set_signal_levels] Using signal levels 05000000
> [ 1442.936193] [drm:intel_dp_set_signal_levels] Using vswing level 1
> [ 1442.936195] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
> [ 1442.936858] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
> [ 1442.936862] [drm:intel_dp_set_signal_levels] Using vswing level 2
> …
> [ 1442.998253] [drm:intel_dp_link_training_clock_recovery [i915]] *ERROR* too many full retries, give up
> [ 1442.998512] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to train DP, aborting
>
> After which the pipe state goes completely out of sync:
>
> [ 70.075596] [drm:check_crtc_state] [CRTC:25]
> [ 70.075696] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in ddi_pll_sel (expected 0x00000000, found 0x00000001)
> [ 70.075747] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in shared_dpll (expected -1, found 0)
> [ 70.075798] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.ctrl1 (expected 0x00000000, found 0x00000021)
> [ 70.075840] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr1 (expected 0x00000000, found 0x80400173)
> [ 70.075884] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr2 (expected 0x00000000, found 0x000003a5)
> [ 70.075954] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 262750, found 72256)
> [ 70.075999] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in port_clock (expected 540000, found 148500)
>
> And if you're especially lucky, it keeps going downhill:
>
> [ 83.309256] Kernel panic - not syncing: Timeout: Not all CPUs entered broadcast exception handler
> [ 83.309265]
> [ 83.309265] =================================
> [ 83.309266] [ INFO: inconsistent lock state ]
> [ 83.309267] 4.5.0-rc1Lyude-Test #265 Not tainted
> [ 83.309267] ---------------------------------
> [ 83.309268] inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage.
> [ 83.309270] Xorg/1194 [HC0[1]:SC0[0]:HE1:SE1] takes:
> [ 83.309293] (&(&dev_priv->uncore.lock)->rlock){?.-...}, at: [<ffffffffa02a6073>] gen9_write32+0x63/0x400 [i915]
> [ 83.309293] {IN-HARDIRQ-W} state was registered at:
> [ 83.309297] [<ffffffff810e84f4>] __lock_acquire+0x9c4/0x1d00
> [ 83.309299] [<ffffffff810ea1be>] lock_acquire+0xce/0x1c0
> [ 83.309302] [<ffffffff8177d936>] _raw_spin_lock_irqsave+0x56/0x90
> [ 83.309321] [<ffffffffa02a5492>] gen9_read32+0x52/0x3d0 [i915]
> [ 83.309332] [<ffffffffa024beea>] gen8_irq_handler+0x27a/0x6a0 [i915]
> [ 83.309337] [<ffffffff810fdbc1>] handle_irq_event_percpu+0x41/0x300
> [ 83.309339] [<ffffffff810fdeb9>] handle_irq_event+0x39/0x60
> [ 83.309341] [<ffffffff811010b4>] handle_edge_irq+0x74/0x130
> [ 83.309344] [<ffffffff81009073>] handle_irq+0x73/0x120
> [ 83.309346] [<ffffffff817805f1>] do_IRQ+0x61/0x120
> [ 83.309348] [<ffffffff8177e6d6>] ret_from_intr+0x0/0x20
> [ 83.309351] [<ffffffff815f5105>] cpuidle_enter_state+0x105/0x330
> [ 83.309353] [<ffffffff815f5367>] cpuidle_enter+0x17/0x20
> [ 83.309356] [<ffffffff810dbe1a>] call_cpuidle+0x2a/0x50
> [ 83.309358] [<ffffffff810dc1dd>] cpu_startup_entry+0x26d/0x3a0
> [ 83.309360] [<ffffffff817701da>] rest_init+0x13a/0x140
> [ 83.309363] [<ffffffff81f2af8e>] start_kernel+0x475/0x482
> [ 83.309365] [<ffffffff81f2a315>] x86_64_start_reservations+0x2a/0x2c
> [ 83.309367] [<ffffffff81f2a452>] x86_64_start_kernel+0x13b/0x14a
>
> Fixes: 82d354370189 ("drm/i915/skl: Implementation of SKL DPLL programming")
> Signed-off-by: Lyude <cpaul@redhat.com>
Somehow CI is ignoring your patch, but then we don't have any dp mst skl
machines in CI anyway yet (would be obvious we'd have noticed this too).
So applied both, with cc: stable for patch 1.
Thanks, Daniel
> ---
> Changes
> * Add "Fixes" line with link to commit that introduced this problem
> * Add some stack traces to aid in future debugging and fixes
>
> drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index e6408e5..54a165b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1589,7 +1589,8 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
> DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
> DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
> wrpll_params.central_freq;
> - } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
> + } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
> + intel_encoder->type == INTEL_OUTPUT_DP_MST) {
> switch (crtc_state->port_clock / 2) {
> case 81000:
> ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
> --
> 2.5.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2016-02-09 9:35 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-02-02 14:35 [PATCH 1/2] drm/i915/skl: Don't skip mst encoders in skl_ddi_pll_select() Lyude
2016-02-02 14:35 ` Lyude
2016-02-02 14:35 ` [PATCH 2/2] drm/i915/skl: Explicitly check for eDP " Lyude
2016-02-02 14:35 ` Lyude
2016-02-02 15:15 ` [PATCH 1/2] drm/i915/skl: Don't skip mst encoders " Jani Nikula
2016-02-02 15:15 ` Jani Nikula
2016-02-02 15:49 ` [PATCH v2 " Lyude
2016-02-02 15:49 ` Lyude
2016-02-09 9:35 ` [Intel-gfx] " Daniel Vetter
2016-02-09 9:35 ` Daniel Vetter
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