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From: Thomas Gleixner <tglx@linutronix.de>
To: "H.J. Lu" <hjl.tools@gmail.com>, Dave Hansen <dave.hansen@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
	"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	Andy Lutomirski <luto@kernel.org>,
	the arch/x86 maintainers <x86@kernel.org>,
	Alexander Potapenko <glider@google.com>,
	Dmitry Vyukov <dvyukov@google.com>,
	Andi Kleen <ak@linux.intel.com>,
	Rick Edgecombe <rick.p.edgecombe@intel.com>,
	Linux-MM <linux-mm@kvack.org>,
	LKML <linux-kernel@vger.kernel.org>
Subject: Re: [RFCv2 00/10] Linear Address Masking enabling
Date: Fri, 13 May 2022 01:35:16 +0200	[thread overview]
Message-ID: <87o802tjd7.ffs@tglx> (raw)
In-Reply-To: <CAMe9rOqb6ZnAZYe4uAWDt-vmhhP=z_+uZwi5fBURqyUWxCX9Cg@mail.gmail.com>

On Thu, May 12 2022 at 15:10, H. J. Lu wrote:
> On Thu, May 12, 2022 at 2:51 PM Dave Hansen <dave.hansen@intel.com> wrote:
>> On 5/12/22 12:39, Thomas Gleixner wrote:
>> >> It's OK for a debugging build that runs on one kind of hardware.  But,
>> >> if we want LAM-using binaries to be portable, we have to do something
>> >> different.
>> >>
>> >> One of the stated reasons for adding LAM hardware is that folks want to
>> >> use sanitizers outside of debugging environments.  To me, that means
>> >> that LAM is something that the same binary might run with or without.
>> > On/off yes, but is there an actual use case where such a mechanism would
>> > at start time dynamically chose the number of bits?
>>
>> I'd love to hear from folks doing the userspace side of this.  Will
>> userspace be saying: "Give me all the bits you can!".  Or, will it
>> really just be looking for 6 bits only, and it doesn't care whether it
>> gets 6 or 15, it will use only 6?
>>
>> Do the sanitizers have more overhead with more bits?  Or *less* overhead
>> because they can store more metadata in the pointers?
>>
>> Will anyone care about the difference about potentially missing 1/64
>> issues with U57 versus 1/32768 with U48?
>
> The only LAM usage I know so far is LAM_U57 in HWASAN.

That's at least a halfways useful answer.

> An application can ask for LAM_U48 or LAM_U57. But the decision should
> be made by application.

It can ask for whatever, but the decision whether it's granted is made
by the kernel for obvious reasons.

> When an application asks for LAM_U57, I expect it will store tags in
> upper 6 bits, even if the kernel enables LAM_U48.

The kernel does not enable LAM_U48 when the application only wants to
have LAM_U57, because that would restrict the address space of the
application to 47 bits on 5-level capable system for no reason.

So what are you trying to tell me?

Thanks,

        tglx




  reply	other threads:[~2022-05-12 23:35 UTC|newest]

Thread overview: 82+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-11  2:27 [RFCv2 00/10] Linear Address Masking enabling Kirill A. Shutemov
2022-05-11  2:27 ` [PATCH] x86: Implement Linear Address Masking support Kirill A. Shutemov
2022-05-12 13:01   ` David Laight
2022-05-12 14:07     ` Matthew Wilcox
2022-05-12 15:06       ` Thomas Gleixner
2022-05-12 15:33         ` David Laight
2022-05-12 14:35     ` Peter Zijlstra
2022-05-12 17:00     ` Kirill A. Shutemov
2022-05-11  2:27 ` [RFCv2 01/10] x86/mm: Fix CR3_ADDR_MASK Kirill A. Shutemov
2022-05-11  2:27 ` [RFCv2 02/10] x86: CPUID and CR3/CR4 flags for Linear Address Masking Kirill A. Shutemov
2022-05-11  2:27 ` [RFCv2 03/10] x86: Introduce userspace API to handle per-thread features Kirill A. Shutemov
2022-05-12 12:02   ` Thomas Gleixner
2022-05-12 12:04     ` [PATCH] x86/prctl: Remove pointless task argument Thomas Gleixner
2022-05-13 12:30       ` [tip: x86/cleanups] " tip-bot2 for Thomas Gleixner
2022-05-13 14:09   ` [RFCv2 03/10] x86: Introduce userspace API to handle per-thread features Alexander Potapenko
2022-05-13 17:34     ` Edgecombe, Rick P
2022-05-13 23:09       ` Kirill A. Shutemov
2022-05-13 23:50         ` Edgecombe, Rick P
2022-05-14  8:37           ` Thomas Gleixner
2022-05-14 23:06             ` Edgecombe, Rick P
2022-05-15  9:02               ` Thomas Gleixner
2022-05-15 18:24                 ` Edgecombe, Rick P
2022-05-15 19:38                   ` Thomas Gleixner
2022-05-15 22:01                     ` Edgecombe, Rick P
2022-05-11  2:27 ` [RFCv2 04/10] x86/mm: Introduce X86_THREAD_LAM_U48 and X86_THREAD_LAM_U57 Kirill A. Shutemov
2022-05-11  7:02   ` Peter Zijlstra
2022-05-12 12:24     ` Thomas Gleixner
2022-05-12 14:37       ` Peter Zijlstra
2022-05-11  2:27 ` [RFCv2 05/10] x86/mm: Provide untagged_addr() helper Kirill A. Shutemov
2022-05-11  7:21   ` Peter Zijlstra
2022-05-11  7:45     ` Peter Zijlstra
2022-05-12 13:06   ` Thomas Gleixner
2022-05-12 14:23     ` Peter Zijlstra
2022-05-12 15:16       ` Thomas Gleixner
2022-05-12 23:14         ` Thomas Gleixner
2022-05-13 10:14           ` David Laight
2022-05-11  2:27 ` [RFCv2 06/10] x86/uaccess: Remove tags from the address before checking Kirill A. Shutemov
2022-05-12 13:02   ` David Laight
2022-05-11  2:27 ` [RFCv2 07/10] x86/mm: Handle tagged memory accesses from kernel threads Kirill A. Shutemov
2022-05-11  7:23   ` Peter Zijlstra
2022-05-12 13:30   ` Thomas Gleixner
2022-05-11  2:27 ` [RFCv2 08/10] x86/mm: Make LAM_U48 and mappings above 47-bits mutually exclusive Kirill A. Shutemov
2022-05-12 13:36   ` Thomas Gleixner
2022-05-13 23:22     ` Kirill A. Shutemov
2022-05-14  8:37       ` Thomas Gleixner
2022-05-18  8:43   ` Bharata B Rao
2022-05-18 17:08     ` Kirill A. Shutemov
2022-05-11  2:27 ` [RFCv2 09/10] x86/mm: Add userspace API to enable Linear Address Masking Kirill A. Shutemov
2022-05-11  7:26   ` Peter Zijlstra
2022-05-12 14:46     ` Thomas Gleixner
2022-05-11 14:15   ` H.J. Lu
2022-05-12 14:21     ` Thomas Gleixner
2022-05-11  2:27 ` [RFCv2 10/10] x86: Expose thread features status in /proc/$PID/arch_status Kirill A. Shutemov
2022-05-11  6:49 ` [RFCv2 00/10] Linear Address Masking enabling Peter Zijlstra
2022-05-12 15:42   ` Thomas Gleixner
2022-05-12 16:56     ` Kirill A. Shutemov
2022-05-12 19:31       ` Thomas Gleixner
2022-05-12 23:21         ` Thomas Gleixner
2022-05-12 17:22   ` Dave Hansen
2022-05-12 19:39     ` Thomas Gleixner
2022-05-12 21:24       ` Thomas Gleixner
2022-05-13 14:43         ` Matthew Wilcox
2022-05-13 22:59         ` Kirill A. Shutemov
2022-05-12 21:51       ` Dave Hansen
2022-05-12 22:10         ` H.J. Lu
2022-05-12 23:35           ` Thomas Gleixner [this message]
2022-05-13  0:08             ` H.J. Lu
2022-05-13  0:46               ` Dave Hansen
2022-05-13  1:27                 ` Thomas Gleixner
2022-05-13  3:05                   ` Dave Hansen
2022-05-13  8:28                     ` Thomas Gleixner
2022-05-13 22:48                     ` Kirill A. Shutemov
2022-05-13  9:14                   ` Catalin Marinas
2022-05-13  9:26                     ` Thomas Gleixner
2022-05-13  0:46               ` Thomas Gleixner
2022-05-13 11:07         ` Alexander Potapenko
2022-05-13 11:28           ` David Laight
2022-05-13 12:26             ` Alexander Potapenko
2022-05-13 14:26               ` David Laight
2022-05-13 15:28                 ` Alexander Potapenko
2022-05-13 23:01           ` Kirill A. Shutemov
2022-05-14 10:00             ` Thomas Gleixner

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