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From: Alexander Potapenko <glider@google.com>
To: Dave Hansen <dave.hansen@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Peter Zijlstra <peterz@infradead.org>,
	"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	Andy Lutomirski <luto@kernel.org>,
	"the arch/x86 maintainers" <x86@kernel.org>,
	Dmitry Vyukov <dvyukov@google.com>,
	"H . J . Lu" <hjl.tools@gmail.com>,
	Andi Kleen <ak@linux.intel.com>,
	Rick Edgecombe <rick.p.edgecombe@intel.com>,
	Linux Memory Management List <linux-mm@kvack.org>,
	LKML <linux-kernel@vger.kernel.org>
Subject: Re: [RFCv2 00/10] Linear Address Masking enabling
Date: Fri, 13 May 2022 13:07:43 +0200	[thread overview]
Message-ID: <CAG_fn=URUve59ZPWRawW+BN-bUy7U3QmFsfOz_7L8ndsL4kQFQ@mail.gmail.com> (raw)
In-Reply-To: <55176b79-90af-4a47-dc06-9f5f2f2c123d@intel.com>

On Thu, May 12, 2022 at 11:51 PM Dave Hansen <dave.hansen@intel.com> wrote:
>
> On 5/12/22 12:39, Thomas Gleixner wrote:
> >> It's OK for a debugging build that runs on one kind of hardware.  But,
> >> if we want LAM-using binaries to be portable, we have to do something
> >> different.
> >>
> >> One of the stated reasons for adding LAM hardware is that folks want to
> >> use sanitizers outside of debugging environments.  To me, that means
> >> that LAM is something that the same binary might run with or without.
> > On/off yes, but is there an actual use case where such a mechanism would
> > at start time dynamically chose the number of bits?
>
> I'd love to hear from folks doing the userspace side of this.  Will
> userspace be saying: "Give me all the bits you can!".  Or, will it
> really just be looking for 6 bits only, and it doesn't care whether it
> gets 6 or 15, it will use only 6?

(speaking more or less on behalf of the userspace folks here)
I think it is safe to assume that in the upcoming year or two HWASan
will be fine having just 6 bits for the tags on x86 machines.
We are interested in running it on kernels with and without
CONFIG_X86_5LEVEL=y, so U48 is not an option in some cases anyway.

> Do the sanitizers have more overhead with more bits?  Or *less* overhead
> because they can store more metadata in the pointers?
Once we have the possibility to store tags in the pointers, we don't
need redzones for heap/stack objects anymore, which saves quite a bit
of memory.
Also, HWASan doesn't use quarantine and has smaller shadow memory size
(see https://clang.llvm.org/docs/HardwareAssistedAddressSanitizerDesign.html
for more details).
Having more bits increases the probability to detect a UAF or buffer
overflow and reduces the shadow memory size further, but that one is
small enough already.

> Will anyone care about the difference about potentially missing 1/64
> issues with U57 versus 1/32768 with U48?
I don't think anyone will.

Having said that, I agree with Dave that it would be nice to have an
interface that would just request the mask from the system.
That way we could have support for U57 in the kernel now and keep the
possibility to add U48 in the future without breaking existing users.

I also may be missing something obvious, but I can't come up with a
case where different apps in the system may request U48 and U57 at the
same time.
It seems natural to me to let the OS decide which of the modes is
supported and give the app the freedom to use it or lose it.

--
Alexander Potapenko
Software Engineer

Google Germany GmbH
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  parent reply	other threads:[~2022-05-13 11:08 UTC|newest]

Thread overview: 82+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-11  2:27 [RFCv2 00/10] Linear Address Masking enabling Kirill A. Shutemov
2022-05-11  2:27 ` [PATCH] x86: Implement Linear Address Masking support Kirill A. Shutemov
2022-05-12 13:01   ` David Laight
2022-05-12 14:07     ` Matthew Wilcox
2022-05-12 15:06       ` Thomas Gleixner
2022-05-12 15:33         ` David Laight
2022-05-12 14:35     ` Peter Zijlstra
2022-05-12 17:00     ` Kirill A. Shutemov
2022-05-11  2:27 ` [RFCv2 01/10] x86/mm: Fix CR3_ADDR_MASK Kirill A. Shutemov
2022-05-11  2:27 ` [RFCv2 02/10] x86: CPUID and CR3/CR4 flags for Linear Address Masking Kirill A. Shutemov
2022-05-11  2:27 ` [RFCv2 03/10] x86: Introduce userspace API to handle per-thread features Kirill A. Shutemov
2022-05-12 12:02   ` Thomas Gleixner
2022-05-12 12:04     ` [PATCH] x86/prctl: Remove pointless task argument Thomas Gleixner
2022-05-13 12:30       ` [tip: x86/cleanups] " tip-bot2 for Thomas Gleixner
2022-05-13 14:09   ` [RFCv2 03/10] x86: Introduce userspace API to handle per-thread features Alexander Potapenko
2022-05-13 17:34     ` Edgecombe, Rick P
2022-05-13 23:09       ` Kirill A. Shutemov
2022-05-13 23:50         ` Edgecombe, Rick P
2022-05-14  8:37           ` Thomas Gleixner
2022-05-14 23:06             ` Edgecombe, Rick P
2022-05-15  9:02               ` Thomas Gleixner
2022-05-15 18:24                 ` Edgecombe, Rick P
2022-05-15 19:38                   ` Thomas Gleixner
2022-05-15 22:01                     ` Edgecombe, Rick P
2022-05-11  2:27 ` [RFCv2 04/10] x86/mm: Introduce X86_THREAD_LAM_U48 and X86_THREAD_LAM_U57 Kirill A. Shutemov
2022-05-11  7:02   ` Peter Zijlstra
2022-05-12 12:24     ` Thomas Gleixner
2022-05-12 14:37       ` Peter Zijlstra
2022-05-11  2:27 ` [RFCv2 05/10] x86/mm: Provide untagged_addr() helper Kirill A. Shutemov
2022-05-11  7:21   ` Peter Zijlstra
2022-05-11  7:45     ` Peter Zijlstra
2022-05-12 13:06   ` Thomas Gleixner
2022-05-12 14:23     ` Peter Zijlstra
2022-05-12 15:16       ` Thomas Gleixner
2022-05-12 23:14         ` Thomas Gleixner
2022-05-13 10:14           ` David Laight
2022-05-11  2:27 ` [RFCv2 06/10] x86/uaccess: Remove tags from the address before checking Kirill A. Shutemov
2022-05-12 13:02   ` David Laight
2022-05-11  2:27 ` [RFCv2 07/10] x86/mm: Handle tagged memory accesses from kernel threads Kirill A. Shutemov
2022-05-11  7:23   ` Peter Zijlstra
2022-05-12 13:30   ` Thomas Gleixner
2022-05-11  2:27 ` [RFCv2 08/10] x86/mm: Make LAM_U48 and mappings above 47-bits mutually exclusive Kirill A. Shutemov
2022-05-12 13:36   ` Thomas Gleixner
2022-05-13 23:22     ` Kirill A. Shutemov
2022-05-14  8:37       ` Thomas Gleixner
2022-05-18  8:43   ` Bharata B Rao
2022-05-18 17:08     ` Kirill A. Shutemov
2022-05-11  2:27 ` [RFCv2 09/10] x86/mm: Add userspace API to enable Linear Address Masking Kirill A. Shutemov
2022-05-11  7:26   ` Peter Zijlstra
2022-05-12 14:46     ` Thomas Gleixner
2022-05-11 14:15   ` H.J. Lu
2022-05-12 14:21     ` Thomas Gleixner
2022-05-11  2:27 ` [RFCv2 10/10] x86: Expose thread features status in /proc/$PID/arch_status Kirill A. Shutemov
2022-05-11  6:49 ` [RFCv2 00/10] Linear Address Masking enabling Peter Zijlstra
2022-05-12 15:42   ` Thomas Gleixner
2022-05-12 16:56     ` Kirill A. Shutemov
2022-05-12 19:31       ` Thomas Gleixner
2022-05-12 23:21         ` Thomas Gleixner
2022-05-12 17:22   ` Dave Hansen
2022-05-12 19:39     ` Thomas Gleixner
2022-05-12 21:24       ` Thomas Gleixner
2022-05-13 14:43         ` Matthew Wilcox
2022-05-13 22:59         ` Kirill A. Shutemov
2022-05-12 21:51       ` Dave Hansen
2022-05-12 22:10         ` H.J. Lu
2022-05-12 23:35           ` Thomas Gleixner
2022-05-13  0:08             ` H.J. Lu
2022-05-13  0:46               ` Dave Hansen
2022-05-13  1:27                 ` Thomas Gleixner
2022-05-13  3:05                   ` Dave Hansen
2022-05-13  8:28                     ` Thomas Gleixner
2022-05-13 22:48                     ` Kirill A. Shutemov
2022-05-13  9:14                   ` Catalin Marinas
2022-05-13  9:26                     ` Thomas Gleixner
2022-05-13  0:46               ` Thomas Gleixner
2022-05-13 11:07         ` Alexander Potapenko [this message]
2022-05-13 11:28           ` David Laight
2022-05-13 12:26             ` Alexander Potapenko
2022-05-13 14:26               ` David Laight
2022-05-13 15:28                 ` Alexander Potapenko
2022-05-13 23:01           ` Kirill A. Shutemov
2022-05-14 10:00             ` Thomas Gleixner

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