* [Intel-gfx] [PATCH 0/5] display: prefer 3-letter acronym
@ 2019-12-18 1:42 Lucas De Marchi
2019-12-18 1:42 ` [Intel-gfx] [PATCH 1/5] drm/i915/display: prefer 3-letter acronym for haswell Lucas De Marchi
` (7 more replies)
0 siblings, 8 replies; 14+ messages in thread
From: Lucas De Marchi @ 2019-12-18 1:42 UTC (permalink / raw)
To: intel-gfx
This bothered me for a while so I decided to give it a try: let's
normalize on using the platform acronym for function prefixes.
This does the conversion for some platforms. There are others missing,
but I'm sending this early for the case the idea is shot down.
Lucas De Marchi (5):
drm/i915/display: prefer 3-letter acronym for haswell
drm/i915/display: prefer 3-letter acronym for skylake
drm/i915/display: prefer 3-letter acronym for cannonlake
drm/i915/display: prefer 3-letter acronym for icelake
drm/i915/display: prefer 3-letter acronym for ironlake
drivers/gpu/drm/i915/display/intel_crt.c | 6 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 278 +++++++++---------
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 34 +--
.../drm/i915/display/intel_fifo_underrun.c | 6 +-
6 files changed, 163 insertions(+), 167 deletions(-)
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 1/5] drm/i915/display: prefer 3-letter acronym for haswell
2019-12-18 1:42 [Intel-gfx] [PATCH 0/5] display: prefer 3-letter acronym Lucas De Marchi
@ 2019-12-18 1:42 ` Lucas De Marchi
2019-12-18 1:42 ` [Intel-gfx] [PATCH 2/5] drm/i915/display: prefer 3-letter acronym for skylake Lucas De Marchi
` (6 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Lucas De Marchi @ 2019-12-18 1:42 UTC (permalink / raw)
To: intel-gfx
We are currently using a mix of platform name and acronym to name the
functions. Let's prefer the acronym as it should be clear what platform
it's about and it's shorter, so it doesn't go over 80 columns in a few
cases. This converts haswell to hsw where appropriate.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 57 ++++++++++----------
2 files changed, 30 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5b6f32517c75..cfce0c64b965 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3457,14 +3457,14 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
* (DFLEXDPSP.DPX4TXLATC)
*
* This was done before tgl_ddi_pre_enable_dp by
- * haswell_crtc_enable()->intel_encoders_pre_pll_enable().
+ * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
*/
/*
* 4. Enable the port PLL.
*
* The PLL enabling itself was already done before this function by
- * haswell_crtc_enable()->intel_enable_shared_dpll(). We need only
+ * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
* configure the PLL to port mapping here.
*/
intel_ddi_clk_select(encoder, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 64e4bfb0dfc9..2e1156cc648d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -158,7 +158,7 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
const struct intel_link_m_n *m2_n2);
static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
-static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
+static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
static void vlv_prepare_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config);
@@ -6557,8 +6557,8 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
I915_WRITE(reg, val);
}
-static void haswell_crtc_enable(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+static void hsw_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
@@ -6599,7 +6599,7 @@ static void haswell_crtc_enable(struct intel_atomic_state *state,
if (!transcoder_is_dsi(cpu_transcoder)) {
hsw_set_frame_start_delay(new_crtc_state);
- haswell_set_pipeconf(new_crtc_state);
+ hsw_set_pipeconf(new_crtc_state);
}
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
@@ -6737,8 +6737,8 @@ static void ironlake_crtc_disable(struct intel_atomic_state *state,
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
}
-static void haswell_crtc_disable(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+static void hsw_crtc_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
@@ -9577,7 +9577,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
POSTING_READ(PIPECONF(pipe));
}
-static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
+static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -10209,8 +10209,9 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
return ret;
}
-static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state)
+
+static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_atomic_state *state =
@@ -10324,9 +10325,8 @@ static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
}
-static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
- enum port port,
- struct intel_crtc_state *pipe_config)
+static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
+ struct intel_crtc_state *pipe_config)
{
enum intel_dpll_id id;
u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
@@ -10514,8 +10514,8 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
return transcoder_is_dsi(pipe_config->cpu_transcoder);
}
-static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
@@ -10543,7 +10543,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
else if (IS_GEN9_LP(dev_priv))
bxt_get_ddi_pll(dev_priv, port, pipe_config);
else
- haswell_get_ddi_pll(dev_priv, port, pipe_config);
+ hsw_get_ddi_pll(dev_priv, port, pipe_config);
pll = pipe_config->shared_dpll;
if (pll) {
@@ -10621,8 +10621,8 @@ static void icelake_get_trans_port_sync_config(struct intel_crtc_state *crtc_sta
crtc_state->sync_mode_slaves_mask);
}
-static bool haswell_get_pipe_config(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static bool hsw_get_pipe_config(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
@@ -10659,7 +10659,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
INTEL_GEN(dev_priv) >= 11) {
- haswell_get_ddi_port_state(crtc, pipe_config);
+ hsw_get_ddi_port_state(crtc, pipe_config);
intel_get_pipe_timings(crtc, pipe_config);
}
@@ -13821,7 +13821,7 @@ static void intel_modeset_clear_plls(struct intel_atomic_state *state)
* multiple pipes, and planes are enabled after the pipe, we need to wait at
* least 2 vblanks on the first pipe before enabling planes on the second pipe.
*/
-static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
+static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
{
struct intel_crtc_state *crtc_state;
struct intel_crtc *crtc;
@@ -13916,7 +13916,7 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
intel_modeset_clear_plls(state);
if (IS_HASWELL(dev_priv))
- return haswell_mode_set_planes_workaround(state);
+ return hsw_mode_set_planes_workaround(state);
return 0;
}
@@ -16602,21 +16602,20 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
intel_init_cdclk_hooks(dev_priv);
if (INTEL_GEN(dev_priv) >= 9) {
- dev_priv->display.get_pipe_config = haswell_get_pipe_config;
+ dev_priv->display.get_pipe_config = hsw_get_pipe_config;
dev_priv->display.get_initial_plane_config =
skylake_get_initial_plane_config;
- dev_priv->display.crtc_compute_clock =
- haswell_crtc_compute_clock;
- dev_priv->display.crtc_enable = haswell_crtc_enable;
- dev_priv->display.crtc_disable = haswell_crtc_disable;
+ dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
+ dev_priv->display.crtc_enable = hsw_crtc_enable;
+ dev_priv->display.crtc_disable = hsw_crtc_disable;
} else if (HAS_DDI(dev_priv)) {
- dev_priv->display.get_pipe_config = haswell_get_pipe_config;
+ dev_priv->display.get_pipe_config = hsw_get_pipe_config;
dev_priv->display.get_initial_plane_config =
i9xx_get_initial_plane_config;
dev_priv->display.crtc_compute_clock =
- haswell_crtc_compute_clock;
- dev_priv->display.crtc_enable = haswell_crtc_enable;
- dev_priv->display.crtc_disable = haswell_crtc_disable;
+ hsw_crtc_compute_clock;
+ dev_priv->display.crtc_enable = hsw_crtc_enable;
+ dev_priv->display.crtc_disable = hsw_crtc_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
dev_priv->display.get_initial_plane_config =
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 2/5] drm/i915/display: prefer 3-letter acronym for skylake
2019-12-18 1:42 [Intel-gfx] [PATCH 0/5] display: prefer 3-letter acronym Lucas De Marchi
2019-12-18 1:42 ` [Intel-gfx] [PATCH 1/5] drm/i915/display: prefer 3-letter acronym for haswell Lucas De Marchi
@ 2019-12-18 1:42 ` Lucas De Marchi
2019-12-18 1:42 ` [Intel-gfx] [PATCH 3/5] drm/i915/display: prefer 3-letter acronym for cannonlake Lucas De Marchi
` (5 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Lucas De Marchi @ 2019-12-18 1:42 UTC (permalink / raw)
To: intel-gfx
We are currently using a mix of platform name and acronym to name the
functions. Let's prefer the acronym as it should be clear what platform
it's about and it's shorter, so it doesn't go over 80 columns in a few
cases. This converts skylake to skl where appropriate.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++----------
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2e1156cc648d..7d14a0144ec3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -166,7 +166,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config);
static void intel_crtc_init_scalers(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
-static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
+static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
static void intel_modeset_setup_hw_state(struct drm_device *dev,
@@ -5769,7 +5769,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
return 0;
}
-static void skylake_scaler_disable(struct intel_crtc *crtc)
+static void skl_scaler_disable(struct intel_crtc *crtc)
{
int i;
@@ -5777,7 +5777,7 @@ static void skylake_scaler_disable(struct intel_crtc *crtc)
skl_detach_scaler(crtc, i);
}
-static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
+static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -6614,7 +6614,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
if (INTEL_GEN(dev_priv) >= 9)
- skylake_pfit_enable(new_crtc_state);
+ skl_pfit_enable(new_crtc_state);
else
ironlake_pfit_enable(new_crtc_state);
@@ -6762,7 +6762,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
intel_dsc_disable(old_crtc_state);
if (INTEL_GEN(dev_priv) >= 9)
- skylake_scaler_disable(crtc);
+ skl_scaler_disable(crtc);
else
ironlake_pfit_disable(old_crtc_state);
@@ -9910,8 +9910,8 @@ static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
&pipe_config->fdi_m_n, NULL);
}
-static void skylake_get_pfit_config(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static void skl_get_pfit_config(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -9942,8 +9942,8 @@ static void skylake_get_pfit_config(struct intel_crtc *crtc,
}
static void
-skylake_get_initial_plane_config(struct intel_crtc *crtc,
- struct intel_initial_plane_config *plane_config)
+skl_get_initial_plane_config(struct intel_crtc *crtc,
+ struct intel_initial_plane_config *plane_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -10309,9 +10309,8 @@ static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
}
-static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
- enum port port,
- struct intel_crtc_state *pipe_config)
+static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
+ struct intel_crtc_state *pipe_config)
{
enum intel_dpll_id id;
u32 temp;
@@ -10539,7 +10538,7 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
else if (IS_CANNONLAKE(dev_priv))
cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
else if (IS_GEN9_BC(dev_priv))
- skylake_get_ddi_pll(dev_priv, port, pipe_config);
+ skl_get_ddi_pll(dev_priv, port, pipe_config);
else if (IS_GEN9_LP(dev_priv))
bxt_get_ddi_pll(dev_priv, port, pipe_config);
else
@@ -10716,7 +10715,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
power_domain_mask |= BIT_ULL(power_domain);
if (INTEL_GEN(dev_priv) >= 9)
- skylake_get_pfit_config(crtc, pipe_config);
+ skl_get_pfit_config(crtc, pipe_config);
else
ironlake_get_pfit_config(crtc, pipe_config);
}
@@ -14245,7 +14244,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
skl_detach_scalers(new_crtc_state);
if (new_crtc_state->pch_pfit.enabled)
- skylake_pfit_enable(new_crtc_state);
+ skl_pfit_enable(new_crtc_state);
} else if (HAS_PCH_SPLIT(dev_priv)) {
if (new_crtc_state->pch_pfit.enabled)
ironlake_pfit_enable(new_crtc_state);
@@ -16604,7 +16603,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) >= 9) {
dev_priv->display.get_pipe_config = hsw_get_pipe_config;
dev_priv->display.get_initial_plane_config =
- skylake_get_initial_plane_config;
+ skl_get_initial_plane_config;
dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
dev_priv->display.crtc_enable = hsw_crtc_enable;
dev_priv->display.crtc_disable = hsw_crtc_disable;
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 3/5] drm/i915/display: prefer 3-letter acronym for cannonlake
2019-12-18 1:42 [Intel-gfx] [PATCH 0/5] display: prefer 3-letter acronym Lucas De Marchi
2019-12-18 1:42 ` [Intel-gfx] [PATCH 1/5] drm/i915/display: prefer 3-letter acronym for haswell Lucas De Marchi
2019-12-18 1:42 ` [Intel-gfx] [PATCH 2/5] drm/i915/display: prefer 3-letter acronym for skylake Lucas De Marchi
@ 2019-12-18 1:42 ` Lucas De Marchi
2019-12-18 1:42 ` [Intel-gfx] [PATCH 4/5] drm/i915/display: prefer 3-letter acronym for icelake Lucas De Marchi
` (4 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Lucas De Marchi @ 2019-12-18 1:42 UTC (permalink / raw)
To: intel-gfx
We are currently using a mix of platform name and acronym to name the
functions. Let's prefer the acronym as it should be clear what platform
it's about and it's shorter, so it doesn't go over 80 columns in a few
cases. This converts cannonlake to cnl where appropriate.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7d14a0144ec3..3b623426f243 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10232,9 +10232,8 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
return 0;
}
-static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
- enum port port,
- struct intel_crtc_state *pipe_config)
+static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
+ struct intel_crtc_state *pipe_config)
{
enum intel_dpll_id id;
u32 temp;
@@ -10536,7 +10535,7 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
if (INTEL_GEN(dev_priv) >= 11)
icelake_get_ddi_pll(dev_priv, port, pipe_config);
else if (IS_CANNONLAKE(dev_priv))
- cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
+ cnl_get_ddi_pll(dev_priv, port, pipe_config);
else if (IS_GEN9_BC(dev_priv))
skl_get_ddi_pll(dev_priv, port, pipe_config);
else if (IS_GEN9_LP(dev_priv))
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 4/5] drm/i915/display: prefer 3-letter acronym for icelake
2019-12-18 1:42 [Intel-gfx] [PATCH 0/5] display: prefer 3-letter acronym Lucas De Marchi
` (2 preceding siblings ...)
2019-12-18 1:42 ` [Intel-gfx] [PATCH 3/5] drm/i915/display: prefer 3-letter acronym for cannonlake Lucas De Marchi
@ 2019-12-18 1:42 ` Lucas De Marchi
2019-12-18 1:42 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: prefer 3-letter acronym for ironlake Lucas De Marchi
` (3 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Lucas De Marchi @ 2019-12-18 1:42 UTC (permalink / raw)
To: intel-gfx
We are currently using a mix of platform name and acronym to name the
functions. Let's prefer the acronym as it should be clear what platform
it's about and it's shorter, so it doesn't go over 80 columns in a few
cases. This converts icelake to icl where appropriate.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3b623426f243..d3a13737552a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10247,9 +10247,8 @@ static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
}
-static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
- enum port port,
- struct intel_crtc_state *pipe_config)
+static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
+ struct intel_crtc_state *pipe_config)
{
enum phy phy = intel_port_to_phy(dev_priv, port);
enum icl_port_dpll_id port_dpll_id;
@@ -10533,7 +10532,7 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
}
if (INTEL_GEN(dev_priv) >= 11)
- icelake_get_ddi_pll(dev_priv, port, pipe_config);
+ icl_get_ddi_pll(dev_priv, port, pipe_config);
else if (IS_CANNONLAKE(dev_priv))
cnl_get_ddi_pll(dev_priv, port, pipe_config);
else if (IS_GEN9_BC(dev_priv))
@@ -10584,7 +10583,7 @@ static enum transcoder transcoder_master_readout(struct drm_i915_private *dev_pr
return master_select - 1;
}
-static void icelake_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
+static void icl_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
u32 transcoders;
@@ -10742,7 +10741,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
if (INTEL_GEN(dev_priv) >= 11 &&
!transcoder_is_dsi(pipe_config->cpu_transcoder))
- icelake_get_trans_port_sync_config(pipe_config);
+ icl_get_trans_port_sync_config(pipe_config);
out:
for_each_power_domain(power_domain, power_domain_mask)
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 5/5] drm/i915/display: prefer 3-letter acronym for ironlake
2019-12-18 1:42 [Intel-gfx] [PATCH 0/5] display: prefer 3-letter acronym Lucas De Marchi
` (3 preceding siblings ...)
2019-12-18 1:42 ` [Intel-gfx] [PATCH 4/5] drm/i915/display: prefer 3-letter acronym for icelake Lucas De Marchi
@ 2019-12-18 1:42 ` Lucas De Marchi
2019-12-18 12:59 ` Ville Syrjälä
2019-12-18 3:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success for display: prefer 3-letter acronym Patchwork
` (2 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Lucas De Marchi @ 2019-12-18 1:42 UTC (permalink / raw)
To: intel-gfx
We are currently using a mix of platform name and acronym to name the
functions. Let's prefer the acronym as it should be clear what platform
it's about and it's shorter, so it doesn't go over 80 columns in a few
cases. This converts ironlake to ilk where appropriate.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 172 +++++++++---------
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 34 ++--
.../drm/i915/display/intel_fifo_underrun.c | 6 +-
5 files changed, 110 insertions(+), 110 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 7a2d36905155..853068b9f909 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -343,7 +343,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
if (HAS_PCH_LPT(dev_priv) &&
- (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
+ ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
return MODE_CLOCK_HIGH;
/* HSW/BDW FDI limited to 4k */
@@ -419,7 +419,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
return 0;
}
-static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
+static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
{
struct drm_device *dev = connector->dev;
struct intel_crt *crt = intel_attached_crt(connector);
@@ -527,7 +527,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
int i, tries = 0;
if (HAS_PCH_SPLIT(dev_priv))
- return intel_ironlake_crt_detect_hotplug(connector);
+ return ilk_crt_detect_hotplug(connector);
if (IS_VALLEYVIEW(dev_priv))
return valleyview_crt_detect_hotplug(connector);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d3a13737552a..a4f516bc850f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -145,8 +145,8 @@ static const u64 cursor_format_modifiers[] = {
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
-static void ironlake_pch_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config);
+static void ilk_pch_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config);
static int intel_framebuffer_init(struct intel_framebuffer *ifb,
struct drm_i915_gem_object *obj,
@@ -157,7 +157,7 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
const struct intel_link_m_n *m_n,
const struct intel_link_m_n *m2_n2);
static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
-static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
+static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
static void vlv_prepare_pll(struct intel_crtc *crtc,
@@ -167,8 +167,8 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
static void intel_crtc_init_scalers(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
-static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
-static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
+static void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
+static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
static void intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx);
@@ -404,7 +404,7 @@ static const struct intel_limit intel_limits_pineview_lvds = {
* We calculate clock using (register_value + 2) for N/M1/M2, so here
* the range value for them is (actual_value - 2).
*/
-static const struct intel_limit intel_limits_ironlake_dac = {
+static const struct intel_limit intel_limits_ilk_dac = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 1760000, .max = 3510000 },
.n = { .min = 1, .max = 5 },
@@ -417,7 +417,7 @@ static const struct intel_limit intel_limits_ironlake_dac = {
.p2_slow = 10, .p2_fast = 5 },
};
-static const struct intel_limit intel_limits_ironlake_single_lvds = {
+static const struct intel_limit intel_limits_ilk_single_lvds = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 1760000, .max = 3510000 },
.n = { .min = 1, .max = 3 },
@@ -430,7 +430,7 @@ static const struct intel_limit intel_limits_ironlake_single_lvds = {
.p2_slow = 14, .p2_fast = 14 },
};
-static const struct intel_limit intel_limits_ironlake_dual_lvds = {
+static const struct intel_limit intel_limits_ilk_dual_lvds = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 1760000, .max = 3510000 },
.n = { .min = 1, .max = 3 },
@@ -444,7 +444,7 @@ static const struct intel_limit intel_limits_ironlake_dual_lvds = {
};
/* LVDS 100mhz refclk limits. */
-static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
+static const struct intel_limit intel_limits_ilk_single_lvds_100m = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 1760000, .max = 3510000 },
.n = { .min = 1, .max = 2 },
@@ -457,7 +457,7 @@ static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
.p2_slow = 14, .p2_fast = 14 },
};
-static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
+static const struct intel_limit intel_limits_ilk_dual_lvds_100m = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 1760000, .max = 3510000 },
.n = { .min = 1, .max = 3 },
@@ -1639,7 +1639,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
I915_READ(dpll_reg) & port_mask, expected_mask);
}
-static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
+static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1737,8 +1737,8 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
DRM_ERROR("Failed to enable PCH transcoder\n");
}
-static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
- enum pipe pipe)
+static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
{
i915_reg_t reg;
u32 val;
@@ -4641,8 +4641,8 @@ static void intel_fdi_normal_train(struct intel_crtc *crtc)
}
/* The FDI link training functions for ILK/Ibexpeak. */
-static void ironlake_fdi_link_train(struct intel_crtc *crtc,
- const struct intel_crtc_state *crtc_state)
+static void ilk_fdi_link_train(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -4994,7 +4994,7 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
DRM_DEBUG_KMS("FDI train done.\n");
}
-static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
+static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
@@ -5031,7 +5031,7 @@ static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
}
}
-static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
+static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc)
{
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -5061,7 +5061,7 @@ static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
udelay(100);
}
-static void ironlake_fdi_disable(struct intel_crtc *crtc)
+static void ilk_fdi_disable(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -5268,8 +5268,8 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
desired_divisor << auxdiv);
}
-static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
- enum pipe pch_transcoder)
+static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
+ enum pipe pch_transcoder)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -5373,8 +5373,8 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
* - DP transcoding bits
* - transcoder
*/
-static void ironlake_pch_enable(const struct intel_atomic_state *state,
- const struct intel_crtc_state *crtc_state)
+static void ilk_pch_enable(const struct intel_atomic_state *state,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_device *dev = crtc->base.dev;
@@ -5422,7 +5422,7 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
/* set transcoder timing, panel must allow it */
assert_panel_unlocked(dev_priv, pipe);
- ironlake_pch_transcoder_set_timings(crtc_state, pipe);
+ ilk_pch_transcoder_set_timings(crtc_state, pipe);
intel_fdi_normal_train(crtc);
@@ -5454,7 +5454,7 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
I915_WRITE(reg, temp);
}
- ironlake_enable_pch_transcoder(crtc_state);
+ ilk_enable_pch_transcoder(crtc_state);
}
static void lpt_pch_enable(const struct intel_atomic_state *state,
@@ -5469,7 +5469,7 @@ static void lpt_pch_enable(const struct intel_atomic_state *state,
lpt_program_iclkip(crtc_state);
/* Set transcoder timing. */
- ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
+ ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
}
@@ -5814,7 +5814,7 @@ static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
}
}
-static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
+static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -6413,8 +6413,8 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
plane->disable_plane(plane, crtc_state);
}
-static void ironlake_crtc_enable(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+static void ilk_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
@@ -6450,7 +6450,7 @@ static void ironlake_crtc_enable(struct intel_atomic_state *state,
intel_cpu_transcoder_set_m_n(new_crtc_state,
&new_crtc_state->fdi_m_n, NULL);
- ironlake_set_pipeconf(new_crtc_state);
+ ilk_set_pipeconf(new_crtc_state);
crtc->active = true;
@@ -6460,13 +6460,13 @@ static void ironlake_crtc_enable(struct intel_atomic_state *state,
/* Note: FDI PLL enabling _must_ be done before we enable the
* cpu pipes, hence this is separate from all the other fdi/pch
* enabling. */
- ironlake_fdi_pll_enable(new_crtc_state);
+ ilk_fdi_pll_enable(new_crtc_state);
} else {
assert_fdi_tx_disabled(dev_priv, pipe);
assert_fdi_rx_disabled(dev_priv, pipe);
}
- ironlake_pfit_enable(new_crtc_state);
+ ilk_pfit_enable(new_crtc_state);
/*
* On ILK+ LUT must be loaded before the pipe is running but with
@@ -6482,7 +6482,7 @@ static void ironlake_crtc_enable(struct intel_atomic_state *state,
intel_enable_pipe(new_crtc_state);
if (new_crtc_state->has_pch_encoder)
- ironlake_pch_enable(state, new_crtc_state);
+ ilk_pch_enable(state, new_crtc_state);
intel_crtc_vblank_on(new_crtc_state);
@@ -6616,7 +6616,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
if (INTEL_GEN(dev_priv) >= 9)
skl_pfit_enable(new_crtc_state);
else
- ironlake_pfit_enable(new_crtc_state);
+ ilk_pfit_enable(new_crtc_state);
/*
* On ILK+ LUT must be loaded before the pipe is running but with
@@ -6665,7 +6665,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
}
}
-static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
+static void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -6680,8 +6680,8 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
}
}
-static void ironlake_crtc_disable(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+static void ilk_crtc_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
@@ -6702,15 +6702,15 @@ static void ironlake_crtc_disable(struct intel_atomic_state *state,
intel_disable_pipe(old_crtc_state);
- ironlake_pfit_disable(old_crtc_state);
+ ilk_pfit_disable(old_crtc_state);
if (old_crtc_state->has_pch_encoder)
- ironlake_fdi_disable(crtc);
+ ilk_fdi_disable(crtc);
intel_encoders_post_disable(state, crtc);
if (old_crtc_state->has_pch_encoder) {
- ironlake_disable_pch_transcoder(dev_priv, pipe);
+ ilk_disable_pch_transcoder(dev_priv, pipe);
if (HAS_PCH_CPT(dev_priv)) {
i915_reg_t reg;
@@ -6730,7 +6730,7 @@ static void ironlake_crtc_disable(struct intel_atomic_state *state,
I915_WRITE(PCH_DPLL_SEL, temp);
}
- ironlake_fdi_pll_disable(crtc);
+ ilk_fdi_pll_disable(crtc);
}
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -6764,7 +6764,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
if (INTEL_GEN(dev_priv) >= 9)
skl_scaler_disable(crtc);
else
- ironlake_pfit_disable(old_crtc_state);
+ ilk_pfit_disable(old_crtc_state);
intel_encoders_post_disable(state, crtc);
@@ -7298,8 +7298,8 @@ static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
return 0;
}
-static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
- struct intel_crtc_state *pipe_config)
+static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
+ struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_atomic_state *state = pipe_config->uapi.state;
@@ -7371,8 +7371,8 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
}
#define RETRY 1
-static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
- struct intel_crtc_state *pipe_config)
+static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = intel_crtc->base.dev;
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
@@ -7391,15 +7391,15 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
fdi_dotclock = adjusted_mode->crtc_clock;
- lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
- pipe_config->pipe_bpp);
+ lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
+ pipe_config->pipe_bpp);
pipe_config->fdi_lanes = lane;
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
link_bw, &pipe_config->fdi_m_n, false, false);
- ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
+ ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
if (ret == -EDEADLK)
return ret;
@@ -7605,7 +7605,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
intel_crtc_compute_pixel_rate(pipe_config);
if (pipe_config->has_pch_encoder)
- return ironlake_fdi_compute_config(crtc, pipe_config);
+ return ilk_fdi_compute_config(crtc, pipe_config);
return 0;
}
@@ -9018,7 +9018,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
return ret;
}
-static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
+static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
{
struct intel_encoder *encoder;
int i;
@@ -9516,12 +9516,12 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
{
if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
- ironlake_init_pch_refclk(dev_priv);
+ ilk_init_pch_refclk(dev_priv);
else if (HAS_PCH_LPT(dev_priv))
lpt_init_pch_refclk(dev_priv);
}
-static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
+static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -9665,7 +9665,7 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
}
}
-int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
+int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
{
/*
* Account for spread spectrum to avoid
@@ -9676,14 +9676,14 @@ int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
return DIV_ROUND_UP(bps, link_bw * 8);
}
-static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
+static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
{
return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
}
-static void ironlake_compute_dpll(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct dpll *reduced_clock)
+static void ilk_compute_dpll(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state,
+ struct dpll *reduced_clock)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 dpll, fp, fp2;
@@ -9703,7 +9703,7 @@ static void ironlake_compute_dpll(struct intel_crtc *crtc,
fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
- if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
+ if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor))
fp |= FP_CB_TUNE;
if (reduced_clock) {
@@ -9783,8 +9783,8 @@ static void ironlake_compute_dpll(struct intel_crtc *crtc,
crtc_state->dpll_hw_state.fp1 = fp2;
}
-static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state)
+static int ilk_crtc_compute_clock(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_atomic_state *state =
@@ -9808,17 +9808,17 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
if (intel_is_dual_link_lvds(dev_priv)) {
if (refclk == 100000)
- limit = &intel_limits_ironlake_dual_lvds_100m;
+ limit = &intel_limits_ilk_dual_lvds_100m;
else
- limit = &intel_limits_ironlake_dual_lvds;
+ limit = &intel_limits_ilk_dual_lvds;
} else {
if (refclk == 100000)
- limit = &intel_limits_ironlake_single_lvds_100m;
+ limit = &intel_limits_ilk_single_lvds_100m;
else
- limit = &intel_limits_ironlake_single_lvds;
+ limit = &intel_limits_ilk_single_lvds;
}
} else {
- limit = &intel_limits_ironlake_dac;
+ limit = &intel_limits_ilk_dac;
}
if (!crtc_state->clock_set &&
@@ -9828,7 +9828,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
return -EINVAL;
}
- ironlake_compute_dpll(crtc, crtc_state, NULL);
+ ilk_compute_dpll(crtc, crtc_state, NULL);
if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
@@ -9903,8 +9903,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
&pipe_config->dp_m2_n2);
}
-static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
{
intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
&pipe_config->fdi_m_n, NULL);
@@ -10068,8 +10068,8 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
kfree(intel_fb);
}
-static void ironlake_get_pfit_config(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static void ilk_get_pfit_config(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -10092,8 +10092,8 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
}
}
-static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static bool ilk_get_pipe_config(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -10164,7 +10164,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
FDI_DP_PORT_WIDTH_SHIFT) + 1;
- ironlake_get_fdi_m_n_config(crtc, pipe_config);
+ ilk_get_fdi_m_n_config(crtc, pipe_config);
if (HAS_PCH_IBX(dev_priv)) {
/*
@@ -10192,7 +10192,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
>> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
- ironlake_pch_clock_get(crtc, pipe_config);
+ ilk_pch_clock_get(crtc, pipe_config);
} else {
pipe_config->pixel_multiplier = 1;
}
@@ -10200,7 +10200,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
intel_get_pipe_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config);
- ironlake_get_pfit_config(crtc, pipe_config);
+ ilk_get_pfit_config(crtc, pipe_config);
ret = true;
@@ -10561,7 +10561,7 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
FDI_DP_PORT_WIDTH_SHIFT) + 1;
- ironlake_get_fdi_m_n_config(crtc, pipe_config);
+ ilk_get_fdi_m_n_config(crtc, pipe_config);
}
}
@@ -10715,7 +10715,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
if (INTEL_GEN(dev_priv) >= 9)
skl_get_pfit_config(crtc, pipe_config);
else
- ironlake_get_pfit_config(crtc, pipe_config);
+ ilk_get_pfit_config(crtc, pipe_config);
}
if (hsw_crtc_supports_ips(crtc)) {
@@ -11658,8 +11658,8 @@ int intel_dotclock_calculate(int link_freq,
return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
}
-static void ironlake_pch_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static void ilk_pch_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -14245,9 +14245,9 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
skl_pfit_enable(new_crtc_state);
} else if (HAS_PCH_SPLIT(dev_priv)) {
if (new_crtc_state->pch_pfit.enabled)
- ironlake_pfit_enable(new_crtc_state);
+ ilk_pfit_enable(new_crtc_state);
else if (old_crtc_state->pch_pfit.enabled)
- ironlake_pfit_disable(old_crtc_state);
+ ilk_pfit_disable(old_crtc_state);
}
if (INTEL_GEN(dev_priv) >= 11)
@@ -16614,13 +16614,13 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.crtc_enable = hsw_crtc_enable;
dev_priv->display.crtc_disable = hsw_crtc_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
+ dev_priv->display.get_pipe_config = ilk_get_pipe_config;
dev_priv->display.get_initial_plane_config =
i9xx_get_initial_plane_config;
dev_priv->display.crtc_compute_clock =
- ironlake_crtc_compute_clock;
- dev_priv->display.crtc_enable = ironlake_crtc_enable;
- dev_priv->display.crtc_disable = ironlake_crtc_disable;
+ ilk_crtc_compute_clock;
+ dev_priv->display.crtc_enable = ilk_crtc_enable;
+ dev_priv->display.crtc_disable = ilk_crtc_disable;
} else if (IS_CHERRYVIEW(dev_priv)) {
dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
dev_priv->display.get_initial_plane_config =
@@ -16666,7 +16666,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
}
if (IS_GEN(dev_priv, 5)) {
- dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
+ dev_priv->display.fdi_link_train = ilk_fdi_link_train;
} else if (IS_GEN(dev_priv, 6)) {
dev_priv->display.fdi_link_train = gen6_fdi_link_train;
} else if (IS_IVYBRIDGE(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 327376810f66..42093539e91c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -519,7 +519,7 @@ int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
-int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
+int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
struct intel_digital_port *dport,
unsigned int expected_mask);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2f31d226c6eb..991f343579ef 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2509,7 +2509,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
*
* CPT PCH is quite different, having many bits moved
* to the TRANS_DP_CTL register instead. That
- * configuration happens (oddly) in ironlake_pch_enable
+ * configuration happens (oddly) in ilk_pch_enable
*/
/* Preserve the BIOS-computed detected bit. This is
@@ -2653,7 +2653,7 @@ static void edp_wait_backlight_off(struct intel_dp *intel_dp)
* is locked
*/
-static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
+static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 control;
@@ -2703,7 +2703,7 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
if (!edp_have_panel_power(intel_dp))
wait_panel_power_cycle(intel_dp);
- pp = ironlake_get_pp_control(intel_dp);
+ pp = ilk_get_pp_control(intel_dp);
pp |= EDP_FORCE_VDD;
pp_stat_reg = _pp_stat_reg(intel_dp);
@@ -2768,7 +2768,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
intel_dig_port->base.base.base.id,
intel_dig_port->base.base.name);
- pp = ironlake_get_pp_control(intel_dp);
+ pp = ilk_get_pp_control(intel_dp);
pp &= ~EDP_FORCE_VDD;
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
@@ -2864,7 +2864,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
wait_panel_power_cycle(intel_dp);
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
- pp = ironlake_get_pp_control(intel_dp);
+ pp = ilk_get_pp_control(intel_dp);
if (IS_GEN(dev_priv, 5)) {
/* ILK workaround: disable reset around power sequence */
pp &= ~PANEL_POWER_RESET;
@@ -2919,7 +2919,7 @@ static void edp_panel_off(struct intel_dp *intel_dp)
WARN(!intel_dp->want_panel_vdd, "Need [ENCODER:%d:%s] VDD to turn off panel\n",
dig_port->base.base.base.id, dig_port->base.base.name);
- pp = ironlake_get_pp_control(intel_dp);
+ pp = ilk_get_pp_control(intel_dp);
/* We need to switch off panel power _and_ force vdd, for otherwise some
* panels get very unhappy and cease to work. */
pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
@@ -2968,7 +2968,7 @@ static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
u32 pp;
- pp = ironlake_get_pp_control(intel_dp);
+ pp = ilk_get_pp_control(intel_dp);
pp |= EDP_BLC_ENABLE;
I915_WRITE(pp_ctrl_reg, pp);
@@ -3004,7 +3004,7 @@ static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
u32 pp;
- pp = ironlake_get_pp_control(intel_dp);
+ pp = ilk_get_pp_control(intel_dp);
pp &= ~EDP_BLC_ENABLE;
I915_WRITE(pp_ctrl_reg, pp);
@@ -3042,7 +3042,7 @@ static void intel_edp_backlight_power(struct intel_connector *connector,
is_enabled = false;
with_pps_lock(intel_dp, wakeref)
- is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
+ is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
if (is_enabled == enable)
return;
@@ -3079,8 +3079,8 @@ static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
-static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
- const struct intel_crtc_state *pipe_config)
+static void ilk_edp_pll_on(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
{
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -3119,8 +3119,8 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
udelay(200);
}
-static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
- const struct intel_crtc_state *old_crtc_state)
+static void ilk_edp_pll_off(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *old_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -3410,7 +3410,7 @@ static void g4x_post_disable_dp(struct intel_encoder *encoder,
/* Only ilk+ has port A */
if (port == PORT_A)
- ironlake_edp_pll_off(intel_dp, old_crtc_state);
+ ilk_edp_pll_off(intel_dp, old_crtc_state);
}
static void vlv_post_disable_dp(struct intel_encoder *encoder,
@@ -3615,7 +3615,7 @@ static void g4x_pre_enable_dp(struct intel_encoder *encoder,
/* Only ilk+ has port A */
if (port == PORT_A)
- ironlake_edp_pll_on(intel_dp, pipe_config);
+ ilk_edp_pll_on(intel_dp, pipe_config);
}
static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
@@ -6693,7 +6693,7 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
intel_pps_get_registers(intel_dp, ®s);
- pp_ctl = ironlake_get_pp_control(intel_dp);
+ pp_ctl = ilk_get_pp_control(intel_dp);
/* Ensure PPS is unlocked */
if (!HAS_DDI(dev_priv))
@@ -6863,7 +6863,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
* soon as the new power sequencer gets initialized.
*/
if (force_disable_vdd) {
- u32 pp = ironlake_get_pp_control(intel_dp);
+ u32 pp = ilk_get_pp_control(intel_dp);
WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index ab61f88d1d33..d6e0d0be842e 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -126,8 +126,8 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
}
}
-static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
- enum pipe pipe, bool enable)
+static void ilk_set_fifo_underrun_reporting(struct drm_device *dev,
+ enum pipe pipe, bool enable)
{
struct drm_i915_private *dev_priv = to_i915(dev);
u32 bit = (pipe == PIPE_A) ?
@@ -264,7 +264,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
if (HAS_GMCH(dev_priv))
i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
else if (IS_GEN_RANGE(dev_priv, 5, 6))
- ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
+ ilk_set_fifo_underrun_reporting(dev, pipe, enable);
else if (IS_GEN(dev_priv, 7))
ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
else if (INTEL_GEN(dev_priv) >= 8)
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for display: prefer 3-letter acronym
2019-12-18 1:42 [Intel-gfx] [PATCH 0/5] display: prefer 3-letter acronym Lucas De Marchi
` (4 preceding siblings ...)
2019-12-18 1:42 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: prefer 3-letter acronym for ironlake Lucas De Marchi
@ 2019-12-18 3:10 ` Patchwork
2019-12-18 6:07 ` [Intel-gfx] [PATCH 0/5] " Jani Nikula
2019-12-18 19:37 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-12-18 3:10 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: display: prefer 3-letter acronym
URL : https://patchwork.freedesktop.org/series/71079/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7591 -> Patchwork_15822
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/index.html
Known issues
------------
Here are the changes found in Patchwork_15822 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2] ([i915#770])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/fi-hsw-4770r/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-byt-n2820: [PASS][3] -> [INCOMPLETE][4] ([i915#45])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
* igt@kms_frontbuffer_tracking@basic:
- fi-tgl-y: [PASS][5] -> [INCOMPLETE][6] ([i915#435] / [i915#667])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/fi-tgl-y/igt@kms_frontbuffer_tracking@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/fi-tgl-y/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111735]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/fi-tgl-u/igt@gem_ctx_create@basic-files.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/fi-tgl-u/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_gttfill@basic:
- {fi-tgl-guc}: [INCOMPLETE][9] ([fdo#111593]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/fi-tgl-guc/igt@gem_exec_gttfill@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/fi-tgl-guc/igt@gem_exec_gttfill@basic.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [FAIL][11] ([i915#178]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[i915#178]: https://gitlab.freedesktop.org/drm/intel/issues/178
[i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#667]: https://gitlab.freedesktop.org/drm/intel/issues/667
[i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770
Participating hosts (51 -> 27)
------------------------------
Missing (24): fi-snb-2520m fi-skl-lmem fi-icl-guc fi-cml-u2 fi-bxt-dsi fi-bdw-5557u fi-byt-j1900 fi-glk-dsi fi-bwr-2160 fi-ilk-650 fi-ctg-p8600 fi-hsw-4770 fi-elk-e7500 fi-ilk-m540 fi-cfl-8700k fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-kbl-guc fi-kbl-x1275 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7591 -> Patchwork_15822
CI-20190529: 20190529
CI_DRM_7591: 977eb2b7ca4efceca4baf88a612e751f5f819999 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5350: 36431c5923099582e87379aec8e16d43090d06a7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15822: a4de0a21a8155c710cfc7379d0cd1d244dad297c @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a4de0a21a815 drm/i915/display: prefer 3-letter acronym for ironlake
81aef5d3814d drm/i915/display: prefer 3-letter acronym for icelake
b292edbc52f1 drm/i915/display: prefer 3-letter acronym for cannonlake
3abc3a1d32ce drm/i915/display: prefer 3-letter acronym for skylake
6c1cdecc46e5 drm/i915/display: prefer 3-letter acronym for haswell
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 0/5] display: prefer 3-letter acronym
2019-12-18 1:42 [Intel-gfx] [PATCH 0/5] display: prefer 3-letter acronym Lucas De Marchi
` (5 preceding siblings ...)
2019-12-18 3:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success for display: prefer 3-letter acronym Patchwork
@ 2019-12-18 6:07 ` Jani Nikula
2019-12-19 0:27 ` Lucas De Marchi
2019-12-18 19:37 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
7 siblings, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2019-12-18 6:07 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Tue, 17 Dec 2019, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> This bothered me for a while so I decided to give it a try: let's
> normalize on using the platform acronym for function prefixes.
The mixed use has always bothered me too.
Acked-by: Jani Nikula <jani.nikula@intel.com>
(Up next, IS_BROADWELL vs. IS_BDW_ULT etc... ;)
>
> This does the conversion for some platforms. There are others missing,
> but I'm sending this early for the case the idea is shot down.
>
> Lucas De Marchi (5):
> drm/i915/display: prefer 3-letter acronym for haswell
> drm/i915/display: prefer 3-letter acronym for skylake
> drm/i915/display: prefer 3-letter acronym for cannonlake
> drm/i915/display: prefer 3-letter acronym for icelake
> drm/i915/display: prefer 3-letter acronym for ironlake
>
> drivers/gpu/drm/i915/display/intel_crt.c | 6 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_display.c | 278 +++++++++---------
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 34 +--
> .../drm/i915/display/intel_fifo_underrun.c | 6 +-
> 6 files changed, 163 insertions(+), 167 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 5/5] drm/i915/display: prefer 3-letter acronym for ironlake
2019-12-18 1:42 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: prefer 3-letter acronym for ironlake Lucas De Marchi
@ 2019-12-18 12:59 ` Ville Syrjälä
2019-12-19 0:25 ` Lucas De Marchi
0 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjälä @ 2019-12-18 12:59 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, Dec 17, 2019 at 05:42:08PM -0800, Lucas De Marchi wrote:
> We are currently using a mix of platform name and acronym to name the
> functions. Let's prefer the acronym as it should be clear what platform
> it's about and it's shorter, so it doesn't go over 80 columns in a few
> cases. This converts ironlake to ilk where appropriate.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crt.c | 6 +-
> drivers/gpu/drm/i915/display/intel_display.c | 172 +++++++++---------
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 34 ++--
> .../drm/i915/display/intel_fifo_underrun.c | 6 +-
> 5 files changed, 110 insertions(+), 110 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 7a2d36905155..853068b9f909 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -343,7 +343,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
>
> /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
> if (HAS_PCH_LPT(dev_priv) &&
> - (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
> + ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
> return MODE_CLOCK_HIGH;
>
> /* HSW/BDW FDI limited to 4k */
> @@ -419,7 +419,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
> return 0;
> }
>
> -static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
> +static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
> {
> struct drm_device *dev = connector->dev;
> struct intel_crt *crt = intel_attached_crt(connector);
> @@ -527,7 +527,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
> int i, tries = 0;
>
> if (HAS_PCH_SPLIT(dev_priv))
> - return intel_ironlake_crt_detect_hotplug(connector);
> + return ilk_crt_detect_hotplug(connector);
>
> if (IS_VALLEYVIEW(dev_priv))
> return valleyview_crt_detect_hotplug(connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index d3a13737552a..a4f516bc850f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -145,8 +145,8 @@ static const u64 cursor_format_modifiers[] = {
>
> static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config);
> -static void ironlake_pch_clock_get(struct intel_crtc *crtc,
> - struct intel_crtc_state *pipe_config);
> +static void ilk_pch_clock_get(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config);
>
> static int intel_framebuffer_init(struct intel_framebuffer *ifb,
> struct drm_i915_gem_object *obj,
> @@ -157,7 +157,7 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
> const struct intel_link_m_n *m_n,
> const struct intel_link_m_n *m2_n2);
> static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
> -static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
> +static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
> static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
> static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
> static void vlv_prepare_pll(struct intel_crtc *crtc,
> @@ -167,8 +167,8 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> static void intel_crtc_init_scalers(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state);
> static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
> -static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
> -static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
> +static void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
> +static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
> static void intel_modeset_setup_hw_state(struct drm_device *dev,
> struct drm_modeset_acquire_ctx *ctx);
>
> @@ -404,7 +404,7 @@ static const struct intel_limit intel_limits_pineview_lvds = {
> * We calculate clock using (register_value + 2) for N/M1/M2, so here
> * the range value for them is (actual_value - 2).
> */
> -static const struct intel_limit intel_limits_ironlake_dac = {
> +static const struct intel_limit intel_limits_ilk_dac = {
These could be further shortened to just ilk_limits_dac etc.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for display: prefer 3-letter acronym
2019-12-18 1:42 [Intel-gfx] [PATCH 0/5] display: prefer 3-letter acronym Lucas De Marchi
` (6 preceding siblings ...)
2019-12-18 6:07 ` [Intel-gfx] [PATCH 0/5] " Jani Nikula
@ 2019-12-18 19:37 ` Patchwork
7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-12-18 19:37 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: display: prefer 3-letter acronym
URL : https://patchwork.freedesktop.org/series/71079/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7591_full -> Patchwork_15822_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15822_full:
### Piglit changes ###
#### Possible regressions ####
* spec@ext_texture_compression_s3tc@fbo-generatemipmap-formats (NEW):
- {pig-hsw-4770r}: NOTRUN -> [FAIL][1] +51 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/pig-hsw-4770r/spec@ext_texture_compression_s3tc@fbo-generatemipmap-formats.html
New tests
---------
New tests have been introduced between CI_DRM_7591_full and Patchwork_15822_full:
### New Piglit tests (52) ###
* spec@arb_copy_buffer@overlap:
- Statuses : 1 fail(s)
- Exec time: [0.17] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_1d_array 32 1 12 gl_texture_2d_array 32 16 18 11 0 3 5 9 7 14 1 8:
- Statuses : 1 fail(s)
- Exec time: [0.20] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_1d_array 32 1 12 gl_texture_3d 32 16 18 11 0 3 5 9 2 14 1 7:
- Statuses : 1 fail(s)
- Exec time: [0.24] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_1d_array 32 1 12 gl_texture_cube_map_array 32 32 18 11 0 3 5 17 2 14 1 7:
- Statuses : 1 fail(s)
- Exec time: [0.21] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_2d 32 32 1 gl_texture_2d_array 32 16 15 11 12 0 5 7 12 14 8 1:
- Statuses : 1 fail(s)
- Exec time: [0.10] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_2d 32 32 1 gl_texture_3d 32 16 18 11 5 0 5 9 7 14 7 1:
- Statuses : 1 fail(s)
- Exec time: [0.15] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_2d 32 32 1 gl_texture_rectangle 32 16 1 11 12 0 5 7 0 14 9 1:
- Statuses : 1 fail(s)
- Exec time: [0.12] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_2d_array 32 32 15 gl_texture_1d 32 1 1 11 23 7 5 0 0 14 1 1:
- Statuses : 1 fail(s)
- Exec time: [0.11] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_2d_array 32 32 15 gl_texture_1d_array 32 1 16 11 2 5 5 0 7 14 1 7:
- Statuses : 1 fail(s)
- Exec time: [0.15] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_2d_array 32 32 15 gl_texture_2d_array 32 16 15 11 12 5 5 7 2 14 9 9:
- Statuses : 1 fail(s)
- Exec time: [0.27] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_2d_array 32 32 15 gl_texture_3d 32 16 18 11 5 2 5 9 7 14 7 11:
- Statuses : 1 fail(s)
- Exec time: [0.20] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_2d_array 32 32 15 gl_texture_cube_map 32 32 6 11 5 1 5 9 2 14 7 3:
- Statuses : 1 fail(s)
- Exec time: [0.21] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_2d_array 32 32 15 gl_texture_cube_map_array 32 32 18 11 5 2 5 9 7 14 7 11:
- Statuses : 1 fail(s)
- Exec time: [0.19] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_cube_map 32 32 6 gl_texture_2d_array 32 16 15 11 12 1 5 3 2 14 11 4:
- Statuses : 1 fail(s)
- Exec time: [0.20] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_cube_map 32 32 6 gl_texture_3d 32 16 18 11 5 0 5 9 7 14 7 4:
- Statuses : 1 fail(s)
- Exec time: [0.19] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_cube_map 32 32 6 gl_texture_cube_map 32 32 6 11 5 1 5 9 2 14 7 3:
- Statuses : 1 fail(s)
- Exec time: [0.17] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_cube_map 32 32 6 gl_texture_cube_map_array 32 32 18 11 5 1 5 9 9 14 7 5:
- Statuses : 1 fail(s)
- Exec time: [0.28] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_cube_map_array 32 32 18 gl_texture_1d 32 1 1 11 23 7 5 0 0 14 1 1:
- Statuses : 1 fail(s)
- Exec time: [0.16] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_cube_map_array 32 32 18 gl_texture_1d_array 32 1 16 11 2 5 5 0 7 14 1 7:
- Statuses : 1 fail(s)
- Exec time: [0.19] s
* spec@arb_copy_image@arb_copy_image-targets gl_texture_cube_map_array 32 32 18 gl_texture_2d 32 16 1 11 12 13 5 7 0 14 8 1:
- Statuses : 1 fail(s)
- Exec time: [0.14] s
* spec@arb_gpu_shader5@texturegather@vs-r-0-unorm-2drect:
- Statuses : 1 fail(s)
- Exec time: [1.71] s
* spec@arb_gpu_shader5@texturegather@vs-rgb-2-unorm-cube:
- Statuses : 1 fail(s)
- Exec time: [1.69] s
* spec@arb_gpu_shader5@texturegatheroffset@vs-rg-0-float-2d:
- Statuses : 1 fail(s)
- Exec time: [7.34] s
* spec@arb_texture_cube_map_array@fbo-generatemipmap-cubemap array:
- Statuses : 1 fail(s)
- Exec time: [0.70] s
* spec@arb_texture_cube_map_array@texturesize@fs-texturesize-isamplercubearray:
- Statuses : 1 fail(s)
- Exec time: [0.09] s
* spec@arb_texture_cube_map_array@texturesize@tes-texturesize-isamplercubearray:
- Statuses : 1 fail(s)
- Exec time: [0.10] s
* spec@arb_texture_cube_map_array@texturesize@vs-texturesize-samplercubearray:
- Statuses : 1 fail(s)
- Exec time: [0.09] s
* spec@arb_texture_float@multisample-formats 2 gl_arb_texture_float:
- Statuses : 1 fail(s)
- Exec time: [0.29] s
* spec@arb_texture_rg@fbo-clear-formats-float:
- Statuses : 1 fail(s)
- Exec time: [0.12] s
* spec@arb_texture_rg@multisample-formats 4 gl_arb_texture_rg:
- Statuses : 1 fail(s)
- Exec time: [0.23] s
* spec@arb_texture_rg@multisample-formats 6 gl_arb_texture_rg:
- Statuses : 1 fail(s)
- Exec time: [0.20] s
* spec@arb_texture_rg@multisample-formats 8 gl_arb_texture_rg:
- Statuses : 1 fail(s)
- Exec time: [0.21] s
* spec@arb_texture_rg@texwrap formats-float bordercolor:
- Statuses : 1 fail(s)
- Exec time: [0.10] s
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-int_ivec3-position-double_dvec2:
- Statuses : 1 fail(s)
- Exec time: [0.17] s
* spec@ext_packed_float@texwrap formats:
- Statuses : 1 fail(s)
- Exec time: [0.12] s
* spec@ext_texture_array@fbo-depth-array depth-clear:
- Statuses : 1 fail(s)
- Exec time: [26.74] s
* spec@ext_texture_array@fbo-depth-array depth-draw:
- Statuses : 1 fail(s)
- Exec time: [21.70] s
* spec@ext_texture_array@fbo-depth-array depth-layered-clear:
- Statuses : 1 fail(s)
- Exec time: [21.61] s
* spec@ext_texture_array@fbo-depth-array fs-writes-depth:
- Statuses : 1 fail(s)
- Exec time: [22.18] s
* spec@ext_texture_array@fbo-depth-array stencil-clear:
- Statuses : 1 fail(s)
- Exec time: [16.33] s
* spec@ext_texture_compression_rgtc@texwrap formats bordercolor:
- Statuses : 1 fail(s)
- Exec time: [0.11] s
* spec@ext_texture_compression_s3tc@compressedteximage gl_compressed_rgba_s3tc_dxt1_ext:
- Statuses : 1 fail(s)
- Exec time: [0.10] s
* spec@ext_texture_compression_s3tc@fbo-generatemipmap-formats:
- Statuses : 1 fail(s)
- Exec time: [0.24] s
* spec@ext_texture_compression_s3tc@getteximage-targets cube_array s3tc:
- Statuses : 1 fail(s)
- Exec time: [0.10] s
* spec@ext_texture_compression_s3tc@texwrap formats:
- Statuses : 1 fail(s)
- Exec time: [0.12] s
* spec@ext_texture_swizzle@ext_texture_swizzle-swizzle:
- Statuses : 1 fail(s)
- Exec time: [0.15] s
* spec@ext_transform_feedback@order elements triangles:
- Statuses : 1 fail(s)
- Exec time: [0.10] s
* spec@ext_transform_feedback@position-readback-bufferoffset-discard:
- Statuses : 1 fail(s)
- Exec time: [0.12] s
* spec@glsl-1.50@execution@texelfetchoffset@gs-texelfetch-sampler1d:
- Statuses : 1 fail(s)
- Exec time: [0.09] s
* spec@glsl-4.20@execution@vs_in@vs-input-double_dvec4_array5-uint_uvec4_array3-position:
- Statuses : 1 fail(s)
- Exec time: [0.16] s
* spec@glsl-4.20@execution@vs_in@vs-input-uint_uvec2-position-double_dvec4:
- Statuses : 1 fail(s)
- Exec time: [0.15] s
* spec@nv_conditional_render@generatemipmap:
- Statuses : 1 fail(s)
- Exec time: [0.08] s
Known issues
------------
Here are the changes found in Patchwork_15822_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [PASS][2] -> [DMESG-WARN][3] ([i915#180])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-apl1/igt@gem_ctx_isolation@bcs0-s3.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-apl1/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_ctx_isolation@vcs0-s3:
- shard-tglb: [PASS][4] -> [INCOMPLETE][5] ([i915#456])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb6/igt@gem_ctx_isolation@vcs0-s3.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb3/igt@gem_ctx_isolation@vcs0-s3.html
* igt@gem_ctx_persistence@rcs0-mixed-process:
- shard-apl: [PASS][6] -> [FAIL][7] ([i915#679])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-apl1/igt@gem_ctx_persistence@rcs0-mixed-process.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-apl1/igt@gem_ctx_persistence@rcs0-mixed-process.html
* igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#109276] / [fdo#112080]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb5/igt@gem_ctx_persistence@vcs1-queued.html
* igt@gem_ctx_shared@exec-shared-gtt-bsd1:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#616])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb9/igt@gem_ctx_shared@exec-shared-gtt-bsd1.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb6/igt@gem_ctx_shared@exec-shared-gtt-bsd1.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#110841])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#112146]) +2 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb8/igt@gem_exec_async@concurrent-writes-bsd.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html
* igt@gem_exec_parallel@vecs0:
- shard-tglb: [PASS][16] -> [INCOMPLETE][17] ([fdo#111736])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb7/igt@gem_exec_parallel@vecs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb4/igt@gem_exec_parallel@vecs0.html
* igt@gem_exec_schedule@fifo-bsd1:
- shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#109276]) +4 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb2/igt@gem_exec_schedule@fifo-bsd1.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb5/igt@gem_exec_schedule@fifo-bsd1.html
* igt@gem_exec_schedule@preempt-queue-chain-render:
- shard-tglb: [PASS][20] -> [INCOMPLETE][21] ([fdo#111606] / [fdo#111677])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb5/igt@gem_exec_schedule@preempt-queue-chain-render.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-render.html
* igt@gem_persistent_relocs@forked-thrash-inactive:
- shard-tglb: [PASS][22] -> [TIMEOUT][23] ([fdo#112126] / [i915#530])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb3/igt@gem_persistent_relocs@forked-thrash-inactive.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb2/igt@gem_persistent_relocs@forked-thrash-inactive.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [PASS][24] -> [DMESG-WARN][25] ([fdo#111870])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][26] -> [FAIL][27] ([i915#454])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
* igt@i915_selftest@live_gt_timelines:
- shard-tglb: [PASS][28] -> [INCOMPLETE][29] ([i915#455])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb7/igt@i915_selftest@live_gt_timelines.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb1/igt@i915_selftest@live_gt_timelines.html
* igt@i915_suspend@forcewake:
- shard-kbl: [PASS][30] -> [DMESG-WARN][31] ([i915#180]) +4 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-kbl3/igt@i915_suspend@forcewake.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-kbl2/igt@i915_suspend@forcewake.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#54]) +5 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-tglb: [PASS][34] -> [FAIL][35] ([i915#49])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-kbl: [PASS][36] -> [INCOMPLETE][37] ([fdo#103665] / [i915#667])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
- shard-tglb: [PASS][38] -> [INCOMPLETE][39] ([i915#667])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
- shard-iclb: [PASS][40] -> [INCOMPLETE][41] ([i915#123] / [i915#140])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
- shard-skl: [PASS][42] -> [FAIL][43] ([i915#53])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-skl4/igt@kms_pipe_crc_basic@hang-read-crc-pipe-c.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-skl9/igt@kms_pipe_crc_basic@hang-read-crc-pipe-c.html
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-kbl: [PASS][44] -> [INCOMPLETE][45] ([fdo#103665] / [i915#435] / [i915#648] / [i915#667])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-kbl1/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-kbl4/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][46] -> [FAIL][47] ([fdo#108145] / [i915#265])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][48] -> [FAIL][49] ([fdo#108145]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr2_su@frontbuffer:
- shard-tglb: [PASS][50] -> [FAIL][51] ([fdo#111842] / [i915#608])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb3/igt@kms_psr2_su@frontbuffer.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb6/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [PASS][52] -> [SKIP][53] ([fdo#109441])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb3/igt@kms_psr@psr2_sprite_render.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][54] -> [FAIL][55] ([i915#31])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-apl8/igt@kms_setmode@basic.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-apl7/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-tglb: [PASS][56] -> [INCOMPLETE][57] ([i915#456] / [i915#460]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb2/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb2/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
* igt@perf@oa-exponents:
- shard-tglb: [PASS][58] -> [FAIL][59] ([i915#84])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb3/igt@perf@oa-exponents.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb6/igt@perf@oa-exponents.html
* igt@perf_pmu@busy-vcs1:
- shard-iclb: [PASS][60] -> [SKIP][61] ([fdo#112080]) +4 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb2/igt@perf_pmu@busy-vcs1.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb5/igt@perf_pmu@busy-vcs1.html
#### Possible fixes ####
* igt@gem_exec_gttfill@basic:
- shard-tglb: [INCOMPLETE][62] ([fdo#111593]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb6/igt@gem_exec_gttfill@basic.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb1/igt@gem_exec_gttfill@basic.html
* {igt@gem_exec_schedule@pi-common-bsd}:
- shard-iclb: [SKIP][64] ([i915#677]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb2/igt@gem_exec_schedule@pi-common-bsd.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb5/igt@gem_exec_schedule@pi-common-bsd.html
* igt@gem_exec_schedule@preempt-queue-blt:
- shard-tglb: [INCOMPLETE][66] ([fdo#111677]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb6/igt@gem_exec_schedule@preempt-queue-blt.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb5/igt@gem_exec_schedule@preempt-queue-blt.html
* igt@gem_exec_schedule@preempt-self-bsd:
- shard-iclb: [SKIP][68] ([fdo#112146]) -> [PASS][69] +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb4/igt@gem_exec_schedule@preempt-self-bsd.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb8/igt@gem_exec_schedule@preempt-self-bsd.html
* igt@gem_exec_schedule@smoketest-vebox:
- shard-tglb: [INCOMPLETE][70] ([i915#707]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb4/igt@gem_exec_schedule@smoketest-vebox.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb7/igt@gem_exec_schedule@smoketest-vebox.html
* igt@gem_flink_race@flink_name:
- shard-iclb: [INCOMPLETE][72] ([i915#140]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb7/igt@gem_flink_race@flink_name.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb1/igt@gem_flink_race@flink_name.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-iclb: [TIMEOUT][74] ([i915#530]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb8/igt@gem_persistent_relocs@forked-thrashing.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb5/igt@gem_persistent_relocs@forked-thrashing.html
* igt@gem_sync@basic-store-each:
- shard-tglb: [INCOMPLETE][76] ([i915#435] / [i915#472]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb9/igt@gem_sync@basic-store-each.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb9/igt@gem_sync@basic-store-each.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [DMESG-WARN][78] ([fdo#111870]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-snb6/igt@gem_userptr_blits@sync-unmap.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-snb4/igt@gem_userptr_blits@sync-unmap.html
* igt@gem_wait@write-busy-vcs1:
- shard-iclb: [SKIP][80] ([fdo#112080]) -> [PASS][81] +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb8/igt@gem_wait@write-busy-vcs1.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb1/igt@gem_wait@write-busy-vcs1.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [DMESG-WARN][82] ([i915#180]) -> [PASS][83] +2 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-apl4/igt@gem_workarounds@suspend-resume.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-apl2/igt@gem_workarounds@suspend-resume.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][84] ([i915#180]) -> [PASS][85] +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-kbl3/igt@gem_workarounds@suspend-resume-fd.html
* {igt@gen9_exec_parse@allowed-all}:
- shard-glk: [DMESG-WARN][86] ([i915#716]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-glk5/igt@gen9_exec_parse@allowed-all.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-glk4/igt@gen9_exec_parse@allowed-all.html
* igt@i915_selftest@mock_sanitycheck:
- shard-skl: [DMESG-WARN][88] ([i915#747]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-skl2/igt@i915_selftest@mock_sanitycheck.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-skl1/igt@i915_selftest@mock_sanitycheck.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-180:
- shard-tglb: [DMESG-WARN][90] ([i915#851]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb1/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb2/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen:
- shard-skl: [FAIL][92] ([i915#54]) -> [PASS][93] +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html
* igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled:
- shard-tglb: [INCOMPLETE][94] ([i915#667]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb5/igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb5/igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: [FAIL][96] ([i915#79]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-tglb: [INCOMPLETE][98] ([i915#456] / [i915#460] / [i915#516]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb1/igt@kms_flip@flip-vs-suspend-interruptible.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb9/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt:
- shard-tglb: [FAIL][100] ([i915#49]) -> [PASS][101] +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-kbl: [INCOMPLETE][102] ([fdo#103665] / [i915#648] / [i915#667]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-kbl2/igt@kms_plane@pixel-format-pipe-a-planes.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-kbl2/igt@kms_plane@pixel-format-pipe-a-planes.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-tglb: [INCOMPLETE][104] ([i915#456] / [i915#460]) -> [PASS][105] +2 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-tglb4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-tglb4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [SKIP][106] ([fdo#109441]) -> [PASS][107] +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb4/igt@kms_psr@psr2_primary_mmap_gtt.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-snb: [SKIP][108] ([fdo#109271]) -> [PASS][109] +2 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-snb5/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-snb6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][110] ([fdo#109276]) -> [PASS][111] +6 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][112] ([fdo#109276] / [fdo#112080]) -> [FAIL][113] ([IGT#28])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7591/shard-iclb8/igt@gem_ctx_isolation@vcs1-nonpriv.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
[fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
[fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
[fdo#111842]: https://bugs.freedesktop.org/show_bug.cgi?id=111842
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112126]: https://bugs.freedesktop.org/show_bug.cgi?id=112126
[fdo#1121
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15822/index.html
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 5/5] drm/i915/display: prefer 3-letter acronym for ironlake
2019-12-18 12:59 ` Ville Syrjälä
@ 2019-12-19 0:25 ` Lucas De Marchi
0 siblings, 0 replies; 14+ messages in thread
From: Lucas De Marchi @ 2019-12-19 0:25 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Dec 18, 2019 at 02:59:17PM +0200, Ville Syrjälä wrote:
>On Tue, Dec 17, 2019 at 05:42:08PM -0800, Lucas De Marchi wrote:
>> We are currently using a mix of platform name and acronym to name the
>> functions. Let's prefer the acronym as it should be clear what platform
>> it's about and it's shorter, so it doesn't go over 80 columns in a few
>> cases. This converts ironlake to ilk where appropriate.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_crt.c | 6 +-
>> drivers/gpu/drm/i915/display/intel_display.c | 172 +++++++++---------
>> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
>> drivers/gpu/drm/i915/display/intel_dp.c | 34 ++--
>> .../drm/i915/display/intel_fifo_underrun.c | 6 +-
>> 5 files changed, 110 insertions(+), 110 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
>> index 7a2d36905155..853068b9f909 100644
>> --- a/drivers/gpu/drm/i915/display/intel_crt.c
>> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
>> @@ -343,7 +343,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
>>
>> /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
>> if (HAS_PCH_LPT(dev_priv) &&
>> - (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
>> + ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
>> return MODE_CLOCK_HIGH;
>>
>> /* HSW/BDW FDI limited to 4k */
>> @@ -419,7 +419,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
>> return 0;
>> }
>>
>> -static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
>> +static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
>> {
>> struct drm_device *dev = connector->dev;
>> struct intel_crt *crt = intel_attached_crt(connector);
>> @@ -527,7 +527,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
>> int i, tries = 0;
>>
>> if (HAS_PCH_SPLIT(dev_priv))
>> - return intel_ironlake_crt_detect_hotplug(connector);
>> + return ilk_crt_detect_hotplug(connector);
>>
>> if (IS_VALLEYVIEW(dev_priv))
>> return valleyview_crt_detect_hotplug(connector);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index d3a13737552a..a4f516bc850f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -145,8 +145,8 @@ static const u64 cursor_format_modifiers[] = {
>>
>> static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
>> struct intel_crtc_state *pipe_config);
>> -static void ironlake_pch_clock_get(struct intel_crtc *crtc,
>> - struct intel_crtc_state *pipe_config);
>> +static void ilk_pch_clock_get(struct intel_crtc *crtc,
>> + struct intel_crtc_state *pipe_config);
>>
>> static int intel_framebuffer_init(struct intel_framebuffer *ifb,
>> struct drm_i915_gem_object *obj,
>> @@ -157,7 +157,7 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
>> const struct intel_link_m_n *m_n,
>> const struct intel_link_m_n *m2_n2);
>> static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
>> -static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
>> +static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
>> static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
>> static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
>> static void vlv_prepare_pll(struct intel_crtc *crtc,
>> @@ -167,8 +167,8 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>> static void intel_crtc_init_scalers(struct intel_crtc *crtc,
>> struct intel_crtc_state *crtc_state);
>> static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
>> -static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
>> -static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
>> +static void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
>> +static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
>> static void intel_modeset_setup_hw_state(struct drm_device *dev,
>> struct drm_modeset_acquire_ctx *ctx);
>>
>> @@ -404,7 +404,7 @@ static const struct intel_limit intel_limits_pineview_lvds = {
>> * We calculate clock using (register_value + 2) for N/M1/M2, so here
>> * the range value for them is (actual_value - 2).
>> */
>> -static const struct intel_limit intel_limits_ironlake_dac = {
>> +static const struct intel_limit intel_limits_ilk_dac = {
>
>These could be further shortened to just ilk_limits_dac etc.
yeah, I did for some cases but these ones slip through. I'll add those
in next iteration, thanks.
Lucas De Marchi
>
>--
>Ville Syrjälä
>Intel
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 0/5] display: prefer 3-letter acronym
2019-12-18 6:07 ` [Intel-gfx] [PATCH 0/5] " Jani Nikula
@ 2019-12-19 0:27 ` Lucas De Marchi
2019-12-19 0:36 ` Lucas De Marchi
0 siblings, 1 reply; 14+ messages in thread
From: Lucas De Marchi @ 2019-12-19 0:27 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Dec 18, 2019 at 08:07:55AM +0200, Jani Nikula wrote:
>On Tue, 17 Dec 2019, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> This bothered me for a while so I decided to give it a try: let's
>> normalize on using the platform acronym for function prefixes.
>
>The mixed use has always bothered me too.
>
>Acked-by: Jani Nikula <jani.nikula@intel.com>
>
>(Up next, IS_BROADWELL vs. IS_BDW_ULT etc... ;)
actually next are the functions using <platform>_ prefix. I will leave
the IS_* macros for later or bundle them in the respective commits (not
that I didn't change IS_ICELAKE, IS_TIGERLAKE, etc. Maybe it's a good
idea to just bundle them in next iteration.
thanks
Lucas De Marchi
>
>
>>
>> This does the conversion for some platforms. There are others missing,
>> but I'm sending this early for the case the idea is shot down.
>>
>> Lucas De Marchi (5):
>> drm/i915/display: prefer 3-letter acronym for haswell
>> drm/i915/display: prefer 3-letter acronym for skylake
>> drm/i915/display: prefer 3-letter acronym for cannonlake
>> drm/i915/display: prefer 3-letter acronym for icelake
>> drm/i915/display: prefer 3-letter acronym for ironlake
>>
>> drivers/gpu/drm/i915/display/intel_crt.c | 6 +-
>> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
>> drivers/gpu/drm/i915/display/intel_display.c | 278 +++++++++---------
>> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
>> drivers/gpu/drm/i915/display/intel_dp.c | 34 +--
>> .../drm/i915/display/intel_fifo_underrun.c | 6 +-
>> 6 files changed, 163 insertions(+), 167 deletions(-)
>
>--
>Jani Nikula, Intel Open Source Graphics Center
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 0/5] display: prefer 3-letter acronym
2019-12-19 0:27 ` Lucas De Marchi
@ 2019-12-19 0:36 ` Lucas De Marchi
2019-12-19 8:25 ` Jani Nikula
0 siblings, 1 reply; 14+ messages in thread
From: Lucas De Marchi @ 2019-12-19 0:36 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Dec 18, 2019 at 04:27:30PM -0800, Lucas De Marchi wrote:
>On Wed, Dec 18, 2019 at 08:07:55AM +0200, Jani Nikula wrote:
>>On Tue, 17 Dec 2019, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>>This bothered me for a while so I decided to give it a try: let's
>>>normalize on using the platform acronym for function prefixes.
>>
>>The mixed use has always bothered me too.
>>
>>Acked-by: Jani Nikula <jani.nikula@intel.com>
>>
>>(Up next, IS_BROADWELL vs. IS_BDW_ULT etc... ;)
>
>actually next are the functions using <platform>_ prefix. I will leave
>the IS_* macros for later or bundle them in the respective commits (not
>that I didn't change IS_ICELAKE, IS_TIGERLAKE, etc. Maybe it's a good
>idea to just bundle them in next iteration.
>
also I was concentrating only on display/. If we are to change all the
IS_* macros this has to be done in the entire driver. Do you think it
belongs in the same commit? It will be pretty intrusive.
Lucas De Marchi
>thanks
>Lucas De Marchi
>
>
>>
>>
>>>
>>>This does the conversion for some platforms. There are others missing,
>>>but I'm sending this early for the case the idea is shot down.
>>>
>>>Lucas De Marchi (5):
>>> drm/i915/display: prefer 3-letter acronym for haswell
>>> drm/i915/display: prefer 3-letter acronym for skylake
>>> drm/i915/display: prefer 3-letter acronym for cannonlake
>>> drm/i915/display: prefer 3-letter acronym for icelake
>>> drm/i915/display: prefer 3-letter acronym for ironlake
>>>
>>> drivers/gpu/drm/i915/display/intel_crt.c | 6 +-
>>> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
>>> drivers/gpu/drm/i915/display/intel_display.c | 278 +++++++++---------
>>> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
>>> drivers/gpu/drm/i915/display/intel_dp.c | 34 +--
>>> .../drm/i915/display/intel_fifo_underrun.c | 6 +-
>>> 6 files changed, 163 insertions(+), 167 deletions(-)
>>
>>--
>>Jani Nikula, Intel Open Source Graphics Center
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 0/5] display: prefer 3-letter acronym
2019-12-19 0:36 ` Lucas De Marchi
@ 2019-12-19 8:25 ` Jani Nikula
0 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2019-12-19 8:25 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Wed, 18 Dec 2019, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Wed, Dec 18, 2019 at 04:27:30PM -0800, Lucas De Marchi wrote:
>>On Wed, Dec 18, 2019 at 08:07:55AM +0200, Jani Nikula wrote:
>>>On Tue, 17 Dec 2019, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>>>This bothered me for a while so I decided to give it a try: let's
>>>>normalize on using the platform acronym for function prefixes.
>>>
>>>The mixed use has always bothered me too.
>>>
>>>Acked-by: Jani Nikula <jani.nikula@intel.com>
>>>
>>>(Up next, IS_BROADWELL vs. IS_BDW_ULT etc... ;)
>>
>>actually next are the functions using <platform>_ prefix. I will leave
>>the IS_* macros for later or bundle them in the respective commits (not
>>that I didn't change IS_ICELAKE, IS_TIGERLAKE, etc. Maybe it's a good
>>idea to just bundle them in next iteration.
>>
>
> also I was concentrating only on display/. If we are to change all the
> IS_* macros this has to be done in the entire driver. Do you think it
> belongs in the same commit? It will be pretty intrusive.
Maybe just leave the IS_* later for now? Because it's going to be one
big ugly commit, or you have to add the TLA versions on the side and
migrate gradually. Either way it's pretty painful I think...
BR,
Jani.
>
> Lucas De Marchi
>
>>thanks
>>Lucas De Marchi
>>
>>
>>>
>>>
>>>>
>>>>This does the conversion for some platforms. There are others missing,
>>>>but I'm sending this early for the case the idea is shot down.
>>>>
>>>>Lucas De Marchi (5):
>>>> drm/i915/display: prefer 3-letter acronym for haswell
>>>> drm/i915/display: prefer 3-letter acronym for skylake
>>>> drm/i915/display: prefer 3-letter acronym for cannonlake
>>>> drm/i915/display: prefer 3-letter acronym for icelake
>>>> drm/i915/display: prefer 3-letter acronym for ironlake
>>>>
>>>> drivers/gpu/drm/i915/display/intel_crt.c | 6 +-
>>>> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
>>>> drivers/gpu/drm/i915/display/intel_display.c | 278 +++++++++---------
>>>> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
>>>> drivers/gpu/drm/i915/display/intel_dp.c | 34 +--
>>>> .../drm/i915/display/intel_fifo_underrun.c | 6 +-
>>>> 6 files changed, 163 insertions(+), 167 deletions(-)
>>>
>>>--
>>>Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2019-12-19 8:25 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-18 1:42 [Intel-gfx] [PATCH 0/5] display: prefer 3-letter acronym Lucas De Marchi
2019-12-18 1:42 ` [Intel-gfx] [PATCH 1/5] drm/i915/display: prefer 3-letter acronym for haswell Lucas De Marchi
2019-12-18 1:42 ` [Intel-gfx] [PATCH 2/5] drm/i915/display: prefer 3-letter acronym for skylake Lucas De Marchi
2019-12-18 1:42 ` [Intel-gfx] [PATCH 3/5] drm/i915/display: prefer 3-letter acronym for cannonlake Lucas De Marchi
2019-12-18 1:42 ` [Intel-gfx] [PATCH 4/5] drm/i915/display: prefer 3-letter acronym for icelake Lucas De Marchi
2019-12-18 1:42 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: prefer 3-letter acronym for ironlake Lucas De Marchi
2019-12-18 12:59 ` Ville Syrjälä
2019-12-19 0:25 ` Lucas De Marchi
2019-12-18 3:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success for display: prefer 3-letter acronym Patchwork
2019-12-18 6:07 ` [Intel-gfx] [PATCH 0/5] " Jani Nikula
2019-12-19 0:27 ` Lucas De Marchi
2019-12-19 0:36 ` Lucas De Marchi
2019-12-19 8:25 ` Jani Nikula
2019-12-18 19:37 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
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