From: Marc Zyngier <maz@kernel.org>
To: Reiji Watanabe <reijiw@google.com>
Cc: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev,
kvm@vger.kernel.org, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Ricardo Koller <ricarkol@google.com>
Subject: Re: [PATCH v2 11/14] KVM: arm64: PMU: Allow ID_AA64DFR0_EL1.PMUver to be set from userspace
Date: Sun, 06 Nov 2022 12:47:54 +0000 [thread overview]
Message-ID: <87pme0fdvp.wl-maz@kernel.org> (raw)
In-Reply-To: <CAAeT=Fzp-7MMBJshAAQBgFwXLH2z5ASDgmDBLNJsQoFA=MSciw@mail.gmail.com>
Hi Reiji,
On Fri, 04 Nov 2022 15:53:21 +0000,
Reiji Watanabe <reijiw@google.com> wrote:
>
> BTW, if we have no intention of supporting a mix of vCPUs with and
> without PMU, I think it would be nice if we have a clear comment on
> that in the code. Or I'm hoping to disallow it if possible though.
I'm not sure we're in a position to do this right now. The current API
has always (for good or bad reasons) been per-vcpu as it is tied to
the vcpu initialisation.
However, once we move to a sysreg-based API to control the vcpu
features, we can revisit this and say that some features have a
VM-wide effect if the vcpus have been created with some special flag
(or some other TBD mechanism).
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Reiji Watanabe <reijiw@google.com>
Cc: kvm@vger.kernel.org, kvmarm@lists.linux.dev,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 11/14] KVM: arm64: PMU: Allow ID_AA64DFR0_EL1.PMUver to be set from userspace
Date: Sun, 06 Nov 2022 12:47:54 +0000 [thread overview]
Message-ID: <87pme0fdvp.wl-maz@kernel.org> (raw)
In-Reply-To: <CAAeT=Fzp-7MMBJshAAQBgFwXLH2z5ASDgmDBLNJsQoFA=MSciw@mail.gmail.com>
Hi Reiji,
On Fri, 04 Nov 2022 15:53:21 +0000,
Reiji Watanabe <reijiw@google.com> wrote:
>
> BTW, if we have no intention of supporting a mix of vCPUs with and
> without PMU, I think it would be nice if we have a clear comment on
> that in the code. Or I'm hoping to disallow it if possible though.
I'm not sure we're in a position to do this right now. The current API
has always (for good or bad reasons) been per-vcpu as it is tied to
the vcpu initialisation.
However, once we move to a sysreg-based API to control the vcpu
features, we can revisit this and say that some features have a
VM-wide effect if the vcpus have been created with some special flag
(or some other TBD mechanism).
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Reiji Watanabe <reijiw@google.com>
Cc: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev,
kvm@vger.kernel.org, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Ricardo Koller <ricarkol@google.com>
Subject: Re: [PATCH v2 11/14] KVM: arm64: PMU: Allow ID_AA64DFR0_EL1.PMUver to be set from userspace
Date: Sun, 06 Nov 2022 12:47:54 +0000 [thread overview]
Message-ID: <87pme0fdvp.wl-maz@kernel.org> (raw)
In-Reply-To: <CAAeT=Fzp-7MMBJshAAQBgFwXLH2z5ASDgmDBLNJsQoFA=MSciw@mail.gmail.com>
Hi Reiji,
On Fri, 04 Nov 2022 15:53:21 +0000,
Reiji Watanabe <reijiw@google.com> wrote:
>
> BTW, if we have no intention of supporting a mix of vCPUs with and
> without PMU, I think it would be nice if we have a clear comment on
> that in the code. Or I'm hoping to disallow it if possible though.
I'm not sure we're in a position to do this right now. The current API
has always (for good or bad reasons) been per-vcpu as it is tied to
the vcpu initialisation.
However, once we move to a sysreg-based API to control the vcpu
features, we can revisit this and say that some features have a
VM-wide effect if the vcpus have been created with some special flag
(or some other TBD mechanism).
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-11-06 12:48 UTC|newest]
Thread overview: 87+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-28 10:53 [PATCH v2 00/14] KVM: arm64: PMU: Fixing chained events, and PMUv3p5 support Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 01/14] arm64: Add ID_DFR0_EL1.PerfMon values for PMUv3p7 and IMP_DEF Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-11-04 20:47 ` Oliver Upton
2022-11-04 20:47 ` Oliver Upton
2022-11-04 20:47 ` Oliver Upton
2022-11-05 9:42 ` Marc Zyngier
2022-11-05 9:42 ` Marc Zyngier
2022-11-05 9:42 ` Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 02/14] KVM: arm64: PMU: Align chained counter implementation with architecture pseudocode Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 03/14] KVM: arm64: PMU: Always advertise the CHAIN event Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-11-12 8:01 ` Reiji Watanabe
2022-11-12 8:01 ` Reiji Watanabe
2022-11-12 8:01 ` Reiji Watanabe
2022-10-28 10:53 ` [PATCH v2 04/14] KVM: arm64: PMU: Distinguish between 64bit counter and 64bit overflow Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 05/14] KVM: arm64: PMU: Narrow the overflow checking when required Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 06/14] KVM: arm64: PMU: Only narrow counters that are not 64bit wide Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 07/14] KVM: arm64: PMU: Add counter_index_to_*reg() helpers Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 08/14] KVM: arm64: PMU: Simplify setting a counter to a specific value Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 09/14] KVM: arm64: PMU: Do not let AArch32 change the counters' top 32 bits Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 10/14] KVM: arm64: PMU: Move the ID_AA64DFR0_EL1.PMUver limit to VM creation Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-11-03 4:55 ` Reiji Watanabe
2022-11-03 4:55 ` Reiji Watanabe
2022-11-03 4:55 ` Reiji Watanabe
2022-11-03 8:44 ` Marc Zyngier
2022-11-03 8:44 ` Marc Zyngier
2022-11-03 8:44 ` Marc Zyngier
2022-11-03 14:52 ` Reiji Watanabe
2022-11-03 14:52 ` Reiji Watanabe
2022-11-03 14:52 ` Reiji Watanabe
2022-10-28 10:53 ` [PATCH v2 11/14] KVM: arm64: PMU: Allow ID_AA64DFR0_EL1.PMUver to be set from userspace Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-10-28 10:53 ` Marc Zyngier
2022-11-03 5:31 ` Reiji Watanabe
2022-11-03 5:31 ` Reiji Watanabe
2022-11-03 5:31 ` Reiji Watanabe
2022-11-03 10:24 ` Marc Zyngier
2022-11-03 10:24 ` Marc Zyngier
2022-11-03 10:24 ` Marc Zyngier
2022-11-04 7:00 ` Reiji Watanabe
2022-11-04 7:00 ` Reiji Watanabe
2022-11-04 7:00 ` Reiji Watanabe
2022-11-04 12:20 ` Marc Zyngier
2022-11-04 12:20 ` Marc Zyngier
2022-11-04 12:20 ` Marc Zyngier
2022-11-04 15:53 ` Reiji Watanabe
2022-11-04 15:53 ` Reiji Watanabe
2022-11-04 15:53 ` Reiji Watanabe
2022-11-06 12:47 ` Marc Zyngier [this message]
2022-11-06 12:47 ` Marc Zyngier
2022-11-06 12:47 ` Marc Zyngier
2022-11-08 5:36 ` Reiji Watanabe
2022-11-08 5:36 ` Reiji Watanabe
2022-11-08 5:36 ` Reiji Watanabe
2022-11-13 10:56 ` Marc Zyngier
2022-11-13 10:56 ` Marc Zyngier
2022-11-13 10:56 ` Marc Zyngier
2022-10-28 10:54 ` [PATCH v2 12/14] KVM: arm64: PMU: Allow ID_DFR0_EL1.PerfMon " Marc Zyngier
2022-10-28 10:54 ` Marc Zyngier
2022-10-28 10:54 ` Marc Zyngier
2022-10-28 10:54 ` [PATCH v2 13/14] KVM: arm64: PMU: Implement PMUv3p5 long counter support Marc Zyngier
2022-10-28 10:54 ` Marc Zyngier
2022-10-28 10:54 ` Marc Zyngier
2022-10-28 10:54 ` [PATCH v2 14/14] KVM: arm64: PMU: Allow PMUv3p5 to be exposed to the guest Marc Zyngier
2022-10-28 10:54 ` Marc Zyngier
2022-10-28 10:54 ` Marc Zyngier
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