* [PATCH] target/ppc: raise HV interrupts for partition table entry problems
@ 2022-02-14 12:31 Nicholas Piggin
2022-02-14 13:18 ` Daniel Henrique Barboza
2022-02-14 13:21 ` Fabiano Rosas
0 siblings, 2 replies; 3+ messages in thread
From: Nicholas Piggin @ 2022-02-14 12:31 UTC (permalink / raw)
To: qemu-ppc; +Cc: qemu-devel, Nicholas Piggin
Invalid or missing partition table entry exceptions should cause HV
interrupts. HDSISR is set to bad MMU config, which is consistent with
the ISA and experimentally matches what POWER9 generates.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/mmu-radix64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 040c055bff..54fb3ce98d 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -560,13 +560,13 @@ static bool ppc_radix64_xlate_impl(PowerPCCPU *cpu, vaddr eaddr,
} else {
if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
if (guest_visible) {
- ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE);
+ ppc_radix64_raise_hsi(cpu, access_type, eaddr, eaddr, DSISR_R_BADCONFIG);
}
return false;
}
if (!validate_pate(cpu, lpid, &pate)) {
if (guest_visible) {
- ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_R_BADCONFIG);
+ ppc_radix64_raise_hsi(cpu, access_type, eaddr, eaddr, DSISR_R_BADCONFIG);
}
return false;
}
--
2.23.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] target/ppc: raise HV interrupts for partition table entry problems
2022-02-14 12:31 [PATCH] target/ppc: raise HV interrupts for partition table entry problems Nicholas Piggin
@ 2022-02-14 13:18 ` Daniel Henrique Barboza
2022-02-14 13:21 ` Fabiano Rosas
1 sibling, 0 replies; 3+ messages in thread
From: Daniel Henrique Barboza @ 2022-02-14 13:18 UTC (permalink / raw)
To: Nicholas Piggin, qemu-ppc; +Cc: qemu-devel
On 2/14/22 09:31, Nicholas Piggin wrote:
> Invalid or missing partition table entry exceptions should cause HV
> interrupts. HDSISR is set to bad MMU config, which is consistent with
> the ISA and experimentally matches what POWER9 generates.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> target/ppc/mmu-radix64.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
> index 040c055bff..54fb3ce98d 100644
> --- a/target/ppc/mmu-radix64.c
> +++ b/target/ppc/mmu-radix64.c
> @@ -560,13 +560,13 @@ static bool ppc_radix64_xlate_impl(PowerPCCPU *cpu, vaddr eaddr,
> } else {
> if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
> if (guest_visible) {
> - ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE);
> + ppc_radix64_raise_hsi(cpu, access_type, eaddr, eaddr, DSISR_R_BADCONFIG);
> }
> return false;
> }
> if (!validate_pate(cpu, lpid, &pate)) {
> if (guest_visible) {
> - ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_R_BADCONFIG);
> + ppc_radix64_raise_hsi(cpu, access_type, eaddr, eaddr, DSISR_R_BADCONFIG);
> }
> return false;
> }
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] target/ppc: raise HV interrupts for partition table entry problems
2022-02-14 12:31 [PATCH] target/ppc: raise HV interrupts for partition table entry problems Nicholas Piggin
2022-02-14 13:18 ` Daniel Henrique Barboza
@ 2022-02-14 13:21 ` Fabiano Rosas
1 sibling, 0 replies; 3+ messages in thread
From: Fabiano Rosas @ 2022-02-14 13:21 UTC (permalink / raw)
To: Nicholas Piggin, qemu-ppc; +Cc: qemu-devel, Nicholas Piggin
Nicholas Piggin <npiggin@gmail.com> writes:
> Invalid or missing partition table entry exceptions should cause HV
> interrupts. HDSISR is set to bad MMU config, which is consistent with
> the ISA and experimentally matches what POWER9 generates.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> target/ppc/mmu-radix64.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
> index 040c055bff..54fb3ce98d 100644
> --- a/target/ppc/mmu-radix64.c
> +++ b/target/ppc/mmu-radix64.c
> @@ -560,13 +560,13 @@ static bool ppc_radix64_xlate_impl(PowerPCCPU *cpu, vaddr eaddr,
> } else {
> if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
> if (guest_visible) {
> - ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE);
> + ppc_radix64_raise_hsi(cpu, access_type, eaddr, eaddr, DSISR_R_BADCONFIG);
> }
> return false;
> }
> if (!validate_pate(cpu, lpid, &pate)) {
> if (guest_visible) {
> - ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_R_BADCONFIG);
> + ppc_radix64_raise_hsi(cpu, access_type, eaddr, eaddr, DSISR_R_BADCONFIG);
> }
> return false;
> }
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-02-14 14:20 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2022-02-14 12:31 [PATCH] target/ppc: raise HV interrupts for partition table entry problems Nicholas Piggin
2022-02-14 13:18 ` Daniel Henrique Barboza
2022-02-14 13:21 ` Fabiano Rosas
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