[PATCH 0/2] add TOC support

[PATCH 0/2] add TOC support

[Sven Schnelle]

This adds support for the TOC switches found on most PA-RISC
machines. I tested this on my c8000 and a HP 16702A, which is
basically a B160L with some logic analyzer hardware.

Sven Schnelle (2):
  parisc/firmware: add functions to retrieve TOC data
  parisc: add support for TOC (transfer of control)

 arch/parisc/include/asm/pdc.h       |  2 +
 arch/parisc/include/asm/processor.h |  4 ++
 arch/parisc/include/uapi/asm/pdc.h  | 28 +++++++++-
 arch/parisc/kernel/entry.S          | 69 +++++++++++++++++++++++++
 arch/parisc/kernel/firmware.c       | 32 ++++++++++++
 arch/parisc/kernel/processor.c      | 21 ++++++++
 arch/parisc/kernel/traps.c          | 79 +++++++++++++++++++++++++++++
 7 files changed, 233 insertions(+), 2 deletions(-)

-- 
2.33.0

[PATCH 1/2] parisc/firmware: add functions to retrieve TOC data

[Sven Schnelle]

Add functions to retrieve TOC data from firmware both
for 1.1 and 2.0 PDC.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
---
 arch/parisc/include/asm/pdc.h      |  2 ++
 arch/parisc/include/uapi/asm/pdc.h | 22 ++++++++++++++++++++
 arch/parisc/kernel/firmware.c      | 32 ++++++++++++++++++++++++++++++
 3 files changed, 56 insertions(+)

diff --git a/arch/parisc/include/asm/pdc.h b/arch/parisc/include/asm/pdc.h
index b388d8176588..18b957a8630d 100644
--- a/arch/parisc/include/asm/pdc.h
+++ b/arch/parisc/include/asm/pdc.h
@@ -51,6 +51,8 @@ int pdc_spaceid_bits(unsigned long *space_bits);
 int pdc_btlb_info(struct pdc_btlb_info *btlb);
 int pdc_mem_map_hpa(struct pdc_memory_map *r_addr, struct pdc_module_path *mod_path);
 #endif /* !CONFIG_PA20 */
+int pdc_pim_toc11(struct pdc_toc_pim_11 *ret);
+int pdc_pim_toc20(struct pdc_toc_pim_20 *ret);
 int pdc_lan_station_id(char *lan_addr, unsigned long net_hpa);
 
 int pdc_stable_read(unsigned long staddr, void *memaddr, unsigned long count);
diff --git a/arch/parisc/include/uapi/asm/pdc.h b/arch/parisc/include/uapi/asm/pdc.h
index 15211723ebf5..ad51df8ba952 100644
--- a/arch/parisc/include/uapi/asm/pdc.h
+++ b/arch/parisc/include/uapi/asm/pdc.h
@@ -689,6 +689,28 @@ struct pdc_hpmc_pim_20 { /* PDC_PIM */
 	unsigned long long fr[32];
 };
 
+struct pdc_toc_pim_11 {
+	unsigned int gr[32];
+	unsigned int cr[32];
+	unsigned int sr[8];
+	unsigned int iasq_back;
+	unsigned int iaoq_back;
+	unsigned int check_type;
+	unsigned int hversion;
+	unsigned int cpu_state;
+};
+
+struct pdc_toc_pim_20 {
+	unsigned long long gr[32];
+	unsigned long long cr[32];
+	unsigned long long sr[8];
+	unsigned long long iasq_back;
+	unsigned long long iaoq_back;
+	unsigned int check_type;
+	unsigned int hversion;
+	unsigned int cpu_state;
+};
+
 #endif /* !defined(__ASSEMBLY__) */
 
 #endif /* _UAPI_PARISC_PDC_H */
diff --git a/arch/parisc/kernel/firmware.c b/arch/parisc/kernel/firmware.c
index 7034227dbdf3..9179b4409b63 100644
--- a/arch/parisc/kernel/firmware.c
+++ b/arch/parisc/kernel/firmware.c
@@ -1061,6 +1061,38 @@ int pdc_mem_pdt_read_entries(struct pdc_mem_read_pdt *pret,
 	return retval;
 }
 
+/**
+ * pdc_pim_toc11 - Fetch TOC PIM 1.1 data from firmware.
+ * @ret: pointer to return buffer
+ */
+int pdc_pim_toc11(struct pdc_toc_pim_11 *ret)
+{
+	int retval;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pdc_lock, flags);
+	retval = mem_pdc_call(PDC_PIM, PDC_PIM_TOC, __pa(pdc_result),
+			      __pa(ret), sizeof(struct pdc_toc_pim_11));
+	spin_unlock_irqrestore(&pdc_lock, flags);
+	return retval;
+}
+
+/**
+ * pdc_pim_toc20 - Fetch TOC PIM 2.0 data from firmware.
+ * @ret: pointer to return buffer
+ */
+int pdc_pim_toc20(struct pdc_toc_pim_20 *ret)
+{
+	int retval;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pdc_lock, flags);
+	retval = mem_pdc_call(PDC_PIM, PDC_PIM_TOC, __pa(pdc_result),
+			      __pa(ret), sizeof(struct pdc_toc_pim_20));
+	spin_unlock_irqrestore(&pdc_lock, flags);
+	return retval;
+}
+
 /**
  * pdc_tod_set - Set the Time-Of-Day clock.
  * @sec: The number of seconds since epoch.
-- 
2.33.0

[PATCH 2/2] parisc: add support for TOC (transfer of control)

[Sven Schnelle]

Almost all PA-RISC machines have either a button that
is labeled with 'TOC' or a BMC function to trigger a TOC.
TOC is a non-maskable interrupt that is sent to the processor.
This can be used for diagnostic purposes like obtaining a
stack trace/register dump or to enter KDB/KGDB.

As an example, on my c8000, TOC can be used with:

CONFIG_KGDB=y
CONFIG_KGDB_KDB=y

and the 'kgdboc=ttyS0,115200' appended to the command line.

Press ^( on serial console, which will enter the BMC command line,
and enter 'TOC s':

root@(none):/# (
cli>TOC s
Sending TOC/INIT.
<Cpu3> 2800035d03e00000  0000000040c21ac8  CC_ERR_CHECK_TOC
<Cpu0> 2800035d00e00000  0000000040c21ad0  CC_ERR_CHECK_TOC
<Cpu2> 2800035d02e00000  0000000040c21ac8  CC_ERR_CHECK_TOC
<Cpu1> 2800035d01e00000  0000000040c21ad0  CC_ERR_CHECK_TOC
<Cpu3> 37000f7303e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
<Cpu0> 37000f7300e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
<Cpu2> 37000f7302e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
<Cpu1> 37000f7301e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
<Cpu3> 4300100803e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC
<Cpu0> 4300100800e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC
<Cpu2> 4300100802e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC
<Cpu1> 4300100801e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC

Entering kdb (current=0x00000000411cef80, pid 0) on processor 0 due to NonMaskable Interrupt @ 0x40c21ad0
[0]kdb>

Signed-off-by: Sven Schnelle <svens@stackframe.org>
---
 arch/parisc/include/asm/processor.h |  4 ++
 arch/parisc/include/uapi/asm/pdc.h  |  6 ++-
 arch/parisc/kernel/entry.S          | 69 +++++++++++++++++++++++++
 arch/parisc/kernel/processor.c      | 21 ++++++++
 arch/parisc/kernel/traps.c          | 79 +++++++++++++++++++++++++++++
 5 files changed, 177 insertions(+), 2 deletions(-)

diff --git a/arch/parisc/include/asm/processor.h b/arch/parisc/include/asm/processor.h
index eeb7da064289..1e9a4c986921 100644
--- a/arch/parisc/include/asm/processor.h
+++ b/arch/parisc/include/asm/processor.h
@@ -294,6 +294,10 @@ extern int _parisc_requires_coherency;
 
 extern int running_on_qemu;
 
+extern void toc_handler(void);
+extern unsigned int toc_handler_size;
+extern unsigned int toc_handler_csum;
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __ASM_PARISC_PROCESSOR_H */
diff --git a/arch/parisc/include/uapi/asm/pdc.h b/arch/parisc/include/uapi/asm/pdc.h
index ad51df8ba952..acc633c15722 100644
--- a/arch/parisc/include/uapi/asm/pdc.h
+++ b/arch/parisc/include/uapi/asm/pdc.h
@@ -398,8 +398,10 @@ struct zeropage {
 	/* int	(*vec_rendz)(void); */
 	unsigned int vec_rendz;
 	int	vec_pow_fail_flen;
-	int	vec_pad[10];		
-	
+	int	vec_pad0[3];
+	unsigned int vec_toc_hi;
+	int	vec_pad1[6];
+
 	/* [0x040] reserved processor dependent */
 	int	pad0[112];
 
diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index 9f939afe6b88..f486f3b51075 100644
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -28,6 +28,7 @@
 
 #include <linux/linkage.h>
 #include <linux/pgtable.h>
+#include <linux/threads.h>
 
 #ifdef CONFIG_64BIT
 	.level 2.0w
@@ -2414,3 +2415,71 @@ ENTRY_CFI(set_register)
 	copy    %r1,%r31
 ENDPROC_CFI(set_register)
 
+	.import toc_intr,code
+	ENTRY_CFI(toc_handler)
+	/*
+	 * synchronize CPUs and obtain offset
+	 * for stack setup.
+	 */
+	load32		PA(toc_lock),%r1
+0:	ldcw,co		0(%r1),%r2
+	cmpib,=		0,%r2,0b
+	nop
+	addi		1,%r2,%r4
+	stw		%r4,0(%r1)
+	addi		-1,%r2,%r4
+
+	load32	PA(toc_stack),sp
+	/*
+	 * deposit CPU number into stack address,
+	 * so every CPU will have its own stack.
+	 */
+	depw	%r4,18,2,%sp
+
+	/* setup pt_regs on stack and save the
+	 * floating point registers. PIM_TOC doesn't
+	 * save fp registers, so we're doing it here.
+	 */
+	copy	%sp,%arg0
+	ldo	PT_SZ_ALGN(%sp), %sp
+
+	/* clear pt_regs */
+	copy	%arg0,%r1
+0:	cmpb,<<,n %r1,%sp,0b
+	stw,ma	%r0,4(%r1)
+
+	ldo	PT_FR0(%arg0),%r25
+	save_fp	%r25
+
+	/* go virtual */
+	load32	PA(swapper_pg_dir),%r4
+	mtctl	%r4,%cr24
+	mtctl	%r4,%cr25
+
+	/* Clear sr4-sr7 */
+	mtsp	%r0, %sr4
+	mtsp	%r0, %sr5
+	mtsp	%r0, %sr6
+	mtsp	%r0, %sr7
+
+	tovirt_r1 %sp
+	tovirt_r1 %arg0
+	virt_map
+
+	loadgp
+#ifdef CONFIG_64BIT
+	ldo	-16(%sp),%r29
+#endif
+	b,l	toc_intr,%r2
+	nop
+0:	b	0b
+ENDPROC_CFI(toc_handler)
+
+SYM_DATA(toc_handler_csum, .long 0)
+SYM_DATA(toc_handler_size, .long . - toc_handler)
+SYM_DATA(toc_lock, .long 1)
+
+	__PAGE_ALIGNED_BSS
+	.align 16384*NR_CPUS
+toc_stack:
+	.block 16384*NR_CPUS
diff --git a/arch/parisc/kernel/processor.c b/arch/parisc/kernel/processor.c
index 1b6129e7d776..582caf99d952 100644
--- a/arch/parisc/kernel/processor.c
+++ b/arch/parisc/kernel/processor.c
@@ -28,6 +28,7 @@
 #include <asm/pdcpat.h>
 #include <asm/irq.h>		/* for struct irq_region */
 #include <asm/parisc-device.h>
+#include <asm/sections.h>
 
 struct system_cpuinfo_parisc boot_cpu_data __ro_after_init;
 EXPORT_SYMBOL(boot_cpu_data);
@@ -453,6 +454,25 @@ static struct parisc_driver cpu_driver __refdata = {
 	.probe		= processor_probe
 };
 
+static __init void setup_toc(void)
+{
+	unsigned int csum = 0;
+	unsigned long toc_code = (unsigned long)dereference_function_descriptor(toc_handler);
+	int i;
+
+	PAGE0->vec_toc = __pa(toc_code) & 0xffffffff;
+#ifdef CONFIG_64BIT
+	PAGE0->vec_toc_hi = __pa(toc_code) >> 32;
+#else
+	PAGE0->vec_toc_hi = 0;
+#endif
+	PAGE0->vec_toclen = toc_handler_size;
+
+	for (i = 0; i < toc_handler_size/4; i++)
+		csum += ((u32 *)toc_code)[i];
+	toc_handler_csum = -csum;
+}
+
 /**
  * processor_init - Processor initialization procedure.
  *
@@ -460,5 +480,6 @@ static struct parisc_driver cpu_driver __refdata = {
  */
 void __init processor_init(void)
 {
+	setup_toc();
 	register_parisc_driver(&cpu_driver);
 }
diff --git a/arch/parisc/kernel/traps.c b/arch/parisc/kernel/traps.c
index 747c328fb886..e847d37eda3a 100644
--- a/arch/parisc/kernel/traps.c
+++ b/arch/parisc/kernel/traps.c
@@ -30,6 +30,8 @@
 #include <linux/ratelimit.h>
 #include <linux/uaccess.h>
 #include <linux/kdebug.h>
+#include <linux/kdb.h>
+#include <linux/reboot.h>
 
 #include <asm/assembly.h>
 #include <asm/io.h>
@@ -472,6 +474,83 @@ void parisc_terminate(char *msg, struct pt_regs *regs, int code, unsigned long o
 	panic(msg);
 }
 
+static void toc20_to_pt_regs(struct pt_regs *regs, struct pdc_toc_pim_20 *toc)
+{
+	int i;
+
+	regs->gr[0] = (unsigned long)toc->cr[22];
+
+	for (i = 1; i < 32; i++)
+		regs->gr[i] = (unsigned long)toc->gr[i];
+
+	for (i = 0; i < 8; i++)
+		regs->sr[i] = (unsigned long)toc->sr[i];
+
+	regs->iasq[0] = (unsigned long)toc->cr[17];
+	regs->iasq[1] = (unsigned long)toc->iasq_back;
+	regs->iaoq[0] = (unsigned long)toc->cr[18];
+	regs->iaoq[1] = (unsigned long)toc->iaoq_back;
+
+	regs->sar = (unsigned long)toc->cr[11];
+	regs->iir = (unsigned long)toc->cr[19];
+	regs->isr = (unsigned long)toc->cr[20];
+	regs->ior = (unsigned long)toc->cr[21];
+}
+
+static void toc11_to_pt_regs(struct pt_regs *regs, struct pdc_toc_pim_11 *toc)
+{
+	int i;
+
+	regs->gr[0] = toc->cr[22];
+
+	for (i = 1; i < 32; i++)
+		regs->gr[i] = toc->gr[i];
+
+	for (i = 0; i < 8; i++)
+		regs->sr[i] = toc->sr[i];
+
+	regs->iasq[0] = toc->cr[17];
+	regs->iasq[1] = toc->iasq_back;
+	regs->iaoq[0] = toc->cr[18];
+	regs->iaoq[1] = toc->iaoq_back;
+
+	regs->sar  = toc->cr[11];
+	regs->iir  = toc->cr[19];
+	regs->isr  = toc->cr[20];
+	regs->ior  = toc->cr[21];
+}
+
+void notrace toc_intr(struct pt_regs *regs)
+{
+	struct pdc_toc_pim_20 pim_data20;
+	struct pdc_toc_pim_11 pim_data11;
+
+	nmi_enter();
+
+	if (boot_cpu_data.cpu_type >= pcxu) {
+		if (pdc_pim_toc20(&pim_data20))
+			panic("Failed to get PIM data");
+		toc20_to_pt_regs(regs, &pim_data20);
+	} else {
+		if (pdc_pim_toc11(&pim_data11))
+			panic("Failed to get PIM data");
+		toc11_to_pt_regs(regs, &pim_data11);
+	}
+
+#ifdef CONFIG_KGDB
+	if (atomic_read(&kgdb_active) != -1)
+		kgdb_nmicallback(raw_smp_processor_id(), regs);
+	kgdb_handle_exception(KDB_REASON_SYSTEM_NMI, SIGTRAP, 0, regs);
+#endif
+	show_regs(regs);
+
+	/* give other CPUs time to show their backtrace */
+	mdelay(2000);
+	machine_restart("TOC");
+
+	nmi_exit();
+}
+
 void notrace handle_interruption(int code, struct pt_regs *regs)
 {
 	unsigned long fault_address = 0;
-- 
2.33.0

Re: [PATCH 2/2] parisc: add support for TOC (transfer of control)

[Helge Deller]

On 10/9/21 23:38, Sven Schnelle wrote:
> Almost all PA-RISC machines have either a button that
> is labeled with 'TOC' or a BMC function to trigger a TOC.
> TOC is a non-maskable interrupt that is sent to the processor.
> This can be used for diagnostic purposes like obtaining a
> stack trace/register dump or to enter KDB/KGDB.
>
> As an example, on my c8000, TOC can be used with:
>
> CONFIG_KGDB=y
> CONFIG_KGDB_KDB=y
>
> and the 'kgdboc=ttyS0,115200' appended to the command line.
>
> Press ^( on serial console, which will enter the BMC command line,
> and enter 'TOC s':
>
> root@(none):/# (
> cli>TOC s
> Sending TOC/INIT.
> <Cpu3> 2800035d03e00000  0000000040c21ac8  CC_ERR_CHECK_TOC
> <Cpu0> 2800035d00e00000  0000000040c21ad0  CC_ERR_CHECK_TOC
> <Cpu2> 2800035d02e00000  0000000040c21ac8  CC_ERR_CHECK_TOC
> <Cpu1> 2800035d01e00000  0000000040c21ad0  CC_ERR_CHECK_TOC
> <Cpu3> 37000f7303e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
> <Cpu0> 37000f7300e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
> <Cpu2> 37000f7302e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
> <Cpu1> 37000f7301e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
> <Cpu3> 4300100803e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC
> <Cpu0> 4300100800e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC
> <Cpu2> 4300100802e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC
> <Cpu1> 4300100801e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC
>
> Entering kdb (current=0x00000000411cef80, pid 0) on processor 0 due to NonMaskable Interrupt @ 0x40c21ad0
> [0]kdb>
>
> Signed-off-by: Sven Schnelle <svens@stackframe.org>
> ---
>  arch/parisc/include/asm/processor.h |  4 ++
>  arch/parisc/include/uapi/asm/pdc.h  |  6 ++-
>  arch/parisc/kernel/entry.S          | 69 +++++++++++++++++++++++++
>  arch/parisc/kernel/processor.c      | 21 ++++++++
>  arch/parisc/kernel/traps.c          | 79 +++++++++++++++++++++++++++++
>  5 files changed, 177 insertions(+), 2 deletions(-)
>
> diff --git a/arch/parisc/include/asm/processor.h b/arch/parisc/include/asm/processor.h
> index eeb7da064289..1e9a4c986921 100644
> --- a/arch/parisc/include/asm/processor.h
> +++ b/arch/parisc/include/asm/processor.h
> @@ -294,6 +294,10 @@ extern int _parisc_requires_coherency;
>
>  extern int running_on_qemu;
>
> +extern void toc_handler(void);
> +extern unsigned int toc_handler_size;
> +extern unsigned int toc_handler_csum;
> +
>  #endif /* __ASSEMBLY__ */
>
>  #endif /* __ASM_PARISC_PROCESSOR_H */
> diff --git a/arch/parisc/include/uapi/asm/pdc.h b/arch/parisc/include/uapi/asm/pdc.h
> index ad51df8ba952..acc633c15722 100644
> --- a/arch/parisc/include/uapi/asm/pdc.h
> +++ b/arch/parisc/include/uapi/asm/pdc.h
> @@ -398,8 +398,10 @@ struct zeropage {
>  	/* int	(*vec_rendz)(void); */
>  	unsigned int vec_rendz;
>  	int	vec_pow_fail_flen;
> -	int	vec_pad[10];
> -
> +	int	vec_pad0[3];
> +	unsigned int vec_toc_hi;
> +	int	vec_pad1[6];
> +
>  	/* [0x040] reserved processor dependent */
>  	int	pad0[112];
>
> diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
> index 9f939afe6b88..f486f3b51075 100644
> --- a/arch/parisc/kernel/entry.S
> +++ b/arch/parisc/kernel/entry.S
> @@ -28,6 +28,7 @@
>
>  #include <linux/linkage.h>
>  #include <linux/pgtable.h>
> +#include <linux/threads.h>
>
>  #ifdef CONFIG_64BIT
>  	.level 2.0w
> @@ -2414,3 +2415,71 @@ ENTRY_CFI(set_register)
>  	copy    %r1,%r31
>  ENDPROC_CFI(set_register)
>
> +	.import toc_intr,code
> +	ENTRY_CFI(toc_handler)
> +	/*
> +	 * synchronize CPUs and obtain offset
> +	 * for stack setup.
> +	 */
> +	load32		PA(toc_lock),%r1
> +0:	ldcw,co		0(%r1),%r2
> +	cmpib,=		0,%r2,0b
> +	nop
> +	addi		1,%r2,%r4
> +	stw		%r4,0(%r1)
> +	addi		-1,%r2,%r4
> +
> +	load32	PA(toc_stack),sp
> +	/*
> +	 * deposit CPU number into stack address,
> +	 * so every CPU will have its own stack.
> +	 */
> +	depw	%r4,18,2,%sp

Shouldn't this be 5 instead of 2, otherwise it limits it to 4 CPUs,
while we currently can have up to 32 (see arch/parisc/Kconfig).
e.g.:	depw	%r4,18,5,%sp

> +
> ...
> +SYM_DATA(toc_handler_size, .long . - toc_handler)
> +SYM_DATA(toc_lock, .long 1)
> +
> +	__PAGE_ALIGNED_BSS
> +	.align 16384*NR_CPUS

^ This align is too big, esp. since NR_CPUS can be 32.
At minimum a stack needs to be 64-byte aligned.
I think a simple .align 64 here, and changing the multiplication
above with adding the offset is better.

> +toc_stack:
> +	.block 16384*NR_CPUS

all other seems ok.

Thanks!
Helge

Re: [PATCH 2/2] parisc: add support for TOC (transfer of control)

[Sven Schnelle]

Helge Deller <deller@gmx.de> writes:

> On 10/9/21 23:38, Sven Schnelle wrote:
>> +	load32	PA(toc_stack),sp
>> +	/*
>> +	 * deposit CPU number into stack address,
>> +	 * so every CPU will have its own stack.
>> +	 */
>> +	depw	%r4,18,2,%sp
>
> Shouldn't this be 5 instead of 2, otherwise it limits it to 4 CPUs,
> while we currently can have up to 32 (see arch/parisc/Kconfig).
> e.g.:	depw	%r4,18,5,%sp
>
>> +
>> ...
>> +SYM_DATA(toc_handler_size, .long . - toc_handler)
>> +SYM_DATA(toc_lock, .long 1)
>> +
>> +	__PAGE_ALIGNED_BSS
>> +	.align 16384*NR_CPUS
>
> ^ This align is too big, esp. since NR_CPUS can be 32.
> At minimum a stack needs to be 64-byte aligned.
> I think a simple .align 64 here, and changing the multiplication
> above with adding the offset is better.

The .align was a quick way to test the stack offset, but i agree that
doing a regular add is the better way. Also i missed to align toc_lock
at a 16 byte boundary.

Re: [PATCH 2/2] parisc: add support for TOC (transfer of control)

[Rolf Eike Beer]

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> +void notrace toc_intr(struct pt_regs *regs)
> +{
> +	struct pdc_toc_pim_20 pim_data20;
> +	struct pdc_toc_pim_11 pim_data11;
> +
> +	nmi_enter();
> +
> +	if (boot_cpu_data.cpu_type >= pcxu) {
> +		if (pdc_pim_toc20(&pim_data20))
> +			panic("Failed to get PIM data");
> +		toc20_to_pt_regs(regs, &pim_data20);
> +	} else {
> +		if (pdc_pim_toc11(&pim_data11))
> +			panic("Failed to get PIM data");
> +		toc11_to_pt_regs(regs, &pim_data11);
> +	}
> +

You can move the variables into the if/else branches as they are not used 
outside. That would also reduce stack usage.

Eike

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Re: [PATCH 2/2] parisc: add support for TOC (transfer of control)

[Helge Deller]

Hi Sven,

On 10/10/21 21:36, Sven Schnelle wrote:
> Helge Deller <deller@gmx.de> writes:
>
>> On 10/10/21 20:38, Sven Schnelle wrote:
>>> +void notrace toc_intr(struct pt_regs *regs)
>>> +{
>>> +	struct pdc_toc_pim_20 pim_data20;
>>> +	struct pdc_toc_pim_11 pim_data11;
>>> +
>>> +	nmi_enter();
>>> +
>>> +	if (boot_cpu_data.cpu_type >= pcxu) {
>>
>> I wonder if this is correct.
>> If we boot a 32bit-kernel on a 64-bit (pcxu) machine, then
>> I think the code below for pdc_pim_toc11() should be executed.
>> So, maybe we need a #ifdef CONFIG_64BIT above...
>>
>>
>>> +		if (pdc_pim_toc20(&pim_data20))
>>> +			panic("Failed to get PIM data");
>>> +		toc20_to_pt_regs(regs, &pim_data20);
>>> +	} else {
>>
>> ... with an #else here
>>
>>> +		if (pdc_pim_toc11(&pim_data11))
>>> +			panic("Failed to get PIM data");
>>> +		toc11_to_pt_regs(regs, &pim_data11);
>>> +	}
>>
>> and #endif here. ??
>
> Hmm, that's what i understood from the HPMC PIM code,
> transfer_pim_to_trap_frame(). If it's running a 32 Bit OS, than PDC
> returns a wide frame on a 64 bit capable CPU? But maybe i have to read
> the documentation/code again.

No, that seems correct.
On a 64bit machine even a 32bit kernel seems to get the 64bit register PIM data:

64bit kernel:
[0]kdb> rd
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.15.0-rc5-64bit+ #1218
Hardware name: 9000/785/C3700

     YZrvWESTHLNXBCVMcbcbcbcbOGFRQPDI
PSW: 00001000000001001111001000001111 Not tainted
r00-03  000000ff0804f20f 0000000040c45720 0000000040b6dd40 0000000040f004e0
r04-07  0000000040c1c720 0000000040f004b0 0000000040f14608 0000000000000004
r08-11  0000000000000001 0000000040c45720 0000000040c45720 0000000000000003
r12-15  0000000000000000 000000004111f020 0000000040fc7810 0000000040c3cf20
r16-19  0000000040c3cf20 0000000040f00240 0000000040f00240 4000000000000000
r20-23  0000000000000008 0000000000000000 0000000000000000 0000000000000000
r24-27  0000000000000000 0000000000000000 000000000000f45c 0000000040c1c720
r28-31  0000000000000000 0000000040f00530 0000000040f00560 0000000000000004
sr00-03  0000000000000400 0000000000000000 0000000000000000 0000000000000400
sr04-07  0000000000000000 0000000000000000 0000000000000000 0000000000000000

IASQ: 0000000000000000 0000000000000000 IAOQ: 0000000040b6dd5c 0000000040b6dd60
 IIR: 503c0b00    ISR: 0000000000000000  IOR: 0000000000000000
 CPU:        0   CR30: 0000000040f00000 CR31: 00000000ffff55ff
 ORIG_R28: 0000000000000000
 IAOQ[0]: cpu_idle_poll.isra.0+0x94/0x100
 IAOQ[1]: cpu_idle_poll.isra.0+0x98/0x100
Backtrace:
 [<0000000040287490>] do_idle+0x1d8/0x290
 [<00000000402877a4>] cpu_startup_entry+0x7c/0x88
 [<0000000040b65ff8>] rest_init+0x220/0x248
 [<0000000040100ffc>] arch_call_rest_init+0x2c/0x40


32bit Kernel:
kdb> rd
CPU: 0 PID: 0 Comm: swapper Not tainted 5.15.0-rc5-32bit+ #804
Hardware name: 9000/785/C3700

     YZrvWESTHLNXBCVMcbcbcbcbOGFRQPDI
PSW: 00000000000001001111111100001111 Not tainted
r00-03  0004ff0f 10a03cb0 1079506c 109fd280
r04-07  00000004 10a03cb0 11e01d1a 10a03cb0
r08-11  00000000 10a06cdc 1090ea5c 10aa0cb0
r12-15  1090ea5c ffffffff 00000000 f0400004
r16-19  f0000884 f000017c f0000174 00000004
r20-23  0000000f 00000000 101c0704 00000009
r24-27  84cf5d16 109fd000 10a16f20 109474b0
r28-31  00000001 84cf7ca2 109fd2c0 101b773c
sr00-03  00000000 0000001d 00000000 0000001d
sr04-07  00000000 00000000 00000000 00000000

IASQ: 00000000 00000000 IAOQ: 1079508c 10795090
 IIR: e800001a    ISR: 00000000  IOR: 00000000
 CPU:        0   CR30: 109fd000 CR31: ffff55ff
 ORIG_R28: 00000000
 IAOQ[0]: cpu_idle_poll.isra.0+0x38/0x50
 IAOQ[1]: cpu_idle_poll.isra.0+0x3c/0x50
 RP(r2): cpu_idle_poll.isra.0+0x18/0x50
Backtrace:
 [<101bd500>] do_idle+0x88/0xd8
 [<101bd6fc>] cpu_startup_entry+0x20/0x24
 [<1078f14c>] rest_init+0xb0/0xc4
 [<10102820>] 0x10102820

Your patch is correct.

Helge

Re: [PATCH 2/2] parisc: add support for TOC (transfer of control)

[Sven Schnelle]

Hi Helge,

Helge Deller <deller@gmx.de> writes:

> On 10/10/21 20:38, Sven Schnelle wrote:
>> +void notrace toc_intr(struct pt_regs *regs)
>> +{
>> +	struct pdc_toc_pim_20 pim_data20;
>> +	struct pdc_toc_pim_11 pim_data11;
>> +
>> +	nmi_enter();
>> +
>> +	if (boot_cpu_data.cpu_type >= pcxu) {
>
> I wonder if this is correct.
> If we boot a 32bit-kernel on a 64-bit (pcxu) machine, then
> I think the code below for pdc_pim_toc11() should be executed.
> So, maybe we need a #ifdef CONFIG_64BIT above...
>
>
>> +		if (pdc_pim_toc20(&pim_data20))
>> +			panic("Failed to get PIM data");
>> +		toc20_to_pt_regs(regs, &pim_data20);
>> +	} else {
>
> ... with an #else here
>
>> +		if (pdc_pim_toc11(&pim_data11))
>> +			panic("Failed to get PIM data");
>> +		toc11_to_pt_regs(regs, &pim_data11);
>> +	}
>
> and #endif here. ??

Hmm, that's what i understood from the HPMC PIM code,
transfer_pim_to_trap_frame(). If it's running a 32 Bit OS, than PDC
returns a wide frame on a 64 bit capable CPU? But maybe i have to read
the documentation/code again.

Regards
Sven

Re: [PATCH 2/2] parisc: add support for TOC (transfer of control)

[Helge Deller]

On 10/10/21 20:38, Sven Schnelle wrote:
> Almost all PA-RISC machines have either a button that
> is labeled with 'TOC' or a BMC function to trigger a TOC.
> TOC is a non-maskable interrupt that is sent to the processor.
> This can be used for diagnostic purposes like obtaining a
> stack trace/register dump or to enter KDB/KGDB.
>
> As an example, on my c8000, TOC can be used with:
>
> CONFIG_KGDB=y
> CONFIG_KGDB_KDB=y
>
> and the 'kgdboc=ttyS0,115200' appended to the command line.
>
> Press ^( on serial console, which will enter the BMC command line,
> and enter 'TOC s':
>
> root@(none):/# (
> cli>TOC s
> Sending TOC/INIT.
> <Cpu3> 2800035d03e00000  0000000040c21ac8  CC_ERR_CHECK_TOC
> <Cpu0> 2800035d00e00000  0000000040c21ad0  CC_ERR_CHECK_TOC
> <Cpu2> 2800035d02e00000  0000000040c21ac8  CC_ERR_CHECK_TOC
> <Cpu1> 2800035d01e00000  0000000040c21ad0  CC_ERR_CHECK_TOC
> <Cpu3> 37000f7303e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
> <Cpu0> 37000f7300e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
> <Cpu2> 37000f7302e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
> <Cpu1> 37000f7301e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
> <Cpu3> 4300100803e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC
> <Cpu0> 4300100800e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC
> <Cpu2> 4300100802e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC
> <Cpu1> 4300100801e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC
>
> Entering kdb (current=0x00000000411cef80, pid 0) on processor 0 due to NonMaskable Interrupt @ 0x40c21ad0
> [0]kdb>
>
> Signed-off-by: Sven Schnelle <svens@stackframe.org>
> ---
>  arch/parisc/include/asm/processor.h |  4 ++
>  arch/parisc/include/uapi/asm/pdc.h  |  6 ++-
>  arch/parisc/kernel/entry.S          | 74 +++++++++++++++++++++++++++
>  arch/parisc/kernel/processor.c      | 22 ++++++++
>  arch/parisc/kernel/traps.c          | 79 +++++++++++++++++++++++++++++
>  5 files changed, 183 insertions(+), 2 deletions(-)
>
> diff --git a/arch/parisc/include/asm/processor.h b/arch/parisc/include/asm/processor.h
> index eeb7da064289..1e9a4c986921 100644
> --- a/arch/parisc/include/asm/processor.h
> +++ b/arch/parisc/include/asm/processor.h
> @@ -294,6 +294,10 @@ extern int _parisc_requires_coherency;
>
>  extern int running_on_qemu;
>
> +extern void toc_handler(void);
> +extern unsigned int toc_handler_size;
> +extern unsigned int toc_handler_csum;
> +
>  #endif /* __ASSEMBLY__ */
>
>  #endif /* __ASM_PARISC_PROCESSOR_H */
> diff --git a/arch/parisc/include/uapi/asm/pdc.h b/arch/parisc/include/uapi/asm/pdc.h
> index ad51df8ba952..acc633c15722 100644
> --- a/arch/parisc/include/uapi/asm/pdc.h
> +++ b/arch/parisc/include/uapi/asm/pdc.h
> @@ -398,8 +398,10 @@ struct zeropage {
>  	/* int	(*vec_rendz)(void); */
>  	unsigned int vec_rendz;
>  	int	vec_pow_fail_flen;
> -	int	vec_pad[10];
> -
> +	int	vec_pad0[3];
> +	unsigned int vec_toc_hi;
> +	int	vec_pad1[6];
> +
>  	/* [0x040] reserved processor dependent */
>  	int	pad0[112];
>
> diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
> index 9f939afe6b88..25ec47e9ae24 100644
> --- a/arch/parisc/kernel/entry.S
> +++ b/arch/parisc/kernel/entry.S
> @@ -28,6 +28,7 @@
>
>  #include <linux/linkage.h>
>  #include <linux/pgtable.h>
> +#include <linux/threads.h>
>
>  #ifdef CONFIG_64BIT
>  	.level 2.0w
> @@ -2414,3 +2415,76 @@ ENTRY_CFI(set_register)
>  	copy    %r1,%r31
>  ENDPROC_CFI(set_register)
>
> +	.import toc_intr,code
> +	.import toc_lock,data
> +	ENTRY_CFI(toc_handler)
> +	/*
> +	 * synchronize CPUs and obtain offset
> +	 * for stack setup.
> +	 */
> +	load32		PA(toc_lock),%r1
> +0:	ldcw,co		0(%r1),%r2
> +	cmpib,=		0,%r2,0b
> +	nop
> +	addi		1,%r2,%r4
> +	stw		%r4,0(%r1)
> +	addi		-1,%r2,%r4
> +
> +	load32	PA(toc_stack),%sp
> +	/*
> +	 * deposit CPU number into stack address,
> +	 * so every CPU will have its own stack.
> +	 */
> +	SHLREG	%r4,14,%r4
> +	add	%r4,%sp,%sp
> +
> +	/* setup pt_regs on stack and save the
> +	 * floating point registers. PIM_TOC doesn't
> +	 * save fp registers, so we're doing it here.
> +	 */
> +	copy	%sp,%arg0
> +	ldo	PT_SZ_ALGN(%sp), %sp
> +
> +	/* clear pt_regs */
> +	copy	%arg0,%r1
> +0:	cmpb,<<,n %r1,%sp,0b
> +	stw,ma	%r0,4(%r1)
> +
> +	ldo	PT_FR0(%arg0),%r25
> +	save_fp	%r25
> +
> +	/* go virtual */
> +	load32	PA(swapper_pg_dir),%r4
> +	mtctl	%r4,%cr24
> +	mtctl	%r4,%cr25
> +
> +	/* Clear sr4-sr7 */
> +	mtsp	%r0, %sr4
> +	mtsp	%r0, %sr5
> +	mtsp	%r0, %sr6
> +	mtsp	%r0, %sr7
> +
> +	tovirt_r1 %sp
> +	tovirt_r1 %arg0
> +	virt_map
> +
> +	loadgp
> +#ifdef CONFIG_64BIT
> +	ldo	-16(%sp),%r29
> +#endif
> +	b,l	toc_intr,%r2
> +	nop
> +0:	b	0b
> +ENDPROC_CFI(toc_handler)
> +
> +	/*
> +	 * keep this checksum here, as it is part of the toc_handler
> +	 * spanned by toc_handler_size (all words in toc_handler are
> +	 * added in PDC and the sum must equal to zero.
> +	 */
> +SYM_DATA(toc_handler_csum, .long 0)
> +SYM_DATA(toc_handler_size, .long . - toc_handler)
> +
> +	__PAGE_ALIGNED_BSS
> +	.align 64
> +SYM_DATA(toc_stack, .block 16384*NR_CPUS)
> diff --git a/arch/parisc/kernel/processor.c b/arch/parisc/kernel/processor.c
> index 1b6129e7d776..c6e4fee79f30 100644
> --- a/arch/parisc/kernel/processor.c
> +++ b/arch/parisc/kernel/processor.c
> @@ -28,6 +28,7 @@
>  #include <asm/pdcpat.h>
>  #include <asm/irq.h>		/* for struct irq_region */
>  #include <asm/parisc-device.h>
> +#include <asm/sections.h>
>
>  struct system_cpuinfo_parisc boot_cpu_data __ro_after_init;
>  EXPORT_SYMBOL(boot_cpu_data);
> @@ -37,6 +38,7 @@ EXPORT_SYMBOL(_parisc_requires_coherency);
>  #endif
>
>  DEFINE_PER_CPU(struct cpuinfo_parisc, cpu_data);
> +unsigned int __aligned(16) toc_lock = 1;
>
>  /*
>  **  	PARISC CPU driver - claim "device" and initialize CPU data structures.
> @@ -453,6 +455,25 @@ static struct parisc_driver cpu_driver __refdata = {
>  	.probe		= processor_probe
>  };
>
> +static __init void setup_toc(void)
> +{
> +	unsigned int csum = 0;
> +	unsigned long toc_code = (unsigned long)dereference_function_descriptor(toc_handler);
> +	int i;
> +
> +	PAGE0->vec_toc = __pa(toc_code) & 0xffffffff;
> +#ifdef CONFIG_64BIT
> +	PAGE0->vec_toc_hi = __pa(toc_code) >> 32;
> +#else
> +	PAGE0->vec_toc_hi = 0;
> +#endif
> +	PAGE0->vec_toclen = toc_handler_size;
> +
> +	for (i = 0; i < toc_handler_size/4; i++)
> +		csum += ((u32 *)toc_code)[i];
> +	toc_handler_csum = -csum;
> +}
> +
>  /**
>   * processor_init - Processor initialization procedure.
>   *
> @@ -460,5 +481,6 @@ static struct parisc_driver cpu_driver __refdata = {
>   */
>  void __init processor_init(void)
>  {
> +	setup_toc();
>  	register_parisc_driver(&cpu_driver);
>  }
> diff --git a/arch/parisc/kernel/traps.c b/arch/parisc/kernel/traps.c
> index 747c328fb886..e847d37eda3a 100644
> --- a/arch/parisc/kernel/traps.c
> +++ b/arch/parisc/kernel/traps.c
> @@ -30,6 +30,8 @@
>  #include <linux/ratelimit.h>
>  #include <linux/uaccess.h>
>  #include <linux/kdebug.h>
> +#include <linux/kdb.h>
> +#include <linux/reboot.h>
>
>  #include <asm/assembly.h>
>  #include <asm/io.h>
> @@ -472,6 +474,83 @@ void parisc_terminate(char *msg, struct pt_regs *regs, int code, unsigned long o
>  	panic(msg);
>  }
>
> +static void toc20_to_pt_regs(struct pt_regs *regs, struct pdc_toc_pim_20 *toc)
> +{
> +	int i;
> +
> +	regs->gr[0] = (unsigned long)toc->cr[22];
> +
> +	for (i = 1; i < 32; i++)
> +		regs->gr[i] = (unsigned long)toc->gr[i];
> +
> +	for (i = 0; i < 8; i++)
> +		regs->sr[i] = (unsigned long)toc->sr[i];
> +
> +	regs->iasq[0] = (unsigned long)toc->cr[17];
> +	regs->iasq[1] = (unsigned long)toc->iasq_back;
> +	regs->iaoq[0] = (unsigned long)toc->cr[18];
> +	regs->iaoq[1] = (unsigned long)toc->iaoq_back;
> +
> +	regs->sar = (unsigned long)toc->cr[11];
> +	regs->iir = (unsigned long)toc->cr[19];
> +	regs->isr = (unsigned long)toc->cr[20];
> +	regs->ior = (unsigned long)toc->cr[21];
> +}
> +
> +static void toc11_to_pt_regs(struct pt_regs *regs, struct pdc_toc_pim_11 *toc)
> +{
> +	int i;
> +
> +	regs->gr[0] = toc->cr[22];
> +
> +	for (i = 1; i < 32; i++)
> +		regs->gr[i] = toc->gr[i];
> +
> +	for (i = 0; i < 8; i++)
> +		regs->sr[i] = toc->sr[i];
> +
> +	regs->iasq[0] = toc->cr[17];
> +	regs->iasq[1] = toc->iasq_back;
> +	regs->iaoq[0] = toc->cr[18];
> +	regs->iaoq[1] = toc->iaoq_back;
> +
> +	regs->sar  = toc->cr[11];
> +	regs->iir  = toc->cr[19];
> +	regs->isr  = toc->cr[20];
> +	regs->ior  = toc->cr[21];
> +}
> +
> +void notrace toc_intr(struct pt_regs *regs)
> +{
> +	struct pdc_toc_pim_20 pim_data20;
> +	struct pdc_toc_pim_11 pim_data11;
> +
> +	nmi_enter();
> +
> +	if (boot_cpu_data.cpu_type >= pcxu) {

I wonder if this is correct.
If we boot a 32bit-kernel on a 64-bit (pcxu) machine, then
I think the code below for pdc_pim_toc11() should be executed.
So, maybe we need a #ifdef CONFIG_64BIT above...


> +		if (pdc_pim_toc20(&pim_data20))
> +			panic("Failed to get PIM data");
> +		toc20_to_pt_regs(regs, &pim_data20);
> +	} else {

... with an #else here

> +		if (pdc_pim_toc11(&pim_data11))
> +			panic("Failed to get PIM data");
> +		toc11_to_pt_regs(regs, &pim_data11);
> +	}

and #endif here. ??

Helge

[PATCH 2/2] parisc: add support for TOC (transfer of control)

[Sven Schnelle]

Almost all PA-RISC machines have either a button that
is labeled with 'TOC' or a BMC function to trigger a TOC.
TOC is a non-maskable interrupt that is sent to the processor.
This can be used for diagnostic purposes like obtaining a
stack trace/register dump or to enter KDB/KGDB.

As an example, on my c8000, TOC can be used with:

CONFIG_KGDB=y
CONFIG_KGDB_KDB=y

and the 'kgdboc=ttyS0,115200' appended to the command line.

Press ^( on serial console, which will enter the BMC command line,
and enter 'TOC s':

root@(none):/# (
cli>TOC s
Sending TOC/INIT.
<Cpu3> 2800035d03e00000  0000000040c21ac8  CC_ERR_CHECK_TOC
<Cpu0> 2800035d00e00000  0000000040c21ad0  CC_ERR_CHECK_TOC
<Cpu2> 2800035d02e00000  0000000040c21ac8  CC_ERR_CHECK_TOC
<Cpu1> 2800035d01e00000  0000000040c21ad0  CC_ERR_CHECK_TOC
<Cpu3> 37000f7303e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
<Cpu0> 37000f7300e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
<Cpu2> 37000f7302e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
<Cpu1> 37000f7301e00000  2000000000000000  CC_ERR_CPU_CHECK_SUMMARY
<Cpu3> 4300100803e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC
<Cpu0> 4300100800e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC
<Cpu2> 4300100802e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC
<Cpu1> 4300100801e00000  c0000000001d26cc  CC_MC_BR_TO_OS_TOC

Entering kdb (current=0x00000000411cef80, pid 0) on processor 0 due to NonMaskable Interrupt @ 0x40c21ad0
[0]kdb>

Signed-off-by: Sven Schnelle <svens@stackframe.org>
---
 arch/parisc/include/asm/processor.h |  4 ++
 arch/parisc/include/uapi/asm/pdc.h  |  6 ++-
 arch/parisc/kernel/entry.S          | 74 +++++++++++++++++++++++++++
 arch/parisc/kernel/processor.c      | 22 ++++++++
 arch/parisc/kernel/traps.c          | 79 +++++++++++++++++++++++++++++
 5 files changed, 183 insertions(+), 2 deletions(-)

diff --git a/arch/parisc/include/asm/processor.h b/arch/parisc/include/asm/processor.h
index eeb7da064289..1e9a4c986921 100644
--- a/arch/parisc/include/asm/processor.h
+++ b/arch/parisc/include/asm/processor.h
@@ -294,6 +294,10 @@ extern int _parisc_requires_coherency;
 
 extern int running_on_qemu;
 
+extern void toc_handler(void);
+extern unsigned int toc_handler_size;
+extern unsigned int toc_handler_csum;
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __ASM_PARISC_PROCESSOR_H */
diff --git a/arch/parisc/include/uapi/asm/pdc.h b/arch/parisc/include/uapi/asm/pdc.h
index ad51df8ba952..acc633c15722 100644
--- a/arch/parisc/include/uapi/asm/pdc.h
+++ b/arch/parisc/include/uapi/asm/pdc.h
@@ -398,8 +398,10 @@ struct zeropage {
 	/* int	(*vec_rendz)(void); */
 	unsigned int vec_rendz;
 	int	vec_pow_fail_flen;
-	int	vec_pad[10];		
-	
+	int	vec_pad0[3];
+	unsigned int vec_toc_hi;
+	int	vec_pad1[6];
+
 	/* [0x040] reserved processor dependent */
 	int	pad0[112];
 
diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index 9f939afe6b88..25ec47e9ae24 100644
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -28,6 +28,7 @@
 
 #include <linux/linkage.h>
 #include <linux/pgtable.h>
+#include <linux/threads.h>
 
 #ifdef CONFIG_64BIT
 	.level 2.0w
@@ -2414,3 +2415,76 @@ ENTRY_CFI(set_register)
 	copy    %r1,%r31
 ENDPROC_CFI(set_register)
 
+	.import toc_intr,code
+	.import toc_lock,data
+	ENTRY_CFI(toc_handler)
+	/*
+	 * synchronize CPUs and obtain offset
+	 * for stack setup.
+	 */
+	load32		PA(toc_lock),%r1
+0:	ldcw,co		0(%r1),%r2
+	cmpib,=		0,%r2,0b
+	nop
+	addi		1,%r2,%r4
+	stw		%r4,0(%r1)
+	addi		-1,%r2,%r4
+
+	load32	PA(toc_stack),%sp
+	/*
+	 * deposit CPU number into stack address,
+	 * so every CPU will have its own stack.
+	 */
+	SHLREG	%r4,14,%r4
+	add	%r4,%sp,%sp
+
+	/* setup pt_regs on stack and save the
+	 * floating point registers. PIM_TOC doesn't
+	 * save fp registers, so we're doing it here.
+	 */
+	copy	%sp,%arg0
+	ldo	PT_SZ_ALGN(%sp), %sp
+
+	/* clear pt_regs */
+	copy	%arg0,%r1
+0:	cmpb,<<,n %r1,%sp,0b
+	stw,ma	%r0,4(%r1)
+
+	ldo	PT_FR0(%arg0),%r25
+	save_fp	%r25
+
+	/* go virtual */
+	load32	PA(swapper_pg_dir),%r4
+	mtctl	%r4,%cr24
+	mtctl	%r4,%cr25
+
+	/* Clear sr4-sr7 */
+	mtsp	%r0, %sr4
+	mtsp	%r0, %sr5
+	mtsp	%r0, %sr6
+	mtsp	%r0, %sr7
+
+	tovirt_r1 %sp
+	tovirt_r1 %arg0
+	virt_map
+
+	loadgp
+#ifdef CONFIG_64BIT
+	ldo	-16(%sp),%r29
+#endif
+	b,l	toc_intr,%r2
+	nop
+0:	b	0b
+ENDPROC_CFI(toc_handler)
+
+	/*
+	 * keep this checksum here, as it is part of the toc_handler
+	 * spanned by toc_handler_size (all words in toc_handler are
+	 * added in PDC and the sum must equal to zero.
+	 */
+SYM_DATA(toc_handler_csum, .long 0)
+SYM_DATA(toc_handler_size, .long . - toc_handler)
+
+	__PAGE_ALIGNED_BSS
+	.align 64
+SYM_DATA(toc_stack, .block 16384*NR_CPUS)
diff --git a/arch/parisc/kernel/processor.c b/arch/parisc/kernel/processor.c
index 1b6129e7d776..c6e4fee79f30 100644
--- a/arch/parisc/kernel/processor.c
+++ b/arch/parisc/kernel/processor.c
@@ -28,6 +28,7 @@
 #include <asm/pdcpat.h>
 #include <asm/irq.h>		/* for struct irq_region */
 #include <asm/parisc-device.h>
+#include <asm/sections.h>
 
 struct system_cpuinfo_parisc boot_cpu_data __ro_after_init;
 EXPORT_SYMBOL(boot_cpu_data);
@@ -37,6 +38,7 @@ EXPORT_SYMBOL(_parisc_requires_coherency);
 #endif
 
 DEFINE_PER_CPU(struct cpuinfo_parisc, cpu_data);
+unsigned int __aligned(16) toc_lock = 1;
 
 /*
 **  	PARISC CPU driver - claim "device" and initialize CPU data structures.
@@ -453,6 +455,25 @@ static struct parisc_driver cpu_driver __refdata = {
 	.probe		= processor_probe
 };
 
+static __init void setup_toc(void)
+{
+	unsigned int csum = 0;
+	unsigned long toc_code = (unsigned long)dereference_function_descriptor(toc_handler);
+	int i;
+
+	PAGE0->vec_toc = __pa(toc_code) & 0xffffffff;
+#ifdef CONFIG_64BIT
+	PAGE0->vec_toc_hi = __pa(toc_code) >> 32;
+#else
+	PAGE0->vec_toc_hi = 0;
+#endif
+	PAGE0->vec_toclen = toc_handler_size;
+
+	for (i = 0; i < toc_handler_size/4; i++)
+		csum += ((u32 *)toc_code)[i];
+	toc_handler_csum = -csum;
+}
+
 /**
  * processor_init - Processor initialization procedure.
  *
@@ -460,5 +481,6 @@ static struct parisc_driver cpu_driver __refdata = {
  */
 void __init processor_init(void)
 {
+	setup_toc();
 	register_parisc_driver(&cpu_driver);
 }
diff --git a/arch/parisc/kernel/traps.c b/arch/parisc/kernel/traps.c
index 747c328fb886..e847d37eda3a 100644
--- a/arch/parisc/kernel/traps.c
+++ b/arch/parisc/kernel/traps.c
@@ -30,6 +30,8 @@
 #include <linux/ratelimit.h>
 #include <linux/uaccess.h>
 #include <linux/kdebug.h>
+#include <linux/kdb.h>
+#include <linux/reboot.h>
 
 #include <asm/assembly.h>
 #include <asm/io.h>
@@ -472,6 +474,83 @@ void parisc_terminate(char *msg, struct pt_regs *regs, int code, unsigned long o
 	panic(msg);
 }
 
+static void toc20_to_pt_regs(struct pt_regs *regs, struct pdc_toc_pim_20 *toc)
+{
+	int i;
+
+	regs->gr[0] = (unsigned long)toc->cr[22];
+
+	for (i = 1; i < 32; i++)
+		regs->gr[i] = (unsigned long)toc->gr[i];
+
+	for (i = 0; i < 8; i++)
+		regs->sr[i] = (unsigned long)toc->sr[i];
+
+	regs->iasq[0] = (unsigned long)toc->cr[17];
+	regs->iasq[1] = (unsigned long)toc->iasq_back;
+	regs->iaoq[0] = (unsigned long)toc->cr[18];
+	regs->iaoq[1] = (unsigned long)toc->iaoq_back;
+
+	regs->sar = (unsigned long)toc->cr[11];
+	regs->iir = (unsigned long)toc->cr[19];
+	regs->isr = (unsigned long)toc->cr[20];
+	regs->ior = (unsigned long)toc->cr[21];
+}
+
+static void toc11_to_pt_regs(struct pt_regs *regs, struct pdc_toc_pim_11 *toc)
+{
+	int i;
+
+	regs->gr[0] = toc->cr[22];
+
+	for (i = 1; i < 32; i++)
+		regs->gr[i] = toc->gr[i];
+
+	for (i = 0; i < 8; i++)
+		regs->sr[i] = toc->sr[i];
+
+	regs->iasq[0] = toc->cr[17];
+	regs->iasq[1] = toc->iasq_back;
+	regs->iaoq[0] = toc->cr[18];
+	regs->iaoq[1] = toc->iaoq_back;
+
+	regs->sar  = toc->cr[11];
+	regs->iir  = toc->cr[19];
+	regs->isr  = toc->cr[20];
+	regs->ior  = toc->cr[21];
+}
+
+void notrace toc_intr(struct pt_regs *regs)
+{
+	struct pdc_toc_pim_20 pim_data20;
+	struct pdc_toc_pim_11 pim_data11;
+
+	nmi_enter();
+
+	if (boot_cpu_data.cpu_type >= pcxu) {
+		if (pdc_pim_toc20(&pim_data20))
+			panic("Failed to get PIM data");
+		toc20_to_pt_regs(regs, &pim_data20);
+	} else {
+		if (pdc_pim_toc11(&pim_data11))
+			panic("Failed to get PIM data");
+		toc11_to_pt_regs(regs, &pim_data11);
+	}
+
+#ifdef CONFIG_KGDB
+	if (atomic_read(&kgdb_active) != -1)
+		kgdb_nmicallback(raw_smp_processor_id(), regs);
+	kgdb_handle_exception(KDB_REASON_SYSTEM_NMI, SIGTRAP, 0, regs);
+#endif
+	show_regs(regs);
+
+	/* give other CPUs time to show their backtrace */
+	mdelay(2000);
+	machine_restart("TOC");
+
+	nmi_exit();
+}
+
 void notrace handle_interruption(int code, struct pt_regs *regs)
 {
 	unsigned long fault_address = 0;
-- 
2.33.0