* [Qemu-devel] [PATCH risu v2] ppc64: Fix patterns for rotate doubleword instructions
@ 2017-05-22 9:17 Sandipan Das
2017-05-30 15:26 ` Nikunj A Dadhania
0 siblings, 1 reply; 6+ messages in thread
From: Sandipan Das @ 2017-05-22 9:17 UTC (permalink / raw)
To: nikunj; +Cc: qemu-devel, peter.maydell, joserz
The patterns for the following instructions are fixed:
* Rotate Left Doubleword then Clear Right (rldcr[.])
* Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
* Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
The first instruction has a typo. For the other two instructions,
the extended opcodes are incorrect and the shift field 'sha' is
absent. Also, the shift field 'sh' should be used in place of the
register field 'rb'.
Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
---
ppc64.risu | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/ppc64.risu b/ppc64.risu
index 28df9da..dd304e2 100644
--- a/ppc64.risu
+++ b/ppc64.risu
@@ -1451,7 +1451,7 @@ RLDCLd PPC64LE 011110 rs:5 ra:5 rb:5 mb:6 10001 \
!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
# format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
-RLCDR PPC64LE 011110 rs:5 ra:5 rb:5 mb:6 10010 \
+RLDCR PPC64LE 011110 rs:5 ra:5 rb:5 mb:6 10010 \
!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
# format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
RLDCRd PPC64LE 011110 rs:5 ra:5 rb:5 mb:6 10011 \
@@ -1472,17 +1472,17 @@ RLDICLd PPC64LE 011110 rs:5 ra:5 sh:5 mb:6 000 sha:1 1 \
!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
# format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate then Clear Right
-RLDICR PPC64LE 011110 rs:5 ra:5 rb:5 me:6 00010 \
+RLDICR PPC64LE 011110 rs:5 ra:5 sh:5 me:6 001 sha:1 0 \
!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
# format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate then Clear Right
-RLDICRd PPC64LE 011110 rs:5 ra:5 rb:5 me:6 00011 \
+RLDICRd PPC64LE 011110 rs:5 ra:5 sh:5 me:6 001 sha:1 1 \
!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
# format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate then Mask Insert
-RLDIMI PPC64LE 011110 rs:5 ra:5 rb:5 me:6 00110 \
+RLDIMI PPC64LE 011110 rs:5 ra:5 sh:5 me:6 011 sha:1 0 \
!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
# format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate then Mask Insert
-RLDIMId PPC64LE 011110 rs:5 ra:5 rb:5 me:6 00111 \
+RLDIMId PPC64LE 011110 rs:5 ra:5 sh:5 me:6 011 sha:1 1 \
!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
# format:M book:I page:102 v:P1 SR rlwimi[.] Rotate Left Word Immediate then Mask Insert
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH risu v2] ppc64: Fix patterns for rotate doubleword instructions
2017-05-22 9:17 [Qemu-devel] [PATCH risu v2] ppc64: Fix patterns for rotate doubleword instructions Sandipan Das
@ 2017-05-30 15:26 ` Nikunj A Dadhania
2017-05-30 15:39 ` Peter Maydell
0 siblings, 1 reply; 6+ messages in thread
From: Nikunj A Dadhania @ 2017-05-30 15:26 UTC (permalink / raw)
To: Sandipan Das; +Cc: qemu-devel, peter.maydell, joserz
Sandipan Das <sandipandas1990@gmail.com> writes:
> The patterns for the following instructions are fixed:
> * Rotate Left Doubleword then Clear Right (rldcr[.])
> * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
> * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
>
> The first instruction has a typo. For the other two instructions,
> the extended opcodes are incorrect and the shift field 'sha' is
> absent. Also, the shift field 'sh' should be used in place of the
> register field 'rb'.
>
> Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
Reviewed-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> ppc64.risu | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/ppc64.risu b/ppc64.risu
> index 28df9da..dd304e2 100644
> --- a/ppc64.risu
> +++ b/ppc64.risu
> @@ -1451,7 +1451,7 @@ RLDCLd PPC64LE 011110 rs:5 ra:5 rb:5 mb:6 10001 \
> !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
>
> # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
> -RLCDR PPC64LE 011110 rs:5 ra:5 rb:5 mb:6 10010 \
> +RLDCR PPC64LE 011110 rs:5 ra:5 rb:5 mb:6 10010 \
> !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
> # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
> RLDCRd PPC64LE 011110 rs:5 ra:5 rb:5 mb:6 10011 \
> @@ -1472,17 +1472,17 @@ RLDICLd PPC64LE 011110 rs:5 ra:5 sh:5 mb:6 000 sha:1 1 \
> !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
>
> # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate then Clear Right
> -RLDICR PPC64LE 011110 rs:5 ra:5 rb:5 me:6 00010 \
> +RLDICR PPC64LE 011110 rs:5 ra:5 sh:5 me:6 001 sha:1 0 \
> !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
> # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate then Clear Right
> -RLDICRd PPC64LE 011110 rs:5 ra:5 rb:5 me:6 00011 \
> +RLDICRd PPC64LE 011110 rs:5 ra:5 sh:5 me:6 001 sha:1 1 \
> !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
>
> # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate then Mask Insert
> -RLDIMI PPC64LE 011110 rs:5 ra:5 rb:5 me:6 00110 \
> +RLDIMI PPC64LE 011110 rs:5 ra:5 sh:5 me:6 011 sha:1 0 \
> !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
> # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate then Mask Insert
> -RLDIMId PPC64LE 011110 rs:5 ra:5 rb:5 me:6 00111 \
> +RLDIMId PPC64LE 011110 rs:5 ra:5 sh:5 me:6 011 sha:1 1 \
> !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
>
> # format:M book:I page:102 v:P1 SR rlwimi[.] Rotate Left Word Immediate then Mask Insert
> --
> 2.7.4
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH risu v2] ppc64: Fix patterns for rotate doubleword instructions
2017-05-30 15:26 ` Nikunj A Dadhania
@ 2017-05-30 15:39 ` Peter Maydell
2017-05-30 16:37 ` Peter Maydell
0 siblings, 1 reply; 6+ messages in thread
From: Peter Maydell @ 2017-05-30 15:39 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: Sandipan Das, QEMU Developers, Jose Ricardo Ziviani
On 30 May 2017 at 16:26, Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> wrote:
> Sandipan Das <sandipandas1990@gmail.com> writes:
>
>> The patterns for the following instructions are fixed:
>> * Rotate Left Doubleword then Clear Right (rldcr[.])
>> * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
>> * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
>>
>> The first instruction has a typo. For the other two instructions,
>> the extended opcodes are incorrect and the shift field 'sha' is
>> absent. Also, the shift field 'sh' should be used in place of the
>> register field 'rb'.
>>
>> Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
>
> Reviewed-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Thanks; applied to risu master.
-- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH risu v2] ppc64: Fix patterns for rotate doubleword instructions
2017-05-30 15:39 ` Peter Maydell
@ 2017-05-30 16:37 ` Peter Maydell
2017-05-31 5:12 ` Nikunj A Dadhania
0 siblings, 1 reply; 6+ messages in thread
From: Peter Maydell @ 2017-05-30 16:37 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: Sandipan Das, QEMU Developers, Jose Ricardo Ziviani
On 30 May 2017 at 16:39, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 30 May 2017 at 16:26, Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> wrote:
>> Sandipan Das <sandipandas1990@gmail.com> writes:
>>
>>> The patterns for the following instructions are fixed:
>>> * Rotate Left Doubleword then Clear Right (rldcr[.])
>>> * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
>>> * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
>>>
>>> The first instruction has a typo. For the other two instructions,
>>> the extended opcodes are incorrect and the shift field 'sha' is
>>> absent. Also, the shift field 'sh' should be used in place of the
>>> register field 'rb'.
>>>
>>> Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
>>
>> Reviewed-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>
> Thanks; applied to risu master.
...but I foolishly didn't run build-all-archs first, which
points out that there's a bug:
Syntax error detected evaluating RLDIMId PPC64LE constraints string: ]
{ $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
Global symbol "$rb" requires explicit package name (did you forget to
declare "my $rb"?) at (eval 429) line 1.
Global symbol "$rb" requires explicit package name (did you forget to
declare "my $rb"?) at (eval 429) line 1.
You forgot to update the constraints when you changed the
field names... I think that the constraints on $rb should
be removed rather than just changed to use $sh because this
field is an immediate, not a register number, so we don't need
to make it avoid 1 and 13. This would bring them into line with
the other rotate-immediates. I'll post a patch in a second.
thanks
-- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH risu v2] ppc64: Fix patterns for rotate doubleword instructions
2017-05-30 16:37 ` Peter Maydell
@ 2017-05-31 5:12 ` Nikunj A Dadhania
0 siblings, 0 replies; 6+ messages in thread
From: Nikunj A Dadhania @ 2017-05-31 5:12 UTC (permalink / raw)
To: Peter Maydell; +Cc: Sandipan Das, QEMU Developers, Jose Ricardo Ziviani
Peter Maydell <peter.maydell@linaro.org> writes:
> On 30 May 2017 at 16:39, Peter Maydell <peter.maydell@linaro.org> wrote:
>> On 30 May 2017 at 16:26, Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> wrote:
>>> Sandipan Das <sandipandas1990@gmail.com> writes:
>>>
>>>> The patterns for the following instructions are fixed:
>>>> * Rotate Left Doubleword then Clear Right (rldcr[.])
>>>> * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
>>>> * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
>>>>
>>>> The first instruction has a typo. For the other two instructions,
>>>> the extended opcodes are incorrect and the shift field 'sha' is
>>>> absent. Also, the shift field 'sh' should be used in place of the
>>>> register field 'rb'.
>>>>
>>>> Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
>>>
>>> Reviewed-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>>
>> Thanks; applied to risu master.
>
> ...but I foolishly didn't run build-all-archs first, which
> points out that there's a bug:
Ouch :(
> Syntax error detected evaluating RLDIMId PPC64LE constraints string: ]
> { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
> Global symbol "$rb" requires explicit package name (did you forget to
> declare "my $rb"?) at (eval 429) line 1.
> Global symbol "$rb" requires explicit package name (did you forget to
> declare "my $rb"?) at (eval 429) line 1.
>
> You forgot to update the constraints when you changed the
> field names... I think that the constraints on $rb should
> be removed rather than just changed to use $sh because this
> field is an immediate, not a register number, so we don't need
> to make it avoid 1 and 13. This would bring them into line with
> the other rotate-immediates. I'll post a patch in a second.
Regards
Nikunj
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH risu v2] ppc64: Fix patterns for rotate doubleword instructions
@ 2017-05-30 14:29 Peter Maydell
0 siblings, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2017-05-30 14:29 UTC (permalink / raw)
To: Sandipan Das; +Cc: Nikunj A Dadhania, QEMU Developers, Jose Ricardo Ziviani
On 22 May 2017 at 10:17, Sandipan Das <sandipandas1990@gmail.com> wrote:
> The patterns for the following instructions are fixed:
> * Rotate Left Doubleword then Clear Right (rldcr[.])
> * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
> * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
>
> The first instruction has a typo. For the other two instructions,
> the extended opcodes are incorrect and the shift field 'sha' is
> absent. Also, the shift field 'sh' should be used in place of the
> register field 'rb'.
>
> Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
> ---
> ppc64.risu | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/ppc64.risu b/ppc64.risu
> index 28df9da..dd304e2 100644
> --- a/ppc64.risu
> +++ b/ppc64.risu
> @@ -1451,7 +1451,7 @@ RLDCLd PPC64LE 011110 rs:5 ra:5 rb:5 mb:6 10001 \
> !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
>
> # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
> -RLCDR PPC64LE 011110 rs:5 ra:5 rb:5 mb:6 10010 \
> +RLDCR PPC64LE 011110 rs:5 ra:5 rb:5 mb:6 10010 \
> !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
> # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
> RLDCRd PPC64LE 011110 rs:5 ra:5 rb:5 mb:6 10011 \
> @@ -1472,17 +1472,17 @@ RLDICLd PPC64LE 011110 rs:5 ra:5 sh:5 mb:6 000 sha:1 1 \
> !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
>
> # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate then Clear Right
> -RLDICR PPC64LE 011110 rs:5 ra:5 rb:5 me:6 00010 \
> +RLDICR PPC64LE 011110 rs:5 ra:5 sh:5 me:6 001 sha:1 0 \
> !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
> # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate then Clear Right
> -RLDICRd PPC64LE 011110 rs:5 ra:5 rb:5 me:6 00011 \
> +RLDICRd PPC64LE 011110 rs:5 ra:5 sh:5 me:6 001 sha:1 1 \
> !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
>
> # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate then Mask Insert
> -RLDIMI PPC64LE 011110 rs:5 ra:5 rb:5 me:6 00110 \
> +RLDIMI PPC64LE 011110 rs:5 ra:5 sh:5 me:6 011 sha:1 0 \
> !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
> # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate then Mask Insert
> -RLDIMId PPC64LE 011110 rs:5 ra:5 rb:5 me:6 00111 \
> +RLDIMId PPC64LE 011110 rs:5 ra:5 sh:5 me:6 011 sha:1 1 \
> !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }
>
> # format:M book:I page:102 v:P1 SR rlwimi[.] Rotate Left Word Immediate then Mask Insert
> --
> 2.7.4
Nikunj or Jose, if you're ok with this version of this patch
can you give me an acked-by or reviewed-by tag and I'll
apply it to risu?
thanks
-- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-05-31 5:13 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2017-05-22 9:17 [Qemu-devel] [PATCH risu v2] ppc64: Fix patterns for rotate doubleword instructions Sandipan Das
2017-05-30 15:26 ` Nikunj A Dadhania
2017-05-30 15:39 ` Peter Maydell
2017-05-30 16:37 ` Peter Maydell
2017-05-31 5:12 ` Nikunj A Dadhania
2017-05-30 14:29 Peter Maydell
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