* [PATCH 1/4] drm/i915: Add support for DP link training compliance
2017-01-21 3:09 [PATCH 0/4] Add automation support for DP Compliance (Rev 6) Manasi Navare
@ 2017-01-21 3:09 ` Manasi Navare
2017-01-24 16:16 ` [PATCH v5 " Manasi Navare
2017-01-21 3:09 ` [PATCH 2/4] drm/i915: Fixes to support DP Compliance EDID tests Manasi Navare
` (6 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Manasi Navare @ 2017-01-21 3:09 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Manasi Navare, Daniel Vetter
This patch adds support to handle automated DP compliance
link training test requests. This patch has been tested with
Unigraf DPR-120 DP Compliance device for testing Link
Training Compliance.
After we get a short pulse Compliance test request, test
request values are read and hotplug uevent is sent in order
to trigger another modeset during which the pipe is configured
and link is retrained and enabled for link parameters requested
by the test.
v4:
* Return TEST_NAK for read failures and invalid
values (Jani Nikula)
* Conver the test link BW to link rate before storing (Jani Nikula)
v3:
* Validate the test link rate and lane count as soon as
the request comes (Jani Nikula)
v2:
* Validate the test lane count before using it in
intel_dp_compute_config (Jani Nikula)
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 64 ++++++++++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/intel_drv.h | 2 ++
2 files changed, 61 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e80d620..8d5008c7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1613,6 +1613,7 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
/* Conveniently, the link BW constants become indices with a shift...*/
int min_clock = 0;
int max_clock;
+ int link_rate_index;
int bpp, mode_rate;
int link_avail, link_clock;
int common_rates[DP_MAX_SUPPORTED_RATES] = {};
@@ -1654,6 +1655,15 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
return false;
+ /* Use values requested by Compliance Test Request */
+ if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
+ link_rate_index = intel_dp_link_rate_index(intel_dp,
+ common_rates,
+ intel_dp->compliance.test_link_rate);
+ if (link_rate_index >= 0)
+ min_clock = max_clock = link_rate_index;
+ min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
+ }
DRM_DEBUG_KMS("DP link computation with max lane count %i "
"max bw %d pixel clock %iKHz\n",
max_lane_count, common_rates[max_clock],
@@ -3920,7 +3930,46 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
{
- uint8_t test_result = DP_TEST_ACK;
+ uint8_t test_result = DP_TEST_NAK;
+ int status = 0;
+ int min_lane_count = 1;
+ int common_rates[DP_MAX_SUPPORTED_RATES] = {};
+ int link_rate_index, test_link_rate;
+ uint8_t test_lane_count, test_link_bw;
+ /* (DP CTS 1.2)
+ * 4.3.1.11
+ */
+ /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
+ status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
+ &test_lane_count);
+
+ if (status <= 0) {
+ DRM_DEBUG_KMS("Lane count read failed\n");
+ return test_result;
+ }
+ test_lane_count &= DP_MAX_LANE_COUNT_MASK;
+ /* Validate the requested lane count */
+ if (test_lane_count < min_lane_count ||
+ test_lane_count > intel_dp->max_sink_lane_count)
+ return test_result;
+ intel_dp->compliance.test_lane_count = test_lane_count;
+
+ status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
+ &test_link_bw);
+ if (status <= 0) {
+ DRM_DEBUG_KMS("Link Rate read failed\n");
+ return test_result;
+ }
+ /* Validate the requested link rate */
+ test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
+ link_rate_index = intel_dp_link_rate_index(intel_dp,
+ common_rates,
+ test_link_rate);
+ if (link_rate_index < 0)
+ return test_result;
+ intel_dp->compliance.test_link_rate = test_link_rate;
+
+ test_result = DP_TEST_ACK;
return test_result;
}
@@ -4135,9 +4184,8 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
if (!intel_dp->lane_count)
return;
- /* if link training is requested we should perform it always */
- if ((intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) ||
- (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
+ /* Retrain if Channel EQ or CR not ok */
+ if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
intel_encoder->base.name);
@@ -4162,6 +4210,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
intel_dp_short_pulse(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
u8 sink_irq_vector = 0;
u8 old_sink_count = intel_dp->sink_count;
bool ret;
@@ -4195,7 +4244,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
sink_irq_vector);
if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
- DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
+ intel_dp_handle_test_request(intel_dp);
if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
}
@@ -4203,6 +4252,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
intel_dp_check_link_status(intel_dp);
drm_modeset_unlock(&dev->mode_config.connection_mutex);
+ if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
+ DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
+ /* Send a Hotplug Uevent to userspace to start modeset */
+ drm_kms_helper_hotplug_event(intel_encoder->base.dev);
+ }
return true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0cec001..0b8d6e4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -894,6 +894,8 @@ struct intel_dp_compliance {
unsigned long test_type;
struct intel_dp_compliance_data test_data;
bool test_active;
+ int test_link_rate;
+ u8 test_lane_count;
};
struct intel_dp {
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v5 1/4] drm/i915: Add support for DP link training compliance
2017-01-21 3:09 ` [PATCH 1/4] drm/i915: Add support for DP link training compliance Manasi Navare
@ 2017-01-24 16:16 ` Manasi Navare
0 siblings, 0 replies; 23+ messages in thread
From: Manasi Navare @ 2017-01-24 16:16 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Manasi Navare, Daniel Vetter
This patch adds support to handle automated DP compliance
link training test requests. This patch has been tested with
Unigraf DPR-120 DP Compliance device for testing Link
Training Compliance.
After we get a short pulse Compliance test request, test
request values are read and hotplug uevent is sent in order
to trigger another modeset during which the pipe is configured
and link is retrained and enabled for link parameters requested
by the test.
v5:
* Only modify the compliance structure after all validation
is done (Jani Nikula)
* Remove the variable test_result (Jani Nikula)
v4:
* Return TEST_NAK for read failures and invalid
values (Jani Nikula)
* Conver the test link BW to link rate before storing (Jani Nikula)
v3:
* Validate the test link rate and lane count as soon as
the request comes (Jani Nikula)
v2:
* Validate the test lane count before using it in
intel_dp_compute_config (Jani Nikula)
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 65 ++++++++++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/intel_drv.h | 2 ++
2 files changed, 61 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e80d620..4233b79 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1613,6 +1613,7 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
/* Conveniently, the link BW constants become indices with a shift...*/
int min_clock = 0;
int max_clock;
+ int link_rate_index;
int bpp, mode_rate;
int link_avail, link_clock;
int common_rates[DP_MAX_SUPPORTED_RATES] = {};
@@ -1654,6 +1655,15 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
return false;
+ /* Use values requested by Compliance Test Request */
+ if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
+ link_rate_index = intel_dp_link_rate_index(intel_dp,
+ common_rates,
+ intel_dp->compliance.test_link_rate);
+ if (link_rate_index >= 0)
+ min_clock = max_clock = link_rate_index;
+ min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
+ }
DRM_DEBUG_KMS("DP link computation with max lane count %i "
"max bw %d pixel clock %iKHz\n",
max_lane_count, common_rates[max_clock],
@@ -3920,8 +3930,46 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
{
- uint8_t test_result = DP_TEST_ACK;
- return test_result;
+ int status = 0;
+ int min_lane_count = 1;
+ int common_rates[DP_MAX_SUPPORTED_RATES] = {};
+ int link_rate_index, test_link_rate;
+ uint8_t test_lane_count, test_link_bw;
+ /* (DP CTS 1.2)
+ * 4.3.1.11
+ */
+ /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
+ status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
+ &test_lane_count);
+
+ if (status <= 0) {
+ DRM_DEBUG_KMS("Lane count read failed\n");
+ return DP_TEST_NAK;
+ }
+ test_lane_count &= DP_MAX_LANE_COUNT_MASK;
+ /* Validate the requested lane count */
+ if (test_lane_count < min_lane_count ||
+ test_lane_count > intel_dp->max_sink_lane_count)
+ return DP_TEST_NAK;
+
+ status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
+ &test_link_bw);
+ if (status <= 0) {
+ DRM_DEBUG_KMS("Link Rate read failed\n");
+ return DP_TEST_NAK;
+ }
+ /* Validate the requested link rate */
+ test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
+ link_rate_index = intel_dp_link_rate_index(intel_dp,
+ common_rates,
+ test_link_rate);
+ if (link_rate_index < 0)
+ return DP_TEST_NAK;
+
+ intel_dp->compliance.test_lane_count = test_lane_count;
+ intel_dp->compliance.test_link_rate = test_link_rate;
+
+ return DP_TEST_ACK;
}
static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
@@ -4135,9 +4183,8 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
if (!intel_dp->lane_count)
return;
- /* if link training is requested we should perform it always */
- if ((intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) ||
- (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
+ /* Retrain if Channel EQ or CR not ok */
+ if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
intel_encoder->base.name);
@@ -4162,6 +4209,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
intel_dp_short_pulse(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
u8 sink_irq_vector = 0;
u8 old_sink_count = intel_dp->sink_count;
bool ret;
@@ -4195,7 +4243,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
sink_irq_vector);
if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
- DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
+ intel_dp_handle_test_request(intel_dp);
if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
}
@@ -4203,6 +4251,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
intel_dp_check_link_status(intel_dp);
drm_modeset_unlock(&dev->mode_config.connection_mutex);
+ if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
+ DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
+ /* Send a Hotplug Uevent to userspace to start modeset */
+ drm_kms_helper_hotplug_event(intel_encoder->base.dev);
+ }
return true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0cec001..0b8d6e4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -894,6 +894,8 @@ struct intel_dp_compliance {
unsigned long test_type;
struct intel_dp_compliance_data test_data;
bool test_active;
+ int test_link_rate;
+ u8 test_lane_count;
};
struct intel_dp {
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/4] drm/i915: Fixes to support DP Compliance EDID tests
2017-01-21 3:09 [PATCH 0/4] Add automation support for DP Compliance (Rev 6) Manasi Navare
2017-01-21 3:09 ` [PATCH 1/4] drm/i915: Add support for DP link training compliance Manasi Navare
@ 2017-01-21 3:09 ` Manasi Navare
2017-01-21 3:09 ` [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests Manasi Navare
` (5 subsequent siblings)
7 siblings, 0 replies; 23+ messages in thread
From: Manasi Navare @ 2017-01-21 3:09 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Daniel Vetter
This patch addresses a few issues from the original patch for
DP Compliance EDID test support submitted by
Todd Previte<todd.previte@gmail.com>
Video Mode requested in the EDID test handler for the EDID Read
test (CTS 4.2.2.3) should be set to PREFERRED as per the CTS spec.
v2:
* Added read debugfs data from test_data.edid if its EDID test (Jani NIkula)
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++++-
drivers/gpu/drm/i915/intel_dp.c | 4 ++--
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fa69d72..8ec7edf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3772,7 +3772,10 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data)
if (connector->status == connector_status_connected &&
connector->encoder != NULL) {
intel_dp = enc_to_intel_dp(connector->encoder);
- seq_printf(m, "%lx", intel_dp->compliance.test_data.edid);
+ if (intel_dp->compliance.test_type ==
+ DP_TEST_LINK_EDID_READ)
+ seq_printf(m, "%lx",
+ intel_dp->compliance.test_data.edid);
} else
seq_puts(m, "0");
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8d5008c7..a65c909 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3981,7 +3981,7 @@ static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
{
- uint8_t test_result = DP_TEST_NAK;
+ uint8_t test_result = DP_TEST_ACK;
struct intel_connector *intel_connector = intel_dp->attached_connector;
struct drm_connector *connector = &intel_connector->base;
@@ -4016,7 +4016,7 @@ static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("Failed to write EDID checksum\n");
test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
- intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_STANDARD;
+ intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
}
/* Set test active flag here so userspace doesn't interrupt things */
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests
2017-01-21 3:09 [PATCH 0/4] Add automation support for DP Compliance (Rev 6) Manasi Navare
2017-01-21 3:09 ` [PATCH 1/4] drm/i915: Add support for DP link training compliance Manasi Navare
2017-01-21 3:09 ` [PATCH 2/4] drm/i915: Fixes to support DP Compliance EDID tests Manasi Navare
@ 2017-01-21 3:09 ` Manasi Navare
2017-01-24 16:05 ` Jani Nikula
2017-01-21 3:09 ` [PATCH 4/4] drm/i915: Add support for DP Video pattern compliance tests Manasi Navare
` (4 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Manasi Navare @ 2017-01-21 3:09 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Daniel Vetter
v4:
* Remove redundant single bit defs (Jani Nikula)
v3:
* Fix the conventions in bit definitions (Jani Nikula)
v2:
* Add all the other DP Complianec TEST register defs (Jani Nikula)
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
include/drm/drm_dp_helper.h | 57 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 0468135..ba89295 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -417,6 +417,63 @@
#define DP_TEST_LANE_COUNT 0x220
#define DP_TEST_PATTERN 0x221
+# define DP_NO_TEST_PATTERN 0x0
+# define DP_COLOR_RAMP 0x1
+# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
+# define DP_COLOR_SQUARE 0x3
+
+#define DP_TEST_H_TOTAL_HI 0x222
+#define DP_TEST_H_TOTAL_LO 0x223
+
+#define DP_TEST_V_TOTAL_HI 0x224
+#define DP_TEST_V_TOTAL_LO 0x225
+
+#define DP_TEST_H_START_HI 0x226
+#define DP_TEST_H_START_LO 0x227
+
+#define DP_TEST_V_START_HI 0x228
+#define DP_TEST_V_START_LO 0x229
+
+#define DP_TEST_HSYNC_HI 0x22A
+# define DP_TEST_HSYNC_POLARITY (1 << 7)
+# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
+#define DP_TEST_HSYNC_WIDTH_LO 0x22B
+
+#define DP_TEST_VSYNC_HI 0x22C
+# define DP_TEST_VSYNC_POLARITY (1 << 7)
+# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
+#define DP_TEST_VSYNC_WIDTH_LO 0x22D
+
+#define DP_TEST_H_WIDTH_HI 0x22E
+#define DP_TEST_H_WIDTH_LO 0x22F
+
+#define DP_TEST_V_HEIGHT_HI 0x230
+#define DP_TEST_V_HEIGHT_LO 0x231
+
+#define DP_TEST_MISC0 0x232
+# define DP_TEST_SYNC_CLOCK (1 << 0)
+# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
+# define DP_TEST_COLOR_FORMAT_SHIFT 1
+# define DP_COLOR_FORMAT_RGB (0 << 1)
+# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
+# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
+# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
+# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
+# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
+# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
+# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
+# define DP_TEST_BIT_DEPTH_SHIFT 5
+# define DP_TEST_BIT_DEPTH_6 (0 << 5)
+# define DP_TEST_BIT_DEPTH_8 (1 << 5)
+# define DP_TEST_BIT_DEPTH_10 (2 << 5)
+# define DP_TEST_BIT_DEPTH_12 (3 << 5)
+# define DP_TEST_BIT_DEPTH_16 (4 << 5)
+
+#define DP_TEST_MISC1 0x233
+# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
+# define DP_TEST_INTERLACED (1 << 1)
+
+#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
#define DP_TEST_CRC_R_CR 0x240
#define DP_TEST_CRC_G_Y 0x242
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests
2017-01-21 3:09 ` [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests Manasi Navare
@ 2017-01-24 16:05 ` Jani Nikula
0 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2017-01-24 16:05 UTC (permalink / raw)
To: intel-gfx, dri-devel, Dave Airlie; +Cc: Manasi Navare, Daniel Vetter
On Sat, 21 Jan 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> v4:
> * Remove redundant single bit defs (Jani Nikula)
> v3:
> * Fix the conventions in bit definitions (Jani Nikula)
> v2:
> * Add all the other DP Complianec TEST register defs (Jani Nikula)
> Cc: dri-devel@lists.freedesktop.org
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Dave, ack on merging this through drm-intel to not require a backmerge
for the follow-up patches?
> ---
> include/drm/drm_dp_helper.h | 57 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 57 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 0468135..ba89295 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -417,6 +417,63 @@
> #define DP_TEST_LANE_COUNT 0x220
>
> #define DP_TEST_PATTERN 0x221
> +# define DP_NO_TEST_PATTERN 0x0
> +# define DP_COLOR_RAMP 0x1
> +# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
> +# define DP_COLOR_SQUARE 0x3
> +
> +#define DP_TEST_H_TOTAL_HI 0x222
> +#define DP_TEST_H_TOTAL_LO 0x223
> +
> +#define DP_TEST_V_TOTAL_HI 0x224
> +#define DP_TEST_V_TOTAL_LO 0x225
> +
> +#define DP_TEST_H_START_HI 0x226
> +#define DP_TEST_H_START_LO 0x227
> +
> +#define DP_TEST_V_START_HI 0x228
> +#define DP_TEST_V_START_LO 0x229
> +
> +#define DP_TEST_HSYNC_HI 0x22A
> +# define DP_TEST_HSYNC_POLARITY (1 << 7)
> +# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
> +#define DP_TEST_HSYNC_WIDTH_LO 0x22B
> +
> +#define DP_TEST_VSYNC_HI 0x22C
> +# define DP_TEST_VSYNC_POLARITY (1 << 7)
> +# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
> +#define DP_TEST_VSYNC_WIDTH_LO 0x22D
> +
> +#define DP_TEST_H_WIDTH_HI 0x22E
> +#define DP_TEST_H_WIDTH_LO 0x22F
> +
> +#define DP_TEST_V_HEIGHT_HI 0x230
> +#define DP_TEST_V_HEIGHT_LO 0x231
> +
> +#define DP_TEST_MISC0 0x232
> +# define DP_TEST_SYNC_CLOCK (1 << 0)
> +# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
> +# define DP_TEST_COLOR_FORMAT_SHIFT 1
> +# define DP_COLOR_FORMAT_RGB (0 << 1)
> +# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
> +# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
> +# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
> +# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
> +# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
> +# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
> +# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
> +# define DP_TEST_BIT_DEPTH_SHIFT 5
> +# define DP_TEST_BIT_DEPTH_6 (0 << 5)
> +# define DP_TEST_BIT_DEPTH_8 (1 << 5)
> +# define DP_TEST_BIT_DEPTH_10 (2 << 5)
> +# define DP_TEST_BIT_DEPTH_12 (3 << 5)
> +# define DP_TEST_BIT_DEPTH_16 (4 << 5)
> +
> +#define DP_TEST_MISC1 0x233
> +# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
> +# define DP_TEST_INTERLACED (1 << 1)
> +
> +#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
>
> #define DP_TEST_CRC_R_CR 0x240
> #define DP_TEST_CRC_G_Y 0x242
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 4/4] drm/i915: Add support for DP Video pattern compliance tests
2017-01-21 3:09 [PATCH 0/4] Add automation support for DP Compliance (Rev 6) Manasi Navare
` (2 preceding siblings ...)
2017-01-21 3:09 ` [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests Manasi Navare
@ 2017-01-21 3:09 ` Manasi Navare
2017-01-24 16:21 ` [PATCH v4 " Manasi Navare
2017-01-21 4:24 ` ✓ Fi.CI.BAT: success for Add automation support for DP Compliance (Rev 6) Patchwork
` (3 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Manasi Navare @ 2017-01-21 3:09 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Daniel Vetter
The intel_dp_autotest_video_pattern() function gets invoked through the
compliance test handler on a HPD short pulse if the test type is
set to DP_TEST_VIDEO_PATTERN. This performs the DPCD registers
reads to read the requested test pattern, video pattern resolution,
frame rate and bits per color value. The results of this analysis
are handed off to userspace so that the userspace app can set the
video pattern mode appropriately for the test result/response.
When the test is requested with specific BPC value, we read the BPC
value from the DPCD register. If this BPC value in intel_dp structure
has a non-zero value and we're on a display port connector, then we use
the value to calculate the bpp for the pipe. Also in this case if its
a 18bpp video pattern request, then we force the dithering on pipe to be
disabled since it causes CRC mismatches.
The compliance_test_active flag is set at the end of the individual
test handling functions. This is so that the kernel-side operations
can be completed without the risk of interruption from the userspace
app that is polling on that flag.
v4:
*Return TEST_NAK on read failures and invalid values (Jani Nikula)
* Address CRC mismatch errors
v3:
* Use the updated properly shifted bit definitions (Jani Nikula)
* Force dithering to be disabled on 18bpp compliance
test request (Manasi Navare)
v2:
* Updated the DPCD Register reads based on proper defines in header (Jani Nikula)
* Squahsed the patch that forced the pipe bpp to compliance test bpp (Jani Nikula)
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 +++++
drivers/gpu/drm/i915/intel_display.c | 7 ++--
drivers/gpu/drm/i915/intel_dp.c | 66 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dp_mst.c | 7 +++-
drivers/gpu/drm/i915/intel_drv.h | 11 ++++++
5 files changed, 97 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8ec7edf..2eb8e50 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3776,6 +3776,15 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data)
DP_TEST_LINK_EDID_READ)
seq_printf(m, "%lx",
intel_dp->compliance.test_data.edid);
+ else if (intel_dp->compliance.test_type ==
+ DP_TEST_LINK_VIDEO_PATTERN) {
+ seq_printf(m, "hdisplay: %d\n",
+ intel_dp->compliance.test_data.hdisplay);
+ seq_printf(m, "vdisplay: %d\n",
+ intel_dp->compliance.test_data.vdisplay);
+ seq_printf(m, "bpc: %u\n",
+ intel_dp->compliance.test_data.bpc);
+ }
} else
seq_puts(m, "0");
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0f4272f..9674a1a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13052,8 +13052,11 @@ static bool check_digital_port_conflicts(struct drm_atomic_state *state)
}
/* Dithering seems to not pass-through bits correctly when it should, so
- * only enable it on 6bpc panels. */
- pipe_config->dither = pipe_config->pipe_bpp == 6*3;
+ * only enable it on 6bpc panels and when its not a compliance
+ * test requesting 6bpc video pattern.
+ */
+ pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
+ !pipe_config->dither_force_disable;
DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a65c909..76c52e7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -28,8 +28,10 @@
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/export.h>
+#include <linux/types.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
+#include <asm/byteorder.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
@@ -1593,6 +1595,13 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
if (bpc > 0)
bpp = min(bpp, 3*bpc);
+ /* For DP Compliance we override the computed bpp for the pipe */
+ if (intel_dp->compliance.test_data.bpc != 0) {
+ pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
+ pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
+ DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
+ pipe_config->pipe_bpp);
+ }
return bpp;
}
@@ -3976,6 +3985,63 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
{
uint8_t test_result = DP_TEST_NAK;
+ uint8_t test_pattern;
+ uint16_t test_misc;
+ __be16 h_width, v_height;
+ int status = 0;
+
+ /* Read the TEST_PATTERN (DP CTS 3.1.5) */
+ status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_PATTERN,
+ &test_pattern, 1);
+ if (status <= 0) {
+ DRM_DEBUG_KMS("Test pattern read failed\n");
+ return test_result;
+ }
+ if (test_pattern != DP_COLOR_RAMP)
+ return test_result;
+ intel_dp->compliance.test_data.video_pattern = test_pattern;
+
+ status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
+ &h_width, 2);
+ if (status <= 0) {
+ DRM_DEBUG_KMS("H Width read failed\n");
+ return test_result;
+ }
+ intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
+
+ status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
+ &v_height, 2);
+ if (status <= 0) {
+ DRM_DEBUG_KMS("V Height read failed\n");
+ return test_result;
+ }
+ intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
+
+ status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_MISC0,
+ &test_misc, 1);
+ if (status <= 0) {
+ DRM_DEBUG_KMS("TEST MISC read failed\n");
+ return test_result;
+ }
+ if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
+ return test_result;
+ if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
+ return test_result;
+ switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
+ case DP_TEST_BIT_DEPTH_6:
+ intel_dp->compliance.test_data.bpc = 6;
+ break;
+ case DP_TEST_BIT_DEPTH_8:
+ intel_dp->compliance.test_data.bpc = 8;
+ break;
+ default:
+ return test_result;
+ }
+ /* Set test active flag here so userspace doesn't interrupt things */
+ intel_dp->compliance.test_active = 1;
+
+ test_result = DP_TEST_ACK;
+
return test_result;
}
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 205fe47..29a9af1 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -47,6 +47,11 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
pipe_config->has_pch_encoder = false;
bpp = 24;
+ if (intel_dp->compliance.test_data.bpc) {
+ bpp = intel_dp->compliance.test_data.bpc * 3;
+ DRM_DEBUG_KMS("Setting pipe bpp to %d\n",
+ bpp);
+ }
/*
* for MST we always configure max link bw - the spec doesn't
* seem to suggest we should do otherwise.
@@ -55,7 +60,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
pipe_config->lane_count = lane_count;
- pipe_config->pipe_bpp = 24;
+ pipe_config->pipe_bpp = bpp;
pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);
state = pipe_config->base.state;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0b8d6e4..1fec2f5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -578,6 +578,14 @@ struct intel_crtc_state {
*/
bool dither;
+ /*
+ * Dither gets enabled for 18bpp which causes CRC mismatch errors for
+ * compliance video pattern tests.
+ * Disable dither only if it is a compliance test request for
+ * 18bpp.
+ */
+ bool dither_force_disable;
+
/* Controls for the clock computation, to override various stages. */
bool clock_set;
@@ -888,6 +896,9 @@ struct intel_dp_desc {
struct intel_dp_compliance_data {
unsigned long edid;
+ uint8_t video_pattern;
+ uint16_t hdisplay, vdisplay;
+ uint8_t bpc;
};
struct intel_dp_compliance {
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 4/4] drm/i915: Add support for DP Video pattern compliance tests
2017-01-21 3:09 ` [PATCH 4/4] drm/i915: Add support for DP Video pattern compliance tests Manasi Navare
@ 2017-01-24 16:21 ` Manasi Navare
0 siblings, 0 replies; 23+ messages in thread
From: Manasi Navare @ 2017-01-24 16:21 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Manasi Navare, Daniel Vetter
The intel_dp_autotest_video_pattern() function gets invoked through the
compliance test handler on a HPD short pulse if the test type is
set to DP_TEST_VIDEO_PATTERN. This performs the DPCD registers
reads to read the requested test pattern, video pattern resolution,
frame rate and bits per color value. The results of this analysis
are handed off to userspace so that the userspace app can set the
video pattern mode appropriately for the test result/response.
When the test is requested with specific BPC value, we read the BPC
value from the DPCD register. If this BPC value in intel_dp structure
has a non-zero value and we're on a display port connector, then we use
the value to calculate the bpp for the pipe. Also in this case if its
a 18bpp video pattern request, then we force the dithering on pipe to be
disabled since it causes CRC mismatches.
The compliance_test_active flag is set at the end of the individual
test handling functions. This is so that the kernel-side operations
can be completed without the risk of interruption from the userspace
app that is polling on that flag.
v5:
* Remove test_result variable
* Populate the compliance test data at the end of the function (Jani Nikula)
v4:
*Return TEST_NAK on read failures and invalid values (Jani Nikula)
* Address CRC mismatch errors
v3:
* Use the updated properly shifted bit definitions (Jani Nikula)
* Force dithering to be disabled on 18bpp compliance
test request (Manasi Navare)
v2:
* Updated the DPCD Register reads based on proper defines in header (Jani Nikula)
* Squahsed the patch that forced the pipe bpp to compliance test bpp (Jani Nikula)
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 +++++
drivers/gpu/drm/i915/intel_display.c | 7 ++--
drivers/gpu/drm/i915/intel_dp.c | 68 ++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_dp_mst.c | 7 +++-
drivers/gpu/drm/i915/intel_drv.h | 11 ++++++
5 files changed, 97 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8ec7edf..2eb8e50 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3776,6 +3776,15 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data)
DP_TEST_LINK_EDID_READ)
seq_printf(m, "%lx",
intel_dp->compliance.test_data.edid);
+ else if (intel_dp->compliance.test_type ==
+ DP_TEST_LINK_VIDEO_PATTERN) {
+ seq_printf(m, "hdisplay: %d\n",
+ intel_dp->compliance.test_data.hdisplay);
+ seq_printf(m, "vdisplay: %d\n",
+ intel_dp->compliance.test_data.vdisplay);
+ seq_printf(m, "bpc: %u\n",
+ intel_dp->compliance.test_data.bpc);
+ }
} else
seq_puts(m, "0");
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0bf8e1b..87621f0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13060,8 +13060,11 @@ static bool check_digital_port_conflicts(struct drm_atomic_state *state)
}
/* Dithering seems to not pass-through bits correctly when it should, so
- * only enable it on 6bpc panels. */
- pipe_config->dither = pipe_config->pipe_bpp == 6*3;
+ * only enable it on 6bpc panels and when its not a compliance
+ * test requesting 6bpc video pattern.
+ */
+ pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
+ !pipe_config->dither_force_disable;
DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 29aab9e..59130b5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -28,8 +28,10 @@
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/export.h>
+#include <linux/types.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
+#include <asm/byteorder.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
@@ -1593,6 +1595,13 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
if (bpc > 0)
bpp = min(bpp, 3*bpc);
+ /* For DP Compliance we override the computed bpp for the pipe */
+ if (intel_dp->compliance.test_data.bpc != 0) {
+ pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
+ pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
+ DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
+ pipe_config->pipe_bpp);
+ }
return bpp;
}
@@ -3974,8 +3983,63 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
{
- uint8_t test_result = DP_TEST_NAK;
- return test_result;
+ uint8_t test_pattern;
+ uint16_t test_misc;
+ __be16 h_width, v_height;
+ int status = 0;
+
+ /* Read the TEST_PATTERN (DP CTS 3.1.5) */
+ status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_PATTERN,
+ &test_pattern, 1);
+ if (status <= 0) {
+ DRM_DEBUG_KMS("Test pattern read failed\n");
+ return DP_TEST_NAK;
+ }
+ if (test_pattern != DP_COLOR_RAMP)
+ return DP_TEST_NAK;
+
+ status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
+ &h_width, 2);
+ if (status <= 0) {
+ DRM_DEBUG_KMS("H Width read failed\n");
+ return DP_TEST_NAK;
+ }
+
+ status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
+ &v_height, 2);
+ if (status <= 0) {
+ DRM_DEBUG_KMS("V Height read failed\n");
+ return DP_TEST_NAK;
+ }
+
+ status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_MISC0,
+ &test_misc, 1);
+ if (status <= 0) {
+ DRM_DEBUG_KMS("TEST MISC read failed\n");
+ return DP_TEST_NAK;
+ }
+ if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
+ return DP_TEST_NAK;
+ if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
+ return DP_TEST_NAK;
+ switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
+ case DP_TEST_BIT_DEPTH_6:
+ intel_dp->compliance.test_data.bpc = 6;
+ break;
+ case DP_TEST_BIT_DEPTH_8:
+ intel_dp->compliance.test_data.bpc = 8;
+ break;
+ default:
+ return DP_TEST_NAK;
+ }
+
+ intel_dp->compliance.test_data.video_pattern = test_pattern;
+ intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
+ intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
+ /* Set test active flag here so userspace doesn't interrupt things */
+ intel_dp->compliance.test_active = 1;
+
+ return DP_TEST_ACK;
}
static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 205fe47..29a9af1 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -47,6 +47,11 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
pipe_config->has_pch_encoder = false;
bpp = 24;
+ if (intel_dp->compliance.test_data.bpc) {
+ bpp = intel_dp->compliance.test_data.bpc * 3;
+ DRM_DEBUG_KMS("Setting pipe bpp to %d\n",
+ bpp);
+ }
/*
* for MST we always configure max link bw - the spec doesn't
* seem to suggest we should do otherwise.
@@ -55,7 +60,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
pipe_config->lane_count = lane_count;
- pipe_config->pipe_bpp = 24;
+ pipe_config->pipe_bpp = bpp;
pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);
state = pipe_config->base.state;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0b8d6e4..1fec2f5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -578,6 +578,14 @@ struct intel_crtc_state {
*/
bool dither;
+ /*
+ * Dither gets enabled for 18bpp which causes CRC mismatch errors for
+ * compliance video pattern tests.
+ * Disable dither only if it is a compliance test request for
+ * 18bpp.
+ */
+ bool dither_force_disable;
+
/* Controls for the clock computation, to override various stages. */
bool clock_set;
@@ -888,6 +896,9 @@ struct intel_dp_desc {
struct intel_dp_compliance_data {
unsigned long edid;
+ uint8_t video_pattern;
+ uint16_t hdisplay, vdisplay;
+ uint8_t bpc;
};
struct intel_dp_compliance {
--
1.9.1
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 23+ messages in thread
* ✓ Fi.CI.BAT: success for Add automation support for DP Compliance (Rev 6)
2017-01-21 3:09 [PATCH 0/4] Add automation support for DP Compliance (Rev 6) Manasi Navare
` (3 preceding siblings ...)
2017-01-21 3:09 ` [PATCH 4/4] drm/i915: Add support for DP Video pattern compliance tests Manasi Navare
@ 2017-01-21 4:24 ` Patchwork
2017-01-21 15:16 ` [PATCH 0/4] " Jani Nikula
` (2 subsequent siblings)
7 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2017-01-21 4:24 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: intel-gfx
== Series Details ==
Series: Add automation support for DP Compliance (Rev 6)
URL : https://patchwork.freedesktop.org/series/18329/
State : success
== Summary ==
Series 18329v1 Add automation support for DP Compliance (Rev 6)
https://patchwork.freedesktop.org/api/1.0/series/18329/revisions/1/mbox/
fi-bdw-5557u total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14
fi-bsw-n3050 total:246 pass:207 dwarn:0 dfail:0 fail:0 skip:39
fi-bxt-j4205 total:246 pass:224 dwarn:0 dfail:0 fail:0 skip:22
fi-bxt-t5700 total:79 pass:66 dwarn:0 dfail:0 fail:0 skip:12
fi-byt-j1900 total:246 pass:219 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-n2820 total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31
fi-hsw-4770 total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19
fi-hsw-4770r total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19
fi-ivb-3520m total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21
fi-ivb-3770 total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21
fi-kbl-7500u total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6260u total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13
fi-skl-6700hq total:246 pass:226 dwarn:0 dfail:0 fail:0 skip:20
fi-skl-6700k total:246 pass:222 dwarn:3 dfail:0 fail:0 skip:21
fi-skl-6770hq total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13
fi-snb-2520m total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31
fi-snb-2600 total:246 pass:214 dwarn:0 dfail:0 fail:0 skip:32
b32b21b117a110873013e5e6d4fa880b6a81a404 drm-tip: 2017y-01m-20d-20h-00m-57s UTC integration manifest
d1aa695 drm/i915: Add support for DP Video pattern compliance tests
b78e690 drm: Add definitions for DP compliance Video pattern tests
2f7e02d drm/i915: Fixes to support DP Compliance EDID tests
f77526f drm/i915: Add support for DP link training compliance
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3568/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH 0/4] Add automation support for DP Compliance (Rev 6)
2017-01-21 3:09 [PATCH 0/4] Add automation support for DP Compliance (Rev 6) Manasi Navare
` (4 preceding siblings ...)
2017-01-21 4:24 ` ✓ Fi.CI.BAT: success for Add automation support for DP Compliance (Rev 6) Patchwork
@ 2017-01-21 15:16 ` Jani Nikula
2017-01-23 17:05 ` Manasi Navare
2017-01-24 17:24 ` ✗ Fi.CI.BAT: warning for Add automation support for DP Compliance (Rev 6) (rev3) Patchwork
2017-01-26 14:17 ` [Intel-gfx] [PATCH 0/4] Add automation support for DP Compliance (Rev 6) Jani Nikula
7 siblings, 1 reply; 23+ messages in thread
From: Jani Nikula @ 2017-01-21 15:16 UTC (permalink / raw)
To: Manasi Navare, intel-gfx, dri-devel
On Sat, 21 Jan 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> This patch series addresses all the review comments from the previous series:
> https://patchwork.freedesktop.org/series/18256/
It does not, and it frustrates me.
BR,
Jani.
>
> On top of that it also adds a fix for CRC mismatches seen during
> 18bpp video pattern compliance testing. This is done by forcing dither
> on the pipe to be disabled if it is a 18bpp compliance test request.
>
> Manasi Navare (4):
> drm/i915: Add support for DP link training compliance
> drm/i915: Fixes to support DP Compliance EDID tests
> drm: Add definitions for DP compliance Video pattern tests
> drm/i915: Add support for DP Video pattern compliance tests
>
> drivers/gpu/drm/i915/i915_debugfs.c | 14 +++-
> drivers/gpu/drm/i915/intel_display.c | 7 +-
> drivers/gpu/drm/i915/intel_dp.c | 134 +++++++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/intel_dp_mst.c | 7 +-
> drivers/gpu/drm/i915/intel_drv.h | 13 ++++
> include/drm/drm_dp_helper.h | 57 +++++++++++++++
> 6 files changed, 221 insertions(+), 11 deletions(-)
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH 0/4] Add automation support for DP Compliance (Rev 6)
2017-01-21 15:16 ` [PATCH 0/4] " Jani Nikula
@ 2017-01-23 17:05 ` Manasi Navare
2017-01-23 18:39 ` [Intel-gfx] " Manasi Navare
0 siblings, 1 reply; 23+ messages in thread
From: Manasi Navare @ 2017-01-23 17:05 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
On Sat, Jan 21, 2017 at 05:16:42PM +0200, Jani Nikula wrote:
> On Sat, 21 Jan 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> > This patch series addresses all the review comments from the previous series:
> > https://patchwork.freedesktop.org/series/18256/
>
> It does not, and it frustrates me.
>
> BR,
> Jani.
>
>
Hi Jani,
I have addressed the comments:
* Use link rate instead of link BW, validate the values before storing in the compliance structure
and return NAK on invalid and read failures.
* Corrected the definitins in drm_dp_helper.h
Could you please explain which of the comments were not addressed that made it so frustrating?
It has been frustrating enough for me to be carrying this series of patches for a year almost
knowing that it passes 100% compliance but still is not merged.
Regards
Manasi
> >
> > On top of that it also adds a fix for CRC mismatches seen during
> > 18bpp video pattern compliance testing. This is done by forcing dither
> > on the pipe to be disabled if it is a 18bpp compliance test request.
> >
> > Manasi Navare (4):
> > drm/i915: Add support for DP link training compliance
> > drm/i915: Fixes to support DP Compliance EDID tests
> > drm: Add definitions for DP compliance Video pattern tests
> > drm/i915: Add support for DP Video pattern compliance tests
> >
> > drivers/gpu/drm/i915/i915_debugfs.c | 14 +++-
> > drivers/gpu/drm/i915/intel_display.c | 7 +-
> > drivers/gpu/drm/i915/intel_dp.c | 134 +++++++++++++++++++++++++++++++++--
> > drivers/gpu/drm/i915/intel_dp_mst.c | 7 +-
> > drivers/gpu/drm/i915/intel_drv.h | 13 ++++
> > include/drm/drm_dp_helper.h | 57 +++++++++++++++
> > 6 files changed, 221 insertions(+), 11 deletions(-)
>
> --
> Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH 0/4] Add automation support for DP Compliance (Rev 6)
2017-01-23 17:05 ` Manasi Navare
@ 2017-01-23 18:39 ` Manasi Navare
2017-01-24 16:40 ` Jani Nikula
0 siblings, 1 reply; 23+ messages in thread
From: Manasi Navare @ 2017-01-23 18:39 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
On Mon, Jan 23, 2017 at 09:05:02AM -0800, Manasi Navare wrote:
> On Sat, Jan 21, 2017 at 05:16:42PM +0200, Jani Nikula wrote:
> > On Sat, 21 Jan 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> > > This patch series addresses all the review comments from the previous series:
> > > https://patchwork.freedesktop.org/series/18256/
> >
> > It does not, and it frustrates me.
> >
> > BR,
> > Jani.
> >
> >
Jani,
I really appreciate all your feedback. I also agree that it is very important
that the patches are correct and improve the driver quality and that non eof the review
comments should be ignored even if it takes many review cycles.
As far as I know, I have addressed the review comments from previous round and answered
the questions/concerns that you had either in the M-L or in IRC.
May be answering them on IRC created some confusion and you thought that it was
unanswered. I will reply to all your review comments from previous round with what
I have chnaged to address it or why it wasnt changed. That way we can make sure that
none of them are getting ignored.
Hope this method works for you.
Regards
Manasi
>
> Hi Jani,
> I have addressed the comments:
>
> * Use link rate instead of link BW, validate the values before storing in the compliance structure
> and return NAK on invalid and read failures.
> * Corrected the definitins in drm_dp_helper.h
>
> Could you please explain which of the comments were not addressed that made it so frustrating?
> It has been frustrating enough for me to be carrying this series of patches for a year almost
> knowing that it passes 100% compliance but still is not merged.
>
> Regards
> Manasi
>
>
> > >
> > > On top of that it also adds a fix for CRC mismatches seen during
> > > 18bpp video pattern compliance testing. This is done by forcing dither
> > > on the pipe to be disabled if it is a 18bpp compliance test request.
> > >
> > > Manasi Navare (4):
> > > drm/i915: Add support for DP link training compliance
> > > drm/i915: Fixes to support DP Compliance EDID tests
> > > drm: Add definitions for DP compliance Video pattern tests
> > > drm/i915: Add support for DP Video pattern compliance tests
> > >
> > > drivers/gpu/drm/i915/i915_debugfs.c | 14 +++-
> > > drivers/gpu/drm/i915/intel_display.c | 7 +-
> > > drivers/gpu/drm/i915/intel_dp.c | 134 +++++++++++++++++++++++++++++++++--
> > > drivers/gpu/drm/i915/intel_dp_mst.c | 7 +-
> > > drivers/gpu/drm/i915/intel_drv.h | 13 ++++
> > > include/drm/drm_dp_helper.h | 57 +++++++++++++++
> > > 6 files changed, 221 insertions(+), 11 deletions(-)
> >
> > --
> > Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 0/4] Add automation support for DP Compliance (Rev 6)
2017-01-23 18:39 ` [Intel-gfx] " Manasi Navare
@ 2017-01-24 16:40 ` Jani Nikula
2017-01-24 17:20 ` Manasi Navare
0 siblings, 1 reply; 23+ messages in thread
From: Jani Nikula @ 2017-01-24 16:40 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx, dri-devel
On Mon, 23 Jan 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> As far as I know, I have addressed the review comments from previous
> round and answered the questions/concerns that you had either in the
> M-L or in IRC. May be answering them on IRC created some confusion
> and you thought that it was unanswered. I will reply to all your
> review comments from previous round with what I have chnaged to
> address it or why it wasnt changed. That way we can make sure that
> none of them are getting ignored. Hope this method works for you.
In general, all review comments *must* be addressed, either by
responding to them (ask for details or rationale or question them) or
making the changes in code. Sending new patch versions without
mentioning why review comments have not been addressed is not okay, and
rubs many people the wrong way, and I'm not immune to that.
IRC may be okay for discussion, but if the other person does not seem to
be around or does not acknowledge your comments, you can't assume the
other person will (or even can) read all of the backlog. For bigger
design discussions, it is usually best to recap the IRC discussions in a
reply to the mailing list (but that's general advice, and not really the
case here).
IIUC you're going to make additional changes to the series. Please make
them, and read the patches carefully before you send them. (Please note
that this is not intended as patronising advise; I read almost all of my
contributions as patches before I send them. And it's not unusual for me
to change stuff at this stage to make it easier to read and review.)
Let's drive this to conclusion now.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 0/4] Add automation support for DP Compliance (Rev 6)
2017-01-24 16:40 ` Jani Nikula
@ 2017-01-24 17:20 ` Manasi Navare
0 siblings, 0 replies; 23+ messages in thread
From: Manasi Navare @ 2017-01-24 17:20 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
On Tue, Jan 24, 2017 at 06:40:51PM +0200, Jani Nikula wrote:
> On Mon, 23 Jan 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> > As far as I know, I have addressed the review comments from previous
> > round and answered the questions/concerns that you had either in the
> > M-L or in IRC. May be answering them on IRC created some confusion
> > and you thought that it was unanswered. I will reply to all your
> > review comments from previous round with what I have chnaged to
> > address it or why it wasnt changed. That way we can make sure that
> > none of them are getting ignored. Hope this method works for you.
>
> In general, all review comments *must* be addressed, either by
> responding to them (ask for details or rationale or question them) or
> making the changes in code. Sending new patch versions without
> mentioning why review comments have not been addressed is not okay, and
> rubs many people the wrong way, and I'm not immune to that.
>
> IRC may be okay for discussion, but if the other person does not seem to
> be around or does not acknowledge your comments, you can't assume the
> other person will (or even can) read all of the backlog. For bigger
> design discussions, it is usually best to recap the IRC discussions in a
> reply to the mailing list (but that's general advice, and not really the
> case here).
>
> IIUC you're going to make additional changes to the series. Please make
> them, and read the patches carefully before you send them. (Please note
> that this is not intended as patronising advise; I read almost all of my
> contributions as patches before I send them. And it's not unusual for me
> to change stuff at this stage to make it easier to read and review.)
>
> Let's drive this to conclusion now.
>
>
> BR,
> Jani.
>
I agree and I will take care of these things next time.
For now yes lets drive this to conclusion. I went over the comments all over again and
noticed that there were these things that I interpreted differently or had a different opinion
on and were not addressed:
* Remove test_result variable
* Populate intel-dp->compliance.test_data values at the end of the function for
all test handlers (link training and video pattern) after all reads and validations
are done.
I have changed above two things in Patches 1 and 4 and resubmitted newer versions of those.
Hope those revisions would drive us to conclusion.
Thanks again for taking time for driving this to completion.
Regards
Manasi
>
> --
> Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✗ Fi.CI.BAT: warning for Add automation support for DP Compliance (Rev 6) (rev3)
2017-01-21 3:09 [PATCH 0/4] Add automation support for DP Compliance (Rev 6) Manasi Navare
` (5 preceding siblings ...)
2017-01-21 15:16 ` [PATCH 0/4] " Jani Nikula
@ 2017-01-24 17:24 ` Patchwork
2017-01-26 14:17 ` [Intel-gfx] [PATCH 0/4] Add automation support for DP Compliance (Rev 6) Jani Nikula
7 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2017-01-24 17:24 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: intel-gfx
== Series Details ==
Series: Add automation support for DP Compliance (Rev 6) (rev3)
URL : https://patchwork.freedesktop.org/series/18329/
State : warning
== Summary ==
Series 18329v3 Add automation support for DP Compliance (Rev 6)
https://patchwork.freedesktop.org/api/1.0/series/18329/revisions/3/mbox/
Test gem_exec_suspend:
Subgroup basic-s3:
pass -> DMESG-WARN (fi-bxt-j4205)
fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14
fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39
fi-bxt-j4205 total:247 pass:224 dwarn:1 dfail:0 fail:0 skip:22
fi-bxt-t5700 total:79 pass:66 dwarn:0 dfail:0 fail:0 skip:12
fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31
fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19
fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19
fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21
fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21
fi-kbl-7500u total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13
fi-skl-6700hq total:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20
fi-skl-6700k total:247 pass:222 dwarn:4 dfail:0 fail:0 skip:21
fi-skl-6770hq total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13
fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31
fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32
d1b225ff77cf018e7169bd6253815afd8709e05d drm-tip: 2017y-01m-24d-16h-05m-12s UTC integration manifest
5ee120f drm/i915: Add support for DP Video pattern compliance tests
652ddd1e drm: Add definitions for DP compliance Video pattern tests
7b18159 drm/i915: Fixes to support DP Compliance EDID tests
a48a894 drm/i915: Add support for DP link training compliance
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3595/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [Intel-gfx] [PATCH 0/4] Add automation support for DP Compliance (Rev 6)
2017-01-21 3:09 [PATCH 0/4] Add automation support for DP Compliance (Rev 6) Manasi Navare
` (6 preceding siblings ...)
2017-01-24 17:24 ` ✗ Fi.CI.BAT: warning for Add automation support for DP Compliance (Rev 6) (rev3) Patchwork
@ 2017-01-26 14:17 ` Jani Nikula
7 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2017-01-26 14:17 UTC (permalink / raw)
To: Manasi Navare, intel-gfx, dri-devel
On Sat, 21 Jan 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> This patch series addresses all the review comments from the previous series:
> https://patchwork.freedesktop.org/series/18256/
>
> On top of that it also adds a fix for CRC mismatches seen during
> 18bpp video pattern compliance testing. This is done by forcing dither
> on the pipe to be disabled if it is a 18bpp compliance test request.
Pushed to drm-intel-next-queued, thanks for the patches.
BR,
Jani.
>
> Manasi Navare (4):
> drm/i915: Add support for DP link training compliance
> drm/i915: Fixes to support DP Compliance EDID tests
> drm: Add definitions for DP compliance Video pattern tests
> drm/i915: Add support for DP Video pattern compliance tests
>
> drivers/gpu/drm/i915/i915_debugfs.c | 14 +++-
> drivers/gpu/drm/i915/intel_display.c | 7 +-
> drivers/gpu/drm/i915/intel_dp.c | 134 +++++++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/intel_dp_mst.c | 7 +-
> drivers/gpu/drm/i915/intel_drv.h | 13 ++++
> include/drm/drm_dp_helper.h | 57 +++++++++++++++
> 6 files changed, 221 insertions(+), 11 deletions(-)
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 23+ messages in thread