* [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT
@ 2015-09-01 14:11 Uma Shankar
2015-09-01 14:11 ` [BXT MIPI PATCH v3 01/14] drm/i915/bxt: Initialize MIPI " Uma Shankar
` (13 more replies)
0 siblings, 14 replies; 69+ messages in thread
From: Uma Shankar @ 2015-09-01 14:11 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shobhit.kumar
This patch series adds support for MIPI DSI for BXT platform.
Support for VBT v3 sequence parsing and programming is needed
for panel, backlight enable and control. The same will be added
as part of a different patch series. This is already floated and
is under review.
Below is the link for earlier patch series in mailing list:
v1: http://www.spinics.net/lists/intel-gfx/msg67354.html
v2: http://lists.freedesktop.org/archives/intel-gfx/2015-July/072353.html
v2: Addressed the review comments from Jani. Fixed Macros
definitions as per convention. Adjusted the BXT DSI MACROS to
get proper offsets for PORT C. DDI/DSI handling in generic
code has been simplified. Backlight handling for BXT DSI has
been re-designed.
v3: Rebased on latest drm-nightly branch. Addressed review comments
fom Jani.
Shashank Sharma (10):
drm/i915/bxt: Initialize MIPI for BXT
drm/i915/bxt: Enable BXT DSI PLL
drm/i915/bxt: Disable DSI PLL for BXT
drm/i915/bxt: DSI prepare changes for BXT
drm/i915/bxt: DSI encoder support in CRTC modeset
drm/i915/bxt: DSI enable for BXT
drm/i915/bxt: Program Tx Rx and Dphy clocks
drm/i915/bxt: DSI disable and post-disable
drm/i915/bxt: get_hw_state for BXT
drm/i915/bxt: get DSI pixelclock
Sunil Kamath (1):
drm/i915/bxt: Modify BXT BLC according to VBT changes
Uma Shankar (3):
drm/i915/bxt: Program Backlight PWM frequency
drm/i915/bxt: Remove DSP CLK_GATE programming for BXT
drm/i915: Added BXT DSI backlight support
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 140 ++++++++++++++-
drivers/gpu/drm/i915/intel_ddi.c | 29 ++-
drivers/gpu/drm/i915/intel_display.c | 22 ++-
drivers/gpu/drm/i915/intel_dp_mst.c | 1 +
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_dsi.c | 313 ++++++++++++++++++++++++---------
drivers/gpu/drm/i915/intel_dsi.h | 7 +-
drivers/gpu/drm/i915/intel_dsi_pll.c | 240 ++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_opregion.c | 3 +-
drivers/gpu/drm/i915/intel_panel.c | 95 ++++++++--
11 files changed, 732 insertions(+), 121 deletions(-)
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v3 01/14] drm/i915/bxt: Initialize MIPI for BXT
2015-09-01 14:11 [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT Uma Shankar
@ 2015-09-01 14:11 ` Uma Shankar
2015-09-18 12:17 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 02/14] drm/i915/bxt: Enable BXT DSI PLL Uma Shankar
` (12 subsequent siblings)
13 siblings, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-01 14:11 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shobhit.kumar
From: Shashank Sharma <shashank.sharma@intel.com>
This patch contains following changes:
1. Add BXT MIPI display address base.
2. Call dsi_init from display_setup function.
v2: Rebased on latest nightly branch
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 3 +++
drivers/gpu/drm/i915/intel_dsi.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2030f60..621151b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1641,6 +1641,7 @@ enum skl_disp_power_wells {
#define VLV_DISPLAY_BASE 0x180000
#define VLV_MIPI_BASE VLV_DISPLAY_BASE
+#define BXT_MIPI_BASE 0x60000
#define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030)
#define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 87476ff..b8e0310 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13906,6 +13906,9 @@ static void intel_setup_outputs(struct drm_device *dev)
* DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
* detect the ports.
*/
+ /* Initialize MIPI for BXT */
+ intel_dsi_init(dev);
+
intel_ddi_init(dev, PORT_A);
intel_ddi_init(dev, PORT_B);
intel_ddi_init(dev, PORT_C);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index b5a5558..b59b828 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -998,6 +998,8 @@ void intel_dsi_init(struct drm_device *dev)
if (IS_VALLEYVIEW(dev)) {
dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
+ } else if (IS_BROXTON(dev)) {
+ dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
} else {
DRM_ERROR("Unsupported Mipi device to reg base");
return;
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v3 02/14] drm/i915/bxt: Enable BXT DSI PLL
2015-09-01 14:11 [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT Uma Shankar
2015-09-01 14:11 ` [BXT MIPI PATCH v3 01/14] drm/i915/bxt: Initialize MIPI " Uma Shankar
@ 2015-09-01 14:11 ` Uma Shankar
2015-09-18 12:32 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 03/14] drm/i915/bxt: Disable DSI PLL for BXT Uma Shankar
` (11 subsequent siblings)
13 siblings, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-01 14:11 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shobhit.kumar
From: Shashank Sharma <shashank.sharma@intel.com>
This patch adds new functions for BXT clock and PLL programming.
They are:
1. configure_dsi_pll for BXT.
This function does the basic math and generates the divider ratio
based on requested pixclock, and program clock registers.
2. enable_dsi_pll function.
This function programs the calculated clock values on the PLL.
3. intel_enable_dsi_pll
Wrapper function to use same code for multiple platforms. It checks the
platform and calls appropriate core pll enable function.
v2: Fixed Jani's review comments. Macros are adjusted as per convention.
v3: Removed a redundant change wrt code comment.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++
drivers/gpu/drm/i915/intel_dsi.c | 2 +-
drivers/gpu/drm/i915/intel_dsi.h | 2 +-
drivers/gpu/drm/i915/intel_dsi_pll.c | 95 +++++++++++++++++++++++++++++++++-
4 files changed, 118 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 621151b..06bb2e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7362,6 +7362,28 @@ enum skl_disp_power_wells {
#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
+#define BXT_DSI_PLL_CTL 0x161000
+#define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
+#define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
+#define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
+#define BXT_DSIC_16X_BY2 (1 << 10)
+#define BXT_DSIC_16X_BY3 (2 << 10)
+#define BXT_DSIC_16X_BY4 (3 << 10)
+#define BXT_DSIA_16X_BY2 (1 << 8)
+#define BXT_DSIA_16X_BY3 (2 << 8)
+#define BXT_DSIA_16X_BY4 (3 << 8)
+#define BXT_DSI_FREQ_SEL_SHIFT 8
+#define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
+
+#define BXT_DSI_PLL_RATIO_MAX 0x7D
+#define BXT_DSI_PLL_RATIO_MIN 0x22
+#define BXT_DSI_PLL_RATIO_MASK 0xFF
+#define BXT_REF_CLOCK_KHZ 19500
+
+#define BXT_DSI_PLL_ENABLE 0x46080
+#define BXT_DSI_PLL_DO_ENABLE (1 << 31)
+#define BXT_DSI_PLL_LOCKED (1 << 30)
+
#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
#define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index b59b828..fb259fb 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -903,8 +903,8 @@ static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
intel_dsi_prepare(encoder);
+ intel_enable_dsi_pll(encoder);
- vlv_enable_dsi_pll(encoder);
}
static enum drm_connector_status
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 2784ac4..20cfcf07 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -121,7 +121,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
return container_of(encoder, struct intel_dsi, base.base);
}
-extern void vlv_enable_dsi_pll(struct intel_encoder *encoder);
+extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index d20cf37..3830a4f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -237,7 +237,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
}
-void vlv_enable_dsi_pll(struct intel_encoder *encoder)
+static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
u32 tmp;
@@ -368,3 +368,96 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
return pclk;
}
+
+static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ u8 dsi_ratio;
+ u32 dsi_clk;
+ u32 val;
+
+ dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
+ intel_dsi->lane_count);
+
+ /*
+ * From clock diagram, to get PLL ratio divider, divide double of DSI
+ * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
+ * round 'up' the result
+ */
+ dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
+ if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
+ dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
+ DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
+ return false;
+ }
+
+ /*
+ * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
+ * Spec says both have to be programmed, even if one is not getting
+ * used. Configure MIPI_CLOCK_CTL dividers in modeset
+ */
+ val = I915_READ(BXT_DSI_PLL_CTL);
+ val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
+ val &= ~BXT_DSI_FREQ_SEL_MASK;
+ val &= ~BXT_DSI_PLL_RATIO_MASK;
+ val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2);
+
+ /* As per recommendation from hardware team,
+ * Prog PVD ratio =1 if dsi ratio <= 50
+ */
+ if (dsi_ratio <= 50) {
+ val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
+ val |= BXT_DSI_PLL_PVD_RATIO_1;
+ }
+
+ I915_WRITE(BXT_DSI_PLL_CTL, val);
+ POSTING_READ(BXT_DSI_PLL_CTL);
+
+ return true;
+}
+
+static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ u32 val;
+
+ DRM_DEBUG_KMS("\n");
+
+ val = I915_READ(BXT_DSI_PLL_ENABLE);
+
+ if (val & BXT_DSI_PLL_DO_ENABLE) {
+ WARN(1, "DSI PLL already enabled. Disabling it.\n");
+ val &= ~BXT_DSI_PLL_DO_ENABLE;
+ I915_WRITE(BXT_DSI_PLL_ENABLE, val);
+ }
+
+ /* Configure PLL vales */
+ if (!bxt_configure_dsi_pll(encoder)) {
+ DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");
+ return;
+ }
+
+ /* Enable DSI PLL */
+ val = I915_READ(BXT_DSI_PLL_ENABLE);
+ val |= BXT_DSI_PLL_DO_ENABLE;
+ I915_WRITE(BXT_DSI_PLL_ENABLE, val);
+
+ /* Timeout and fail if PLL not locked */
+ if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) {
+ DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
+ return;
+ }
+
+ DRM_DEBUG_KMS("DSI PLL locked\n");
+}
+
+void intel_enable_dsi_pll(struct intel_encoder *encoder)
+{
+ struct drm_device *dev = encoder->base.dev;
+
+ if (IS_VALLEYVIEW(dev))
+ vlv_enable_dsi_pll(encoder);
+ else if (IS_BROXTON(dev))
+ bxt_enable_dsi_pll(encoder);
+}
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v3 03/14] drm/i915/bxt: Disable DSI PLL for BXT
2015-09-01 14:11 [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT Uma Shankar
2015-09-01 14:11 ` [BXT MIPI PATCH v3 01/14] drm/i915/bxt: Initialize MIPI " Uma Shankar
2015-09-01 14:11 ` [BXT MIPI PATCH v3 02/14] drm/i915/bxt: Enable BXT DSI PLL Uma Shankar
@ 2015-09-01 14:11 ` Uma Shankar
2015-09-18 12:57 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 04/14] drm/i915/bxt: DSI prepare changes " Uma Shankar
` (10 subsequent siblings)
13 siblings, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-01 14:11 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shobhit.kumar
From: Shashank Sharma <shashank.sharma@intel.com>
This patch adds two new functions:
- disable_dsi_pll.
BXT DSI disable sequence and registers are
different from previous platforms.
- intel_disable_dsi_pll
wrapper function to re-use the same code for
multiple platforms. It checks platform type and
calls appropriate core pll disable function.
v2: Fixed Jani's review comments.
v3: Rebased on latest drm-nightly branch.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 2 +-
drivers/gpu/drm/i915/intel_dsi.h | 2 +-
drivers/gpu/drm/i915/intel_dsi_pll.c | 32 +++++++++++++++++++++++++++++++-
3 files changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index fb259fb..bac988a 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -553,7 +553,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
usleep_range(2000, 2500);
}
- vlv_disable_dsi_pll(encoder);
+ intel_disable_dsi_pll(encoder);
}
static void intel_dsi_post_disable(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 20cfcf07..759983e 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -122,7 +122,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
}
extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
-extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
+extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 3830a4f..21a2e37 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -267,7 +267,7 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
DRM_DEBUG_KMS("DSI PLL locked\n");
}
-void vlv_disable_dsi_pll(struct intel_encoder *encoder)
+static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
u32 tmp;
@@ -284,6 +284,26 @@ void vlv_disable_dsi_pll(struct intel_encoder *encoder)
mutex_unlock(&dev_priv->sb_lock);
}
+static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ u32 val;
+
+ DRM_DEBUG_KMS("\n");
+
+ val = I915_READ(BXT_DSI_PLL_ENABLE);
+ val &= ~BXT_DSI_PLL_DO_ENABLE;
+ I915_WRITE(BXT_DSI_PLL_ENABLE, val);
+
+ /*
+ * PLL lock should deassert within 200us.
+ * Wait up to 1ms before timing out.
+ */
+ if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE)
+ & BXT_DSI_PLL_LOCKED) == 0, 1))
+ DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
+}
+
static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
{
int bpp;
@@ -461,3 +481,13 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder)
else if (IS_BROXTON(dev))
bxt_enable_dsi_pll(encoder);
}
+
+void intel_disable_dsi_pll(struct intel_encoder *encoder)
+{
+ struct drm_device *dev = encoder->base.dev;
+
+ if (IS_VALLEYVIEW(dev))
+ vlv_disable_dsi_pll(encoder);
+ else if (IS_BROXTON(dev))
+ bxt_disable_dsi_pll(encoder);
+}
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v3 04/14] drm/i915/bxt: DSI prepare changes for BXT
2015-09-01 14:11 [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT Uma Shankar
` (2 preceding siblings ...)
2015-09-01 14:11 ` [BXT MIPI PATCH v3 03/14] drm/i915/bxt: Disable DSI PLL for BXT Uma Shankar
@ 2015-09-01 14:11 ` Uma Shankar
2015-09-18 13:05 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset Uma Shankar
` (9 subsequent siblings)
13 siblings, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-01 14:11 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shobhit.kumar
From: Shashank Sharma <shashank.sharma@intel.com>
This patch modifies dsi_prepare() function to support the same
modeset prepare sequence for BXT also. Main changes are:
1. BXT port control register is different than VLV.
2. BXT modeset sequence needs vdisplay and hdisplay programmed
for transcoder.
3. BXT can select PIPE for MIPI transcoders.
4. BXT needs to program register MIPI_INIT_COUNT for both the ports,
even if only one is being used.
v2: Fixed Jani's review comments. Rectified the DSI Macros to get
proper register offsets using _MIPI_PORT instead of _TRANSCODER
v3: Rebased on latest drm-nightly branch. Fixed Jani's review comments.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 21 ++++++++++++
drivers/gpu/drm/i915/intel_dsi.c | 69 ++++++++++++++++++++++++++++++++------
2 files changed, 80 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 06bb2e1..997a999 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7362,6 +7362,22 @@ enum skl_disp_power_wells {
#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
+/* BXT MIPI mode configure */
+#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
+#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
+#define BXT_MIPI_TRANS_HACTIVE(tc) _MIPI_PORT(tc, \
+ _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
+
+#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
+#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
+#define BXT_MIPI_TRANS_VACTIVE(tc) _MIPI_PORT(tc, \
+ _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
+
+#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
+#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
+#define BXT_MIPI_TRANS_VTOTAL(tc) _MIPI_PORT(tc, \
+ _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
+
#define BXT_DSI_PLL_CTL 0x161000
#define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
#define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
@@ -7797,6 +7813,11 @@ enum skl_disp_power_wells {
#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
#define RGB_FLIP_TO_BGR (1 << 2)
+#define BXT_PIPE_SELECT_MASK (7 << 7)
+#define BXT_PIPE_SELECT_C (2 << 7)
+#define BXT_PIPE_SELECT_B (1 << 7)
+#define BXT_PIPE_SELECT_A (0 << 7)
+
#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
#define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index bac988a..6d0c992 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -726,6 +726,21 @@ static void set_dsi_timings(struct drm_encoder *encoder,
hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
for_each_dsi_port(port, intel_dsi->ports) {
+ if (IS_BROXTON(dev)) {
+ /*
+ * Program hdisplay and vdisplay on MIPI transcoder.
+ * This is different from calculated hactive and
+ * vactive, as they are calculated per channel basis,
+ * whereas these values should be based on resolution.
+ */
+ I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
+ mode->hdisplay);
+ I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
+ mode->vdisplay);
+ I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
+ mode->vtotal);
+ }
+
I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
I915_WRITE(MIPI_HFP_COUNT(port), hfp);
@@ -766,16 +781,39 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
}
for_each_dsi_port(port, intel_dsi->ports) {
- /* escape clock divider, 20MHz, shared for A and C.
- * device ready must be off when doing this! txclkesc? */
- tmp = I915_READ(MIPI_CTRL(PORT_A));
- tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
- I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
-
- /* read request priority is per pipe */
- tmp = I915_READ(MIPI_CTRL(port));
- tmp &= ~READ_REQUEST_PRIORITY_MASK;
- I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
+ if (IS_VALLEYVIEW(dev)) {
+ /*
+ * escape clock divider, 20MHz, shared for A and C.
+ * device ready must be off when doing this! txclkesc?
+ */
+ tmp = I915_READ(MIPI_CTRL(PORT_A));
+ tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
+ I915_WRITE(MIPI_CTRL(PORT_A), tmp |
+ ESCAPE_CLOCK_DIVIDER_1);
+
+ /* read request priority is per pipe */
+ tmp = I915_READ(MIPI_CTRL(port));
+ tmp &= ~READ_REQUEST_PRIORITY_MASK;
+ I915_WRITE(MIPI_CTRL(port), tmp |
+ READ_REQUEST_PRIORITY_HIGH);
+ } else if (IS_BROXTON(dev)) {
+ /*
+ * FIXME:
+ * BXT can connect any PIPE to any MIPI port.
+ * Select the pipe based on the MIPI port read from
+ * VBT for now. Pick PIPE A for MIPI port A and C
+ * for port C.
+ */
+ tmp = I915_READ(MIPI_CTRL(port));
+ tmp &= ~BXT_PIPE_SELECT_MASK;
+
+ if (port == PORT_A)
+ tmp |= BXT_PIPE_SELECT_A;
+ else if (port == PORT_C)
+ tmp |= BXT_PIPE_SELECT_C;
+
+ I915_WRITE(MIPI_CTRL(port), tmp);
+ }
/* XXX: why here, why like this? handling in irq handler?! */
I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
@@ -852,6 +890,17 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
I915_WRITE(MIPI_INIT_COUNT(port),
txclkesc(intel_dsi->escape_clk_div, 100));
+ if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
+ /*
+ * BXT spec says write MIPI_INIT_COUNT for
+ * both the ports, even if only one is
+ * getting used. So write the other port
+ * if not in dual link mode.
+ */
+ I915_WRITE(MIPI_INIT_COUNT(port ==
+ PORT_A ? PORT_C : PORT_A),
+ intel_dsi->init_count);
+ }
/* recovery disables */
I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-01 14:11 [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT Uma Shankar
` (3 preceding siblings ...)
2015-09-01 14:11 ` [BXT MIPI PATCH v3 04/14] drm/i915/bxt: DSI prepare changes " Uma Shankar
@ 2015-09-01 14:11 ` Uma Shankar
2015-09-18 14:18 ` Jani Nikula
2015-09-23 12:53 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 06/14] drm/i915/bxt: DSI enable for BXT Uma Shankar
` (8 subsequent siblings)
13 siblings, 2 replies; 69+ messages in thread
From: Uma Shankar @ 2015-09-01 14:11 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shobhit.kumar
From: Shashank Sharma <shashank.sharma@intel.com>
SKL and BXT qualifies the HAS_DDI() check, and hence haswell
modeset functions are re-used for modeset sequence. But DDI
interface doesn't include support for DSI.
This patch adds:
1. cases for DSI encoder, in those modeset functions and allows
a CRTC modeset
2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
needs to be done as such in CRTC for DSI encoder, as PLL, clock
and and transcoder programming will be taken care in encoder's
pre_enable and pre_pll_enable function.
v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
encoder like DSI for platforms having HAS_DDI as true.
v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
encoder.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 29 ++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_display.c | 19 ++++++++++++++-----
drivers/gpu/drm/i915/intel_dp_mst.c | 1 +
drivers/gpu/drm/i915/intel_opregion.c | 3 ++-
5 files changed, 46 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fd1de45..78d31c5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -142,6 +142,7 @@ enum plane {
#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
enum port {
+ PORT_INVALID = -1,
PORT_A = 0,
PORT_B,
PORT_C,
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cacb07b..5d5aad2 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
} else if (type == INTEL_OUTPUT_ANALOG) {
*dig_port = NULL;
*port = PORT_E;
+ } else if (type == INTEL_OUTPUT_DSI) {
+ *dig_port = NULL;
+ *port = PORT_INVALID;
+ DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
} else {
DRM_ERROR("Invalid DDI encoder type %d\n", type);
BUG();
@@ -392,6 +396,11 @@ void intel_prepare_ddi(struct drm_device *dev)
ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
+ if (port == PORT_INVALID) {
+ WARN_ON(1);
+ continue;
+ }
+
if (visited[port])
continue;
@@ -980,6 +989,8 @@ static void bxt_ddi_clock_get(struct intel_encoder *encoder,
enum port port = intel_ddi_get_encoder_port(encoder);
uint32_t dpll = port;
+ WARN_ON(port == PORT_INVALID);
+
pipe_config->port_clock =
bxt_calc_pll_link(dev_priv, dpll);
@@ -1572,6 +1583,8 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
int type = intel_encoder->type;
uint32_t temp;
+ WARN_ON(port == PORT_INVALID);
+
/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
temp = TRANS_DDI_FUNC_ENABLE;
temp |= TRANS_DDI_SELECT_PORT(port);
@@ -1684,6 +1697,8 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
enum intel_display_power_domain power_domain;
uint32_t tmp;
+ WARN_ON(port == PORT_INVALID);
+
power_domain = intel_display_port_power_domain(intel_encoder);
if (!intel_display_power_is_enabled(dev_priv, power_domain))
return false;
@@ -1730,6 +1745,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
u32 tmp;
int i;
+ WARN_ON(port == PORT_INVALID);
+
power_domain = intel_display_port_power_domain(encoder);
if (!intel_display_power_is_enabled(dev_priv, power_domain))
return false;
@@ -1779,11 +1796,14 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
{
struct drm_crtc *crtc = &intel_crtc->base;
- struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
enum port port = intel_ddi_get_encoder_port(intel_encoder);
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
+ WARN_ON(port == PORT_INVALID);
+
if (cpu_transcoder != TRANSCODER_EDP)
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
TRANS_CLK_SEL_PORT(port));
@@ -1870,6 +1890,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
int type = intel_encoder->type;
int hdmi_level;
+ WARN_ON(port == PORT_INVALID);
+
if (type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
intel_edp_panel_on(intel_dp);
@@ -1947,6 +1969,8 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
uint32_t val;
bool wait = false;
+ WARN_ON(port == PORT_INVALID);
+
val = I915_READ(DDI_BUF_CTL(port));
if (val & DDI_BUF_CTL_ENABLE) {
val &= ~DDI_BUF_CTL_ENABLE;
@@ -1986,6 +2010,8 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
enum port port = intel_ddi_get_encoder_port(intel_encoder);
int type = intel_encoder->type;
+ WARN_ON(port == PORT_INVALID);
+
if (type == INTEL_OUTPUT_HDMI) {
struct intel_digital_port *intel_dig_port =
enc_to_dig_port(encoder);
@@ -2732,6 +2758,7 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
int port = intel_ddi_get_encoder_port(encoder);
WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
+ WARN_ON(port == PORT_INVALID);
if (port == PORT_A)
pipe_config->cpu_transcoder = TRANSCODER_EDP;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b8e0310..7f39cc9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4991,6 +4991,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
+ bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
int pipe = intel_crtc->pipe;
WARN_ON(!crtc->state->enable);
@@ -5033,7 +5034,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
dev_priv->display.fdi_link_train(crtc);
}
- intel_ddi_enable_pipe_clock(intel_crtc);
+ if (!is_dsi)
+ intel_ddi_enable_pipe_clock(intel_crtc);
if (INTEL_INFO(dev)->gen == 9)
skylake_pfit_update(intel_crtc, 1);
@@ -5049,7 +5051,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_crtc_load_lut(crtc);
intel_ddi_set_pipe_settings(crtc);
- intel_ddi_enable_transcoder_func(crtc);
+ if (!is_dsi)
+ intel_ddi_enable_transcoder_func(crtc);
intel_update_watermarks(crtc);
intel_enable_pipe(intel_crtc);
@@ -5057,13 +5060,16 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
if (intel_crtc->config->has_pch_encoder)
lpt_pch_enable(crtc);
- if (intel_crtc->config->dp_encoder_is_mst)
+ if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
intel_ddi_set_vc_payload_alloc(crtc, true);
assert_vblank_disabled(crtc);
drm_crtc_vblank_on(crtc);
for_each_encoder_on_crtc(dev, crtc, encoder) {
+ if (encoder->pre_pll_enable)
+ encoder->pre_pll_enable(encoder);
+
encoder->enable(encoder);
intel_opregion_notify_encoder(encoder, true);
}
@@ -5159,6 +5165,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
+ bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
if (!intel_crtc->active)
return;
@@ -5179,7 +5186,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
if (intel_crtc->config->dp_encoder_is_mst)
intel_ddi_set_vc_payload_alloc(crtc, false);
- intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
+ if (!is_dsi)
+ intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
if (INTEL_INFO(dev)->gen == 9)
skylake_pfit_update(intel_crtc, 0);
@@ -5188,7 +5196,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
else
MISSING_CASE(INTEL_INFO(dev)->gen);
- intel_ddi_disable_pipe_clock(intel_crtc);
+ if (!is_dsi)
+ intel_ddi_disable_pipe_clock(intel_crtc);
if (intel_crtc->config->has_pch_encoder) {
lpt_disable_pch_transcoder(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 600afdb..d69186c 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -173,6 +173,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
if (intel_dp->active_mst_links == 0) {
enum port port = intel_ddi_get_encoder_port(encoder);
+ WARN_ON(port == PORT_INVALID);
/* FIXME: add support for SKL */
if (INTEL_INFO(dev)->gen < 9)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index 4813374..326aa6b 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -335,7 +335,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
return 0;
port = intel_ddi_get_encoder_port(intel_encoder);
- if (port == PORT_E) {
+ if ((port == PORT_E) || (port == PORT_INVALID)) {
port = 0;
} else {
parm |= 1 << port;
@@ -356,6 +356,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
break;
case INTEL_OUTPUT_EDP:
+ case INTEL_OUTPUT_DSI:
type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
break;
default:
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v3 06/14] drm/i915/bxt: DSI enable for BXT
2015-09-01 14:11 [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT Uma Shankar
` (4 preceding siblings ...)
2015-09-01 14:11 ` [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset Uma Shankar
@ 2015-09-01 14:11 ` Uma Shankar
2015-09-18 13:17 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 07/14] drm/i915/bxt: Program Tx Rx and Dphy clocks Uma Shankar
` (7 subsequent siblings)
13 siblings, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-01 14:11 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shobhit.kumar
From: Shashank Sharma <shashank.sharma@intel.com>
This patch contains following changes:
1. MIPI device ready changes to support dsi_pre_enable. Changes
are specific to BXT device ready sequence. Added check for
ULPS mode(No effects on VLV).
2. Changes in dsi_enable to pick BXT port control register.
3. Changes in dsi_pre_enable to restrict DPIO programming for VLV
v2: Fixed Jani's review comments. Removed the changes in VLV/CHV
code. Fixed the macros to get proper port offsets.
v3: Rebased on latest drm-nightly branch. Fixed Jani's review comments.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 7 ++
drivers/gpu/drm/i915/intel_dsi.c | 165 ++++++++++++++++++++++++++------------
2 files changed, 119 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 997a999..57c5dbf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7403,6 +7403,13 @@ enum skl_disp_power_wells {
#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
#define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
+
+ /* BXT port control */
+#define _BXT_MIPIA_PORT_CTRL 0x6B0C0
+#define _BXT_MIPIC_PORT_CTRL 0x6B8C0
+#define BXT_MIPI_PORT_CTRL(tc) _MIPI_PORT(tc, _BXT_MIPIA_PORT_CTRL, \
+ _BXT_MIPIC_PORT_CTRL)
+
#define DPI_ENABLE (1 << 31) /* A + C */
#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 6d0c992..5a42f87 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -286,58 +286,46 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
return true;
}
-static void intel_dsi_port_enable(struct intel_encoder *encoder)
+static void bxt_dsi_device_ready(struct intel_encoder *encoder)
{
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
enum port port;
- u32 temp;
+ u32 val;
- if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
- temp = I915_READ(VLV_CHICKEN_3);
- temp &= ~PIXEL_OVERLAP_CNT_MASK |
- intel_dsi->pixel_overlap <<
- PIXEL_OVERLAP_CNT_SHIFT;
- I915_WRITE(VLV_CHICKEN_3, temp);
- }
+ DRM_DEBUG_KMS("\n");
+ /* Exit Low power state in 4 steps*/
for_each_dsi_port(port, intel_dsi->ports) {
- temp = I915_READ(MIPI_PORT_CTRL(port));
- temp &= ~LANE_CONFIGURATION_MASK;
- temp &= ~DUAL_LINK_MODE_MASK;
- if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
- temp |= (intel_dsi->dual_link - 1)
- << DUAL_LINK_MODE_SHIFT;
- temp |= intel_crtc->pipe ?
- LANE_CONFIGURATION_DUAL_LINK_B :
- LANE_CONFIGURATION_DUAL_LINK_A;
- }
- /* assert ip_tg_enable signal */
- I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
- POSTING_READ(MIPI_PORT_CTRL(port));
- }
-}
+ /* 1. Enable MIPI PHY transparent latch */
+ val = I915_READ(BXT_MIPI_PORT_CTRL(port));
+ I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
+ usleep_range(2000, 2500);
-static void intel_dsi_port_disable(struct intel_encoder *encoder)
-{
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
- enum port port;
- u32 temp;
+ /* 2. Enter ULPS */
+ val = I915_READ(MIPI_DEVICE_READY(port));
+ val &= ~ULPS_STATE_MASK;
+ val |= (ULPS_STATE_ENTER | DEVICE_READY);
+ I915_WRITE(MIPI_DEVICE_READY(port), val);
+ usleep_range(2, 3);
+
+ /* 3. Exit ULPS */
+ val = I915_READ(MIPI_DEVICE_READY(port));
+ val &= ~ULPS_STATE_MASK;
+ val |= (ULPS_STATE_EXIT | DEVICE_READY);
+ I915_WRITE(MIPI_DEVICE_READY(port), val);
+ usleep_range(1000, 1500);
- for_each_dsi_port(port, intel_dsi->ports) {
- /* de-assert ip_tg_enable signal */
- temp = I915_READ(MIPI_PORT_CTRL(port));
- I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
- POSTING_READ(MIPI_PORT_CTRL(port));
+ /* Clear ULPS and set device ready */
+ val = I915_READ(MIPI_DEVICE_READY(port));
+ val &= ~ULPS_STATE_MASK;
+ val |= DEVICE_READY;
+ I915_WRITE(MIPI_DEVICE_READY(port), val);
}
}
-static void intel_dsi_device_ready(struct intel_encoder *encoder)
+static void vlv_dsi_device_ready(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -376,6 +364,72 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
}
}
+static void intel_dsi_device_ready(struct intel_encoder *encoder)
+{
+ struct drm_device *dev = encoder->base.dev;
+
+ if (IS_VALLEYVIEW(dev))
+ vlv_dsi_device_ready(encoder);
+ else if (IS_BROXTON(dev))
+ bxt_dsi_device_ready(encoder);
+}
+
+static void intel_dsi_port_enable(struct intel_encoder *encoder)
+{
+ struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ u32 temp;
+ u32 port_ctrl;
+
+ if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+ temp = I915_READ(VLV_CHICKEN_3);
+ temp &= ~PIXEL_OVERLAP_CNT_MASK |
+ intel_dsi->pixel_overlap <<
+ PIXEL_OVERLAP_CNT_SHIFT;
+ I915_WRITE(VLV_CHICKEN_3, temp);
+ }
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
+ MIPI_PORT_CTRL(port);
+
+ temp = I915_READ(port_ctrl);
+
+ temp &= ~LANE_CONFIGURATION_MASK;
+ temp &= ~DUAL_LINK_MODE_MASK;
+
+ if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
+ temp |= (intel_dsi->dual_link - 1)
+ << DUAL_LINK_MODE_SHIFT;
+ temp |= intel_crtc->pipe ?
+ LANE_CONFIGURATION_DUAL_LINK_B :
+ LANE_CONFIGURATION_DUAL_LINK_A;
+ }
+ /* assert ip_tg_enable signal */
+ I915_WRITE(port_ctrl, temp | DPI_ENABLE);
+ POSTING_READ(port_ctrl);
+ }
+}
+
+static void intel_dsi_port_disable(struct intel_encoder *encoder)
+{
+ struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ u32 temp;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ /* de-assert ip_tg_enable signal */
+ temp = I915_READ(MIPI_PORT_CTRL(port));
+ I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
+ POSTING_READ(MIPI_PORT_CTRL(port));
+ }
+}
+
static void intel_dsi_enable(struct intel_encoder *encoder)
{
struct drm_device *dev = encoder->base.dev;
@@ -415,19 +469,24 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
- /* Disable DPOunit clock gating, can stall pipe
- * and we need DPLL REFA always enabled */
- tmp = I915_READ(DPLL(pipe));
- tmp |= DPLL_REFA_CLK_ENABLE_VLV;
- I915_WRITE(DPLL(pipe), tmp);
-
- /* update the hw state for DPLL */
- intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
- DPLL_REFA_CLK_ENABLE_VLV;
-
- tmp = I915_READ(DSPCLK_GATE_D);
- tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
- I915_WRITE(DSPCLK_GATE_D, tmp);
+ if (IS_VALLEYVIEW(dev)) {
+ /*
+ * Disable DPOunit clock gating, can stall pipe
+ * and we need DPLL REFA always enabled
+ */
+ tmp = I915_READ(DPLL(pipe));
+ tmp |= DPLL_REFA_CLK_ENABLE_VLV;
+ I915_WRITE(DPLL(pipe), tmp);
+
+ /* update the hw state for DPLL */
+ intel_crtc->config->dpll_hw_state.dpll =
+ DPLL_INTEGRATED_CLOCK_VLV |
+ DPLL_REFA_CLK_ENABLE_VLV;
+
+ tmp = I915_READ(DSPCLK_GATE_D);
+ tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
+ I915_WRITE(DSPCLK_GATE_D, tmp);
+ }
/* put device in ready state */
intel_dsi_device_ready(encoder);
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v3 07/14] drm/i915/bxt: Program Tx Rx and Dphy clocks
2015-09-01 14:11 [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT Uma Shankar
` (5 preceding siblings ...)
2015-09-01 14:11 ` [BXT MIPI PATCH v3 06/14] drm/i915/bxt: DSI enable for BXT Uma Shankar
@ 2015-09-01 14:11 ` Uma Shankar
2015-09-18 13:27 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 08/14] drm/i915/bxt: DSI disable and post-disable Uma Shankar
` (6 subsequent siblings)
13 siblings, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-01 14:11 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shobhit.kumar
From: Shashank Sharma <shashank.sharma@intel.com>
BXT DSI clocks are different than previous platforms. So adding a
new function to program following clocks and dividers:
1. Program variable divider to generate input to Tx clock divider
(Output value must be < 39.5Mhz)
2. Select divide by 2 option to get < 20Mhz for Tx clock
3. Program 8by3 divider to generate Rx clock
v2: Fixed Jani's review comments. Adjusted the Macro definition as
per convention. Simplified the logic for bit definitions for
MIPI PORT A and PORT C in same registers.
v3: Refactored the macros for TX, RX Escape and DPHY clocks as per
Jani's suggestion.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 62 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dsi_pll.c | 39 +++++++++++++++++++++
2 files changed, 101 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 57c5dbf..e43b053 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7362,6 +7362,68 @@ enum skl_disp_power_wells {
#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
+/* BXT MIPI clock controls */
+#define BXT_MAX_VAR_OUTPUT_KHZ 39500
+
+#define BXT_MIPI_CLOCK_CTL 0x46090
+#define BXT_MIPI1_DIV_SHIFT 26
+#define BXT_MIPI2_DIV_SHIFT 10
+#define BXT_MIPI_DIV_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
+ BXT_MIPI2_DIV_SHIFT)
+/* Var clock divider to generate TX source. Result must be < 39.5 M */
+#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
+#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
+#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
+ _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
+ BXT_MIPI2_ESCLK_VAR_DIV_MASK)
+
+#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
+ (val << BXT_MIPI_DIV_SHIFT(port))
+/* TX control divider to select actual TX clock output from (8x/var) */
+#define BXT_MIPI1_TX_ESCLK_SHIFT 21
+#define BXT_MIPI2_TX_ESCLK_SHIFT 5
+#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
+ BXT_MIPI2_TX_ESCLK_SHIFT)
+#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
+#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
+#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
+ _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
+ BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
+#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
+ (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
+#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
+ (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
+#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
+ (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
+/* RX control divider to select actual RX clock output from 8x*/
+#define BXT_MIPI1_RX_ESCLK_SHIFT 19
+#define BXT_MIPI2_RX_ESCLK_SHIFT 3
+#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
+ BXT_MIPI2_RX_ESCLK_SHIFT)
+#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
+#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
+#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
+ (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
+ (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
+ (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
+ (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+/* BXT: Always prog DPHY dividers to 00 */
+#define BXT_MIPI1_DPHY_DIV_SHIFT 16
+#define BXT_MIPI2_DPHY_DIV_SHIFT 0
+#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
+ BXT_MIPI2_DPHY_DIV_SHIFT)
+#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
+#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
+#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
+ (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
+
/* BXT MIPI mode configure */
#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 21a2e37..63f9aed 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -389,6 +389,39 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
return pclk;
}
+/* Program BXT Mipi clocks and dividers */
+static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
+{
+ u32 tmp;
+ u32 divider;
+ u32 dsi_rate;
+ u32 pll_ratio;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /* Clear old configurations */
+ tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
+ tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
+ tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
+ tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
+
+ /* Get the current DSI rate(actual) */
+ pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
+ BXT_DSI_PLL_RATIO_MASK;
+ dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
+
+ /* Max possible output of clock is 39.5 MHz, program value -1 */
+ divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
+ tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
+
+ /* Tx escape clock should be >=20MHz, so select divide by 2 */
+ tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
+
+ tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
+
+ I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+}
+
static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
@@ -440,6 +473,8 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
u32 val;
DRM_DEBUG_KMS("\n");
@@ -458,6 +493,10 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
return;
}
+ /* Program TX, RX, Dphy clocks */
+ for_each_dsi_port(port, intel_dsi->ports)
+ bxt_dsi_program_clocks(encoder->base.dev, port);
+
/* Enable DSI PLL */
val = I915_READ(BXT_DSI_PLL_ENABLE);
val |= BXT_DSI_PLL_DO_ENABLE;
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v3 08/14] drm/i915/bxt: DSI disable and post-disable
2015-09-01 14:11 [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT Uma Shankar
` (6 preceding siblings ...)
2015-09-01 14:11 ` [BXT MIPI PATCH v3 07/14] drm/i915/bxt: Program Tx Rx and Dphy clocks Uma Shankar
@ 2015-09-01 14:11 ` Uma Shankar
2015-09-18 13:29 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 09/14] drm/i915/bxt: get_hw_state for BXT Uma Shankar
` (5 subsequent siblings)
13 siblings, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-01 14:11 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shobhit.kumar
From: Shashank Sharma <shashank.sharma@intel.com>
This patch contains changes to support DSI disble sequence in BXT.
The changes are:
1. BXT specific changes in clear_device_ready function.
2. BXT specific changes in DSI disable and post-disable functions.
3. Add a new function to reset BXT Dphy clock and dividers
(bxt_dsi_reset_clocks).
4. Moved some part of the vlv clock reset code, in a new function
(vlv_dsi_reset_clocks) maintaining the exact same sequence.
5. Wrapper function to call corresponding reset clock function.
v2: Fixed Jani's review comments.
v3: Removed the GET_DSI_PORT_CTRL Macro for consistency with earlier
implementations as per Jani's suggestion.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 36 +++++++++++++++++--------------
drivers/gpu/drm/i915/intel_dsi.h | 2 ++
drivers/gpu/drm/i915/intel_dsi_pll.c | 39 ++++++++++++++++++++++++++++++++++
3 files changed, 61 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 5a42f87..110a895 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -421,12 +421,15 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
enum port port;
u32 temp;
+ u32 port_ctrl;
for_each_dsi_port(port, intel_dsi->ports) {
/* de-assert ip_tg_enable signal */
- temp = I915_READ(MIPI_PORT_CTRL(port));
- I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
- POSTING_READ(MIPI_PORT_CTRL(port));
+ port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
+ MIPI_PORT_CTRL(port);
+ temp = I915_READ(port_ctrl);
+ I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
+ POSTING_READ(port_ctrl);
}
}
@@ -550,12 +553,7 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
/* Panel commands can be sent when clock is in LP11 */
I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
- temp = I915_READ(MIPI_CTRL(port));
- temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
- I915_WRITE(MIPI_CTRL(port), temp |
- intel_dsi->escape_clk_div <<
- ESCAPE_CLOCK_DIVIDER_SHIFT);
-
+ intel_dsi_reset_clocks(encoder, port);
I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
@@ -574,10 +572,12 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
{
+ struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
enum port port;
u32 val;
+ u32 port_ctrl = 0;
DRM_DEBUG_KMS("\n");
for_each_dsi_port(port, intel_dsi->ports) {
@@ -594,18 +594,22 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
ULPS_STATE_ENTER);
usleep_range(2000, 2500);
+ if (IS_BROXTON(dev))
+ port_ctrl = BXT_MIPI_PORT_CTRL(port);
+ else if (IS_VALLEYVIEW(dev))
+ /* Common bit for both MIPI Port A & MIPI Port C */
+ port_ctrl = MIPI_PORT_CTRL(PORT_A);
+
/* Wait till Clock lanes are in LP-00 state for MIPI Port A
* only. MIPI Port C has no similar bit for checking
*/
- if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT)
- == 0x00000), 30))
+ if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT)
+ == 0x00000), 30))
DRM_ERROR("DSI LP not going Low\n");
- /* Disable MIPI PHY transparent latch
- * Common bit for both MIPI Port A & MIPI Port C
- */
- val = I915_READ(MIPI_PORT_CTRL(PORT_A));
- I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD);
+ /* Disable MIPI PHY transparent latch */
+ val = I915_READ(port_ctrl);
+ I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
usleep_range(1000, 1500);
I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 759983e..078ea1b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -124,6 +124,8 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
+extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,
+ enum port port);
struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 63f9aed..918bc5f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -389,6 +389,19 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
return pclk;
}
+void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
+{
+ u32 temp;
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+
+ temp = I915_READ(MIPI_CTRL(port));
+ temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
+ I915_WRITE(MIPI_CTRL(port), temp |
+ intel_dsi->escape_clk_div <<
+ ESCAPE_CLOCK_DIVIDER_SHIFT);
+}
+
/* Program BXT Mipi clocks and dividers */
static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
{
@@ -530,3 +543,29 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
else if (IS_BROXTON(dev))
bxt_disable_dsi_pll(encoder);
}
+
+void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
+{
+ u32 tmp;
+ struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /* Clear old configurations */
+ tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
+ tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
+ tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
+ tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
+ I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+ I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
+}
+
+void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
+{
+ struct drm_device *dev = encoder->base.dev;
+
+ if (IS_BROXTON(dev))
+ bxt_dsi_reset_clocks(encoder, port);
+ else if (IS_VALLEYVIEW(dev))
+ vlv_dsi_reset_clocks(encoder, port);
+}
--
1.7.9.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v3 09/14] drm/i915/bxt: get_hw_state for BXT
2015-09-01 14:11 [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT Uma Shankar
` (7 preceding siblings ...)
2015-09-01 14:11 ` [BXT MIPI PATCH v3 08/14] drm/i915/bxt: DSI disable and post-disable Uma Shankar
@ 2015-09-01 14:11 ` Uma Shankar
2015-09-18 13:30 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 10/14] drm/i915/bxt: get DSI pixelclock Uma Shankar
` (4 subsequent siblings)
13 siblings, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-01 14:11 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shobhit.kumar
From: Shashank Sharma <shashank.sharma@intel.com>
Pick appropriate port control register (BXT or VLV), based on device.
Get the current hw state wrt Mipi port.
v2: Rebased on latest drm nightly branch.
v3: Removed the GET_DSI_PORT_CTRL Macro for consistency with earlier
implementations as per Jani's suggestion.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 110a895..001569b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -648,7 +648,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
struct drm_device *dev = encoder->base.dev;
enum intel_display_power_domain power_domain;
- u32 dpi_enabled, func;
+ u32 dpi_enabled, func, ctrl_reg;
enum port port;
DRM_DEBUG_KMS("\n");
@@ -660,8 +660,9 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
/* XXX: this only works for one DSI output */
for_each_dsi_port(port, intel_dsi->ports) {
func = I915_READ(MIPI_DSI_FUNC_PRG(port));
- dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) &
- DPI_ENABLE;
+ ctrl_reg = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
+ MIPI_PORT_CTRL(port);
+ dpi_enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
/* Due to some hardware limitations on BYT, MIPI Port C DPI
* Enable bit does not get set. To check whether DSI Port C
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v3 10/14] drm/i915/bxt: get DSI pixelclock
2015-09-01 14:11 [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT Uma Shankar
` (8 preceding siblings ...)
2015-09-01 14:11 ` [BXT MIPI PATCH v3 09/14] drm/i915/bxt: get_hw_state for BXT Uma Shankar
@ 2015-09-01 14:11 ` Uma Shankar
2015-09-18 13:30 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 11/14] drm/i915/bxt: Modify BXT BLC according to VBT changes Uma Shankar
` (3 subsequent siblings)
13 siblings, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-01 14:11 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shobhit.kumar
From: Shashank Sharma <shashank.sharma@intel.com>
BXT's DSI PLL is different from that of VLV. So this patch
adds a new function to get the current DSI pixel clock based
on the PLL divider ratio and lane count.
This function is required for intel_dsi_get_config() function.
v2: Fixed Jani's review comments.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 8 ++++++--
drivers/gpu/drm/i915/intel_dsi.h | 1 +
drivers/gpu/drm/i915/intel_dsi_pll.c | 35 ++++++++++++++++++++++++++++++++++
3 files changed, 42 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 001569b..6a0071f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -687,7 +687,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
static void intel_dsi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
- u32 pclk;
+ u32 pclk = 0;
DRM_DEBUG_KMS("\n");
/*
@@ -696,7 +696,11 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
*/
pipe_config->dpll_hw_state.dpll_md = 0;
- pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
+ if (IS_BROXTON(encoder->base.dev))
+ pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
+ else if (IS_VALLEYVIEW(encoder->base.dev))
+ pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
+
if (!pclk)
return;
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 078ea1b..24fc550 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -124,6 +124,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
+extern u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,
enum port port);
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 918bc5f..9860bb5 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -389,6 +389,41 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
return pclk;
}
+u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
+{
+ u32 pclk;
+ u32 dsi_clk;
+ u32 dsi_ratio;
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+
+ /* Divide by zero */
+ if (!pipe_bpp) {
+ DRM_ERROR("Invalid BPP(0)\n");
+ return 0;
+ }
+
+ dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) &
+ BXT_DSI_PLL_RATIO_MASK;
+
+ /* Invalid DSI ratio ? */
+ if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
+ dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
+ DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio);
+ return 0;
+ }
+
+ dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
+
+ /* pixel_format and pipe_bpp should agree */
+ assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
+
+ pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);
+
+ DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
+ return pclk;
+}
+
void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
{
u32 temp;
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v3 11/14] drm/i915/bxt: Modify BXT BLC according to VBT changes
2015-09-01 14:11 [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT Uma Shankar
` (9 preceding siblings ...)
2015-09-01 14:11 ` [BXT MIPI PATCH v3 10/14] drm/i915/bxt: get DSI pixelclock Uma Shankar
@ 2015-09-01 14:11 ` Uma Shankar
2015-09-18 13:51 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 12/14] drm/i915/bxt: Program Backlight PWM frequency Uma Shankar
` (2 subsequent siblings)
13 siblings, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-01 14:11 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shobhit.kumar
From: Sunil Kamath <sunil.kamath@intel.com>
Latest VBT mentions which set of registers will be used for BLC,
as controller number field. Making use of this field in BXT
BLC implementation. Also, the registers are used in case control
pin indicates display DDI. Adding a check for this.
According to Bspec, BLC_PWM_*_2 uses the display utility pin for output.
To use backlight 2, enable the utility pin with mode = PWM
v2: Jani's review comments
addressed
- Add a prefix _ to BXT BLC registers definitions.
- Add "bxt only" comment for u8 controller
- Remove control_pin check for DDI controller
- Check for valid controller values
- Set pipe bits in UTIL_PIN_CTL
- Enable/Disable UTIL_PIN_CTL in enable/disable_backlight()
- If BLC 2 is used, read active_low_pwm from UTIL_PIN polarity
Satheesh's review comment addressed
- If UTIL PIN is already enabled, BIOS would have programmed it. No
need to disable and enable again.
v3: Jani's review comments
- add UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK
- Disable UTIL_PIN if controller 1 is used
- Mask out UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK before enabling
UTIL_PIN
- check valid controller value in intel_bios.c
- add backlight.util_pin_active_low
- disable util pin before enabling
v4: Change for BXT-PO branch:
Stubbed unwanted definition which was existing before
because of DC6 patch.
UTIL_PIN_MODE_PWM (0x1b << 24)
v2: Fixed Jani's review comment.
v3: Split the backight PWM frequency programming into separate patch,
in cases BIOS doesn't initializes it.
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++----
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_panel.c | 84 ++++++++++++++++++++++++++++--------
3 files changed, 89 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e43b053..8407b5c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3512,17 +3512,29 @@ enum skl_disp_power_wells {
#define UTIL_PIN_CTL 0x48400
#define UTIL_PIN_ENABLE (1 << 31)
+#define UTIL_PIN_PIPE(x) ((x) << 29)
+#define UTIL_PIN_PIPE_MASK (3 << 29)
+#define UTIL_PIN_MODE_PWM (1 << 24)
+#define UTIL_PIN_MODE_MASK (0xf << 24)
+#define UTIL_PIN_POLARITY (1 << 22)
+
/* BXT backlight register definition. */
-#define BXT_BLC_PWM_CTL1 0xC8250
+#define _BXT_BLC_PWM_CTL1 0xC8250
#define BXT_BLC_PWM_ENABLE (1 << 31)
#define BXT_BLC_PWM_POLARITY (1 << 29)
-#define BXT_BLC_PWM_FREQ1 0xC8254
-#define BXT_BLC_PWM_DUTY1 0xC8258
-
-#define BXT_BLC_PWM_CTL2 0xC8350
-#define BXT_BLC_PWM_FREQ2 0xC8354
-#define BXT_BLC_PWM_DUTY2 0xC8358
-
+#define _BXT_BLC_PWM_FREQ1 0xC8254
+#define _BXT_BLC_PWM_DUTY1 0xC8258
+
+#define _BXT_BLC_PWM_CTL2 0xC8350
+#define _BXT_BLC_PWM_FREQ2 0xC8354
+#define _BXT_BLC_PWM_DUTY2 0xC8358
+
+#define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \
+ _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
+#define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \
+ _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
+#define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \
+ _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
#define PCH_GTC_CTL 0xe7000
#define PCH_GTC_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1059283..d8ca075 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -182,7 +182,9 @@ struct intel_panel {
bool enabled;
bool combination_mode; /* gen 2/4 only */
bool active_low_pwm;
+ bool util_pin_active_low; /* bxt+ */
struct backlight_device *device;
+ u8 controller; /* bxt+ only */
} backlight;
void (*backlight_power)(struct intel_connector *, bool enable);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 55aad23..9fcf86c 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -539,9 +539,10 @@ static u32 vlv_get_backlight(struct intel_connector *connector)
static u32 bxt_get_backlight(struct intel_connector *connector)
{
struct drm_device *dev = connector->base.dev;
+ struct intel_panel *panel = &connector->panel;
struct drm_i915_private *dev_priv = dev->dev_private;
- return I915_READ(BXT_BLC_PWM_DUTY1);
+ return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
}
static u32 intel_panel_get_backlight(struct intel_connector *connector)
@@ -628,8 +629,9 @@ static void bxt_set_backlight(struct intel_connector *connector, u32 level)
{
struct drm_device *dev = connector->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_panel *panel = &connector->panel;
- I915_WRITE(BXT_BLC_PWM_DUTY1, level);
+ I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
}
static void
@@ -761,12 +763,20 @@ static void bxt_disable_backlight(struct intel_connector *connector)
{
struct drm_device *dev = connector->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- u32 tmp;
+ struct intel_panel *panel = &connector->panel;
+ u32 tmp, val;
intel_panel_actually_set_backlight(connector, 0);
- tmp = I915_READ(BXT_BLC_PWM_CTL1);
- I915_WRITE(BXT_BLC_PWM_CTL1, tmp & ~BXT_BLC_PWM_ENABLE);
+ tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+ tmp & ~BXT_BLC_PWM_ENABLE);
+
+ if (panel->backlight.controller == 1) {
+ val = I915_READ(UTIL_PIN_CTL);
+ val &= ~UTIL_PIN_ENABLE;
+ I915_WRITE(UTIL_PIN_CTL, val);
+ }
}
void intel_panel_disable_backlight(struct intel_connector *connector)
@@ -988,16 +998,39 @@ static void bxt_enable_backlight(struct intel_connector *connector)
struct drm_device *dev = connector->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_panel *panel = &connector->panel;
- u32 pwm_ctl;
+ enum pipe pipe = intel_get_pipe_from_connector(connector);
+ u32 pwm_ctl, val;
+
+ /* To use 2nd set of backlight registers, utility pin has to be
+ * enabled with PWM mode.
+ * The field should only be changed when the utility pin is disabled
+ */
+ if (panel->backlight.controller == 1) {
+ val = I915_READ(UTIL_PIN_CTL);
+ if (val & UTIL_PIN_ENABLE) {
+ DRM_DEBUG_KMS("util pin already enabled\n");
+ val &= ~UTIL_PIN_ENABLE;
+ I915_WRITE(UTIL_PIN_CTL, val);
+ }
+ /* mask out UTIL_PIN_PIPE and UTIL_PIN_MODE */
+ val &= ~(UTIL_PIN_PIPE_MASK | UTIL_PIN_MODE_MASK);
+ I915_WRITE(UTIL_PIN_CTL, val);
+ if (panel->backlight.util_pin_active_low)
+ val |= UTIL_PIN_POLARITY;
+ I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) |
+ UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
+ }
- pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
+ pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
DRM_DEBUG_KMS("backlight already enabled\n");
pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
- I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+ pwm_ctl);
}
- I915_WRITE(BXT_BLC_PWM_FREQ1, panel->backlight.max);
+ I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
+ panel->backlight.max);
intel_panel_actually_set_backlight(connector, panel->backlight.level);
@@ -1005,9 +1038,10 @@ static void bxt_enable_backlight(struct intel_connector *connector)
if (panel->backlight.active_low_pwm)
pwm_ctl |= BXT_BLC_PWM_POLARITY;
- I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
- POSTING_READ(BXT_BLC_PWM_CTL1);
- I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl | BXT_BLC_PWM_ENABLE);
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
+ POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+ pwm_ctl | BXT_BLC_PWM_ENABLE);
}
void intel_panel_enable_backlight(struct intel_connector *connector)
@@ -1370,12 +1404,28 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
struct intel_panel *panel = &connector->panel;
u32 pwm_ctl, val;
- pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
- panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
+ /*
+ * For BXT hard coding the Backlight controller to 0.
+ * TODO : Read the controller value from VBT and generalize
+ */
+ panel->backlight.controller = 0;
- panel->backlight.max = I915_READ(BXT_BLC_PWM_FREQ1);
- if (!panel->backlight.max)
- return -ENODEV;
+ pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+
+ /* Keeping the check if controller 1 is to be programmed.
+ * This will come into affect once the VBT parsing
+ * is fixed for controller selection, and controller 1 is used
+ * for a prticular display configuration.
+ */
+ if (panel->backlight.controller == 1) {
+ val = I915_READ(UTIL_PIN_CTL);
+ panel->backlight.util_pin_active_low =
+ val & UTIL_PIN_POLARITY;
+ }
+
+ panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
+ panel->backlight.max = I915_READ(
+ BXT_BLC_PWM_FREQ(panel->backlight.controller));
val = bxt_get_backlight(connector);
panel->backlight.level = intel_panel_compute_brightness(connector, val);
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v3 12/14] drm/i915/bxt: Program Backlight PWM frequency
2015-09-01 14:11 [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT Uma Shankar
` (10 preceding siblings ...)
2015-09-01 14:11 ` [BXT MIPI PATCH v3 11/14] drm/i915/bxt: Modify BXT BLC according to VBT changes Uma Shankar
@ 2015-09-01 14:11 ` Uma Shankar
2015-09-18 13:33 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 13/14] drm/i915/bxt: Remove DSP CLK_GATE programming for BXT Uma Shankar
2015-09-01 14:11 ` [BXT MIPI PATCH v3 14/14] drm/i915: Added BXT DSI backlight support Uma Shankar
13 siblings, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-01 14:11 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shobhit.kumar
In some cases, BIOS doesn't initializes DSI panel.DSI and
backlight registers are thereby not initialized. Programming
the same in driver backlight setup.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_panel.c | 11 +++++++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8407b5c..10f73b1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7166,6 +7166,9 @@ enum skl_disp_power_wells {
#define TRANS_MSA_12_BPC (3<<5)
#define TRANS_MSA_16_BPC (4<<5)
+/* Max CDCLK freq for BXT in HZ */
+#define BXT_CDCLK_MAX 624000000
+
/* LCPLL Control */
#define LCPLL_CTL 0x130040
#define LCPLL_PLL_DISABLE (1<<31)
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 9fcf86c..8225cea 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1427,6 +1427,17 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
panel->backlight.max = I915_READ(
BXT_BLC_PWM_FREQ(panel->backlight.controller));
+ if (!panel->backlight.max) {
+ DRM_DEBUG_KMS("PWM freq not programmed by BIOS\n");
+ DRM_DEBUG_KMS("Programming PWM freq\n");
+
+ /* Max Backlight = Max CD Clock / pwm freq) */
+ panel->backlight.max = (BXT_CDCLK_MAX /
+ dev_priv->vbt.backlight.pwm_freq_hz);
+ I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
+ panel->backlight.max);
+ }
+
val = bxt_get_backlight(connector);
panel->backlight.level = intel_panel_compute_brightness(connector, val);
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v3 13/14] drm/i915/bxt: Remove DSP CLK_GATE programming for BXT
2015-09-01 14:11 [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT Uma Shankar
` (11 preceding siblings ...)
2015-09-01 14:11 ` [BXT MIPI PATCH v3 12/14] drm/i915/bxt: Program Backlight PWM frequency Uma Shankar
@ 2015-09-01 14:11 ` Uma Shankar
2015-09-18 13:38 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 14/14] drm/i915: Added BXT DSI backlight support Uma Shankar
13 siblings, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-01 14:11 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shobhit.kumar
DSP CLK_GATE registers are specific to BYT and CHT.
Avoid programming the same for BXT platform.
v2: Rebased on latest drm nightly branch.
v3: Fixed Jani's review comments
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 6a0071f..08bade2 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -631,9 +631,11 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
intel_dsi_clear_device_ready(encoder);
- val = I915_READ(DSPCLK_GATE_D);
- val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
- I915_WRITE(DSPCLK_GATE_D, val);
+ if (!IS_BROXTON(dev_priv->dev)) {
+ val = I915_READ(DSPCLK_GATE_D);
+ val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
+ I915_WRITE(DSPCLK_GATE_D, val);
+ }
drm_panel_unprepare(intel_dsi->panel);
--
1.7.9.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v3 14/14] drm/i915: Added BXT DSI backlight support
2015-09-01 14:11 [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT Uma Shankar
` (12 preceding siblings ...)
2015-09-01 14:11 ` [BXT MIPI PATCH v3 13/14] drm/i915/bxt: Remove DSP CLK_GATE programming for BXT Uma Shankar
@ 2015-09-01 14:11 ` Uma Shankar
2015-09-18 13:37 ` Jani Nikula
13 siblings, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-01 14:11 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shobhit.kumar
DSI backlight support for bxt is added.
TODO: There is no support for backlight control in drm panel
framework. This will be added as part of VBT version patches
fixing the backlight sequence.
v2: Fixed Jani's review comments from previous patch. Added the
BXT DSI backlight code in this patch. Backlight setup and
enable/disable code for backlight is added in intel_dsi.c.
v3: Rebased on latest drm-nightly. Fixed Jani's review comments.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 08bade2..aee1539 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -438,6 +438,7 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct intel_connector *intel_connector = intel_dsi->attached_connector;
enum port port;
DRM_DEBUG_KMS("\n");
@@ -458,6 +459,11 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
intel_dsi_port_enable(encoder);
}
+
+ if (IS_BROXTON(dev)) {
+ msleep(intel_dsi->backlight_on_delay);
+ intel_panel_enable_backlight(intel_connector);
+ }
}
static void intel_dsi_pre_enable(struct intel_encoder *encoder)
@@ -623,10 +629,16 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct intel_connector *intel_connector = intel_dsi->attached_connector;
u32 val;
DRM_DEBUG_KMS("\n");
+ if (IS_BROXTON(dev_priv->dev)) {
+ intel_panel_disable_backlight(intel_connector);
+ msleep(intel_dsi->backlight_off_delay);
+ }
+
intel_dsi_disable(encoder);
intel_dsi_clear_device_ready(encoder);
@@ -1226,8 +1238,14 @@ void intel_dsi_init(struct drm_device *dev)
intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
- return;
+ /*
+ * Pipe parameter is not used for BXT.
+ * Passing INVALID_PIPE to adher to API requirement.
+ */
+ if (IS_BROXTON(dev))
+ intel_panel_setup_backlight(connector, INVALID_PIPE);
+ return;
err:
drm_encoder_cleanup(&intel_encoder->base);
kfree(intel_dsi);
--
1.7.9.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 01/14] drm/i915/bxt: Initialize MIPI for BXT
2015-09-01 14:11 ` [BXT MIPI PATCH v3 01/14] drm/i915/bxt: Initialize MIPI " Uma Shankar
@ 2015-09-18 12:17 ` Jani Nikula
2015-09-23 8:08 ` Daniel Vetter
0 siblings, 1 reply; 69+ messages in thread
From: Jani Nikula @ 2015-09-18 12:17 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> This patch contains following changes:
> 1. Add BXT MIPI display address base.
> 2. Call dsi_init from display_setup function.
>
> v2: Rebased on latest nightly branch
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
I'm not sure if this should be applied as the first patch or not, but
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 3 +++
> drivers/gpu/drm/i915/intel_dsi.c | 2 ++
> 3 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2030f60..621151b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1641,6 +1641,7 @@ enum skl_disp_power_wells {
>
> #define VLV_DISPLAY_BASE 0x180000
> #define VLV_MIPI_BASE VLV_DISPLAY_BASE
> +#define BXT_MIPI_BASE 0x60000
>
> #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030)
> #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 87476ff..b8e0310 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13906,6 +13906,9 @@ static void intel_setup_outputs(struct drm_device *dev)
> * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
> * detect the ports.
> */
> + /* Initialize MIPI for BXT */
> + intel_dsi_init(dev);
> +
> intel_ddi_init(dev, PORT_A);
> intel_ddi_init(dev, PORT_B);
> intel_ddi_init(dev, PORT_C);
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index b5a5558..b59b828 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -998,6 +998,8 @@ void intel_dsi_init(struct drm_device *dev)
>
> if (IS_VALLEYVIEW(dev)) {
> dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> + } else if (IS_BROXTON(dev)) {
> + dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
> } else {
> DRM_ERROR("Unsupported Mipi device to reg base");
> return;
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 02/14] drm/i915/bxt: Enable BXT DSI PLL
2015-09-01 14:11 ` [BXT MIPI PATCH v3 02/14] drm/i915/bxt: Enable BXT DSI PLL Uma Shankar
@ 2015-09-18 12:32 ` Jani Nikula
0 siblings, 0 replies; 69+ messages in thread
From: Jani Nikula @ 2015-09-18 12:32 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> This patch adds new functions for BXT clock and PLL programming.
> They are:
> 1. configure_dsi_pll for BXT.
> This function does the basic math and generates the divider ratio
> based on requested pixclock, and program clock registers.
> 2. enable_dsi_pll function.
> This function programs the calculated clock values on the PLL.
> 3. intel_enable_dsi_pll
> Wrapper function to use same code for multiple platforms. It checks the
> platform and calls appropriate core pll enable function.
>
> v2: Fixed Jani's review comments. Macros are adjusted as per convention.
>
> v3: Removed a redundant change wrt code comment.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++
> drivers/gpu/drm/i915/intel_dsi.c | 2 +-
> drivers/gpu/drm/i915/intel_dsi.h | 2 +-
> drivers/gpu/drm/i915/intel_dsi_pll.c | 95 +++++++++++++++++++++++++++++++++-
> 4 files changed, 118 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 621151b..06bb2e1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7362,6 +7362,28 @@ enum skl_disp_power_wells {
>
> #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
>
> +#define BXT_DSI_PLL_CTL 0x161000
> +#define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
> +#define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> +#define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> +#define BXT_DSIC_16X_BY2 (1 << 10)
> +#define BXT_DSIC_16X_BY3 (2 << 10)
> +#define BXT_DSIC_16X_BY4 (3 << 10)
> +#define BXT_DSIA_16X_BY2 (1 << 8)
> +#define BXT_DSIA_16X_BY3 (2 << 8)
> +#define BXT_DSIA_16X_BY4 (3 << 8)
> +#define BXT_DSI_FREQ_SEL_SHIFT 8
> +#define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
> +
> +#define BXT_DSI_PLL_RATIO_MAX 0x7D
> +#define BXT_DSI_PLL_RATIO_MIN 0x22
> +#define BXT_DSI_PLL_RATIO_MASK 0xFF
> +#define BXT_REF_CLOCK_KHZ 19500
> +
> +#define BXT_DSI_PLL_ENABLE 0x46080
> +#define BXT_DSI_PLL_DO_ENABLE (1 << 31)
> +#define BXT_DSI_PLL_LOCKED (1 << 30)
> +
> #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
> #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
> #define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index b59b828..fb259fb 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -903,8 +903,8 @@ static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
> DRM_DEBUG_KMS("\n");
>
> intel_dsi_prepare(encoder);
> + intel_enable_dsi_pll(encoder);
>
> - vlv_enable_dsi_pll(encoder);
> }
>
> static enum drm_connector_status
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 2784ac4..20cfcf07 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -121,7 +121,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
> return container_of(encoder, struct intel_dsi, base.base);
> }
>
> -extern void vlv_enable_dsi_pll(struct intel_encoder *encoder);
> +extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
> extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
> extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index d20cf37..3830a4f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -237,7 +237,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
> vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
> }
>
> -void vlv_enable_dsi_pll(struct intel_encoder *encoder)
> +static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> u32 tmp;
> @@ -368,3 +368,96 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
>
> return pclk;
> }
> +
> +static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + u8 dsi_ratio;
> + u32 dsi_clk;
> + u32 val;
> +
> + dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
> + intel_dsi->lane_count);
> +
> + /*
> + * From clock diagram, to get PLL ratio divider, divide double of DSI
> + * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
> + * round 'up' the result
> + */
> + dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
> + if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
> + dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
> + DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
> + return false;
> + }
> +
> + /*
> + * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
> + * Spec says both have to be programmed, even if one is not getting
> + * used. Configure MIPI_CLOCK_CTL dividers in modeset
> + */
> + val = I915_READ(BXT_DSI_PLL_CTL);
> + val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
> + val &= ~BXT_DSI_FREQ_SEL_MASK;
> + val &= ~BXT_DSI_PLL_RATIO_MASK;
> + val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2);
> +
> + /* As per recommendation from hardware team,
> + * Prog PVD ratio =1 if dsi ratio <= 50
> + */
> + if (dsi_ratio <= 50) {
> + val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
> + val |= BXT_DSI_PLL_PVD_RATIO_1;
> + }
> +
> + I915_WRITE(BXT_DSI_PLL_CTL, val);
> + POSTING_READ(BXT_DSI_PLL_CTL);
> +
> + return true;
> +}
> +
> +static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + u32 val;
> +
> + DRM_DEBUG_KMS("\n");
> +
> + val = I915_READ(BXT_DSI_PLL_ENABLE);
> +
> + if (val & BXT_DSI_PLL_DO_ENABLE) {
> + WARN(1, "DSI PLL already enabled. Disabling it.\n");
> + val &= ~BXT_DSI_PLL_DO_ENABLE;
> + I915_WRITE(BXT_DSI_PLL_ENABLE, val);
> + }
> +
> + /* Configure PLL vales */
> + if (!bxt_configure_dsi_pll(encoder)) {
> + DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");
> + return;
> + }
> +
> + /* Enable DSI PLL */
> + val = I915_READ(BXT_DSI_PLL_ENABLE);
> + val |= BXT_DSI_PLL_DO_ENABLE;
> + I915_WRITE(BXT_DSI_PLL_ENABLE, val);
> +
> + /* Timeout and fail if PLL not locked */
> + if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) {
> + DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
> + return;
> + }
> +
> + DRM_DEBUG_KMS("DSI PLL locked\n");
> +}
> +
> +void intel_enable_dsi_pll(struct intel_encoder *encoder)
> +{
> + struct drm_device *dev = encoder->base.dev;
> +
> + if (IS_VALLEYVIEW(dev))
> + vlv_enable_dsi_pll(encoder);
> + else if (IS_BROXTON(dev))
> + bxt_enable_dsi_pll(encoder);
> +}
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 03/14] drm/i915/bxt: Disable DSI PLL for BXT
2015-09-01 14:11 ` [BXT MIPI PATCH v3 03/14] drm/i915/bxt: Disable DSI PLL for BXT Uma Shankar
@ 2015-09-18 12:57 ` Jani Nikula
0 siblings, 0 replies; 69+ messages in thread
From: Jani Nikula @ 2015-09-18 12:57 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> This patch adds two new functions:
> - disable_dsi_pll.
> BXT DSI disable sequence and registers are
> different from previous platforms.
> - intel_disable_dsi_pll
> wrapper function to re-use the same code for
> multiple platforms. It checks platform type and
> calls appropriate core pll disable function.
>
> v2: Fixed Jani's review comments.
>
> v3: Rebased on latest drm-nightly branch.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 2 +-
> drivers/gpu/drm/i915/intel_dsi.h | 2 +-
> drivers/gpu/drm/i915/intel_dsi_pll.c | 32 +++++++++++++++++++++++++++++++-
> 3 files changed, 33 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index fb259fb..bac988a 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -553,7 +553,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> usleep_range(2000, 2500);
> }
>
> - vlv_disable_dsi_pll(encoder);
> + intel_disable_dsi_pll(encoder);
> }
>
> static void intel_dsi_post_disable(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 20cfcf07..759983e 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -122,7 +122,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
> }
>
> extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
> -extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
> +extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
> extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
>
> struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 3830a4f..21a2e37 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -267,7 +267,7 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
> DRM_DEBUG_KMS("DSI PLL locked\n");
> }
>
> -void vlv_disable_dsi_pll(struct intel_encoder *encoder)
> +static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> u32 tmp;
> @@ -284,6 +284,26 @@ void vlv_disable_dsi_pll(struct intel_encoder *encoder)
> mutex_unlock(&dev_priv->sb_lock);
> }
>
> +static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + u32 val;
> +
> + DRM_DEBUG_KMS("\n");
> +
> + val = I915_READ(BXT_DSI_PLL_ENABLE);
> + val &= ~BXT_DSI_PLL_DO_ENABLE;
> + I915_WRITE(BXT_DSI_PLL_ENABLE, val);
> +
> + /*
> + * PLL lock should deassert within 200us.
> + * Wait up to 1ms before timing out.
> + */
> + if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE)
> + & BXT_DSI_PLL_LOCKED) == 0, 1))
> + DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
> +}
> +
> static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
> {
> int bpp;
> @@ -461,3 +481,13 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder)
> else if (IS_BROXTON(dev))
> bxt_enable_dsi_pll(encoder);
> }
> +
> +void intel_disable_dsi_pll(struct intel_encoder *encoder)
> +{
> + struct drm_device *dev = encoder->base.dev;
> +
> + if (IS_VALLEYVIEW(dev))
> + vlv_disable_dsi_pll(encoder);
> + else if (IS_BROXTON(dev))
> + bxt_disable_dsi_pll(encoder);
> +}
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 04/14] drm/i915/bxt: DSI prepare changes for BXT
2015-09-01 14:11 ` [BXT MIPI PATCH v3 04/14] drm/i915/bxt: DSI prepare changes " Uma Shankar
@ 2015-09-18 13:05 ` Jani Nikula
2015-09-23 8:16 ` Daniel Vetter
0 siblings, 1 reply; 69+ messages in thread
From: Jani Nikula @ 2015-09-18 13:05 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> This patch modifies dsi_prepare() function to support the same
> modeset prepare sequence for BXT also. Main changes are:
> 1. BXT port control register is different than VLV.
> 2. BXT modeset sequence needs vdisplay and hdisplay programmed
> for transcoder.
> 3. BXT can select PIPE for MIPI transcoders.
> 4. BXT needs to program register MIPI_INIT_COUNT for both the ports,
> even if only one is being used.
>
> v2: Fixed Jani's review comments. Rectified the DSI Macros to get
> proper register offsets using _MIPI_PORT instead of _TRANSCODER
>
> v3: Rebased on latest drm-nightly branch. Fixed Jani's review comments.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 21 ++++++++++++
> drivers/gpu/drm/i915/intel_dsi.c | 69 ++++++++++++++++++++++++++++++++------
> 2 files changed, 80 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 06bb2e1..997a999 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7362,6 +7362,22 @@ enum skl_disp_power_wells {
>
> #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
>
> +/* BXT MIPI mode configure */
> +#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
> +#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
> +#define BXT_MIPI_TRANS_HACTIVE(tc) _MIPI_PORT(tc, \
> + _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
> +
> +#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
> +#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
> +#define BXT_MIPI_TRANS_VACTIVE(tc) _MIPI_PORT(tc, \
> + _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
> +
> +#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
> +#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
> +#define BXT_MIPI_TRANS_VTOTAL(tc) _MIPI_PORT(tc, \
> + _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
> +
> #define BXT_DSI_PLL_CTL 0x161000
> #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
> #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> @@ -7797,6 +7813,11 @@ enum skl_disp_power_wells {
> #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
> #define RGB_FLIP_TO_BGR (1 << 2)
>
> +#define BXT_PIPE_SELECT_MASK (7 << 7)
> +#define BXT_PIPE_SELECT_C (2 << 7)
> +#define BXT_PIPE_SELECT_B (1 << 7)
> +#define BXT_PIPE_SELECT_A (0 << 7)
> +
> #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
> #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
> #define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index bac988a..6d0c992 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -726,6 +726,21 @@ static void set_dsi_timings(struct drm_encoder *encoder,
> hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
>
> for_each_dsi_port(port, intel_dsi->ports) {
> + if (IS_BROXTON(dev)) {
> + /*
> + * Program hdisplay and vdisplay on MIPI transcoder.
> + * This is different from calculated hactive and
> + * vactive, as they are calculated per channel basis,
> + * whereas these values should be based on resolution.
> + */
> + I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
> + mode->hdisplay);
> + I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
> + mode->vdisplay);
> + I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
> + mode->vtotal);
> + }
> +
> I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
> I915_WRITE(MIPI_HFP_COUNT(port), hfp);
>
> @@ -766,16 +781,39 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - /* escape clock divider, 20MHz, shared for A and C.
> - * device ready must be off when doing this! txclkesc? */
> - tmp = I915_READ(MIPI_CTRL(PORT_A));
> - tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> - I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
> -
> - /* read request priority is per pipe */
> - tmp = I915_READ(MIPI_CTRL(port));
> - tmp &= ~READ_REQUEST_PRIORITY_MASK;
> - I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
> + if (IS_VALLEYVIEW(dev)) {
> + /*
> + * escape clock divider, 20MHz, shared for A and C.
> + * device ready must be off when doing this! txclkesc?
> + */
> + tmp = I915_READ(MIPI_CTRL(PORT_A));
> + tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> + I915_WRITE(MIPI_CTRL(PORT_A), tmp |
> + ESCAPE_CLOCK_DIVIDER_1);
> +
> + /* read request priority is per pipe */
> + tmp = I915_READ(MIPI_CTRL(port));
> + tmp &= ~READ_REQUEST_PRIORITY_MASK;
> + I915_WRITE(MIPI_CTRL(port), tmp |
> + READ_REQUEST_PRIORITY_HIGH);
> + } else if (IS_BROXTON(dev)) {
> + /*
> + * FIXME:
> + * BXT can connect any PIPE to any MIPI port.
> + * Select the pipe based on the MIPI port read from
> + * VBT for now. Pick PIPE A for MIPI port A and C
> + * for port C.
> + */
> + tmp = I915_READ(MIPI_CTRL(port));
> + tmp &= ~BXT_PIPE_SELECT_MASK;
> +
> + if (port == PORT_A)
> + tmp |= BXT_PIPE_SELECT_A;
> + else if (port == PORT_C)
> + tmp |= BXT_PIPE_SELECT_C;
> +
> + I915_WRITE(MIPI_CTRL(port), tmp);
> + }
>
> /* XXX: why here, why like this? handling in irq handler?! */
> I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
> @@ -852,6 +890,17 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
> I915_WRITE(MIPI_INIT_COUNT(port),
> txclkesc(intel_dsi->escape_clk_div, 100));
>
> + if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
> + /*
> + * BXT spec says write MIPI_INIT_COUNT for
> + * both the ports, even if only one is
> + * getting used. So write the other port
> + * if not in dual link mode.
> + */
> + I915_WRITE(MIPI_INIT_COUNT(port ==
> + PORT_A ? PORT_C : PORT_A),
> + intel_dsi->init_count);
> + }
>
> /* recovery disables */
> I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 06/14] drm/i915/bxt: DSI enable for BXT
2015-09-01 14:11 ` [BXT MIPI PATCH v3 06/14] drm/i915/bxt: DSI enable for BXT Uma Shankar
@ 2015-09-18 13:17 ` Jani Nikula
2015-09-21 9:33 ` Shankar, Uma
0 siblings, 1 reply; 69+ messages in thread
From: Jani Nikula @ 2015-09-18 13:17 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> This patch contains following changes:
> 1. MIPI device ready changes to support dsi_pre_enable. Changes
> are specific to BXT device ready sequence. Added check for
> ULPS mode(No effects on VLV).
> 2. Changes in dsi_enable to pick BXT port control register.
> 3. Changes in dsi_pre_enable to restrict DPIO programming for VLV
>
> v2: Fixed Jani's review comments. Removed the changes in VLV/CHV
> code. Fixed the macros to get proper port offsets.
>
> v3: Rebased on latest drm-nightly branch. Fixed Jani's review comments.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
When you look at the commits before sending, you should pay more
attention to what the diffs end up looking like. In this case, the
review becomes unnecessarily hard just because you've moved code
(intel_dsi_port_enable) around for no apparent reason, and the diff
seems like intel_dsi_port_enable is rewritten into
bxt_dsi_device_ready. It should be a hint to *not* combine code movement
into the same patch.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 ++
> drivers/gpu/drm/i915/intel_dsi.c | 165 ++++++++++++++++++++++++++------------
> 2 files changed, 119 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 997a999..57c5dbf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7403,6 +7403,13 @@ enum skl_disp_power_wells {
> #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
> #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
> #define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
> +
> + /* BXT port control */
> +#define _BXT_MIPIA_PORT_CTRL 0x6B0C0
> +#define _BXT_MIPIC_PORT_CTRL 0x6B8C0
> +#define BXT_MIPI_PORT_CTRL(tc) _MIPI_PORT(tc, _BXT_MIPIA_PORT_CTRL, \
> + _BXT_MIPIC_PORT_CTRL)
> +
> #define DPI_ENABLE (1 << 31) /* A + C */
> #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
> #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 6d0c992..5a42f87 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -286,58 +286,46 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
> return true;
> }
>
> -static void intel_dsi_port_enable(struct intel_encoder *encoder)
> +static void bxt_dsi_device_ready(struct intel_encoder *encoder)
> {
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> enum port port;
> - u32 temp;
> + u32 val;
>
> - if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> - temp = I915_READ(VLV_CHICKEN_3);
> - temp &= ~PIXEL_OVERLAP_CNT_MASK |
> - intel_dsi->pixel_overlap <<
> - PIXEL_OVERLAP_CNT_SHIFT;
> - I915_WRITE(VLV_CHICKEN_3, temp);
> - }
> + DRM_DEBUG_KMS("\n");
>
> + /* Exit Low power state in 4 steps*/
> for_each_dsi_port(port, intel_dsi->ports) {
> - temp = I915_READ(MIPI_PORT_CTRL(port));
> - temp &= ~LANE_CONFIGURATION_MASK;
> - temp &= ~DUAL_LINK_MODE_MASK;
>
> - if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
> - temp |= (intel_dsi->dual_link - 1)
> - << DUAL_LINK_MODE_SHIFT;
> - temp |= intel_crtc->pipe ?
> - LANE_CONFIGURATION_DUAL_LINK_B :
> - LANE_CONFIGURATION_DUAL_LINK_A;
> - }
> - /* assert ip_tg_enable signal */
> - I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
> - POSTING_READ(MIPI_PORT_CTRL(port));
> - }
> -}
> + /* 1. Enable MIPI PHY transparent latch */
> + val = I915_READ(BXT_MIPI_PORT_CTRL(port));
> + I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
> + usleep_range(2000, 2500);
>
> -static void intel_dsi_port_disable(struct intel_encoder *encoder)
> -{
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> - enum port port;
> - u32 temp;
> + /* 2. Enter ULPS */
> + val = I915_READ(MIPI_DEVICE_READY(port));
> + val &= ~ULPS_STATE_MASK;
> + val |= (ULPS_STATE_ENTER | DEVICE_READY);
> + I915_WRITE(MIPI_DEVICE_READY(port), val);
> + usleep_range(2, 3);
> +
> + /* 3. Exit ULPS */
> + val = I915_READ(MIPI_DEVICE_READY(port));
> + val &= ~ULPS_STATE_MASK;
> + val |= (ULPS_STATE_EXIT | DEVICE_READY);
> + I915_WRITE(MIPI_DEVICE_READY(port), val);
> + usleep_range(1000, 1500);
>
> - for_each_dsi_port(port, intel_dsi->ports) {
> - /* de-assert ip_tg_enable signal */
> - temp = I915_READ(MIPI_PORT_CTRL(port));
> - I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
> - POSTING_READ(MIPI_PORT_CTRL(port));
> + /* Clear ULPS and set device ready */
> + val = I915_READ(MIPI_DEVICE_READY(port));
> + val &= ~ULPS_STATE_MASK;
> + val |= DEVICE_READY;
> + I915_WRITE(MIPI_DEVICE_READY(port), val);
> }
> }
>
> -static void intel_dsi_device_ready(struct intel_encoder *encoder)
> +static void vlv_dsi_device_ready(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> @@ -376,6 +364,72 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
> }
> }
>
> +static void intel_dsi_device_ready(struct intel_encoder *encoder)
> +{
> + struct drm_device *dev = encoder->base.dev;
> +
> + if (IS_VALLEYVIEW(dev))
> + vlv_dsi_device_ready(encoder);
> + else if (IS_BROXTON(dev))
> + bxt_dsi_device_ready(encoder);
> +}
> +
> +static void intel_dsi_port_enable(struct intel_encoder *encoder)
> +{
> + struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + enum port port;
> + u32 temp;
> + u32 port_ctrl;
> +
> + if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> + temp = I915_READ(VLV_CHICKEN_3);
> + temp &= ~PIXEL_OVERLAP_CNT_MASK |
> + intel_dsi->pixel_overlap <<
> + PIXEL_OVERLAP_CNT_SHIFT;
> + I915_WRITE(VLV_CHICKEN_3, temp);
> + }
> +
> + for_each_dsi_port(port, intel_dsi->ports) {
> + port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
> + MIPI_PORT_CTRL(port);
> +
> + temp = I915_READ(port_ctrl);
> +
> + temp &= ~LANE_CONFIGURATION_MASK;
> + temp &= ~DUAL_LINK_MODE_MASK;
> +
> + if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
> + temp |= (intel_dsi->dual_link - 1)
> + << DUAL_LINK_MODE_SHIFT;
> + temp |= intel_crtc->pipe ?
> + LANE_CONFIGURATION_DUAL_LINK_B :
> + LANE_CONFIGURATION_DUAL_LINK_A;
> + }
> + /* assert ip_tg_enable signal */
> + I915_WRITE(port_ctrl, temp | DPI_ENABLE);
> + POSTING_READ(port_ctrl);
> + }
> +}
> +
> +static void intel_dsi_port_disable(struct intel_encoder *encoder)
> +{
> + struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + enum port port;
> + u32 temp;
> +
> + for_each_dsi_port(port, intel_dsi->ports) {
> + /* de-assert ip_tg_enable signal */
> + temp = I915_READ(MIPI_PORT_CTRL(port));
> + I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
> + POSTING_READ(MIPI_PORT_CTRL(port));
> + }
> +}
> +
> static void intel_dsi_enable(struct intel_encoder *encoder)
> {
> struct drm_device *dev = encoder->base.dev;
> @@ -415,19 +469,24 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
>
> DRM_DEBUG_KMS("\n");
>
> - /* Disable DPOunit clock gating, can stall pipe
> - * and we need DPLL REFA always enabled */
> - tmp = I915_READ(DPLL(pipe));
> - tmp |= DPLL_REFA_CLK_ENABLE_VLV;
> - I915_WRITE(DPLL(pipe), tmp);
> -
> - /* update the hw state for DPLL */
> - intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
> - DPLL_REFA_CLK_ENABLE_VLV;
> -
> - tmp = I915_READ(DSPCLK_GATE_D);
> - tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
> - I915_WRITE(DSPCLK_GATE_D, tmp);
> + if (IS_VALLEYVIEW(dev)) {
> + /*
> + * Disable DPOunit clock gating, can stall pipe
> + * and we need DPLL REFA always enabled
> + */
> + tmp = I915_READ(DPLL(pipe));
> + tmp |= DPLL_REFA_CLK_ENABLE_VLV;
> + I915_WRITE(DPLL(pipe), tmp);
> +
> + /* update the hw state for DPLL */
> + intel_crtc->config->dpll_hw_state.dpll =
> + DPLL_INTEGRATED_CLOCK_VLV |
> + DPLL_REFA_CLK_ENABLE_VLV;
> +
> + tmp = I915_READ(DSPCLK_GATE_D);
> + tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
> + I915_WRITE(DSPCLK_GATE_D, tmp);
> + }
>
> /* put device in ready state */
> intel_dsi_device_ready(encoder);
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 07/14] drm/i915/bxt: Program Tx Rx and Dphy clocks
2015-09-01 14:11 ` [BXT MIPI PATCH v3 07/14] drm/i915/bxt: Program Tx Rx and Dphy clocks Uma Shankar
@ 2015-09-18 13:27 ` Jani Nikula
2015-09-21 10:11 ` Shankar, Uma
2015-09-23 17:57 ` [BXT MIPI PATCH v4 " Uma Shankar
0 siblings, 2 replies; 69+ messages in thread
From: Jani Nikula @ 2015-09-18 13:27 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> BXT DSI clocks are different than previous platforms. So adding a
> new function to program following clocks and dividers:
> 1. Program variable divider to generate input to Tx clock divider
> (Output value must be < 39.5Mhz)
> 2. Select divide by 2 option to get < 20Mhz for Tx clock
> 3. Program 8by3 divider to generate Rx clock
>
> v2: Fixed Jani's review comments. Adjusted the Macro definition as
> per convention. Simplified the logic for bit definitions for
> MIPI PORT A and PORT C in same registers.
>
> v3: Refactored the macros for TX, RX Escape and DPHY clocks as per
> Jani's suggestion.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Minor comments below, anyway
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 62 ++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_dsi_pll.c | 39 +++++++++++++++++++++
> 2 files changed, 101 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 57c5dbf..e43b053 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7362,6 +7362,68 @@ enum skl_disp_power_wells {
>
> #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
>
> +/* BXT MIPI clock controls */
> +#define BXT_MAX_VAR_OUTPUT_KHZ 39500
> +
> +#define BXT_MIPI_CLOCK_CTL 0x46090
> +#define BXT_MIPI1_DIV_SHIFT 26
> +#define BXT_MIPI2_DIV_SHIFT 10
> +#define BXT_MIPI_DIV_SHIFT(port) \
> + _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
> + BXT_MIPI2_DIV_SHIFT)
> +/* Var clock divider to generate TX source. Result must be < 39.5 M */
> +#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
> +#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
> +#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
> + _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
> + BXT_MIPI2_ESCLK_VAR_DIV_MASK)
> +
> +#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
> + (val << BXT_MIPI_DIV_SHIFT(port))
> +/* TX control divider to select actual TX clock output from (8x/var) */
> +#define BXT_MIPI1_TX_ESCLK_SHIFT 21
> +#define BXT_MIPI2_TX_ESCLK_SHIFT 5
> +#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
> + _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
> + BXT_MIPI2_TX_ESCLK_SHIFT)
> +#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
> +#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
> +#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
> + _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
> + BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
> +#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
> + (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> +#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
> + (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> +#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
> + (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> +/* RX control divider to select actual RX clock output from 8x*/
> +#define BXT_MIPI1_RX_ESCLK_SHIFT 19
> +#define BXT_MIPI2_RX_ESCLK_SHIFT 3
> +#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
> + BXT_MIPI2_RX_ESCLK_SHIFT)
> +#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
> +#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
> +#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
> + (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> +#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
> + (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> +#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
> + (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> +#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
> + (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> +/* BXT: Always prog DPHY dividers to 00 */
Actually BXT A stepping W/A, but I don't know the name for it.
> +#define BXT_MIPI1_DPHY_DIV_SHIFT 16
> +#define BXT_MIPI2_DPHY_DIV_SHIFT 0
> +#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
> + _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
> + BXT_MIPI2_DPHY_DIV_SHIFT)
> +#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
> +#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
> +#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
> + (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
> +
> /* BXT MIPI mode configure */
> #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
> #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 21a2e37..63f9aed 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -389,6 +389,39 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
> return pclk;
> }
>
> +/* Program BXT Mipi clocks and dividers */
> +static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
> +{
> + u32 tmp;
> + u32 divider;
> + u32 dsi_rate;
> + u32 pll_ratio;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + /* Clear old configurations */
> + tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> + tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> + tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
> + tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
> + tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
> +
> + /* Get the current DSI rate(actual) */
> + pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
> + BXT_DSI_PLL_RATIO_MASK;
> + dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
> +
> + /* Max possible output of clock is 39.5 MHz, program value -1 */
> + divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
> + tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
> +
> + /* Tx escape clock should be >=20MHz, so select divide by 2 */
Actually the Tx escape clock must be as close as possible to, but not
exceed, 20 MHz.
> + tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
> +
> + tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
> +
> + I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> +}
> +
> static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> @@ -440,6 +473,8 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
> static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + enum port port;
> u32 val;
>
> DRM_DEBUG_KMS("\n");
> @@ -458,6 +493,10 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
> return;
> }
>
> + /* Program TX, RX, Dphy clocks */
> + for_each_dsi_port(port, intel_dsi->ports)
> + bxt_dsi_program_clocks(encoder->base.dev, port);
> +
> /* Enable DSI PLL */
> val = I915_READ(BXT_DSI_PLL_ENABLE);
> val |= BXT_DSI_PLL_DO_ENABLE;
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 08/14] drm/i915/bxt: DSI disable and post-disable
2015-09-01 14:11 ` [BXT MIPI PATCH v3 08/14] drm/i915/bxt: DSI disable and post-disable Uma Shankar
@ 2015-09-18 13:29 ` Jani Nikula
0 siblings, 0 replies; 69+ messages in thread
From: Jani Nikula @ 2015-09-18 13:29 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> This patch contains changes to support DSI disble sequence in BXT.
> The changes are:
> 1. BXT specific changes in clear_device_ready function.
> 2. BXT specific changes in DSI disable and post-disable functions.
> 3. Add a new function to reset BXT Dphy clock and dividers
> (bxt_dsi_reset_clocks).
> 4. Moved some part of the vlv clock reset code, in a new function
> (vlv_dsi_reset_clocks) maintaining the exact same sequence.
> 5. Wrapper function to call corresponding reset clock function.
>
> v2: Fixed Jani's review comments.
>
> v3: Removed the GET_DSI_PORT_CTRL Macro for consistency with earlier
> implementations as per Jani's suggestion.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 36 +++++++++++++++++--------------
> drivers/gpu/drm/i915/intel_dsi.h | 2 ++
> drivers/gpu/drm/i915/intel_dsi_pll.c | 39 ++++++++++++++++++++++++++++++++++
> 3 files changed, 61 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 5a42f87..110a895 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -421,12 +421,15 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> enum port port;
> u32 temp;
> + u32 port_ctrl;
>
> for_each_dsi_port(port, intel_dsi->ports) {
> /* de-assert ip_tg_enable signal */
> - temp = I915_READ(MIPI_PORT_CTRL(port));
> - I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
> - POSTING_READ(MIPI_PORT_CTRL(port));
> + port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
> + MIPI_PORT_CTRL(port);
> + temp = I915_READ(port_ctrl);
> + I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
> + POSTING_READ(port_ctrl);
> }
> }
>
> @@ -550,12 +553,7 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
> /* Panel commands can be sent when clock is in LP11 */
> I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
>
> - temp = I915_READ(MIPI_CTRL(port));
> - temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> - I915_WRITE(MIPI_CTRL(port), temp |
> - intel_dsi->escape_clk_div <<
> - ESCAPE_CLOCK_DIVIDER_SHIFT);
> -
> + intel_dsi_reset_clocks(encoder, port);
> I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
>
> temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
> @@ -574,10 +572,12 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
>
> static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> {
> + struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> enum port port;
> u32 val;
> + u32 port_ctrl = 0;
>
> DRM_DEBUG_KMS("\n");
> for_each_dsi_port(port, intel_dsi->ports) {
> @@ -594,18 +594,22 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> ULPS_STATE_ENTER);
> usleep_range(2000, 2500);
>
> + if (IS_BROXTON(dev))
> + port_ctrl = BXT_MIPI_PORT_CTRL(port);
> + else if (IS_VALLEYVIEW(dev))
> + /* Common bit for both MIPI Port A & MIPI Port C */
> + port_ctrl = MIPI_PORT_CTRL(PORT_A);
> +
> /* Wait till Clock lanes are in LP-00 state for MIPI Port A
> * only. MIPI Port C has no similar bit for checking
> */
> - if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT)
> - == 0x00000), 30))
> + if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT)
> + == 0x00000), 30))
> DRM_ERROR("DSI LP not going Low\n");
>
> - /* Disable MIPI PHY transparent latch
> - * Common bit for both MIPI Port A & MIPI Port C
> - */
> - val = I915_READ(MIPI_PORT_CTRL(PORT_A));
> - I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD);
> + /* Disable MIPI PHY transparent latch */
> + val = I915_READ(port_ctrl);
> + I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
> usleep_range(1000, 1500);
>
> I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 759983e..078ea1b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -124,6 +124,8 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
> extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
> extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
> extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
> +extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,
> + enum port port);
>
> struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 63f9aed..918bc5f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -389,6 +389,19 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
> return pclk;
> }
>
> +void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> +{
> + u32 temp;
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +
> + temp = I915_READ(MIPI_CTRL(port));
> + temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> + I915_WRITE(MIPI_CTRL(port), temp |
> + intel_dsi->escape_clk_div <<
> + ESCAPE_CLOCK_DIVIDER_SHIFT);
> +}
> +
> /* Program BXT Mipi clocks and dividers */
> static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
> {
> @@ -530,3 +543,29 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
> else if (IS_BROXTON(dev))
> bxt_disable_dsi_pll(encoder);
> }
> +
> +void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> +{
> + u32 tmp;
> + struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + /* Clear old configurations */
> + tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> + tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> + tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
> + tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
> + tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
> + I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> + I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> +}
> +
> +void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> +{
> + struct drm_device *dev = encoder->base.dev;
> +
> + if (IS_BROXTON(dev))
> + bxt_dsi_reset_clocks(encoder, port);
> + else if (IS_VALLEYVIEW(dev))
> + vlv_dsi_reset_clocks(encoder, port);
> +}
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 09/14] drm/i915/bxt: get_hw_state for BXT
2015-09-01 14:11 ` [BXT MIPI PATCH v3 09/14] drm/i915/bxt: get_hw_state for BXT Uma Shankar
@ 2015-09-18 13:30 ` Jani Nikula
0 siblings, 0 replies; 69+ messages in thread
From: Jani Nikula @ 2015-09-18 13:30 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> Pick appropriate port control register (BXT or VLV), based on device.
> Get the current hw state wrt Mipi port.
>
> v2: Rebased on latest drm nightly branch.
>
> v3: Removed the GET_DSI_PORT_CTRL Macro for consistency with earlier
> implementations as per Jani's suggestion.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 110a895..001569b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -648,7 +648,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> struct drm_device *dev = encoder->base.dev;
> enum intel_display_power_domain power_domain;
> - u32 dpi_enabled, func;
> + u32 dpi_enabled, func, ctrl_reg;
> enum port port;
>
> DRM_DEBUG_KMS("\n");
> @@ -660,8 +660,9 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> /* XXX: this only works for one DSI output */
> for_each_dsi_port(port, intel_dsi->ports) {
> func = I915_READ(MIPI_DSI_FUNC_PRG(port));
> - dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) &
> - DPI_ENABLE;
> + ctrl_reg = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
> + MIPI_PORT_CTRL(port);
> + dpi_enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
>
> /* Due to some hardware limitations on BYT, MIPI Port C DPI
> * Enable bit does not get set. To check whether DSI Port C
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 10/14] drm/i915/bxt: get DSI pixelclock
2015-09-01 14:11 ` [BXT MIPI PATCH v3 10/14] drm/i915/bxt: get DSI pixelclock Uma Shankar
@ 2015-09-18 13:30 ` Jani Nikula
0 siblings, 0 replies; 69+ messages in thread
From: Jani Nikula @ 2015-09-18 13:30 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> BXT's DSI PLL is different from that of VLV. So this patch
> adds a new function to get the current DSI pixel clock based
> on the PLL divider ratio and lane count.
>
> This function is required for intel_dsi_get_config() function.
>
> v2: Fixed Jani's review comments.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 8 ++++++--
> drivers/gpu/drm/i915/intel_dsi.h | 1 +
> drivers/gpu/drm/i915/intel_dsi_pll.c | 35 ++++++++++++++++++++++++++++++++++
> 3 files changed, 42 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 001569b..6a0071f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -687,7 +687,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> static void intel_dsi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> - u32 pclk;
> + u32 pclk = 0;
> DRM_DEBUG_KMS("\n");
>
> /*
> @@ -696,7 +696,11 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
> */
> pipe_config->dpll_hw_state.dpll_md = 0;
>
> - pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
> + if (IS_BROXTON(encoder->base.dev))
> + pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
> + else if (IS_VALLEYVIEW(encoder->base.dev))
> + pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
> +
> if (!pclk)
> return;
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 078ea1b..24fc550 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -124,6 +124,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
> extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
> extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
> extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
> +extern u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
> extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,
> enum port port);
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 918bc5f..9860bb5 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -389,6 +389,41 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
> return pclk;
> }
>
> +u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
> +{
> + u32 pclk;
> + u32 dsi_clk;
> + u32 dsi_ratio;
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> +
> + /* Divide by zero */
> + if (!pipe_bpp) {
> + DRM_ERROR("Invalid BPP(0)\n");
> + return 0;
> + }
> +
> + dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) &
> + BXT_DSI_PLL_RATIO_MASK;
> +
> + /* Invalid DSI ratio ? */
> + if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
> + dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
> + DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio);
> + return 0;
> + }
> +
> + dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
> +
> + /* pixel_format and pipe_bpp should agree */
> + assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
> +
> + pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);
> +
> + DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
> + return pclk;
> +}
> +
> void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> {
> u32 temp;
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 12/14] drm/i915/bxt: Program Backlight PWM frequency
2015-09-01 14:11 ` [BXT MIPI PATCH v3 12/14] drm/i915/bxt: Program Backlight PWM frequency Uma Shankar
@ 2015-09-18 13:33 ` Jani Nikula
2015-09-21 10:18 ` Shankar, Uma
0 siblings, 1 reply; 69+ messages in thread
From: Jani Nikula @ 2015-09-18 13:33 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> In some cases, BIOS doesn't initializes DSI panel.DSI and
> backlight registers are thereby not initialized. Programming
> the same in driver backlight setup.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
This is probably obsolete now. See current bxt_setup_backlight.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_panel.c | 11 +++++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8407b5c..10f73b1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7166,6 +7166,9 @@ enum skl_disp_power_wells {
> #define TRANS_MSA_12_BPC (3<<5)
> #define TRANS_MSA_16_BPC (4<<5)
>
> +/* Max CDCLK freq for BXT in HZ */
> +#define BXT_CDCLK_MAX 624000000
> +
> /* LCPLL Control */
> #define LCPLL_CTL 0x130040
> #define LCPLL_PLL_DISABLE (1<<31)
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 9fcf86c..8225cea 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1427,6 +1427,17 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
> panel->backlight.max = I915_READ(
> BXT_BLC_PWM_FREQ(panel->backlight.controller));
>
> + if (!panel->backlight.max) {
> + DRM_DEBUG_KMS("PWM freq not programmed by BIOS\n");
> + DRM_DEBUG_KMS("Programming PWM freq\n");
> +
> + /* Max Backlight = Max CD Clock / pwm freq) */
> + panel->backlight.max = (BXT_CDCLK_MAX /
> + dev_priv->vbt.backlight.pwm_freq_hz);
> + I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
> + panel->backlight.max);
> + }
> +
> val = bxt_get_backlight(connector);
> panel->backlight.level = intel_panel_compute_brightness(connector, val);
>
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 14/14] drm/i915: Added BXT DSI backlight support
2015-09-01 14:11 ` [BXT MIPI PATCH v3 14/14] drm/i915: Added BXT DSI backlight support Uma Shankar
@ 2015-09-18 13:37 ` Jani Nikula
2015-09-21 10:22 ` Shankar, Uma
2015-09-23 18:00 ` [BXT MIPI PATCH v4 " Uma Shankar
0 siblings, 2 replies; 69+ messages in thread
From: Jani Nikula @ 2015-09-18 13:37 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> DSI backlight support for bxt is added.
>
> TODO: There is no support for backlight control in drm panel
> framework. This will be added as part of VBT version patches
> fixing the backlight sequence.
>
> v2: Fixed Jani's review comments from previous patch. Added the
> BXT DSI backlight code in this patch. Backlight setup and
> enable/disable code for backlight is added in intel_dsi.c.
>
> v3: Rebased on latest drm-nightly. Fixed Jani's review comments.
I'm not sure why these calls need to be within IS_BROXTON blocks. What
happens with the current backlight calls? Shouldn't we just have one set
of calls?
Also, I think we should get this [1] in first, and see how that affects
things.
BR,
Jani.
[1] http://mid.gmane.org/cover.1442227790.git.jani.nikula@intel.com
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 20 +++++++++++++++++++-
> 1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 08bade2..aee1539 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -438,6 +438,7 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + struct intel_connector *intel_connector = intel_dsi->attached_connector;
> enum port port;
>
> DRM_DEBUG_KMS("\n");
> @@ -458,6 +459,11 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
>
> intel_dsi_port_enable(encoder);
> }
> +
> + if (IS_BROXTON(dev)) {
> + msleep(intel_dsi->backlight_on_delay);
> + intel_panel_enable_backlight(intel_connector);
> + }
> }
>
> static void intel_dsi_pre_enable(struct intel_encoder *encoder)
> @@ -623,10 +629,16 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + struct intel_connector *intel_connector = intel_dsi->attached_connector;
> u32 val;
>
> DRM_DEBUG_KMS("\n");
>
> + if (IS_BROXTON(dev_priv->dev)) {
> + intel_panel_disable_backlight(intel_connector);
> + msleep(intel_dsi->backlight_off_delay);
> + }
> +
> intel_dsi_disable(encoder);
>
> intel_dsi_clear_device_ready(encoder);
> @@ -1226,8 +1238,14 @@ void intel_dsi_init(struct drm_device *dev)
>
> intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
>
> - return;
> + /*
> + * Pipe parameter is not used for BXT.
> + * Passing INVALID_PIPE to adher to API requirement.
> + */
> + if (IS_BROXTON(dev))
> + intel_panel_setup_backlight(connector, INVALID_PIPE);
>
> + return;
> err:
> drm_encoder_cleanup(&intel_encoder->base);
> kfree(intel_dsi);
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 13/14] drm/i915/bxt: Remove DSP CLK_GATE programming for BXT
2015-09-01 14:11 ` [BXT MIPI PATCH v3 13/14] drm/i915/bxt: Remove DSP CLK_GATE programming for BXT Uma Shankar
@ 2015-09-18 13:38 ` Jani Nikula
2015-10-02 13:02 ` Daniel Vetter
0 siblings, 1 reply; 69+ messages in thread
From: Jani Nikula @ 2015-09-18 13:38 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> DSP CLK_GATE registers are specific to BYT and CHT.
> Avoid programming the same for BXT platform.
>
> v2: Rebased on latest drm nightly branch.
>
> v3: Fixed Jani's review comments
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 6a0071f..08bade2 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -631,9 +631,11 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
>
> intel_dsi_clear_device_ready(encoder);
>
> - val = I915_READ(DSPCLK_GATE_D);
> - val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
> - I915_WRITE(DSPCLK_GATE_D, val);
> + if (!IS_BROXTON(dev_priv->dev)) {
> + val = I915_READ(DSPCLK_GATE_D);
> + val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
> + I915_WRITE(DSPCLK_GATE_D, val);
> + }
>
> drm_panel_unprepare(intel_dsi->panel);
>
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 11/14] drm/i915/bxt: Modify BXT BLC according to VBT changes
2015-09-01 14:11 ` [BXT MIPI PATCH v3 11/14] drm/i915/bxt: Modify BXT BLC according to VBT changes Uma Shankar
@ 2015-09-18 13:51 ` Jani Nikula
2015-09-21 10:26 ` Shankar, Uma
2015-09-23 17:59 ` [BXT MIPI PATCH v4 " Uma Shankar
0 siblings, 2 replies; 69+ messages in thread
From: Jani Nikula @ 2015-09-18 13:51 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Sunil Kamath <sunil.kamath@intel.com>
>
> Latest VBT mentions which set of registers will be used for BLC,
> as controller number field. Making use of this field in BXT
> BLC implementation. Also, the registers are used in case control
> pin indicates display DDI. Adding a check for this.
> According to Bspec, BLC_PWM_*_2 uses the display utility pin for output.
> To use backlight 2, enable the utility pin with mode = PWM
> v2: Jani's review comments
> addressed
> - Add a prefix _ to BXT BLC registers definitions.
> - Add "bxt only" comment for u8 controller
> - Remove control_pin check for DDI controller
> - Check for valid controller values
> - Set pipe bits in UTIL_PIN_CTL
> - Enable/Disable UTIL_PIN_CTL in enable/disable_backlight()
> - If BLC 2 is used, read active_low_pwm from UTIL_PIN polarity
> Satheesh's review comment addressed
> - If UTIL PIN is already enabled, BIOS would have programmed it. No
> need to disable and enable again.
> v3: Jani's review comments
> - add UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK
> - Disable UTIL_PIN if controller 1 is used
> - Mask out UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK before enabling
> UTIL_PIN
> - check valid controller value in intel_bios.c
> - add backlight.util_pin_active_low
> - disable util pin before enabling
> v4: Change for BXT-PO branch:
> Stubbed unwanted definition which was existing before
> because of DC6 patch.
> UTIL_PIN_MODE_PWM (0x1b << 24)
>
> v2: Fixed Jani's review comment.
>
> v3: Split the backight PWM frequency programming into separate patch,
> in cases BIOS doesn't initializes it.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Sunil Kamath <sunil.kamath@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++----
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> drivers/gpu/drm/i915/intel_panel.c | 84 ++++++++++++++++++++++++++++--------
> 3 files changed, 89 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e43b053..8407b5c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3512,17 +3512,29 @@ enum skl_disp_power_wells {
> #define UTIL_PIN_CTL 0x48400
> #define UTIL_PIN_ENABLE (1 << 31)
>
> +#define UTIL_PIN_PIPE(x) ((x) << 29)
> +#define UTIL_PIN_PIPE_MASK (3 << 29)
> +#define UTIL_PIN_MODE_PWM (1 << 24)
> +#define UTIL_PIN_MODE_MASK (0xf << 24)
> +#define UTIL_PIN_POLARITY (1 << 22)
> +
> /* BXT backlight register definition. */
> -#define BXT_BLC_PWM_CTL1 0xC8250
> +#define _BXT_BLC_PWM_CTL1 0xC8250
> #define BXT_BLC_PWM_ENABLE (1 << 31)
> #define BXT_BLC_PWM_POLARITY (1 << 29)
> -#define BXT_BLC_PWM_FREQ1 0xC8254
> -#define BXT_BLC_PWM_DUTY1 0xC8258
> -
> -#define BXT_BLC_PWM_CTL2 0xC8350
> -#define BXT_BLC_PWM_FREQ2 0xC8354
> -#define BXT_BLC_PWM_DUTY2 0xC8358
> -
> +#define _BXT_BLC_PWM_FREQ1 0xC8254
> +#define _BXT_BLC_PWM_DUTY1 0xC8258
> +
> +#define _BXT_BLC_PWM_CTL2 0xC8350
> +#define _BXT_BLC_PWM_FREQ2 0xC8354
> +#define _BXT_BLC_PWM_DUTY2 0xC8358
> +
> +#define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \
> + _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
> +#define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \
> + _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
> +#define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \
> + _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
>
> #define PCH_GTC_CTL 0xe7000
> #define PCH_GTC_ENABLE (1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 1059283..d8ca075 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -182,7 +182,9 @@ struct intel_panel {
> bool enabled;
> bool combination_mode; /* gen 2/4 only */
> bool active_low_pwm;
> + bool util_pin_active_low; /* bxt+ */
> struct backlight_device *device;
> + u8 controller; /* bxt+ only */
> } backlight;
>
> void (*backlight_power)(struct intel_connector *, bool enable);
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 55aad23..9fcf86c 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -539,9 +539,10 @@ static u32 vlv_get_backlight(struct intel_connector *connector)
> static u32 bxt_get_backlight(struct intel_connector *connector)
> {
> struct drm_device *dev = connector->base.dev;
> + struct intel_panel *panel = &connector->panel;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - return I915_READ(BXT_BLC_PWM_DUTY1);
> + return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
> }
>
> static u32 intel_panel_get_backlight(struct intel_connector *connector)
> @@ -628,8 +629,9 @@ static void bxt_set_backlight(struct intel_connector *connector, u32 level)
> {
> struct drm_device *dev = connector->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_panel *panel = &connector->panel;
>
> - I915_WRITE(BXT_BLC_PWM_DUTY1, level);
> + I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
> }
>
> static void
> @@ -761,12 +763,20 @@ static void bxt_disable_backlight(struct intel_connector *connector)
> {
> struct drm_device *dev = connector->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - u32 tmp;
> + struct intel_panel *panel = &connector->panel;
> + u32 tmp, val;
>
> intel_panel_actually_set_backlight(connector, 0);
>
> - tmp = I915_READ(BXT_BLC_PWM_CTL1);
> - I915_WRITE(BXT_BLC_PWM_CTL1, tmp & ~BXT_BLC_PWM_ENABLE);
> + tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> + tmp & ~BXT_BLC_PWM_ENABLE);
> +
> + if (panel->backlight.controller == 1) {
> + val = I915_READ(UTIL_PIN_CTL);
> + val &= ~UTIL_PIN_ENABLE;
> + I915_WRITE(UTIL_PIN_CTL, val);
> + }
> }
>
> void intel_panel_disable_backlight(struct intel_connector *connector)
> @@ -988,16 +998,39 @@ static void bxt_enable_backlight(struct intel_connector *connector)
> struct drm_device *dev = connector->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_panel *panel = &connector->panel;
> - u32 pwm_ctl;
> + enum pipe pipe = intel_get_pipe_from_connector(connector);
> + u32 pwm_ctl, val;
> +
> + /* To use 2nd set of backlight registers, utility pin has to be
> + * enabled with PWM mode.
> + * The field should only be changed when the utility pin is disabled
> + */
> + if (panel->backlight.controller == 1) {
> + val = I915_READ(UTIL_PIN_CTL);
> + if (val & UTIL_PIN_ENABLE) {
> + DRM_DEBUG_KMS("util pin already enabled\n");
> + val &= ~UTIL_PIN_ENABLE;
> + I915_WRITE(UTIL_PIN_CTL, val);
> + }
> + /* mask out UTIL_PIN_PIPE and UTIL_PIN_MODE */
> + val &= ~(UTIL_PIN_PIPE_MASK | UTIL_PIN_MODE_MASK);
Please start out with 0 val instead of modifying existing state. This is
the style across backlight enabling, apart from setup which gathers the
needed state.
With that fixed,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> + I915_WRITE(UTIL_PIN_CTL, val);
> + if (panel->backlight.util_pin_active_low)
> + val |= UTIL_PIN_POLARITY;
> + I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) |
> + UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
> + }
>
> - pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
> + pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
> DRM_DEBUG_KMS("backlight already enabled\n");
> pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
> - I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> + pwm_ctl);
> }
>
> - I915_WRITE(BXT_BLC_PWM_FREQ1, panel->backlight.max);
> + I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
> + panel->backlight.max);
>
> intel_panel_actually_set_backlight(connector, panel->backlight.level);
>
> @@ -1005,9 +1038,10 @@ static void bxt_enable_backlight(struct intel_connector *connector)
> if (panel->backlight.active_low_pwm)
> pwm_ctl |= BXT_BLC_PWM_POLARITY;
>
> - I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
> - POSTING_READ(BXT_BLC_PWM_CTL1);
> - I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl | BXT_BLC_PWM_ENABLE);
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
> + POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> + pwm_ctl | BXT_BLC_PWM_ENABLE);
> }
>
> void intel_panel_enable_backlight(struct intel_connector *connector)
> @@ -1370,12 +1404,28 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
> struct intel_panel *panel = &connector->panel;
> u32 pwm_ctl, val;
>
> - pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
> - panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
> + /*
> + * For BXT hard coding the Backlight controller to 0.
> + * TODO : Read the controller value from VBT and generalize
> + */
> + panel->backlight.controller = 0;
>
> - panel->backlight.max = I915_READ(BXT_BLC_PWM_FREQ1);
> - if (!panel->backlight.max)
> - return -ENODEV;
> + pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> +
> + /* Keeping the check if controller 1 is to be programmed.
> + * This will come into affect once the VBT parsing
> + * is fixed for controller selection, and controller 1 is used
> + * for a prticular display configuration.
> + */
> + if (panel->backlight.controller == 1) {
> + val = I915_READ(UTIL_PIN_CTL);
> + panel->backlight.util_pin_active_low =
> + val & UTIL_PIN_POLARITY;
> + }
> +
> + panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
> + panel->backlight.max = I915_READ(
> + BXT_BLC_PWM_FREQ(panel->backlight.controller));
>
> val = bxt_get_backlight(connector);
> panel->backlight.level = intel_panel_compute_brightness(connector, val);
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-01 14:11 ` [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset Uma Shankar
@ 2015-09-18 14:18 ` Jani Nikula
2015-09-21 10:41 ` Shankar, Uma
2015-09-23 12:53 ` Jani Nikula
1 sibling, 1 reply; 69+ messages in thread
From: Jani Nikula @ 2015-09-18 14:18 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> SKL and BXT qualifies the HAS_DDI() check, and hence haswell
> modeset functions are re-used for modeset sequence. But DDI
> interface doesn't include support for DSI.
> This patch adds:
> 1. cases for DSI encoder, in those modeset functions and allows
> a CRTC modeset
> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
> needs to be done as such in CRTC for DSI encoder, as PLL, clock
> and and transcoder programming will be taken care in encoder's
> pre_enable and pre_pll_enable function.
>
> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
> encoder like DSI for platforms having HAS_DDI as true.
>
> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
> encoder.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_ddi.c | 29 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_display.c | 19 ++++++++++++++-----
> drivers/gpu/drm/i915/intel_dp_mst.c | 1 +
> drivers/gpu/drm/i915/intel_opregion.c | 3 ++-
> 5 files changed, 46 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fd1de45..78d31c5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -142,6 +142,7 @@ enum plane {
> #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
>
> enum port {
> + PORT_INVALID = -1,
> PORT_A = 0,
> PORT_B,
> PORT_C,
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cacb07b..5d5aad2 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
> } else if (type == INTEL_OUTPUT_ANALOG) {
> *dig_port = NULL;
> *port = PORT_E;
> + } else if (type == INTEL_OUTPUT_DSI) {
> + *dig_port = NULL;
> + *port = PORT_INVALID;
> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
Please remind me again what are the legitimate paths to get here with
DSI?
With all the changes and warns across the driver, I'm beginning to think
we should have a version of this function that accepts DSI, and another
one that (calls the other one) and WARNS on DSI, and that should be
called on all paths that should never encounter a DSI encoder.
The proliferation of WARNS all over the place is not very nice.
I'm sorry, I know this is not the review I gave previously on this.
BR,
Jani.
> } else {
> DRM_ERROR("Invalid DDI encoder type %d\n", type);
> BUG();
> @@ -392,6 +396,11 @@ void intel_prepare_ddi(struct drm_device *dev)
>
> ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
>
> + if (port == PORT_INVALID) {
> + WARN_ON(1);
> + continue;
> + }
> +
> if (visited[port])
> continue;
>
> @@ -980,6 +989,8 @@ static void bxt_ddi_clock_get(struct intel_encoder *encoder,
> enum port port = intel_ddi_get_encoder_port(encoder);
> uint32_t dpll = port;
>
> + WARN_ON(port == PORT_INVALID);
> +
> pipe_config->port_clock =
> bxt_calc_pll_link(dev_priv, dpll);
>
> @@ -1572,6 +1583,8 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
> int type = intel_encoder->type;
> uint32_t temp;
>
> + WARN_ON(port == PORT_INVALID);
> +
> /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
> temp = TRANS_DDI_FUNC_ENABLE;
> temp |= TRANS_DDI_SELECT_PORT(port);
> @@ -1684,6 +1697,8 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
> enum intel_display_power_domain power_domain;
> uint32_t tmp;
>
> + WARN_ON(port == PORT_INVALID);
> +
> power_domain = intel_display_port_power_domain(intel_encoder);
> if (!intel_display_power_is_enabled(dev_priv, power_domain))
> return false;
> @@ -1730,6 +1745,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> u32 tmp;
> int i;
>
> + WARN_ON(port == PORT_INVALID);
> +
> power_domain = intel_display_port_power_domain(encoder);
> if (!intel_display_power_is_enabled(dev_priv, power_domain))
> return false;
> @@ -1779,11 +1796,14 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
> {
> struct drm_crtc *crtc = &intel_crtc->base;
> - struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
> enum port port = intel_ddi_get_encoder_port(intel_encoder);
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>
> + WARN_ON(port == PORT_INVALID);
> +
> if (cpu_transcoder != TRANSCODER_EDP)
> I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> TRANS_CLK_SEL_PORT(port));
> @@ -1870,6 +1890,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
> int type = intel_encoder->type;
> int hdmi_level;
>
> + WARN_ON(port == PORT_INVALID);
> +
> if (type == INTEL_OUTPUT_EDP) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> intel_edp_panel_on(intel_dp);
> @@ -1947,6 +1969,8 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
> uint32_t val;
> bool wait = false;
>
> + WARN_ON(port == PORT_INVALID);
> +
> val = I915_READ(DDI_BUF_CTL(port));
> if (val & DDI_BUF_CTL_ENABLE) {
> val &= ~DDI_BUF_CTL_ENABLE;
> @@ -1986,6 +2010,8 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
> enum port port = intel_ddi_get_encoder_port(intel_encoder);
> int type = intel_encoder->type;
>
> + WARN_ON(port == PORT_INVALID);
> +
> if (type == INTEL_OUTPUT_HDMI) {
> struct intel_digital_port *intel_dig_port =
> enc_to_dig_port(encoder);
> @@ -2732,6 +2758,7 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
> int port = intel_ddi_get_encoder_port(encoder);
>
> WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
> + WARN_ON(port == PORT_INVALID);
>
> if (port == PORT_A)
> pipe_config->cpu_transcoder = TRANSCODER_EDP;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b8e0310..7f39cc9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4991,6 +4991,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
> int pipe = intel_crtc->pipe;
>
> WARN_ON(!crtc->state->enable);
> @@ -5033,7 +5034,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> dev_priv->display.fdi_link_train(crtc);
> }
>
> - intel_ddi_enable_pipe_clock(intel_crtc);
> + if (!is_dsi)
> + intel_ddi_enable_pipe_clock(intel_crtc);
>
> if (INTEL_INFO(dev)->gen == 9)
> skylake_pfit_update(intel_crtc, 1);
> @@ -5049,7 +5051,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> intel_crtc_load_lut(crtc);
>
> intel_ddi_set_pipe_settings(crtc);
> - intel_ddi_enable_transcoder_func(crtc);
> + if (!is_dsi)
> + intel_ddi_enable_transcoder_func(crtc);
>
> intel_update_watermarks(crtc);
> intel_enable_pipe(intel_crtc);
> @@ -5057,13 +5060,16 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->config->has_pch_encoder)
> lpt_pch_enable(crtc);
>
> - if (intel_crtc->config->dp_encoder_is_mst)
> + if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
> intel_ddi_set_vc_payload_alloc(crtc, true);
>
> assert_vblank_disabled(crtc);
> drm_crtc_vblank_on(crtc);
>
> for_each_encoder_on_crtc(dev, crtc, encoder) {
> + if (encoder->pre_pll_enable)
> + encoder->pre_pll_enable(encoder);
> +
> encoder->enable(encoder);
> intel_opregion_notify_encoder(encoder, true);
> }
> @@ -5159,6 +5165,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>
> if (!intel_crtc->active)
> return;
> @@ -5179,7 +5186,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> if (intel_crtc->config->dp_encoder_is_mst)
> intel_ddi_set_vc_payload_alloc(crtc, false);
>
> - intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
> + if (!is_dsi)
> + intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>
> if (INTEL_INFO(dev)->gen == 9)
> skylake_pfit_update(intel_crtc, 0);
> @@ -5188,7 +5196,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> else
> MISSING_CASE(INTEL_INFO(dev)->gen);
>
> - intel_ddi_disable_pipe_clock(intel_crtc);
> + if (!is_dsi)
> + intel_ddi_disable_pipe_clock(intel_crtc);
>
> if (intel_crtc->config->has_pch_encoder) {
> lpt_disable_pch_transcoder(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 600afdb..d69186c 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -173,6 +173,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
>
> if (intel_dp->active_mst_links == 0) {
> enum port port = intel_ddi_get_encoder_port(encoder);
> + WARN_ON(port == PORT_INVALID);
>
> /* FIXME: add support for SKL */
> if (INTEL_INFO(dev)->gen < 9)
> diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
> index 4813374..326aa6b 100644
> --- a/drivers/gpu/drm/i915/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> @@ -335,7 +335,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
> return 0;
>
> port = intel_ddi_get_encoder_port(intel_encoder);
> - if (port == PORT_E) {
> + if ((port == PORT_E) || (port == PORT_INVALID)) {
> port = 0;
> } else {
> parm |= 1 << port;
> @@ -356,6 +356,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
> type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
> break;
> case INTEL_OUTPUT_EDP:
> + case INTEL_OUTPUT_DSI:
> type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
> break;
> default:
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 06/14] drm/i915/bxt: DSI enable for BXT
2015-09-18 13:17 ` Jani Nikula
@ 2015-09-21 9:33 ` Shankar, Uma
0 siblings, 0 replies; 69+ messages in thread
From: Shankar, Uma @ 2015-09-21 9:33 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: shobhit.kumar
On 9/18/2015 6:47 PM, Jani Nikula wrote:
> On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
>> From: Shashank Sharma <shashank.sharma@intel.com>
>>
>> This patch contains following changes:
>> 1. MIPI device ready changes to support dsi_pre_enable. Changes
>> are specific to BXT device ready sequence. Added check for
>> ULPS mode(No effects on VLV).
>> 2. Changes in dsi_enable to pick BXT port control register.
>> 3. Changes in dsi_pre_enable to restrict DPIO programming for VLV
>>
>> v2: Fixed Jani's review comments. Removed the changes in VLV/CHV
>> code. Fixed the macros to get proper port offsets.
>>
>> v3: Rebased on latest drm-nightly branch. Fixed Jani's review comments.
>>
>> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> When you look at the commits before sending, you should pay more
> attention to what the diffs end up looking like. In this case, the
> review becomes unnecessarily hard just because you've moved code
> (intel_dsi_port_enable) around for no apparent reason, and the diff
> seems like intel_dsi_port_enable is rewritten into
> bxt_dsi_device_ready. It should be a hint to *not* combine code movement
> into the same patch.
>
> I understand the concern. Will be careful of this in future to avoid such issues.
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 7 ++
>> drivers/gpu/drm/i915/intel_dsi.c | 165 ++++++++++++++++++++++++++------------
>> 2 files changed, 119 insertions(+), 53 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 997a999..57c5dbf 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7403,6 +7403,13 @@ enum skl_disp_power_wells {
>> #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
>> #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
>> #define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
>> +
>> + /* BXT port control */
>> +#define _BXT_MIPIA_PORT_CTRL 0x6B0C0
>> +#define _BXT_MIPIC_PORT_CTRL 0x6B8C0
>> +#define BXT_MIPI_PORT_CTRL(tc) _MIPI_PORT(tc, _BXT_MIPIA_PORT_CTRL, \
>> + _BXT_MIPIC_PORT_CTRL)
>> +
>> #define DPI_ENABLE (1 << 31) /* A + C */
>> #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
>> #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index 6d0c992..5a42f87 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -286,58 +286,46 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
>> return true;
>> }
>>
>> -static void intel_dsi_port_enable(struct intel_encoder *encoder)
>> +static void bxt_dsi_device_ready(struct intel_encoder *encoder)
>> {
>> - struct drm_device *dev = encoder->base.dev;
>> - struct drm_i915_private *dev_priv = dev->dev_private;
>> - struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> enum port port;
>> - u32 temp;
>> + u32 val;
>>
>> - if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>> - temp = I915_READ(VLV_CHICKEN_3);
>> - temp &= ~PIXEL_OVERLAP_CNT_MASK |
>> - intel_dsi->pixel_overlap <<
>> - PIXEL_OVERLAP_CNT_SHIFT;
>> - I915_WRITE(VLV_CHICKEN_3, temp);
>> - }
>> + DRM_DEBUG_KMS("\n");
>>
>> + /* Exit Low power state in 4 steps*/
>>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 07/14] drm/i915/bxt: Program Tx Rx and Dphy clocks
2015-09-18 13:27 ` Jani Nikula
@ 2015-09-21 10:11 ` Shankar, Uma
2015-09-23 17:57 ` [BXT MIPI PATCH v4 " Uma Shankar
1 sibling, 0 replies; 69+ messages in thread
From: Shankar, Uma @ 2015-09-21 10:11 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Kumar, Shobhit
>-----Original Message-----
>From: Nikula, Jani
>Sent: Friday, September 18, 2015 6:58 PM
>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
>Subject: Re: [BXT MIPI PATCH v3 07/14] drm/i915/bxt: Program Tx Rx and Dphy
>clocks
>
>On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
>> From: Shashank Sharma <shashank.sharma@intel.com>
>>
>> BXT DSI clocks are different than previous platforms. So adding a new
>> function to program following clocks and dividers:
>> 1. Program variable divider to generate input to Tx clock divider
>> (Output value must be < 39.5Mhz)
>> 2. Select divide by 2 option to get < 20Mhz for Tx clock 3. Program
>> 8by3 divider to generate Rx clock
>>
>> v2: Fixed Jani's review comments. Adjusted the Macro definition as
>> per convention. Simplified the logic for bit definitions for
>> MIPI PORT A and PORT C in same registers.
>>
>> v3: Refactored the macros for TX, RX Escape and DPHY clocks as per
>> Jani's suggestion.
>>
>> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>
>Minor comments below, anyway
Thanks for the comments Jani. Will update while sending next patchset.
>Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 62
>++++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_dsi_pll.c | 39 +++++++++++++++++++++
>> 2 files changed, 101 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 57c5dbf..e43b053 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7362,6 +7362,68 @@ enum skl_disp_power_wells {
>>
>> #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and
>C only */
>>
>> +/* BXT MIPI clock controls */
>> +#define BXT_MAX_VAR_OUTPUT_KHZ 39500
>> +
>> +#define BXT_MIPI_CLOCK_CTL 0x46090
>> +#define BXT_MIPI1_DIV_SHIFT 26
>> +#define BXT_MIPI2_DIV_SHIFT 10
>> +#define BXT_MIPI_DIV_SHIFT(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
>> + BXT_MIPI2_DIV_SHIFT)
>> +/* Var clock divider to generate TX source. Result must be < 39.5 M */
>> +#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
>> +#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
>> +#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
>> +
> BXT_MIPI2_ESCLK_VAR_DIV_MASK)
>> +
>> +#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
>> + (val << BXT_MIPI_DIV_SHIFT(port))
>> +/* TX control divider to select actual TX clock output from (8x/var) */
>> +#define BXT_MIPI1_TX_ESCLK_SHIFT 21
>> +#define BXT_MIPI2_TX_ESCLK_SHIFT 5
>> +#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
>> + BXT_MIPI2_TX_ESCLK_SHIFT)
>> +#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
>> +#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
>> +#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK,
>\
>> + (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> +#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
>> + (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> +/* BXT: Always prog DPHY dividers to 00 */
>
>Actually BXT A stepping W/A, but I don't know the name for it.
>> +#define BXT_MIPI1_DPHY_DIV_SHIFT 16
>> +#define BXT_MIPI2_DPHY_DIV_SHIFT 0
>> +#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
>> + BXT_MIPI2_DPHY_DIV_SHIFT)
>> +/* Program BXT Mipi clocks and dividers */ static void
>> +bxt_dsi_program_clocks(struct drm_device *dev, enum port port) {
>> + u32 tmp;
>> + u32 divider;
>> + u32 dsi_rate;
>> + u32 pll_ratio;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> +
>> + /* Get the current DSI rate(actual) */
>> + pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
>> + BXT_DSI_PLL_RATIO_MASK;
>> + dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
>> +
>> + /* Max possible output of clock is 39.5 MHz, program value -1 */
>> + divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
>> + tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
>> +
>> + /* Tx escape clock should be >=20MHz, so select divide by 2 */
>
>Actually the Tx escape clock must be as close as possible to, but not exceed, 20
>MHz.
>> + tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
>> +
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 12/14] drm/i915/bxt: Program Backlight PWM frequency
2015-09-18 13:33 ` Jani Nikula
@ 2015-09-21 10:18 ` Shankar, Uma
0 siblings, 0 replies; 69+ messages in thread
From: Shankar, Uma @ 2015-09-21 10:18 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Kumar, Shobhit
>-----Original Message-----
>From: Nikula, Jani
>Sent: Friday, September 18, 2015 7:03 PM
>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>Cc: Kumar, Shobhit; Deak, Imre; Shankar, Uma
>Subject: Re: [BXT MIPI PATCH v3 12/14] drm/i915/bxt: Program Backlight PWM
>frequency
>
>On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
>> In some cases, BIOS doesn't initializes DSI panel.DSI and backlight
>> registers are thereby not initialized. Programming the same in driver
>> backlight setup.
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>
>This is probably obsolete now. See current bxt_setup_backlight.
>
>BR,
>Jani.
>
Yeah, we can drop this patch since the values will be updated in VBT. Thanks Jani for notifying.
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 3 +++
>> drivers/gpu/drm/i915/intel_panel.c | 11 +++++++++++
>> 2 files changed, 14 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 8407b5c..10f73b1 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7166,6 +7166,9 @@ enum skl_disp_power_wells {
>> #define TRANS_MSA_12_BPC (3<<5)
>> #define TRANS_MSA_16_BPC (4<<5)
>>
>> +/* Max CDCLK freq for BXT in HZ */
>> +#define BXT_CDCLK_MAX 624000000
>> +
>> /* LCPLL Control */
>> #define LCPLL_CTL 0x130040
>> #define LCPLL_PLL_DISABLE (1<<31)
>> diff --git a/drivers/gpu/drm/i915/intel_panel.c
>> b/drivers/gpu/drm/i915/intel_panel.c
>> index 9fcf86c..8225cea 100644
>> --- a/drivers/gpu/drm/i915/intel_panel.c
>> +++ b/drivers/gpu/drm/i915/intel_panel.c
>> @@ -1427,6 +1427,17 @@ bxt_setup_backlight(struct intel_connector
>*connector, enum pipe unused)
>> panel->backlight.max = I915_READ(
>> BXT_BLC_PWM_FREQ(panel->backlight.controller));
>>
>> + if (!panel->backlight.max) {
>> + DRM_DEBUG_KMS("PWM freq not programmed by BIOS\n");
>> + DRM_DEBUG_KMS("Programming PWM freq\n");
>> +
>> + /* Max Backlight = Max CD Clock / pwm freq) */
>> + panel->backlight.max = (BXT_CDCLK_MAX /
>> + dev_priv->vbt.backlight.pwm_freq_hz);
>> + I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
>> + panel->backlight.max);
>> + }
>> +
>> val = bxt_get_backlight(connector);
>> panel->backlight.level = intel_panel_compute_brightness(connector,
>> val);
>>
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 14/14] drm/i915: Added BXT DSI backlight support
2015-09-18 13:37 ` Jani Nikula
@ 2015-09-21 10:22 ` Shankar, Uma
2015-09-23 18:00 ` [BXT MIPI PATCH v4 " Uma Shankar
1 sibling, 0 replies; 69+ messages in thread
From: Shankar, Uma @ 2015-09-21 10:22 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Kumar, Shobhit
>-----Original Message-----
>From: Nikula, Jani
>Sent: Friday, September 18, 2015 7:08 PM
>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>Cc: Kumar, Shobhit; Deak, Imre; Shankar, Uma
>Subject: Re: [BXT MIPI PATCH v3 14/14] drm/i915: Added BXT DSI backlight
>support
>
>On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
>> DSI backlight support for bxt is added.
>>
>> TODO: There is no support for backlight control in drm panel
>> framework. This will be added as part of VBT version patches
>> fixing the backlight sequence.
>>
>> v2: Fixed Jani's review comments from previous patch. Added the
>> BXT DSI backlight code in this patch. Backlight setup and
>> enable/disable code for backlight is added in intel_dsi.c.
>>
>> v3: Rebased on latest drm-nightly. Fixed Jani's review comments.
>
>I'm not sure why these calls need to be within IS_BROXTON blocks. What
>happens with the current backlight calls? Shouldn't we just have one set of calls?
>
>Also, I think we should get this [1] in first, and see how that affects things.
>
>BR,
>Jani.
>
>[1] http://mid.gmane.org/cover.1442227790.git.jani.nikula@intel.com
>
The idea was not to disturb existing platforms and add support for BXT. We can hold this patch back and get the patch you mentioned merged,
Accordingly if needed we can create a follow up patch to iron things out.
Regards,
Uma Shankar
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dsi.c | 20 +++++++++++++++++++-
>> 1 file changed, 19 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
>> b/drivers/gpu/drm/i915/intel_dsi.c
>> index 08bade2..aee1539 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -438,6 +438,7 @@ static void intel_dsi_enable(struct intel_encoder
>*encoder)
>> struct drm_device *dev = encoder->base.dev;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> + struct intel_connector *intel_connector =
>> +intel_dsi->attached_connector;
>> enum port port;
>>
>> DRM_DEBUG_KMS("\n");
>> @@ -458,6 +459,11 @@ static void intel_dsi_enable(struct intel_encoder
>> *encoder)
>>
>> intel_dsi_port_enable(encoder);
>> }
>> +
>> + if (IS_BROXTON(dev)) {
>> + msleep(intel_dsi->backlight_on_delay);
>> + intel_panel_enable_backlight(intel_connector);
>> + }
>> }
>>
>> static void intel_dsi_pre_enable(struct intel_encoder *encoder) @@
>> -623,10 +629,16 @@ static void intel_dsi_post_disable(struct
>> intel_encoder *encoder) {
>> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> + struct intel_connector *intel_connector =
>> +intel_dsi->attached_connector;
>> u32 val;
>>
>> DRM_DEBUG_KMS("\n");
>>
>> + if (IS_BROXTON(dev_priv->dev)) {
>> + intel_panel_disable_backlight(intel_connector);
>> + msleep(intel_dsi->backlight_off_delay);
>> + }
>> +
>> intel_dsi_disable(encoder);
>>
>> intel_dsi_clear_device_ready(encoder);
>> @@ -1226,8 +1238,14 @@ void intel_dsi_init(struct drm_device *dev)
>>
>> intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
>>
>> - return;
>> + /*
>> + * Pipe parameter is not used for BXT.
>> + * Passing INVALID_PIPE to adher to API requirement.
>> + */
>> + if (IS_BROXTON(dev))
>> + intel_panel_setup_backlight(connector, INVALID_PIPE);
>>
>> + return;
>> err:
>> drm_encoder_cleanup(&intel_encoder->base);
>> kfree(intel_dsi);
>> --
>> 1.7.9.5
>>
>
>--
>Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 11/14] drm/i915/bxt: Modify BXT BLC according to VBT changes
2015-09-18 13:51 ` Jani Nikula
@ 2015-09-21 10:26 ` Shankar, Uma
2015-09-23 17:59 ` [BXT MIPI PATCH v4 " Uma Shankar
1 sibling, 0 replies; 69+ messages in thread
From: Shankar, Uma @ 2015-09-21 10:26 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Kumar, Shobhit
>-----Original Message-----
>From: Nikula, Jani
>Sent: Friday, September 18, 2015 7:21 PM
>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>Cc: Kumar, Shobhit; Deak, Imre; Kamath, Sunil; Kannan, Vandana; Shankar, Uma
>Subject: Re: [BXT MIPI PATCH v3 11/14] drm/i915/bxt: Modify BXT BLC
>according to VBT changes
>
>On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
>> From: Sunil Kamath <sunil.kamath@intel.com>
>>
>> Latest VBT mentions which set of registers will be used for BLC, as
>> controller number field. Making use of this field in BXT BLC
>> implementation. Also, the registers are used in case control pin
>> indicates display DDI. Adding a check for this.
>> According to Bspec, BLC_PWM_*_2 uses the display utility pin for output.
>> To use backlight 2, enable the utility pin with mode = PWM
>> v2: Jani's review comments
>> addressed
>> - Add a prefix _ to BXT BLC registers definitions.
>> - Add "bxt only" comment for u8 controller
>> - Remove control_pin check for DDI controller
>> - Check for valid controller values
>> - Set pipe bits in UTIL_PIN_CTL
>> - Enable/Disable UTIL_PIN_CTL in enable/disable_backlight()
>> - If BLC 2 is used, read active_low_pwm from UTIL_PIN polarity
>> Satheesh's review comment addressed
>> - If UTIL PIN is already enabled, BIOS would have programmed it. No
>> need to disable and enable again.
>> v3: Jani's review comments
>> - add UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK
>> - Disable UTIL_PIN if controller 1 is used
>> - Mask out UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK before
>enabling
>> UTIL_PIN
>> - check valid controller value in intel_bios.c
>> - add backlight.util_pin_active_low
>> - disable util pin before enabling
>> v4: Change for BXT-PO branch:
>> Stubbed unwanted definition which was existing before
>> because of DC6 patch.
>> UTIL_PIN_MODE_PWM (0x1b << 24)
>>
>> v2: Fixed Jani's review comment.
>>
>> v3: Split the backight PWM frequency programming into separate patch,
>> in cases BIOS doesn't initializes it.
>>
>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>> Signed-off-by: Sunil Kamath <sunil.kamath@intel.com>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++----
>> drivers/gpu/drm/i915/intel_drv.h | 2 +
>> drivers/gpu/drm/i915/intel_panel.c | 84 ++++++++++++++++++++++++++++--
>------
>> 3 files changed, 89 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index e43b053..8407b5c 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3512,17 +3512,29 @@ enum skl_disp_power_wells {
>> #define UTIL_PIN_CTL 0x48400
>> #define UTIL_PIN_ENABLE (1 << 31)
>>
>> void intel_panel_disable_backlight(struct intel_connector *connector)
>> @@ -988,16 +998,39 @@ static void bxt_enable_backlight(struct
>intel_connector *connector)
>> struct drm_device *dev = connector->base.dev;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> struct intel_panel *panel = &connector->panel;
>> - u32 pwm_ctl;
>> + enum pipe pipe = intel_get_pipe_from_connector(connector);
>> + u32 pwm_ctl, val;
>> +
>> + /* To use 2nd set of backlight registers, utility pin has to be
>> + * enabled with PWM mode.
>> + * The field should only be changed when the utility pin is disabled
>> + */
>> + if (panel->backlight.controller == 1) {
>> + val = I915_READ(UTIL_PIN_CTL);
>> + if (val & UTIL_PIN_ENABLE) {
>> + DRM_DEBUG_KMS("util pin already enabled\n");
>> + val &= ~UTIL_PIN_ENABLE;
>> + I915_WRITE(UTIL_PIN_CTL, val);
>> + }
>> + /* mask out UTIL_PIN_PIPE and UTIL_PIN_MODE */
>> + val &= ~(UTIL_PIN_PIPE_MASK | UTIL_PIN_MODE_MASK);
>
>Please start out with 0 val instead of modifying existing state. This is the style
>across backlight enabling, apart from setup which gathers the needed state.
>
>With that fixed,
>
>Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
Thanks for the comment and spotting it out. Will update this in subsequent patchset.
Regards,
Uma Shankar
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-18 14:18 ` Jani Nikula
@ 2015-09-21 10:41 ` Shankar, Uma
2015-09-23 8:15 ` Daniel Vetter
0 siblings, 1 reply; 69+ messages in thread
From: Shankar, Uma @ 2015-09-21 10:41 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Kumar, Shobhit
>-----Original Message-----
>From: Nikula, Jani
>Sent: Friday, September 18, 2015 7:48 PM
>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
>Subject: Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in
>CRTC modeset
>
>On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
>> From: Shashank Sharma <shashank.sharma@intel.com>
>>
>> SKL and BXT qualifies the HAS_DDI() check, and hence haswell modeset
>> functions are re-used for modeset sequence. But DDI interface doesn't
>> include support for DSI.
>> This patch adds:
>> 1. cases for DSI encoder, in those modeset functions and allows
>> a CRTC modeset
>> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
>> needs to be done as such in CRTC for DSI encoder, as PLL, clock
>> and and transcoder programming will be taken care in encoder's
>> pre_enable and pre_pll_enable function.
>>
>> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
>> encoder like DSI for platforms having HAS_DDI as true.
>>
>> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
>> encoder.
>>
>> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> drivers/gpu/drm/i915/intel_ddi.c | 29 ++++++++++++++++++++++++++++-
>> drivers/gpu/drm/i915/intel_display.c | 19 ++++++++++++++-----
>> drivers/gpu/drm/i915/intel_dp_mst.c | 1 +
>> drivers/gpu/drm/i915/intel_opregion.c | 3 ++-
>> 5 files changed, 46 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h index fd1de45..78d31c5 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -142,6 +142,7 @@ enum plane {
>> #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] +
>> (s) + 'A')
>>
>> enum port {
>> + PORT_INVALID = -1,
>> PORT_A = 0,
>> PORT_B,
>> PORT_C,
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>> b/drivers/gpu/drm/i915/intel_ddi.c
>> index cacb07b..5d5aad2 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct
>intel_encoder *intel_encoder,
>> } else if (type == INTEL_OUTPUT_ANALOG) {
>> *dig_port = NULL;
>> *port = PORT_E;
>> + } else if (type == INTEL_OUTPUT_DSI) {
>> + *dig_port = NULL;
>> + *port = PORT_INVALID;
>> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
>
>Please remind me again what are the legitimate paths to get here with DSI?
>
>With all the changes and warns across the driver, I'm beginning to think we
>should have a version of this function that accepts DSI, and another one that
>(calls the other one) and WARNS on DSI, and that should be called on all paths
>that should never encounter a DSI encoder.
>
>The proliferation of WARNS all over the place is not very nice.
>
>I'm sorry, I know this is not the review I gave previously on this.
>
>BR,
>Jani.
This is a tricky piece Jani. Our code for BXT extensively uses haswell functions which was a DDI only implementation.
So many functions just use intel_ddi_get_encoder_port (bxt_ddi_clock_get is one such example). Currently I have added
WARN_ON in all of these functions, though some may not get called if DSI encoder is present. We can remove those,
but still this will be a good check to have IMO.
Overall, I feel even if we implement two separate functions, for the generic functions to pick the correct one, we may have
to have a DSI check there in those generic functions.
Please suggest.
Regards,
Uma Shankar
>> } else {
>> DRM_ERROR("Invalid DDI encoder type %d\n", type);
>> BUG();
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 01/14] drm/i915/bxt: Initialize MIPI for BXT
2015-09-18 12:17 ` Jani Nikula
@ 2015-09-23 8:08 ` Daniel Vetter
0 siblings, 0 replies; 69+ messages in thread
From: Daniel Vetter @ 2015-09-23 8:08 UTC (permalink / raw)
To: Jani Nikula; +Cc: shobhit.kumar, intel-gfx
On Fri, Sep 18, 2015 at 03:17:51PM +0300, Jani Nikula wrote:
> On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> > From: Shashank Sharma <shashank.sharma@intel.com>
> >
> > This patch contains following changes:
> > 1. Add BXT MIPI display address base.
> > 2. Call dsi_init from display_setup function.
> >
> > v2: Rebased on latest nightly branch
> >
> > Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>
> I'm not sure if this should be applied as the first patch or not, but
Enabling patch should be last to avoid fireworks shows. I'll reorder while
applying since this isn't the first patch series today with this problem
;-)
Cheers, Daniel
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_display.c | 3 +++
> > drivers/gpu/drm/i915/intel_dsi.c | 2 ++
> > 3 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 2030f60..621151b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1641,6 +1641,7 @@ enum skl_disp_power_wells {
> >
> > #define VLV_DISPLAY_BASE 0x180000
> > #define VLV_MIPI_BASE VLV_DISPLAY_BASE
> > +#define BXT_MIPI_BASE 0x60000
> >
> > #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030)
> > #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 87476ff..b8e0310 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -13906,6 +13906,9 @@ static void intel_setup_outputs(struct drm_device *dev)
> > * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
> > * detect the ports.
> > */
> > + /* Initialize MIPI for BXT */
> > + intel_dsi_init(dev);
> > +
> > intel_ddi_init(dev, PORT_A);
> > intel_ddi_init(dev, PORT_B);
> > intel_ddi_init(dev, PORT_C);
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> > index b5a5558..b59b828 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -998,6 +998,8 @@ void intel_dsi_init(struct drm_device *dev)
> >
> > if (IS_VALLEYVIEW(dev)) {
> > dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> > + } else if (IS_BROXTON(dev)) {
> > + dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
> > } else {
> > DRM_ERROR("Unsupported Mipi device to reg base");
> > return;
> > --
> > 1.7.9.5
> >
>
> --
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-21 10:41 ` Shankar, Uma
@ 2015-09-23 8:15 ` Daniel Vetter
2015-09-23 12:43 ` Jani Nikula
0 siblings, 1 reply; 69+ messages in thread
From: Daniel Vetter @ 2015-09-23 8:15 UTC (permalink / raw)
To: Shankar, Uma; +Cc: Nikula, Jani, Kumar, Shobhit, intel-gfx
On Mon, Sep 21, 2015 at 10:41:58AM +0000, Shankar, Uma wrote:
>
>
> >-----Original Message-----
> >From: Nikula, Jani
> >Sent: Friday, September 18, 2015 7:48 PM
> >To: Shankar, Uma; intel-gfx@lists.freedesktop.org
> >Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
> >Subject: Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in
> >CRTC modeset
> >
> >On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> >> From: Shashank Sharma <shashank.sharma@intel.com>
> >>
> >> SKL and BXT qualifies the HAS_DDI() check, and hence haswell modeset
> >> functions are re-used for modeset sequence. But DDI interface doesn't
> >> include support for DSI.
> >> This patch adds:
> >> 1. cases for DSI encoder, in those modeset functions and allows
> >> a CRTC modeset
> >> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
> >> needs to be done as such in CRTC for DSI encoder, as PLL, clock
> >> and and transcoder programming will be taken care in encoder's
> >> pre_enable and pre_pll_enable function.
> >>
> >> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
> >> encoder like DSI for platforms having HAS_DDI as true.
> >>
> >> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
> >> encoder.
> >>
> >> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> >> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_drv.h | 1 +
> >> drivers/gpu/drm/i915/intel_ddi.c | 29 ++++++++++++++++++++++++++++-
> >> drivers/gpu/drm/i915/intel_display.c | 19 ++++++++++++++-----
> >> drivers/gpu/drm/i915/intel_dp_mst.c | 1 +
> >> drivers/gpu/drm/i915/intel_opregion.c | 3 ++-
> >> 5 files changed, 46 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >> b/drivers/gpu/drm/i915/i915_drv.h index fd1de45..78d31c5 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -142,6 +142,7 @@ enum plane {
> >> #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] +
> >> (s) + 'A')
> >>
> >> enum port {
> >> + PORT_INVALID = -1,
> >> PORT_A = 0,
> >> PORT_B,
> >> PORT_C,
> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> >> b/drivers/gpu/drm/i915/intel_ddi.c
> >> index cacb07b..5d5aad2 100644
> >> --- a/drivers/gpu/drm/i915/intel_ddi.c
> >> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> >> @@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct
> >intel_encoder *intel_encoder,
> >> } else if (type == INTEL_OUTPUT_ANALOG) {
> >> *dig_port = NULL;
> >> *port = PORT_E;
> >> + } else if (type == INTEL_OUTPUT_DSI) {
> >> + *dig_port = NULL;
> >> + *port = PORT_INVALID;
> >> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
> >
> >Please remind me again what are the legitimate paths to get here with DSI?
> >
> >With all the changes and warns across the driver, I'm beginning to think we
> >should have a version of this function that accepts DSI, and another one that
> >(calls the other one) and WARNS on DSI, and that should be called on all paths
> >that should never encounter a DSI encoder.
> >
> >The proliferation of WARNS all over the place is not very nice.
> >
> >I'm sorry, I know this is not the review I gave previously on this.
> >
> >BR,
> >Jani.
>
> This is a tricky piece Jani. Our code for BXT extensively uses haswell functions which was a DDI only implementation.
> So many functions just use intel_ddi_get_encoder_port (bxt_ddi_clock_get is one such example). Currently I have added
> WARN_ON in all of these functions, though some may not get called if DSI encoder is present. We can remove those,
> but still this will be a good check to have IMO.
>
> Overall, I feel even if we implement two separate functions, for the generic functions to pick the correct one, we may have
> to have a DSI check there in those generic functions.
Yeah hsw+ ddi design isn't great since the split between encoder and crtc
isn't where the crossbar is, which means there's lots of calls from crtc
code into DDI encoder functions. I started with that reshuffling a while
back but Paulo shot it down a bit, but I think with bxt dsi we have a good
reason for this.
Essentially all differences between DSI, DDI (hdmi or DP) and DDI in FDI
mode (for vga on hsw) should be hidden behind intel_encoder callbacks.
But since it doesn't make much sense to hold up dsi enabling for even
longer we should do that in parallel. And for doing that refactoring
throwing piles of WARN_ON checks at the code imo makes sense (even if it
doesn't look pretty).
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 04/14] drm/i915/bxt: DSI prepare changes for BXT
2015-09-18 13:05 ` Jani Nikula
@ 2015-09-23 8:16 ` Daniel Vetter
0 siblings, 0 replies; 69+ messages in thread
From: Daniel Vetter @ 2015-09-23 8:16 UTC (permalink / raw)
To: Jani Nikula; +Cc: shobhit.kumar, intel-gfx
On Fri, Sep 18, 2015 at 04:05:17PM +0300, Jani Nikula wrote:
> On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> > From: Shashank Sharma <shashank.sharma@intel.com>
> >
> > This patch modifies dsi_prepare() function to support the same
> > modeset prepare sequence for BXT also. Main changes are:
> > 1. BXT port control register is different than VLV.
> > 2. BXT modeset sequence needs vdisplay and hdisplay programmed
> > for transcoder.
> > 3. BXT can select PIPE for MIPI transcoders.
> > 4. BXT needs to program register MIPI_INIT_COUNT for both the ports,
> > even if only one is being used.
> >
> > v2: Fixed Jani's review comments. Rectified the DSI Macros to get
> > proper register offsets using _MIPI_PORT instead of _TRANSCODER
> >
> > v3: Rebased on latest drm-nightly branch. Fixed Jani's review comments.
> >
> > Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Merged up to this patch (except for patch 1, that should be at the end).
-Daniel
>
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 21 ++++++++++++
> > drivers/gpu/drm/i915/intel_dsi.c | 69 ++++++++++++++++++++++++++++++++------
> > 2 files changed, 80 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 06bb2e1..997a999 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7362,6 +7362,22 @@ enum skl_disp_power_wells {
> >
> > #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
> >
> > +/* BXT MIPI mode configure */
> > +#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
> > +#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
> > +#define BXT_MIPI_TRANS_HACTIVE(tc) _MIPI_PORT(tc, \
> > + _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
> > +
> > +#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
> > +#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
> > +#define BXT_MIPI_TRANS_VACTIVE(tc) _MIPI_PORT(tc, \
> > + _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
> > +
> > +#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
> > +#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
> > +#define BXT_MIPI_TRANS_VTOTAL(tc) _MIPI_PORT(tc, \
> > + _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
> > +
> > #define BXT_DSI_PLL_CTL 0x161000
> > #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
> > #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> > @@ -7797,6 +7813,11 @@ enum skl_disp_power_wells {
> > #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
> > #define RGB_FLIP_TO_BGR (1 << 2)
> >
> > +#define BXT_PIPE_SELECT_MASK (7 << 7)
> > +#define BXT_PIPE_SELECT_C (2 << 7)
> > +#define BXT_PIPE_SELECT_B (1 << 7)
> > +#define BXT_PIPE_SELECT_A (0 << 7)
> > +
> > #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
> > #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
> > #define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> > index bac988a..6d0c992 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -726,6 +726,21 @@ static void set_dsi_timings(struct drm_encoder *encoder,
> > hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
> >
> > for_each_dsi_port(port, intel_dsi->ports) {
> > + if (IS_BROXTON(dev)) {
> > + /*
> > + * Program hdisplay and vdisplay on MIPI transcoder.
> > + * This is different from calculated hactive and
> > + * vactive, as they are calculated per channel basis,
> > + * whereas these values should be based on resolution.
> > + */
> > + I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
> > + mode->hdisplay);
> > + I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
> > + mode->vdisplay);
> > + I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
> > + mode->vtotal);
> > + }
> > +
> > I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
> > I915_WRITE(MIPI_HFP_COUNT(port), hfp);
> >
> > @@ -766,16 +781,39 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
> > }
> >
> > for_each_dsi_port(port, intel_dsi->ports) {
> > - /* escape clock divider, 20MHz, shared for A and C.
> > - * device ready must be off when doing this! txclkesc? */
> > - tmp = I915_READ(MIPI_CTRL(PORT_A));
> > - tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> > - I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
> > -
> > - /* read request priority is per pipe */
> > - tmp = I915_READ(MIPI_CTRL(port));
> > - tmp &= ~READ_REQUEST_PRIORITY_MASK;
> > - I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
> > + if (IS_VALLEYVIEW(dev)) {
> > + /*
> > + * escape clock divider, 20MHz, shared for A and C.
> > + * device ready must be off when doing this! txclkesc?
> > + */
> > + tmp = I915_READ(MIPI_CTRL(PORT_A));
> > + tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> > + I915_WRITE(MIPI_CTRL(PORT_A), tmp |
> > + ESCAPE_CLOCK_DIVIDER_1);
> > +
> > + /* read request priority is per pipe */
> > + tmp = I915_READ(MIPI_CTRL(port));
> > + tmp &= ~READ_REQUEST_PRIORITY_MASK;
> > + I915_WRITE(MIPI_CTRL(port), tmp |
> > + READ_REQUEST_PRIORITY_HIGH);
> > + } else if (IS_BROXTON(dev)) {
> > + /*
> > + * FIXME:
> > + * BXT can connect any PIPE to any MIPI port.
> > + * Select the pipe based on the MIPI port read from
> > + * VBT for now. Pick PIPE A for MIPI port A and C
> > + * for port C.
> > + */
> > + tmp = I915_READ(MIPI_CTRL(port));
> > + tmp &= ~BXT_PIPE_SELECT_MASK;
> > +
> > + if (port == PORT_A)
> > + tmp |= BXT_PIPE_SELECT_A;
> > + else if (port == PORT_C)
> > + tmp |= BXT_PIPE_SELECT_C;
> > +
> > + I915_WRITE(MIPI_CTRL(port), tmp);
> > + }
> >
> > /* XXX: why here, why like this? handling in irq handler?! */
> > I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
> > @@ -852,6 +890,17 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
> > I915_WRITE(MIPI_INIT_COUNT(port),
> > txclkesc(intel_dsi->escape_clk_div, 100));
> >
> > + if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
> > + /*
> > + * BXT spec says write MIPI_INIT_COUNT for
> > + * both the ports, even if only one is
> > + * getting used. So write the other port
> > + * if not in dual link mode.
> > + */
> > + I915_WRITE(MIPI_INIT_COUNT(port ==
> > + PORT_A ? PORT_C : PORT_A),
> > + intel_dsi->init_count);
> > + }
> >
> > /* recovery disables */
> > I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
> > --
> > 1.7.9.5
> >
>
> --
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-23 8:15 ` Daniel Vetter
@ 2015-09-23 12:43 ` Jani Nikula
2015-09-23 13:11 ` Daniel Vetter
0 siblings, 1 reply; 69+ messages in thread
From: Jani Nikula @ 2015-09-23 12:43 UTC (permalink / raw)
To: Daniel Vetter, Shankar, Uma; +Cc: Kumar, Shobhit, intel-gfx
On Wed, 23 Sep 2015, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Mon, Sep 21, 2015 at 10:41:58AM +0000, Shankar, Uma wrote:
>>
>>
>> >-----Original Message-----
>> >From: Nikula, Jani
>> >Sent: Friday, September 18, 2015 7:48 PM
>> >To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>> >Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
>> >Subject: Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in
>> >CRTC modeset
>> >
>> >On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
>> >> From: Shashank Sharma <shashank.sharma@intel.com>
>> >>
>> >> SKL and BXT qualifies the HAS_DDI() check, and hence haswell modeset
>> >> functions are re-used for modeset sequence. But DDI interface doesn't
>> >> include support for DSI.
>> >> This patch adds:
>> >> 1. cases for DSI encoder, in those modeset functions and allows
>> >> a CRTC modeset
>> >> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
>> >> needs to be done as such in CRTC for DSI encoder, as PLL, clock
>> >> and and transcoder programming will be taken care in encoder's
>> >> pre_enable and pre_pll_enable function.
>> >>
>> >> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
>> >> encoder like DSI for platforms having HAS_DDI as true.
>> >>
>> >> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
>> >> encoder.
>> >>
>> >> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
>> >> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> >> ---
>> >> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> >> drivers/gpu/drm/i915/intel_ddi.c | 29 ++++++++++++++++++++++++++++-
>> >> drivers/gpu/drm/i915/intel_display.c | 19 ++++++++++++++-----
>> >> drivers/gpu/drm/i915/intel_dp_mst.c | 1 +
>> >> drivers/gpu/drm/i915/intel_opregion.c | 3 ++-
>> >> 5 files changed, 46 insertions(+), 7 deletions(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> >> b/drivers/gpu/drm/i915/i915_drv.h index fd1de45..78d31c5 100644
>> >> --- a/drivers/gpu/drm/i915/i915_drv.h
>> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> >> @@ -142,6 +142,7 @@ enum plane {
>> >> #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] +
>> >> (s) + 'A')
>> >>
>> >> enum port {
>> >> + PORT_INVALID = -1,
>> >> PORT_A = 0,
>> >> PORT_B,
>> >> PORT_C,
>> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>> >> b/drivers/gpu/drm/i915/intel_ddi.c
>> >> index cacb07b..5d5aad2 100644
>> >> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> >> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> >> @@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct
>> >intel_encoder *intel_encoder,
>> >> } else if (type == INTEL_OUTPUT_ANALOG) {
>> >> *dig_port = NULL;
>> >> *port = PORT_E;
>> >> + } else if (type == INTEL_OUTPUT_DSI) {
>> >> + *dig_port = NULL;
>> >> + *port = PORT_INVALID;
>> >> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
>> >
>> >Please remind me again what are the legitimate paths to get here with DSI?
>> >
>> >With all the changes and warns across the driver, I'm beginning to think we
>> >should have a version of this function that accepts DSI, and another one that
>> >(calls the other one) and WARNS on DSI, and that should be called on all paths
>> >that should never encounter a DSI encoder.
>> >
>> >The proliferation of WARNS all over the place is not very nice.
>> >
>> >I'm sorry, I know this is not the review I gave previously on this.
>> >
>> >BR,
>> >Jani.
>>
>> This is a tricky piece Jani. Our code for BXT extensively uses haswell functions which was a DDI only implementation.
>> So many functions just use intel_ddi_get_encoder_port (bxt_ddi_clock_get is one such example). Currently I have added
>> WARN_ON in all of these functions, though some may not get called if DSI encoder is present. We can remove those,
>> but still this will be a good check to have IMO.
>>
>> Overall, I feel even if we implement two separate functions, for the generic functions to pick the correct one, we may have
>> to have a DSI check there in those generic functions.
>
> Yeah hsw+ ddi design isn't great since the split between encoder and crtc
> isn't where the crossbar is, which means there's lots of calls from crtc
> code into DDI encoder functions. I started with that reshuffling a while
> back but Paulo shot it down a bit, but I think with bxt dsi we have a good
> reason for this.
>
> Essentially all differences between DSI, DDI (hdmi or DP) and DDI in FDI
> mode (for vga on hsw) should be hidden behind intel_encoder callbacks.
>
> But since it doesn't make much sense to hold up dsi enabling for even
> longer we should do that in parallel. And for doing that refactoring
> throwing piles of WARN_ON checks at the code imo makes sense (even if it
> doesn't look pretty).
As far as I can tell, there's two calls to {intel_}ddi_get_encoder_port
that are functionally changed for DSI in this patch: intel_prepare_ddi()
(which adds a WARN for good measure anyway), and
intel_opregion_notify_encoder().
I am wondering if it would be cleaner to check for intel_encoder->type
== INTEL_OUTPUT_DSI in these two sites *instead* of doing the call, and
having a WARN_ON(type == INTEL_OUTPUT_DSI) inside ddi_get_encoder_port.
My worry beyond this patch is that the checks for PORT_INVALID will
proliferate across the driver for no good reason other than this corner
case.
BR,
Jani.
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-01 14:11 ` [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset Uma Shankar
2015-09-18 14:18 ` Jani Nikula
@ 2015-09-23 12:53 ` Jani Nikula
2015-09-23 14:49 ` Shankar, Uma
1 sibling, 1 reply; 69+ messages in thread
From: Jani Nikula @ 2015-09-23 12:53 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> @@ -5057,13 +5060,16 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->config->has_pch_encoder)
> lpt_pch_enable(crtc);
>
> - if (intel_crtc->config->dp_encoder_is_mst)
> + if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
> intel_ddi_set_vc_payload_alloc(crtc, true);
>
> assert_vblank_disabled(crtc);
> drm_crtc_vblank_on(crtc);
>
> for_each_encoder_on_crtc(dev, crtc, encoder) {
> + if (encoder->pre_pll_enable)
> + encoder->pre_pll_enable(encoder);
> +
We should not modify the crtc enable sequence to accommodate the needs
of one encoder type only. The hook names should be taken as describing
roughly when in the sequence they are called, not necessarily what they
must do for each encoder. If an encoder requires a different ordering or
sequence, it should handle this in what it does in its hooks - and this
may possibly need to be different on each platform.
Here, the ->pre_pll_enable call is added after the ->pre_enable call,
making the sequence of calls surprising. Also, there is no point in
calling ->pre_pll_enable in the same loop as ->enable; the encoder could
just as well do everything in ->enable. Indeed, this may be what you
should do on Broxton.
I'm willing to ignore [1] if Daniel thinks my worry is unwarranted, but
this part must be fixed.
BR,
Jani.
[1] http://mid.gmane.org/87twqlnw5k.fsf@intel.com
> encoder->enable(encoder);
> intel_opregion_notify_encoder(encoder, true);
> }
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-23 12:43 ` Jani Nikula
@ 2015-09-23 13:11 ` Daniel Vetter
2015-09-23 14:44 ` Shankar, Uma
0 siblings, 1 reply; 69+ messages in thread
From: Daniel Vetter @ 2015-09-23 13:11 UTC (permalink / raw)
To: Jani Nikula; +Cc: Kumar, Shobhit, intel-gfx
On Wed, Sep 23, 2015 at 03:43:35PM +0300, Jani Nikula wrote:
> On Wed, 23 Sep 2015, Daniel Vetter <daniel@ffwll.ch> wrote:
> > On Mon, Sep 21, 2015 at 10:41:58AM +0000, Shankar, Uma wrote:
> >>
> >>
> >> >-----Original Message-----
> >> >From: Nikula, Jani
> >> >Sent: Friday, September 18, 2015 7:48 PM
> >> >To: Shankar, Uma; intel-gfx@lists.freedesktop.org
> >> >Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
> >> >Subject: Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in
> >> >CRTC modeset
> >> >
> >> >On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> >> >> From: Shashank Sharma <shashank.sharma@intel.com>
> >> >>
> >> >> SKL and BXT qualifies the HAS_DDI() check, and hence haswell modeset
> >> >> functions are re-used for modeset sequence. But DDI interface doesn't
> >> >> include support for DSI.
> >> >> This patch adds:
> >> >> 1. cases for DSI encoder, in those modeset functions and allows
> >> >> a CRTC modeset
> >> >> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
> >> >> needs to be done as such in CRTC for DSI encoder, as PLL, clock
> >> >> and and transcoder programming will be taken care in encoder's
> >> >> pre_enable and pre_pll_enable function.
> >> >>
> >> >> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
> >> >> encoder like DSI for platforms having HAS_DDI as true.
> >> >>
> >> >> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
> >> >> encoder.
> >> >>
> >> >> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> >> >> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> >> >> ---
> >> >> drivers/gpu/drm/i915/i915_drv.h | 1 +
> >> >> drivers/gpu/drm/i915/intel_ddi.c | 29 ++++++++++++++++++++++++++++-
> >> >> drivers/gpu/drm/i915/intel_display.c | 19 ++++++++++++++-----
> >> >> drivers/gpu/drm/i915/intel_dp_mst.c | 1 +
> >> >> drivers/gpu/drm/i915/intel_opregion.c | 3 ++-
> >> >> 5 files changed, 46 insertions(+), 7 deletions(-)
> >> >>
> >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >> >> b/drivers/gpu/drm/i915/i915_drv.h index fd1de45..78d31c5 100644
> >> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> >> @@ -142,6 +142,7 @@ enum plane {
> >> >> #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] +
> >> >> (s) + 'A')
> >> >>
> >> >> enum port {
> >> >> + PORT_INVALID = -1,
> >> >> PORT_A = 0,
> >> >> PORT_B,
> >> >> PORT_C,
> >> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> >> >> b/drivers/gpu/drm/i915/intel_ddi.c
> >> >> index cacb07b..5d5aad2 100644
> >> >> --- a/drivers/gpu/drm/i915/intel_ddi.c
> >> >> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> >> >> @@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct
> >> >intel_encoder *intel_encoder,
> >> >> } else if (type == INTEL_OUTPUT_ANALOG) {
> >> >> *dig_port = NULL;
> >> >> *port = PORT_E;
> >> >> + } else if (type == INTEL_OUTPUT_DSI) {
> >> >> + *dig_port = NULL;
> >> >> + *port = PORT_INVALID;
> >> >> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
> >> >
> >> >Please remind me again what are the legitimate paths to get here with DSI?
> >> >
> >> >With all the changes and warns across the driver, I'm beginning to think we
> >> >should have a version of this function that accepts DSI, and another one that
> >> >(calls the other one) and WARNS on DSI, and that should be called on all paths
> >> >that should never encounter a DSI encoder.
> >> >
> >> >The proliferation of WARNS all over the place is not very nice.
> >> >
> >> >I'm sorry, I know this is not the review I gave previously on this.
> >> >
> >> >BR,
> >> >Jani.
> >>
> >> This is a tricky piece Jani. Our code for BXT extensively uses haswell functions which was a DDI only implementation.
> >> So many functions just use intel_ddi_get_encoder_port (bxt_ddi_clock_get is one such example). Currently I have added
> >> WARN_ON in all of these functions, though some may not get called if DSI encoder is present. We can remove those,
> >> but still this will be a good check to have IMO.
> >>
> >> Overall, I feel even if we implement two separate functions, for the generic functions to pick the correct one, we may have
> >> to have a DSI check there in those generic functions.
> >
> > Yeah hsw+ ddi design isn't great since the split between encoder and crtc
> > isn't where the crossbar is, which means there's lots of calls from crtc
> > code into DDI encoder functions. I started with that reshuffling a while
> > back but Paulo shot it down a bit, but I think with bxt dsi we have a good
> > reason for this.
> >
> > Essentially all differences between DSI, DDI (hdmi or DP) and DDI in FDI
> > mode (for vga on hsw) should be hidden behind intel_encoder callbacks.
> >
> > But since it doesn't make much sense to hold up dsi enabling for even
> > longer we should do that in parallel. And for doing that refactoring
> > throwing piles of WARN_ON checks at the code imo makes sense (even if it
> > doesn't look pretty).
>
> As far as I can tell, there's two calls to {intel_}ddi_get_encoder_port
> that are functionally changed for DSI in this patch: intel_prepare_ddi()
> (which adds a WARN for good measure anyway), and
> intel_opregion_notify_encoder().
>
> I am wondering if it would be cleaner to check for intel_encoder->type
> == INTEL_OUTPUT_DSI in these two sites *instead* of doing the call, and
> having a WARN_ON(type == INTEL_OUTPUT_DSI) inside ddi_get_encoder_port.
>
> My worry beyond this patch is that the checks for PORT_INVALID will
> proliferate across the driver for no good reason other than this corner
> case.
I like this idea, since it also aligns more with the rework we need to do
For that one we probably need to add a ddi_port to the crtc config and
make sure only ddi encoder related code (for hdmi/dp and vga w/ fdi) use
it.
Seems like the simpler solution with less interim detour overall.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-23 13:11 ` Daniel Vetter
@ 2015-09-23 14:44 ` Shankar, Uma
0 siblings, 0 replies; 69+ messages in thread
From: Shankar, Uma @ 2015-09-23 14:44 UTC (permalink / raw)
To: Daniel Vetter, Nikula, Jani; +Cc: Kumar, Shobhit, intel-gfx
>-----Original Message-----
>From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
>Sent: Wednesday, September 23, 2015 6:42 PM
>To: Nikula, Jani
>Cc: Daniel Vetter; Shankar, Uma; intel-gfx@lists.freedesktop.org; Kumar, Shobhit
>Subject: Re: [Intel-gfx] [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder
>support in CRTC modeset
>
>On Wed, Sep 23, 2015 at 03:43:35PM +0300, Jani Nikula wrote:
>> On Wed, 23 Sep 2015, Daniel Vetter <daniel@ffwll.ch> wrote:
>> > On Mon, Sep 21, 2015 at 10:41:58AM +0000, Shankar, Uma wrote:
>> >>
>> >>
>> >> >-----Original Message-----
>> >> >From: Nikula, Jani
>> >> >Sent: Friday, September 18, 2015 7:48 PM
>> >> >To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>> >> >Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
>> >> >Subject: Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder
>> >> >support in CRTC modeset
>> >> >
>> >> >On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
>> >> >> From: Shashank Sharma <shashank.sharma@intel.com>
>> >> >>
>> >> >> SKL and BXT qualifies the HAS_DDI() check, and hence haswell
>> >> >> modeset functions are re-used for modeset sequence. But DDI
>> >> >> interface doesn't include support for DSI.
>> >> >> This patch adds:
>> >> >> 1. cases for DSI encoder, in those modeset functions and allows
>> >> >> a CRTC modeset
>> >> >> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
>> >> >> needs to be done as such in CRTC for DSI encoder, as PLL, clock
>> >> >> and and transcoder programming will be taken care in encoder's
>> >> >> pre_enable and pre_pll_enable function.
>> >> >>
>> >> >> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
>> >> >> encoder like DSI for platforms having HAS_DDI as true.
>> >> >>
>> >> >> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
>> >> >> encoder.
>> >> >>
>> >> >> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
>> >> >> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> >> >> ---
>> >> >> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> >> >> drivers/gpu/drm/i915/intel_ddi.c | 29
>++++++++++++++++++++++++++++-
>> >> >> drivers/gpu/drm/i915/intel_display.c | 19 ++++++++++++++-----
>> >> >> drivers/gpu/drm/i915/intel_dp_mst.c | 1 +
>> >> >> drivers/gpu/drm/i915/intel_opregion.c | 3 ++-
>> >> >> 5 files changed, 46 insertions(+), 7 deletions(-)
>> >> >>
>> >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> >> >> b/drivers/gpu/drm/i915/i915_drv.h index fd1de45..78d31c5 100644
>> >> >> --- a/drivers/gpu/drm/i915/i915_drv.h
>> >> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> >> >> @@ -142,6 +142,7 @@ enum plane { #define sprite_name(p, s) ((p)
>> >> >> * INTEL_INFO(dev)->num_sprites[(p)] +
>> >> >> (s) + 'A')
>> >> >>
>> >> >> enum port {
>> >> >> + PORT_INVALID = -1,
>> >> >> PORT_A = 0,
>> >> >> PORT_B,
>> >> >> PORT_C,
>> >> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>> >> >> b/drivers/gpu/drm/i915/intel_ddi.c
>> >> >> index cacb07b..5d5aad2 100644
>> >> >> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> >> >> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> >> >> @@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct
>> >> >intel_encoder *intel_encoder,
>> >> >> } else if (type == INTEL_OUTPUT_ANALOG) {
>> >> >> *dig_port = NULL;
>> >> >> *port = PORT_E;
>> >> >> + } else if (type == INTEL_OUTPUT_DSI) {
>> >> >> + *dig_port = NULL;
>> >> >> + *port = PORT_INVALID;
>> >> >> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
>> >> >
>> >> >Please remind me again what are the legitimate paths to get here with
>DSI?
>> >> >
>> >> >With all the changes and warns across the driver, I'm beginning to
>> >> >think we should have a version of this function that accepts DSI,
>> >> >and another one that (calls the other one) and WARNS on DSI, and
>> >> >that should be called on all paths that should never encounter a DSI
>encoder.
>> >> >
>> >> >The proliferation of WARNS all over the place is not very nice.
>> >> >
>> >> >I'm sorry, I know this is not the review I gave previously on this.
>> >> >
>> >> >BR,
>> >> >Jani.
>> >>
>> >> This is a tricky piece Jani. Our code for BXT extensively uses haswell
>functions which was a DDI only implementation.
>> >> So many functions just use intel_ddi_get_encoder_port
>> >> (bxt_ddi_clock_get is one such example). Currently I have added
>> >> WARN_ON in all of these functions, though some may not get called if DSI
>encoder is present. We can remove those, but still this will be a good check to
>have IMO.
>> >>
>> >> Overall, I feel even if we implement two separate functions, for
>> >> the generic functions to pick the correct one, we may have to have a DSI
>check there in those generic functions.
>> >
>> > Yeah hsw+ ddi design isn't great since the split between encoder and
>> > crtc isn't where the crossbar is, which means there's lots of calls
>> > from crtc code into DDI encoder functions. I started with that
>> > reshuffling a while back but Paulo shot it down a bit, but I think
>> > with bxt dsi we have a good reason for this.
>> >
>> > Essentially all differences between DSI, DDI (hdmi or DP) and DDI in
>> > FDI mode (for vga on hsw) should be hidden behind intel_encoder callbacks.
>> >
>> > But since it doesn't make much sense to hold up dsi enabling for
>> > even longer we should do that in parallel. And for doing that
>> > refactoring throwing piles of WARN_ON checks at the code imo makes
>> > sense (even if it doesn't look pretty).
>>
>> As far as I can tell, there's two calls to
>> {intel_}ddi_get_encoder_port that are functionally changed for DSI in
>> this patch: intel_prepare_ddi() (which adds a WARN for good measure
>> anyway), and intel_opregion_notify_encoder().
>>
>> I am wondering if it would be cleaner to check for intel_encoder->type
>> == INTEL_OUTPUT_DSI in these two sites *instead* of doing the call,
>> and having a WARN_ON(type == INTEL_OUTPUT_DSI) inside
>ddi_get_encoder_port.
>>
>> My worry beyond this patch is that the checks for PORT_INVALID will
>> proliferate across the driver for no good reason other than this
>> corner case.
>
>I like this idea, since it also aligns more with the rework we need to do For that
>one we probably need to add a ddi_port to the crtc config and make sure only
>ddi encoder related code (for hdmi/dp and vga w/ fdi) use it.
>
>Seems like the simpler solution with less interim detour overall.
>-Daniel
>--
The suggestion looks good. Will remove the WARN_ON spilled all over and put the warning in intel_ddi_get_encoder_port
instead, if it's a NON DSI encoder.
Thanks Jani for the suggestion.
Regards,
Uma Shankar
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-23 12:53 ` Jani Nikula
@ 2015-09-23 14:49 ` Shankar, Uma
2015-09-23 17:03 ` Shankar, Uma
0 siblings, 1 reply; 69+ messages in thread
From: Shankar, Uma @ 2015-09-23 14:49 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Kumar, Shobhit
>-----Original Message-----
>From: Nikula, Jani
>Sent: Wednesday, September 23, 2015 6:24 PM
>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
>Subject: Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in
>CRTC modeset
>
>On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
>> @@ -5057,13 +5060,16 @@ static void haswell_crtc_enable(struct drm_crtc
>*crtc)
>> if (intel_crtc->config->has_pch_encoder)
>> lpt_pch_enable(crtc);
>>
>> - if (intel_crtc->config->dp_encoder_is_mst)
>> + if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
>> intel_ddi_set_vc_payload_alloc(crtc, true);
>>
>> assert_vblank_disabled(crtc);
>> drm_crtc_vblank_on(crtc);
>>
>> for_each_encoder_on_crtc(dev, crtc, encoder) {
>> + if (encoder->pre_pll_enable)
>> + encoder->pre_pll_enable(encoder);
>> +
>
>We should not modify the crtc enable sequence to accommodate the needs of
>one encoder type only. The hook names should be taken as describing roughly
>when in the sequence they are called, not necessarily what they must do for
>each encoder. If an encoder requires a different ordering or sequence, it should
>handle this in what it does in its hooks - and this may possibly need to be
>different on each platform.
>
>Here, the ->pre_pll_enable call is added after the ->pre_enable call, making the
>sequence of calls surprising. Also, there is no point in calling ->pre_pll_enable in
>the same loop as ->enable; the encoder could just as well do everything in -
>>enable. Indeed, this may be what you should do on Broxton.
>
>I'm willing to ignore [1] if Daniel thinks my worry is unwarranted, but this part
>must be fixed.
>
>
>BR,
>Jani.
>
The pre_pll_enable callback was not being used earlier for any encoder in haswell functions.
This is the reason we used it for DSI at place appropriate for DSI sequence. I will remove the
callback and put the code in encoder->enable callback itself.
Regards,
Uma Shankar
>[1] http://mid.gmane.org/87twqlnw5k.fsf@intel.com
>
>
>> encoder->enable(encoder);
>> intel_opregion_notify_encoder(encoder, true);
>> }
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-23 14:49 ` Shankar, Uma
@ 2015-09-23 17:03 ` Shankar, Uma
2015-09-23 17:53 ` [BXT MIPI PATCH v4 " Uma Shankar
0 siblings, 1 reply; 69+ messages in thread
From: Shankar, Uma @ 2015-09-23 17:03 UTC (permalink / raw)
To: Shankar, Uma, Nikula, Jani, intel-gfx; +Cc: Kumar, Shobhit
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Shankar, Uma
>Sent: Wednesday, September 23, 2015 8:19 PM
>To: Nikula, Jani; intel-gfx@lists.freedesktop.org
>Cc: Kumar, Shobhit
>Subject: Re: [Intel-gfx] [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder
>support in CRTC modeset
>
>
>
>>-----Original Message-----
>>From: Nikula, Jani
>>Sent: Wednesday, September 23, 2015 6:24 PM
>>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>>Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
>>Subject: Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder
>>support in CRTC modeset
>>
>>On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
>>> @@ -5057,13 +5060,16 @@ static void haswell_crtc_enable(struct
>>> drm_crtc
>>*crtc)
>>> if (intel_crtc->config->has_pch_encoder)
>>> lpt_pch_enable(crtc);
>>>
>>> - if (intel_crtc->config->dp_encoder_is_mst)
>>> + if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
>>> intel_ddi_set_vc_payload_alloc(crtc, true);
>>>
>>> assert_vblank_disabled(crtc);
>>> drm_crtc_vblank_on(crtc);
>>>
>>> for_each_encoder_on_crtc(dev, crtc, encoder) {
>>> + if (encoder->pre_pll_enable)
>>> + encoder->pre_pll_enable(encoder);
>>> +
>>
>>We should not modify the crtc enable sequence to accommodate the needs
>>of one encoder type only. The hook names should be taken as describing
>>roughly when in the sequence they are called, not necessarily what they
>>must do for each encoder. If an encoder requires a different ordering
>>or sequence, it should handle this in what it does in its hooks - and
>>this may possibly need to be different on each platform.
>>
>>Here, the ->pre_pll_enable call is added after the ->pre_enable call,
>>making the sequence of calls surprising. Also, there is no point in
>>calling ->pre_pll_enable in the same loop as ->enable; the encoder
>>could just as well do everything in -
>>>enable. Indeed, this may be what you should do on Broxton.
>>
>>I'm willing to ignore [1] if Daniel thinks my worry is unwarranted, but
>>this part must be fixed.
>>
>>
>>BR,
>>Jani.
>>
>
>The pre_pll_enable callback was not being used earlier for any encoder in
>haswell functions.
>This is the reason we used it for DSI at place appropriate for DSI sequence. I will
>remove the callback and put the code in encoder->enable callback itself.
>
>Regards,
>Uma Shankar
This callback should ideally be before pre_enable. I will update and resend the patch.
This is the order followed for BYT/CHT as well.
Regards,
Uma Shankar
The correct order for BXT is also pre_pll_enable,
>>[1] http://mid.gmane.org/87twqlnw5k.fsf@intel.com
>>
>>
>>> encoder->enable(encoder);
>>> intel_opregion_notify_encoder(encoder, true);
>>> }
>>
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v4 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-23 17:03 ` Shankar, Uma
@ 2015-09-23 17:53 ` Uma Shankar
2015-09-28 13:28 ` Jani Nikula
0 siblings, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-23 17:53 UTC (permalink / raw)
To: intel-gfx; +Cc: shobhit.kumar
From: Shashank Sharma <shashank.sharma@intel.com>
SKL and BXT qualifies the HAS_DDI() check, and hence haswell
modeset functions are re-used for modeset sequence. But DDI
interface doesn't include support for DSI.
This patch adds:
1. cases for DSI encoder, in those modeset functions and allows
a CRTC modeset
2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
needs to be done as such in CRTC for DSI encoder, as PLL, clock
and and transcoder programming will be taken care in encoder's
pre_enable and pre_pll_enable function.
v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
encoder like DSI for platforms having HAS_DDI as true.
v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
encoder.
v4: WARN_ON for invalid encoder is refactored as per Jani's suggestion.
Fixed the sequence for pre_pll_enable.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 21 ++++++++++++++++++++-
drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++------
drivers/gpu/drm/i915/intel_opregion.c | 3 ++-
4 files changed, 38 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fd1de45..78d31c5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -142,6 +142,7 @@ enum plane {
#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
enum port {
+ PORT_INVALID = -1,
PORT_A = 0,
PORT_B,
PORT_C,
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cacb07b..8edb632 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
} else if (type == INTEL_OUTPUT_ANALOG) {
*dig_port = NULL;
*port = PORT_E;
+ } else if (type == INTEL_OUTPUT_DSI) {
+ *dig_port = NULL;
+ *port = PORT_INVALID;
+ DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
} else {
DRM_ERROR("Invalid DDI encoder type %d\n", type);
BUG();
@@ -237,6 +241,15 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
{
struct intel_digital_port *dig_port;
enum port port;
+ int type = intel_encoder->type;
+
+ if (type == INTEL_OUTPUT_DSI) {
+ port = PORT_INVALID;
+ DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
+ WARN_ON(1);
+
+ return port;
+ }
ddi_get_encoder_port(intel_encoder, &dig_port, &port);
@@ -392,6 +405,11 @@ void intel_prepare_ddi(struct drm_device *dev)
ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
+ if (port == PORT_INVALID) {
+ WARN_ON(1);
+ continue;
+ }
+
if (visited[port])
continue;
@@ -1779,7 +1797,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
{
struct drm_crtc *crtc = &intel_crtc->base;
- struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
enum port port = intel_ddi_get_encoder_port(intel_encoder);
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b8e0310..ea0f533 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4991,6 +4991,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
+ bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
int pipe = intel_crtc->pipe;
WARN_ON(!crtc->state->enable);
@@ -5023,9 +5024,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_crtc->active = true;
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- for_each_encoder_on_crtc(dev, crtc, encoder)
+ for_each_encoder_on_crtc(dev, crtc, encoder) {
+ if (encoder->pre_pll_enable)
+ encoder->pre_pll_enable(encoder);
if (encoder->pre_enable)
encoder->pre_enable(encoder);
+ }
if (intel_crtc->config->has_pch_encoder) {
intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
@@ -5033,7 +5037,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
dev_priv->display.fdi_link_train(crtc);
}
- intel_ddi_enable_pipe_clock(intel_crtc);
+ if (!is_dsi)
+ intel_ddi_enable_pipe_clock(intel_crtc);
if (INTEL_INFO(dev)->gen == 9)
skylake_pfit_update(intel_crtc, 1);
@@ -5049,7 +5054,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_crtc_load_lut(crtc);
intel_ddi_set_pipe_settings(crtc);
- intel_ddi_enable_transcoder_func(crtc);
+ if (!is_dsi)
+ intel_ddi_enable_transcoder_func(crtc);
intel_update_watermarks(crtc);
intel_enable_pipe(intel_crtc);
@@ -5057,7 +5063,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
if (intel_crtc->config->has_pch_encoder)
lpt_pch_enable(crtc);
- if (intel_crtc->config->dp_encoder_is_mst)
+ if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
intel_ddi_set_vc_payload_alloc(crtc, true);
assert_vblank_disabled(crtc);
@@ -5159,6 +5165,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
+ bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
if (!intel_crtc->active)
return;
@@ -5179,7 +5186,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
if (intel_crtc->config->dp_encoder_is_mst)
intel_ddi_set_vc_payload_alloc(crtc, false);
- intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
+ if (!is_dsi)
+ intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
if (INTEL_INFO(dev)->gen == 9)
skylake_pfit_update(intel_crtc, 0);
@@ -5188,7 +5196,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
else
MISSING_CASE(INTEL_INFO(dev)->gen);
- intel_ddi_disable_pipe_clock(intel_crtc);
+ if (!is_dsi)
+ intel_ddi_disable_pipe_clock(intel_crtc);
if (intel_crtc->config->has_pch_encoder) {
lpt_disable_pch_transcoder(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index 4813374..326aa6b 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -335,7 +335,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
return 0;
port = intel_ddi_get_encoder_port(intel_encoder);
- if (port == PORT_E) {
+ if ((port == PORT_E) || (port == PORT_INVALID)) {
port = 0;
} else {
parm |= 1 << port;
@@ -356,6 +356,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
break;
case INTEL_OUTPUT_EDP:
+ case INTEL_OUTPUT_DSI:
type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
break;
default:
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v4 07/14] drm/i915/bxt: Program Tx Rx and Dphy clocks
2015-09-18 13:27 ` Jani Nikula
2015-09-21 10:11 ` Shankar, Uma
@ 2015-09-23 17:57 ` Uma Shankar
2015-09-28 13:04 ` Jani Nikula
1 sibling, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-23 17:57 UTC (permalink / raw)
To: intel-gfx; +Cc: shobhit.kumar
From: Shashank Sharma <shashank.sharma@intel.com>
BXT DSI clocks are different than previous platforms. So adding a
new function to program following clocks and dividers:
1. Program variable divider to generate input to Tx clock divider
(Output value must be < 39.5Mhz)
2. Select divide by 2 option to get < 20Mhz for Tx clock
3. Program 8by3 divider to generate Rx clock
v2: Fixed Jani's review comments. Adjusted the Macro definition as
per convention. Simplified the logic for bit definitions for
MIPI PORT A and PORT C in same registers.
v3: Refactored the macros for TX, RX Escape and DPHY clocks as per
Jani's suggestion.
v4: Addressed Jani's review comments.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 62 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dsi_pll.c | 42 +++++++++++++++++++++++
2 files changed, 104 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 57c5dbf..88a16e2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7362,6 +7362,68 @@ enum skl_disp_power_wells {
#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
+/* BXT MIPI clock controls */
+#define BXT_MAX_VAR_OUTPUT_KHZ 39500
+
+#define BXT_MIPI_CLOCK_CTL 0x46090
+#define BXT_MIPI1_DIV_SHIFT 26
+#define BXT_MIPI2_DIV_SHIFT 10
+#define BXT_MIPI_DIV_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
+ BXT_MIPI2_DIV_SHIFT)
+/* Var clock divider to generate TX source. Result must be < 39.5 M */
+#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
+#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
+#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
+ _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
+ BXT_MIPI2_ESCLK_VAR_DIV_MASK)
+
+#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
+ (val << BXT_MIPI_DIV_SHIFT(port))
+/* TX control divider to select actual TX clock output from (8x/var) */
+#define BXT_MIPI1_TX_ESCLK_SHIFT 21
+#define BXT_MIPI2_TX_ESCLK_SHIFT 5
+#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
+ BXT_MIPI2_TX_ESCLK_SHIFT)
+#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
+#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
+#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
+ _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
+ BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
+#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
+ (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
+#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
+ (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
+#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
+ (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
+/* RX control divider to select actual RX clock output from 8x*/
+#define BXT_MIPI1_RX_ESCLK_SHIFT 19
+#define BXT_MIPI2_RX_ESCLK_SHIFT 3
+#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
+ BXT_MIPI2_RX_ESCLK_SHIFT)
+#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
+#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
+#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
+ (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
+ (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
+ (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
+ (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+/* BXT-A WA: Always prog DPHY dividers to 00 */
+#define BXT_MIPI1_DPHY_DIV_SHIFT 16
+#define BXT_MIPI2_DPHY_DIV_SHIFT 0
+#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
+ BXT_MIPI2_DPHY_DIV_SHIFT)
+#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
+#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
+#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
+ (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
+
/* BXT MIPI mode configure */
#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 21a2e37..e62729f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -389,6 +389,42 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
return pclk;
}
+/* Program BXT Mipi clocks and dividers */
+static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
+{
+ u32 tmp;
+ u32 divider;
+ u32 dsi_rate;
+ u32 pll_ratio;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /* Clear old configurations */
+ tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
+ tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
+ tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
+ tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
+
+ /* Get the current DSI rate(actual) */
+ pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
+ BXT_DSI_PLL_RATIO_MASK;
+ dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
+
+ /* Max possible output of clock is 39.5 MHz, program value -1 */
+ divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
+ tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
+
+ /*
+ * Tx escape clock must be as close to 20MHz possible, but should
+ * not exceed it. Hence select divide by 2
+ */
+ tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
+
+ tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
+
+ I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+}
+
static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
@@ -440,6 +476,8 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
u32 val;
DRM_DEBUG_KMS("\n");
@@ -458,6 +496,10 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
return;
}
+ /* Program TX, RX, Dphy clocks */
+ for_each_dsi_port(port, intel_dsi->ports)
+ bxt_dsi_program_clocks(encoder->base.dev, port);
+
/* Enable DSI PLL */
val = I915_READ(BXT_DSI_PLL_ENABLE);
val |= BXT_DSI_PLL_DO_ENABLE;
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v4 11/14] drm/i915/bxt: Modify BXT BLC according to VBT changes
2015-09-18 13:51 ` Jani Nikula
2015-09-21 10:26 ` Shankar, Uma
@ 2015-09-23 17:59 ` Uma Shankar
2015-09-28 13:13 ` Jani Nikula
1 sibling, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-23 17:59 UTC (permalink / raw)
To: intel-gfx; +Cc: shobhit.kumar
From: Sunil Kamath <sunil.kamath@intel.com>
Latest VBT mentions which set of registers will be used for BLC,
as controller number field. Making use of this field in BXT
BLC implementation. Also, the registers are used in case control
pin indicates display DDI. Adding a check for this.
According to Bspec, BLC_PWM_*_2 uses the display utility pin for output.
To use backlight 2, enable the utility pin with mode = PWM
v2: Jani's review comments
addressed
- Add a prefix _ to BXT BLC registers definitions.
- Add "bxt only" comment for u8 controller
- Remove control_pin check for DDI controller
- Check for valid controller values
- Set pipe bits in UTIL_PIN_CTL
- Enable/Disable UTIL_PIN_CTL in enable/disable_backlight()
- If BLC 2 is used, read active_low_pwm from UTIL_PIN polarity
Satheesh's review comment addressed
- If UTIL PIN is already enabled, BIOS would have programmed it. No
need to disable and enable again.
v3: Jani's review comments
- add UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK
- Disable UTIL_PIN if controller 1 is used
- Mask out UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK before enabling
UTIL_PIN
- check valid controller value in intel_bios.c
- add backlight.util_pin_active_low
- disable util pin before enabling
v4: Change for BXT-PO branch:
Stubbed unwanted definition which was existing before
because of DC6 patch.
UTIL_PIN_MODE_PWM (0x1b << 24)
v2: Fixed Jani's review comment.
v3: Split the backight PWM frequency programming into separate patch,
in cases BIOS doesn't initializes it.
v4: Starting afresh and not modifying existing state for backlight, as
per Jani's recommendation.
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 28 +++++++++----
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_panel.c | 76 ++++++++++++++++++++++++++++--------
3 files changed, 81 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 88a16e2..519f764 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3512,17 +3512,29 @@ enum skl_disp_power_wells {
#define UTIL_PIN_CTL 0x48400
#define UTIL_PIN_ENABLE (1 << 31)
+#define UTIL_PIN_PIPE(x) ((x) << 29)
+#define UTIL_PIN_PIPE_MASK (3 << 29)
+#define UTIL_PIN_MODE_PWM (1 << 24)
+#define UTIL_PIN_MODE_MASK (0xf << 24)
+#define UTIL_PIN_POLARITY (1 << 22)
+
/* BXT backlight register definition. */
-#define BXT_BLC_PWM_CTL1 0xC8250
+#define _BXT_BLC_PWM_CTL1 0xC8250
#define BXT_BLC_PWM_ENABLE (1 << 31)
#define BXT_BLC_PWM_POLARITY (1 << 29)
-#define BXT_BLC_PWM_FREQ1 0xC8254
-#define BXT_BLC_PWM_DUTY1 0xC8258
-
-#define BXT_BLC_PWM_CTL2 0xC8350
-#define BXT_BLC_PWM_FREQ2 0xC8354
-#define BXT_BLC_PWM_DUTY2 0xC8358
-
+#define _BXT_BLC_PWM_FREQ1 0xC8254
+#define _BXT_BLC_PWM_DUTY1 0xC8258
+
+#define _BXT_BLC_PWM_CTL2 0xC8350
+#define _BXT_BLC_PWM_FREQ2 0xC8354
+#define _BXT_BLC_PWM_DUTY2 0xC8358
+
+#define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \
+ _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
+#define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \
+ _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
+#define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \
+ _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
#define PCH_GTC_CTL 0xe7000
#define PCH_GTC_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1059283..d8ca075 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -182,7 +182,9 @@ struct intel_panel {
bool enabled;
bool combination_mode; /* gen 2/4 only */
bool active_low_pwm;
+ bool util_pin_active_low; /* bxt+ */
struct backlight_device *device;
+ u8 controller; /* bxt+ only */
} backlight;
void (*backlight_power)(struct intel_connector *, bool enable);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 55aad23..fafbccc 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -539,9 +539,10 @@ static u32 vlv_get_backlight(struct intel_connector *connector)
static u32 bxt_get_backlight(struct intel_connector *connector)
{
struct drm_device *dev = connector->base.dev;
+ struct intel_panel *panel = &connector->panel;
struct drm_i915_private *dev_priv = dev->dev_private;
- return I915_READ(BXT_BLC_PWM_DUTY1);
+ return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
}
static u32 intel_panel_get_backlight(struct intel_connector *connector)
@@ -628,8 +629,9 @@ static void bxt_set_backlight(struct intel_connector *connector, u32 level)
{
struct drm_device *dev = connector->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_panel *panel = &connector->panel;
- I915_WRITE(BXT_BLC_PWM_DUTY1, level);
+ I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
}
static void
@@ -761,12 +763,20 @@ static void bxt_disable_backlight(struct intel_connector *connector)
{
struct drm_device *dev = connector->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- u32 tmp;
+ struct intel_panel *panel = &connector->panel;
+ u32 tmp, val;
intel_panel_actually_set_backlight(connector, 0);
- tmp = I915_READ(BXT_BLC_PWM_CTL1);
- I915_WRITE(BXT_BLC_PWM_CTL1, tmp & ~BXT_BLC_PWM_ENABLE);
+ tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+ tmp & ~BXT_BLC_PWM_ENABLE);
+
+ if (panel->backlight.controller == 1) {
+ val = I915_READ(UTIL_PIN_CTL);
+ val &= ~UTIL_PIN_ENABLE;
+ I915_WRITE(UTIL_PIN_CTL, val);
+ }
}
void intel_panel_disable_backlight(struct intel_connector *connector)
@@ -988,16 +998,31 @@ static void bxt_enable_backlight(struct intel_connector *connector)
struct drm_device *dev = connector->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_panel *panel = &connector->panel;
- u32 pwm_ctl;
+ enum pipe pipe = intel_get_pipe_from_connector(connector);
+ u32 pwm_ctl, val;
+
+ /* To use 2nd set of backlight registers, utility pin has to be
+ * enabled with PWM mode.
+ * The field should only be changed when the utility pin is disabled
+ */
+ if (panel->backlight.controller == 1) {
+ val = 0;
+ if (panel->backlight.util_pin_active_low)
+ val |= UTIL_PIN_POLARITY;
+ I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) |
+ UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
+ }
- pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
+ pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
DRM_DEBUG_KMS("backlight already enabled\n");
pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
- I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+ pwm_ctl);
}
- I915_WRITE(BXT_BLC_PWM_FREQ1, panel->backlight.max);
+ I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
+ panel->backlight.max);
intel_panel_actually_set_backlight(connector, panel->backlight.level);
@@ -1005,9 +1030,10 @@ static void bxt_enable_backlight(struct intel_connector *connector)
if (panel->backlight.active_low_pwm)
pwm_ctl |= BXT_BLC_PWM_POLARITY;
- I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
- POSTING_READ(BXT_BLC_PWM_CTL1);
- I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl | BXT_BLC_PWM_ENABLE);
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
+ POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+ pwm_ctl | BXT_BLC_PWM_ENABLE);
}
void intel_panel_enable_backlight(struct intel_connector *connector)
@@ -1370,12 +1396,28 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
struct intel_panel *panel = &connector->panel;
u32 pwm_ctl, val;
- pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
- panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
+ /*
+ * For BXT hard coding the Backlight controller to 0.
+ * TODO : Read the controller value from VBT and generalize
+ */
+ panel->backlight.controller = 0;
- panel->backlight.max = I915_READ(BXT_BLC_PWM_FREQ1);
- if (!panel->backlight.max)
- return -ENODEV;
+ pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+
+ /* Keeping the check if controller 1 is to be programmed.
+ * This will come into affect once the VBT parsing
+ * is fixed for controller selection, and controller 1 is used
+ * for a prticular display configuration.
+ */
+ if (panel->backlight.controller == 1) {
+ val = I915_READ(UTIL_PIN_CTL);
+ panel->backlight.util_pin_active_low =
+ val & UTIL_PIN_POLARITY;
+ }
+
+ panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
+ panel->backlight.max = I915_READ(
+ BXT_BLC_PWM_FREQ(panel->backlight.controller));
val = bxt_get_backlight(connector);
panel->backlight.level = intel_panel_compute_brightness(connector, val);
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v4 14/14] drm/i915: Added BXT DSI backlight support
2015-09-18 13:37 ` Jani Nikula
2015-09-21 10:22 ` Shankar, Uma
@ 2015-09-23 18:00 ` Uma Shankar
2015-09-24 16:58 ` Ville Syrjälä
1 sibling, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-23 18:00 UTC (permalink / raw)
To: intel-gfx; +Cc: shobhit.kumar
DSI backlight support for bxt is added.
TODO: There is no support for backlight control in drm panel
framework. This will be added as part of VBT version patches
fixing the backlight sequence.
v2: Fixed Jani's review comments from previous patch. Added the
BXT DSI backlight code in this patch. Backlight setup and
enable/disable code for backlight is added in intel_dsi.c.
v3: Rebased on latest drm-nightly. Fixed Jani's review comments.
v4: Making backlight calls generic as per Jani's suggestion.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 08bade2..3e7f796 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -438,6 +438,7 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct intel_connector *intel_connector = intel_dsi->attached_connector;
enum port port;
DRM_DEBUG_KMS("\n");
@@ -458,6 +459,9 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
intel_dsi_port_enable(encoder);
}
+
+ msleep(intel_dsi->backlight_on_delay);
+ intel_panel_enable_backlight(intel_connector);
}
static void intel_dsi_pre_enable(struct intel_encoder *encoder)
@@ -623,10 +627,14 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct intel_connector *intel_connector = intel_dsi->attached_connector;
u32 val;
DRM_DEBUG_KMS("\n");
+ intel_panel_disable_backlight(intel_connector);
+ msleep(intel_dsi->backlight_off_delay);
+
intel_dsi_disable(encoder);
intel_dsi_clear_device_ready(encoder);
@@ -1226,8 +1234,18 @@ void intel_dsi_init(struct drm_device *dev)
intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
- return;
+ /*
+ * Pipe parameter is not used for BXT.
+ * Passing INVALID_PIPE to adher to API requirement.
+ */
+ if (IS_BROXTON(dev))
+ intel_panel_setup_backlight(connector, INVALID_PIPE);
+ else
+ intel_panel_setup_backlight(connector,
+ intel_encoder->crtc_mask == (1 << PIPE_A) ?
+ PIPE_A : PIPE_B);
+ return;
err:
drm_encoder_cleanup(&intel_encoder->base);
kfree(intel_dsi);
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v4 14/14] drm/i915: Added BXT DSI backlight support
2015-09-23 18:00 ` [BXT MIPI PATCH v4 " Uma Shankar
@ 2015-09-24 16:58 ` Ville Syrjälä
2015-09-25 10:15 ` Shankar, Uma
0 siblings, 1 reply; 69+ messages in thread
From: Ville Syrjälä @ 2015-09-24 16:58 UTC (permalink / raw)
To: Uma Shankar; +Cc: shobhit.kumar, intel-gfx
On Wed, Sep 23, 2015 at 11:30:43PM +0530, Uma Shankar wrote:
> DSI backlight support for bxt is added.
>
> TODO: There is no support for backlight control in drm panel
> framework. This will be added as part of VBT version patches
> fixing the backlight sequence.
>
> v2: Fixed Jani's review comments from previous patch. Added the
> BXT DSI backlight code in this patch. Backlight setup and
> enable/disable code for backlight is added in intel_dsi.c.
>
> v3: Rebased on latest drm-nightly. Fixed Jani's review comments.
>
> v4: Making backlight calls generic as per Jani's suggestion.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 20 +++++++++++++++++++-
> 1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 08bade2..3e7f796 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -438,6 +438,7 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + struct intel_connector *intel_connector = intel_dsi->attached_connector;
> enum port port;
>
> DRM_DEBUG_KMS("\n");
> @@ -458,6 +459,9 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
>
> intel_dsi_port_enable(encoder);
> }
> +
> + msleep(intel_dsi->backlight_on_delay);
> + intel_panel_enable_backlight(intel_connector);
> }
>
> static void intel_dsi_pre_enable(struct intel_encoder *encoder)
> @@ -623,10 +627,14 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + struct intel_connector *intel_connector = intel_dsi->attached_connector;
> u32 val;
>
> DRM_DEBUG_KMS("\n");
>
> + intel_panel_disable_backlight(intel_connector);
> + msleep(intel_dsi->backlight_off_delay);
> +
> intel_dsi_disable(encoder);
>
> intel_dsi_clear_device_ready(encoder);
> @@ -1226,8 +1234,18 @@ void intel_dsi_init(struct drm_device *dev)
>
> intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
>
> - return;
> + /*
> + * Pipe parameter is not used for BXT.
> + * Passing INVALID_PIPE to adher to API requirement.
> + */
> + if (IS_BROXTON(dev))
> + intel_panel_setup_backlight(connector, INVALID_PIPE);
> + else
> + intel_panel_setup_backlight(connector,
> + intel_encoder->crtc_mask == (1 << PIPE_A) ?
> + PIPE_A : PIPE_B);
Is this aganst some ancient kernel version? We have
backlight calls in the dsi code already.
>
> + return;
> err:
> drm_encoder_cleanup(&intel_encoder->base);
> kfree(intel_dsi);
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v4 14/14] drm/i915: Added BXT DSI backlight support
2015-09-24 16:58 ` Ville Syrjälä
@ 2015-09-25 10:15 ` Shankar, Uma
0 siblings, 0 replies; 69+ messages in thread
From: Shankar, Uma @ 2015-09-25 10:15 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Kumar, Shobhit, intel-gfx
>-----Original Message-----
>From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>Sent: Thursday, September 24, 2015 10:29 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Kumar, Shobhit
>Subject: Re: [Intel-gfx] [BXT MIPI PATCH v4 14/14] drm/i915: Added BXT DSI
>backlight support
>
>On Wed, Sep 23, 2015 at 11:30:43PM +0530, Uma Shankar wrote:
>> DSI backlight support for bxt is added.
>>
>> TODO: There is no support for backlight control in drm panel
>> framework. This will be added as part of VBT version patches
>> fixing the backlight sequence.
>>
>> v2: Fixed Jani's review comments from previous patch. Added the
>> BXT DSI backlight code in this patch. Backlight setup and
>> enable/disable code for backlight is added in intel_dsi.c.
>>
>> v3: Rebased on latest drm-nightly. Fixed Jani's review comments.
>>
>> v4: Making backlight calls generic as per Jani's suggestion.
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dsi.c | 20 +++++++++++++++++++-
>> 1 file changed, 19 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
>> b/drivers/gpu/drm/i915/intel_dsi.c
>> index 08bade2..3e7f796 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -438,6 +438,7 @@ static void intel_dsi_enable(struct intel_encoder
>*encoder)
>> struct drm_device *dev = encoder->base.dev;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> + struct intel_connector *intel_connector =
>> +intel_dsi->attached_connector;
>> enum port port;
>>
>> DRM_DEBUG_KMS("\n");
>> @@ -458,6 +459,9 @@ static void intel_dsi_enable(struct intel_encoder
>> *encoder)
>>
>> intel_dsi_port_enable(encoder);
>> }
>> +
>> + msleep(intel_dsi->backlight_on_delay);
>> + intel_panel_enable_backlight(intel_connector);
>> }
>>
>> static void intel_dsi_pre_enable(struct intel_encoder *encoder) @@
>> -623,10 +627,14 @@ static void intel_dsi_post_disable(struct
>> intel_encoder *encoder) {
>> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> + struct intel_connector *intel_connector =
>> +intel_dsi->attached_connector;
>> u32 val;
>>
>> DRM_DEBUG_KMS("\n");
>>
>> + intel_panel_disable_backlight(intel_connector);
>> + msleep(intel_dsi->backlight_off_delay);
>> +
>> intel_dsi_disable(encoder);
>>
>> intel_dsi_clear_device_ready(encoder);
>> @@ -1226,8 +1234,18 @@ void intel_dsi_init(struct drm_device *dev)
>>
>> intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
>>
>> - return;
>> + /*
>> + * Pipe parameter is not used for BXT.
>> + * Passing INVALID_PIPE to adher to API requirement.
>> + */
>> + if (IS_BROXTON(dev))
>> + intel_panel_setup_backlight(connector, INVALID_PIPE);
>> + else
>> + intel_panel_setup_backlight(connector,
>> + intel_encoder->crtc_mask == (1 << PIPE_A) ?
>> + PIPE_A : PIPE_B);
>
>Is this aganst some ancient kernel version? We have backlight calls in the dsi
>code already.
>
This support is added recently with Shobhit's "backlight control using CRC PMIC
Based PWM driver" series. This seems to be merged last week. We can drop this patch,
as it is already taken care in nightly branch.
Regards,
Uma Shankar
>> + return;
>> err:
>> drm_encoder_cleanup(&intel_encoder->base);
>> kfree(intel_dsi);
>> --
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Ville Syrjälä
>Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v4 07/14] drm/i915/bxt: Program Tx Rx and Dphy clocks
2015-09-23 17:57 ` [BXT MIPI PATCH v4 " Uma Shankar
@ 2015-09-28 13:04 ` Jani Nikula
0 siblings, 0 replies; 69+ messages in thread
From: Jani Nikula @ 2015-09-28 13:04 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Wed, 23 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> BXT DSI clocks are different than previous platforms. So adding a
> new function to program following clocks and dividers:
> 1. Program variable divider to generate input to Tx clock divider
> (Output value must be < 39.5Mhz)
> 2. Select divide by 2 option to get < 20Mhz for Tx clock
> 3. Program 8by3 divider to generate Rx clock
>
> v2: Fixed Jani's review comments. Adjusted the Macro definition as
> per convention. Simplified the logic for bit definitions for
> MIPI PORT A and PORT C in same registers.
>
> v3: Refactored the macros for TX, RX Escape and DPHY clocks as per
> Jani's suggestion.
>
> v4: Addressed Jani's review comments.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 62 ++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_dsi_pll.c | 42 +++++++++++++++++++++++
> 2 files changed, 104 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 57c5dbf..88a16e2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7362,6 +7362,68 @@ enum skl_disp_power_wells {
>
> #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
>
> +/* BXT MIPI clock controls */
> +#define BXT_MAX_VAR_OUTPUT_KHZ 39500
> +
> +#define BXT_MIPI_CLOCK_CTL 0x46090
> +#define BXT_MIPI1_DIV_SHIFT 26
> +#define BXT_MIPI2_DIV_SHIFT 10
> +#define BXT_MIPI_DIV_SHIFT(port) \
> + _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
> + BXT_MIPI2_DIV_SHIFT)
> +/* Var clock divider to generate TX source. Result must be < 39.5 M */
> +#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
> +#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
> +#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
> + _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
> + BXT_MIPI2_ESCLK_VAR_DIV_MASK)
> +
> +#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
> + (val << BXT_MIPI_DIV_SHIFT(port))
> +/* TX control divider to select actual TX clock output from (8x/var) */
> +#define BXT_MIPI1_TX_ESCLK_SHIFT 21
> +#define BXT_MIPI2_TX_ESCLK_SHIFT 5
> +#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
> + _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
> + BXT_MIPI2_TX_ESCLK_SHIFT)
> +#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
> +#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
> +#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
> + _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
> + BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
> +#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
> + (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> +#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
> + (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> +#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
> + (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> +/* RX control divider to select actual RX clock output from 8x*/
> +#define BXT_MIPI1_RX_ESCLK_SHIFT 19
> +#define BXT_MIPI2_RX_ESCLK_SHIFT 3
> +#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
> + BXT_MIPI2_RX_ESCLK_SHIFT)
> +#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
> +#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
> +#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
> + (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> +#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
> + (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> +#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
> + (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> +#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
> + (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> +/* BXT-A WA: Always prog DPHY dividers to 00 */
> +#define BXT_MIPI1_DPHY_DIV_SHIFT 16
> +#define BXT_MIPI2_DPHY_DIV_SHIFT 0
> +#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
> + _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
> + BXT_MIPI2_DPHY_DIV_SHIFT)
> +#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
> +#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
> +#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
> + (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
> +
> /* BXT MIPI mode configure */
> #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
> #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 21a2e37..e62729f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -389,6 +389,42 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
> return pclk;
> }
>
> +/* Program BXT Mipi clocks and dividers */
> +static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
> +{
> + u32 tmp;
> + u32 divider;
> + u32 dsi_rate;
> + u32 pll_ratio;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + /* Clear old configurations */
> + tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> + tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> + tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
> + tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
> + tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
> +
> + /* Get the current DSI rate(actual) */
> + pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
> + BXT_DSI_PLL_RATIO_MASK;
> + dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
> +
> + /* Max possible output of clock is 39.5 MHz, program value -1 */
> + divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
> + tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
> +
> + /*
> + * Tx escape clock must be as close to 20MHz possible, but should
> + * not exceed it. Hence select divide by 2
> + */
> + tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
> +
> + tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
> +
> + I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> +}
> +
> static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> @@ -440,6 +476,8 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
> static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + enum port port;
> u32 val;
>
> DRM_DEBUG_KMS("\n");
> @@ -458,6 +496,10 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
> return;
> }
>
> + /* Program TX, RX, Dphy clocks */
> + for_each_dsi_port(port, intel_dsi->ports)
> + bxt_dsi_program_clocks(encoder->base.dev, port);
> +
> /* Enable DSI PLL */
> val = I915_READ(BXT_DSI_PLL_ENABLE);
> val |= BXT_DSI_PLL_DO_ENABLE;
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v4 11/14] drm/i915/bxt: Modify BXT BLC according to VBT changes
2015-09-23 17:59 ` [BXT MIPI PATCH v4 " Uma Shankar
@ 2015-09-28 13:13 ` Jani Nikula
2015-09-30 17:04 ` [BXT MIPI PATCH v5 " Uma Shankar
0 siblings, 1 reply; 69+ messages in thread
From: Jani Nikula @ 2015-09-28 13:13 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Wed, 23 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Sunil Kamath <sunil.kamath@intel.com>
>
> Latest VBT mentions which set of registers will be used for BLC,
> as controller number field. Making use of this field in BXT
> BLC implementation. Also, the registers are used in case control
> pin indicates display DDI. Adding a check for this.
> According to Bspec, BLC_PWM_*_2 uses the display utility pin for output.
> To use backlight 2, enable the utility pin with mode = PWM
> v2: Jani's review comments
> addressed
> - Add a prefix _ to BXT BLC registers definitions.
> - Add "bxt only" comment for u8 controller
> - Remove control_pin check for DDI controller
> - Check for valid controller values
> - Set pipe bits in UTIL_PIN_CTL
> - Enable/Disable UTIL_PIN_CTL in enable/disable_backlight()
> - If BLC 2 is used, read active_low_pwm from UTIL_PIN polarity
> Satheesh's review comment addressed
> - If UTIL PIN is already enabled, BIOS would have programmed it. No
> need to disable and enable again.
> v3: Jani's review comments
> - add UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK
> - Disable UTIL_PIN if controller 1 is used
> - Mask out UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK before enabling
> UTIL_PIN
> - check valid controller value in intel_bios.c
> - add backlight.util_pin_active_low
> - disable util pin before enabling
> v4: Change for BXT-PO branch:
> Stubbed unwanted definition which was existing before
> because of DC6 patch.
> UTIL_PIN_MODE_PWM (0x1b << 24)
>
> v2: Fixed Jani's review comment.
>
> v3: Split the backight PWM frequency programming into separate patch,
> in cases BIOS doesn't initializes it.
>
> v4: Starting afresh and not modifying existing state for backlight, as
> per Jani's recommendation.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Sunil Kamath <sunil.kamath@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 28 +++++++++----
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> drivers/gpu/drm/i915/intel_panel.c | 76 ++++++++++++++++++++++++++++--------
> 3 files changed, 81 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 88a16e2..519f764 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3512,17 +3512,29 @@ enum skl_disp_power_wells {
> #define UTIL_PIN_CTL 0x48400
> #define UTIL_PIN_ENABLE (1 << 31)
>
> +#define UTIL_PIN_PIPE(x) ((x) << 29)
> +#define UTIL_PIN_PIPE_MASK (3 << 29)
> +#define UTIL_PIN_MODE_PWM (1 << 24)
> +#define UTIL_PIN_MODE_MASK (0xf << 24)
> +#define UTIL_PIN_POLARITY (1 << 22)
> +
> /* BXT backlight register definition. */
> -#define BXT_BLC_PWM_CTL1 0xC8250
> +#define _BXT_BLC_PWM_CTL1 0xC8250
> #define BXT_BLC_PWM_ENABLE (1 << 31)
> #define BXT_BLC_PWM_POLARITY (1 << 29)
> -#define BXT_BLC_PWM_FREQ1 0xC8254
> -#define BXT_BLC_PWM_DUTY1 0xC8258
> -
> -#define BXT_BLC_PWM_CTL2 0xC8350
> -#define BXT_BLC_PWM_FREQ2 0xC8354
> -#define BXT_BLC_PWM_DUTY2 0xC8358
> -
> +#define _BXT_BLC_PWM_FREQ1 0xC8254
> +#define _BXT_BLC_PWM_DUTY1 0xC8258
> +
> +#define _BXT_BLC_PWM_CTL2 0xC8350
> +#define _BXT_BLC_PWM_FREQ2 0xC8354
> +#define _BXT_BLC_PWM_DUTY2 0xC8358
> +
> +#define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \
> + _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
> +#define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \
> + _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
> +#define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \
> + _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
>
> #define PCH_GTC_CTL 0xe7000
> #define PCH_GTC_ENABLE (1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 1059283..d8ca075 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -182,7 +182,9 @@ struct intel_panel {
> bool enabled;
> bool combination_mode; /* gen 2/4 only */
> bool active_low_pwm;
> + bool util_pin_active_low; /* bxt+ */
> struct backlight_device *device;
> + u8 controller; /* bxt+ only */
> } backlight;
>
> void (*backlight_power)(struct intel_connector *, bool enable);
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 55aad23..fafbccc 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -539,9 +539,10 @@ static u32 vlv_get_backlight(struct intel_connector *connector)
> static u32 bxt_get_backlight(struct intel_connector *connector)
> {
> struct drm_device *dev = connector->base.dev;
> + struct intel_panel *panel = &connector->panel;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - return I915_READ(BXT_BLC_PWM_DUTY1);
> + return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
> }
>
> static u32 intel_panel_get_backlight(struct intel_connector *connector)
> @@ -628,8 +629,9 @@ static void bxt_set_backlight(struct intel_connector *connector, u32 level)
> {
> struct drm_device *dev = connector->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_panel *panel = &connector->panel;
>
> - I915_WRITE(BXT_BLC_PWM_DUTY1, level);
> + I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
> }
>
> static void
> @@ -761,12 +763,20 @@ static void bxt_disable_backlight(struct intel_connector *connector)
> {
> struct drm_device *dev = connector->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - u32 tmp;
> + struct intel_panel *panel = &connector->panel;
> + u32 tmp, val;
>
> intel_panel_actually_set_backlight(connector, 0);
>
> - tmp = I915_READ(BXT_BLC_PWM_CTL1);
> - I915_WRITE(BXT_BLC_PWM_CTL1, tmp & ~BXT_BLC_PWM_ENABLE);
> + tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> + tmp & ~BXT_BLC_PWM_ENABLE);
> +
> + if (panel->backlight.controller == 1) {
> + val = I915_READ(UTIL_PIN_CTL);
> + val &= ~UTIL_PIN_ENABLE;
> + I915_WRITE(UTIL_PIN_CTL, val);
> + }
> }
>
> void intel_panel_disable_backlight(struct intel_connector *connector)
> @@ -988,16 +998,31 @@ static void bxt_enable_backlight(struct intel_connector *connector)
> struct drm_device *dev = connector->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_panel *panel = &connector->panel;
> - u32 pwm_ctl;
> + enum pipe pipe = intel_get_pipe_from_connector(connector);
> + u32 pwm_ctl, val;
> +
> + /* To use 2nd set of backlight registers, utility pin has to be
> + * enabled with PWM mode.
> + * The field should only be changed when the utility pin is disabled
> + */
> + if (panel->backlight.controller == 1) {
Please put back this part from the previous patch:
+ val = I915_READ(UTIL_PIN_CTL);
+ if (val & UTIL_PIN_ENABLE) {
+ DRM_DEBUG_KMS("util pin already enabled\n");
+ val &= ~UTIL_PIN_ENABLE;
+ I915_WRITE(UTIL_PIN_CTL, val);
+ }
And then continue like below.
With that fixes, this is
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> + val = 0;
> + if (panel->backlight.util_pin_active_low)
> + val |= UTIL_PIN_POLARITY;
> + I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) |
> + UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
> + }
>
> - pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
> + pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
> DRM_DEBUG_KMS("backlight already enabled\n");
> pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
> - I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> + pwm_ctl);
> }
>
> - I915_WRITE(BXT_BLC_PWM_FREQ1, panel->backlight.max);
> + I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
> + panel->backlight.max);
>
> intel_panel_actually_set_backlight(connector, panel->backlight.level);
>
> @@ -1005,9 +1030,10 @@ static void bxt_enable_backlight(struct intel_connector *connector)
> if (panel->backlight.active_low_pwm)
> pwm_ctl |= BXT_BLC_PWM_POLARITY;
>
> - I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
> - POSTING_READ(BXT_BLC_PWM_CTL1);
> - I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl | BXT_BLC_PWM_ENABLE);
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
> + POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> + pwm_ctl | BXT_BLC_PWM_ENABLE);
> }
>
> void intel_panel_enable_backlight(struct intel_connector *connector)
> @@ -1370,12 +1396,28 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
> struct intel_panel *panel = &connector->panel;
> u32 pwm_ctl, val;
>
> - pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
> - panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
> + /*
> + * For BXT hard coding the Backlight controller to 0.
> + * TODO : Read the controller value from VBT and generalize
> + */
> + panel->backlight.controller = 0;
>
> - panel->backlight.max = I915_READ(BXT_BLC_PWM_FREQ1);
> - if (!panel->backlight.max)
> - return -ENODEV;
> + pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> +
> + /* Keeping the check if controller 1 is to be programmed.
> + * This will come into affect once the VBT parsing
> + * is fixed for controller selection, and controller 1 is used
> + * for a prticular display configuration.
> + */
> + if (panel->backlight.controller == 1) {
> + val = I915_READ(UTIL_PIN_CTL);
> + panel->backlight.util_pin_active_low =
> + val & UTIL_PIN_POLARITY;
> + }
> +
> + panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
> + panel->backlight.max = I915_READ(
> + BXT_BLC_PWM_FREQ(panel->backlight.controller));
>
> val = bxt_get_backlight(connector);
> panel->backlight.level = intel_panel_compute_brightness(connector, val);
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v4 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-23 17:53 ` [BXT MIPI PATCH v4 " Uma Shankar
@ 2015-09-28 13:28 ` Jani Nikula
2015-09-28 16:57 ` Shankar, Uma
0 siblings, 1 reply; 69+ messages in thread
From: Jani Nikula @ 2015-09-28 13:28 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Wed, 23 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> SKL and BXT qualifies the HAS_DDI() check, and hence haswell
> modeset functions are re-used for modeset sequence. But DDI
> interface doesn't include support for DSI.
> This patch adds:
> 1. cases for DSI encoder, in those modeset functions and allows
> a CRTC modeset
> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
> needs to be done as such in CRTC for DSI encoder, as PLL, clock
> and and transcoder programming will be taken care in encoder's
> pre_enable and pre_pll_enable function.
>
> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
> encoder like DSI for platforms having HAS_DDI as true.
>
> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
> encoder.
>
> v4: WARN_ON for invalid encoder is refactored as per Jani's suggestion.
> Fixed the sequence for pre_pll_enable.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_ddi.c | 21 ++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++------
> drivers/gpu/drm/i915/intel_opregion.c | 3 ++-
> 4 files changed, 38 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fd1de45..78d31c5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -142,6 +142,7 @@ enum plane {
> #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
>
> enum port {
> + PORT_INVALID = -1,
My idea was that you wouldn't add this. Maybe I wasn't clear enough.
> PORT_A = 0,
> PORT_B,
> PORT_C,
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cacb07b..8edb632 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
> } else if (type == INTEL_OUTPUT_ANALOG) {
> *dig_port = NULL;
> *port = PORT_E;
> + } else if (type == INTEL_OUTPUT_DSI) {
> + *dig_port = NULL;
> + *port = PORT_INVALID;
> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
My idea was that you'd only call this function on DDI (i.e. non-DSI)
encoders. So you could do a warn here. Doesn't matter what you set *port
to, it's going to be wrong anyway, and this is only slightly better than
not oopsing on the BUG below.
> } else {
> DRM_ERROR("Invalid DDI encoder type %d\n", type);
> BUG();
> @@ -237,6 +241,15 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
> {
> struct intel_digital_port *dig_port;
> enum port port;
> + int type = intel_encoder->type;
> +
> + if (type == INTEL_OUTPUT_DSI) {
> + port = PORT_INVALID;
> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
> + WARN_ON(1);
> +
> + return port;
> + }
Remove these.
>
> ddi_get_encoder_port(intel_encoder, &dig_port, &port);
>
> @@ -392,6 +405,11 @@ void intel_prepare_ddi(struct drm_device *dev)
>
> ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
>
My idea was that you'd only call this function on DDI (i.e. non-DSI)
encoders. So you'd have to add a check for DSI here.
> + if (port == PORT_INVALID) {
> + WARN_ON(1);
But this warn now makes me think we don't ever get here on with
DSI. Don't warn for normal cases.
> + continue;
> + }
> +
> if (visited[port])
> continue;
>
> @@ -1779,7 +1797,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
> {
> struct drm_crtc *crtc = &intel_crtc->base;
> - struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
> enum port port = intel_ddi_get_encoder_port(intel_encoder);
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b8e0310..ea0f533 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4991,6 +4991,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
> int pipe = intel_crtc->pipe;
>
> WARN_ON(!crtc->state->enable);
> @@ -5023,9 +5024,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> intel_crtc->active = true;
>
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> - for_each_encoder_on_crtc(dev, crtc, encoder)
> + for_each_encoder_on_crtc(dev, crtc, encoder) {
> + if (encoder->pre_pll_enable)
> + encoder->pre_pll_enable(encoder);
> if (encoder->pre_enable)
> encoder->pre_enable(encoder);
> + }
>
> if (intel_crtc->config->has_pch_encoder) {
> intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
> @@ -5033,7 +5037,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> dev_priv->display.fdi_link_train(crtc);
> }
>
> - intel_ddi_enable_pipe_clock(intel_crtc);
> + if (!is_dsi)
> + intel_ddi_enable_pipe_clock(intel_crtc);
>
> if (INTEL_INFO(dev)->gen == 9)
> skylake_pfit_update(intel_crtc, 1);
> @@ -5049,7 +5054,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> intel_crtc_load_lut(crtc);
>
> intel_ddi_set_pipe_settings(crtc);
> - intel_ddi_enable_transcoder_func(crtc);
> + if (!is_dsi)
> + intel_ddi_enable_transcoder_func(crtc);
>
> intel_update_watermarks(crtc);
> intel_enable_pipe(intel_crtc);
> @@ -5057,7 +5063,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->config->has_pch_encoder)
> lpt_pch_enable(crtc);
>
> - if (intel_crtc->config->dp_encoder_is_mst)
> + if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
> intel_ddi_set_vc_payload_alloc(crtc, true);
>
> assert_vblank_disabled(crtc);
> @@ -5159,6 +5165,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>
> if (!intel_crtc->active)
> return;
> @@ -5179,7 +5186,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> if (intel_crtc->config->dp_encoder_is_mst)
> intel_ddi_set_vc_payload_alloc(crtc, false);
>
> - intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
> + if (!is_dsi)
> + intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>
> if (INTEL_INFO(dev)->gen == 9)
> skylake_pfit_update(intel_crtc, 0);
> @@ -5188,7 +5196,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> else
> MISSING_CASE(INTEL_INFO(dev)->gen);
>
> - intel_ddi_disable_pipe_clock(intel_crtc);
> + if (!is_dsi)
> + intel_ddi_disable_pipe_clock(intel_crtc);
>
> if (intel_crtc->config->has_pch_encoder) {
> lpt_disable_pch_transcoder(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
> index 4813374..326aa6b 100644
> --- a/drivers/gpu/drm/i915/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> @@ -335,7 +335,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
> return 0;
>
> port = intel_ddi_get_encoder_port(intel_encoder);
My idea was that you'd only call this function on DDI (i.e. non-DSI)
encoders. So you'd have to add a check for DSI here.
BR,
Jani.
> - if (port == PORT_E) {
> + if ((port == PORT_E) || (port == PORT_INVALID)) {
> port = 0;
> } else {
> parm |= 1 << port;
> @@ -356,6 +356,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
> type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
> break;
> case INTEL_OUTPUT_EDP:
> + case INTEL_OUTPUT_DSI:
> type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
> break;
> default:
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v4 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-28 13:28 ` Jani Nikula
@ 2015-09-28 16:57 ` Shankar, Uma
2015-09-29 7:29 ` Jani Nikula
0 siblings, 1 reply; 69+ messages in thread
From: Shankar, Uma @ 2015-09-28 16:57 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: Kumar, Shobhit
>-----Original Message-----
>From: Jani Nikula [mailto:jani.nikula@linux.intel.com]
>Sent: Monday, September 28, 2015 6:58 PM
>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
>Subject: Re: [BXT MIPI PATCH v4 05/14] drm/i915/bxt: DSI encoder support in
>CRTC modeset
>
>On Wed, 23 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
>> From: Shashank Sharma <shashank.sharma@intel.com>
>>
>> SKL and BXT qualifies the HAS_DDI() check, and hence haswell modeset
>> functions are re-used for modeset sequence. But DDI interface doesn't
>> include support for DSI.
>> This patch adds:
>> 1. cases for DSI encoder, in those modeset functions and allows
>> a CRTC modeset
>> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
>> needs to be done as such in CRTC for DSI encoder, as PLL, clock
>> and and transcoder programming will be taken care in encoder's
>> pre_enable and pre_pll_enable function.
>>
>> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
>> encoder like DSI for platforms having HAS_DDI as true.
>>
>> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
>> encoder.
>>
>> v4: WARN_ON for invalid encoder is refactored as per Jani's suggestion.
>> Fixed the sequence for pre_pll_enable.
>>
>> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> drivers/gpu/drm/i915/intel_ddi.c | 21 ++++++++++++++++++++-
>> drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++------
>> drivers/gpu/drm/i915/intel_opregion.c | 3 ++-
>> 4 files changed, 38 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h index fd1de45..78d31c5 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -142,6 +142,7 @@ enum plane {
>> #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] +
>> (s) + 'A')
>>
>> enum port {
>> + PORT_INVALID = -1,
>
>My idea was that you wouldn't add this. Maybe I wasn't clear enough.
>
>> PORT_A = 0,
>> PORT_B,
>> PORT_C,
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>> b/drivers/gpu/drm/i915/intel_ddi.c
>> index cacb07b..8edb632 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct
>intel_encoder *intel_encoder,
>> } else if (type == INTEL_OUTPUT_ANALOG) {
>> *dig_port = NULL;
>> *port = PORT_E;
>> + } else if (type == INTEL_OUTPUT_DSI) {
>> + *dig_port = NULL;
>> + *port = PORT_INVALID;
>> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
>
>My idea was that you'd only call this function on DDI (i.e. non-DSI) encoders. So
>you could do a warn here. Doesn't matter what you set *port to, it's going to be
>wrong anyway, and this is only slightly better than not oopsing on the BUG
>below.
>
>> } else {
>> DRM_ERROR("Invalid DDI encoder type %d\n", type);
>> BUG();
>> @@ -237,6 +241,15 @@ enum port intel_ddi_get_encoder_port(struct
>> intel_encoder *intel_encoder) {
>> struct intel_digital_port *dig_port;
>> enum port port;
>> + int type = intel_encoder->type;
>> +
>> + if (type == INTEL_OUTPUT_DSI) {
>> + port = PORT_INVALID;
>> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
>> + WARN_ON(1);
>> +
>> + return port;
>> + }
>
>Remove these.
>
intel_ddi_get_encoder_port is the one getting called from multiple locations. This expects an enum to be returned. We could either set the *port in
@@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct
intel_encoder *intel_encoder,
} else if (type == INTEL_OUTPUT_ANALOG) {
*dig_port = NULL;
*port = PORT_E;
+ } else if (type == INTEL_OUTPUT_DSI) {
+ *dig_port = NULL;
+ *port = PORT_INVALID;
+ DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
And let this function return the PORT_INVALID with a WARN. Or we can initialize the port to PORT_INVALID and return that instead. Then I can remove these lines from here.
Also, If we try to avoid this function getting called from various locations, we will again end up to the original problem of spilled over DSI checks at multiple places in code.
Please suggest which ever looks ok.
>>
>> ddi_get_encoder_port(intel_encoder, &dig_port, &port);
>>
>> @@ -392,6 +405,11 @@ void intel_prepare_ddi(struct drm_device *dev)
>>
>> ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
>>
>
>My idea was that you'd only call this function on DDI (i.e. non-DSI) encoders. So
>you'd have to add a check for DSI here.
>
>> + if (port == PORT_INVALID) {
>> + WARN_ON(1);
>
>But this warn now makes me think we don't ever get here on with DSI. Don't
>warn for normal cases.
Yes, you are right. This shouldn't be Warning, just a DSI protection should be fine. Will rectify this.
>> + continue;
>> + }
>> +
>> if (visited[port])
>> continue;
>>
>> @@ -1779,7 +1797,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder
>> *encoder, void intel_ddi_enable_pipe_clock(struct intel_crtc
>> *intel_crtc) {
>> struct drm_crtc *crtc = &intel_crtc->base;
>> - struct drm_i915_private *dev_priv = crtc->dev->dev_private;
>> + struct drm_device *dev = crtc->dev;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
>> enum port port = intel_ddi_get_encoder_port(intel_encoder);
>> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index b8e0310..ea0f533 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -4991,6 +4991,7 @@ static void haswell_crtc_enable(struct drm_crtc
>*crtc)
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> struct intel_encoder *encoder;
>> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>> int pipe = intel_crtc->pipe;
>>
>> WARN_ON(!crtc->state->enable);
>> @@ -5023,9 +5024,12 @@ static void haswell_crtc_enable(struct drm_crtc
>*crtc)
>> intel_crtc->active = true;
>>
>> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>> - for_each_encoder_on_crtc(dev, crtc, encoder)
>> + for_each_encoder_on_crtc(dev, crtc, encoder) {
>> + if (encoder->pre_pll_enable)
>> + encoder->pre_pll_enable(encoder);
>> if (encoder->pre_enable)
>> encoder->pre_enable(encoder);
>> + }
>>
>> if (intel_crtc->config->has_pch_encoder) {
>> intel_set_pch_fifo_underrun_reporting(dev_priv,
>TRANSCODER_A, @@
>> -5033,7 +5037,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>> dev_priv->display.fdi_link_train(crtc);
>> }
>>
>> - intel_ddi_enable_pipe_clock(intel_crtc);
>> + if (!is_dsi)
>> + intel_ddi_enable_pipe_clock(intel_crtc);
>>
>> if (INTEL_INFO(dev)->gen == 9)
>> skylake_pfit_update(intel_crtc, 1); @@ -5049,7 +5054,8 @@
>static
>> void haswell_crtc_enable(struct drm_crtc *crtc)
>> intel_crtc_load_lut(crtc);
>>
>> intel_ddi_set_pipe_settings(crtc);
>> - intel_ddi_enable_transcoder_func(crtc);
>> + if (!is_dsi)
>> + intel_ddi_enable_transcoder_func(crtc);
>>
>> intel_update_watermarks(crtc);
>> intel_enable_pipe(intel_crtc);
>> @@ -5057,7 +5063,7 @@ static void haswell_crtc_enable(struct drm_crtc
>*crtc)
>> if (intel_crtc->config->has_pch_encoder)
>> lpt_pch_enable(crtc);
>>
>> - if (intel_crtc->config->dp_encoder_is_mst)
>> + if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
>> intel_ddi_set_vc_payload_alloc(crtc, true);
>>
>> assert_vblank_disabled(crtc);
>> @@ -5159,6 +5165,7 @@ static void haswell_crtc_disable(struct drm_crtc
>*crtc)
>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> struct intel_encoder *encoder;
>> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>>
>> if (!intel_crtc->active)
>> return;
>> @@ -5179,7 +5186,8 @@ static void haswell_crtc_disable(struct drm_crtc
>*crtc)
>> if (intel_crtc->config->dp_encoder_is_mst)
>> intel_ddi_set_vc_payload_alloc(crtc, false);
>>
>> - intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>> + if (!is_dsi)
>> + intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>>
>> if (INTEL_INFO(dev)->gen == 9)
>> skylake_pfit_update(intel_crtc, 0); @@ -5188,7 +5196,8 @@
>static
>> void haswell_crtc_disable(struct drm_crtc *crtc)
>> else
>> MISSING_CASE(INTEL_INFO(dev)->gen);
>>
>> - intel_ddi_disable_pipe_clock(intel_crtc);
>> + if (!is_dsi)
>> + intel_ddi_disable_pipe_clock(intel_crtc);
>>
>> if (intel_crtc->config->has_pch_encoder) {
>> lpt_disable_pch_transcoder(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
>> b/drivers/gpu/drm/i915/intel_opregion.c
>> index 4813374..326aa6b 100644
>> --- a/drivers/gpu/drm/i915/intel_opregion.c
>> +++ b/drivers/gpu/drm/i915/intel_opregion.c
>> @@ -335,7 +335,7 @@ int intel_opregion_notify_encoder(struct
>intel_encoder *intel_encoder,
>> return 0;
>>
>> port = intel_ddi_get_encoder_port(intel_encoder);
>
>My idea was that you'd only call this function on DDI (i.e. non-DSI) encoders. So
>you'd have to add a check for DSI here.
>
Currently, I have implemented it as all other occurrences of this function. Even if it gets called for DSI,
it will return PORT_INVALID. That case is handled below.
But it would be better to check for DSI and avoid the call and an unnecessary Warning. Will change this.
Please comment if the overall approach looks OK. Will implement accordingly.
Thanks for all the suggestions and comments.
Regards,
Uma Shankar
>BR,
>Jani.
>
>> - if (port == PORT_E) {
>> + if ((port == PORT_E) || (port == PORT_INVALID)) {
>> port = 0;
>> } else {
>> parm |= 1 << port;
>> @@ -356,6 +356,7 @@ int intel_opregion_notify_encoder(struct
>intel_encoder *intel_encoder,
>> type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
>> break;
>> case INTEL_OUTPUT_EDP:
>> + case INTEL_OUTPUT_DSI:
>> type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
>> break;
>> default:
>> --
>> 1.7.9.5
>>
>
>--
>Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v4 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-28 16:57 ` Shankar, Uma
@ 2015-09-29 7:29 ` Jani Nikula
2015-09-30 16:33 ` Shankar, Uma
2015-09-30 17:03 ` [BXT MIPI PATCH v5 " Uma Shankar
0 siblings, 2 replies; 69+ messages in thread
From: Jani Nikula @ 2015-09-29 7:29 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx; +Cc: Kumar, Shobhit
On Mon, 28 Sep 2015, "Shankar, Uma" <uma.shankar@intel.com> wrote:
>>-----Original Message-----
>>From: Jani Nikula [mailto:jani.nikula@linux.intel.com]
>>Sent: Monday, September 28, 2015 6:58 PM
>>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>>Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
>>Subject: Re: [BXT MIPI PATCH v4 05/14] drm/i915/bxt: DSI encoder support in
>>CRTC modeset
>>
>>On Wed, 23 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
>>> From: Shashank Sharma <shashank.sharma@intel.com>
>>>
>>> SKL and BXT qualifies the HAS_DDI() check, and hence haswell modeset
>>> functions are re-used for modeset sequence. But DDI interface doesn't
>>> include support for DSI.
>>> This patch adds:
>>> 1. cases for DSI encoder, in those modeset functions and allows
>>> a CRTC modeset
>>> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
>>> needs to be done as such in CRTC for DSI encoder, as PLL, clock
>>> and and transcoder programming will be taken care in encoder's
>>> pre_enable and pre_pll_enable function.
>>>
>>> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
>>> encoder like DSI for platforms having HAS_DDI as true.
>>>
>>> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
>>> encoder.
>>>
>>> v4: WARN_ON for invalid encoder is refactored as per Jani's suggestion.
>>> Fixed the sequence for pre_pll_enable.
>>>
>>> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
>>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>>> drivers/gpu/drm/i915/intel_ddi.c | 21 ++++++++++++++++++++-
>>> drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++------
>>> drivers/gpu/drm/i915/intel_opregion.c | 3 ++-
>>> 4 files changed, 38 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>> b/drivers/gpu/drm/i915/i915_drv.h index fd1de45..78d31c5 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -142,6 +142,7 @@ enum plane {
>>> #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] +
>>> (s) + 'A')
>>>
>>> enum port {
>>> + PORT_INVALID = -1,
>>
>>My idea was that you wouldn't add this. Maybe I wasn't clear enough.
>>
>>> PORT_A = 0,
>>> PORT_B,
>>> PORT_C,
>>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>>> b/drivers/gpu/drm/i915/intel_ddi.c
>>> index cacb07b..8edb632 100644
>>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>>> @@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct
>>intel_encoder *intel_encoder,
>>> } else if (type == INTEL_OUTPUT_ANALOG) {
>>> *dig_port = NULL;
>>> *port = PORT_E;
>>> + } else if (type == INTEL_OUTPUT_DSI) {
>>> + *dig_port = NULL;
>>> + *port = PORT_INVALID;
>>> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
>>
>>My idea was that you'd only call this function on DDI (i.e. non-DSI) encoders. So
>>you could do a warn here. Doesn't matter what you set *port to, it's going to be
>>wrong anyway, and this is only slightly better than not oopsing on the BUG
>>below.
>>
>>> } else {
>>> DRM_ERROR("Invalid DDI encoder type %d\n", type);
>>> BUG();
>>> @@ -237,6 +241,15 @@ enum port intel_ddi_get_encoder_port(struct
>>> intel_encoder *intel_encoder) {
>>> struct intel_digital_port *dig_port;
>>> enum port port;
>>> + int type = intel_encoder->type;
>>> +
>>> + if (type == INTEL_OUTPUT_DSI) {
>>> + port = PORT_INVALID;
>>> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
>>> + WARN_ON(1);
>>> +
>>> + return port;
>>> + }
>>
>>Remove these.
>>
>
> intel_ddi_get_encoder_port is the one getting called from multiple locations. This expects an enum to be returned. We could either set the *port in
>
> @@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct
> intel_encoder *intel_encoder,
> } else if (type == INTEL_OUTPUT_ANALOG) {
> *dig_port = NULL;
> *port = PORT_E;
> + } else if (type == INTEL_OUTPUT_DSI) {
> + *dig_port = NULL;
> + *port = PORT_INVALID;
> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
>
> And let this function return the PORT_INVALID with a WARN. Or we can initialize the port to PORT_INVALID and return that instead. Then I can remove these lines from here.
> Also, If we try to avoid this function getting called from various locations, we will again end up to the original problem of spilled over DSI checks at multiple places in code.
>
> Please suggest which ever looks ok.
I just sent two patches [1][2] to modify ddi_get_encoder_port a
little. Rebase on top, and don't modify ddi_get_encoder_port() or
intel_ddi_get_encoder_port() at all. Just make sure you don't call the
functions for DSI. No need to add PORT_INVALID either.
BR,
Jani.
[1] http://mid.gmane.org/1443511466-8017-1-git-send-email-jani.nikula@intel.com
[2] http://mid.gmane.org/1443511466-8017-2-git-send-email-jani.nikula@intel.com
>
>>>
>>> ddi_get_encoder_port(intel_encoder, &dig_port, &port);
>>>
>>> @@ -392,6 +405,11 @@ void intel_prepare_ddi(struct drm_device *dev)
>>>
>>> ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
>>>
>>
>>My idea was that you'd only call this function on DDI (i.e. non-DSI) encoders. So
>>you'd have to add a check for DSI here.
>>
>>> + if (port == PORT_INVALID) {
>>> + WARN_ON(1);
>>
>>But this warn now makes me think we don't ever get here on with DSI. Don't
>>warn for normal cases.
>
> Yes, you are right. This shouldn't be Warning, just a DSI protection should be fine. Will rectify this.
>
>>> + continue;
>>> + }
>>> +
>>> if (visited[port])
>>> continue;
>>>
>>> @@ -1779,7 +1797,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder
>>> *encoder, void intel_ddi_enable_pipe_clock(struct intel_crtc
>>> *intel_crtc) {
>>> struct drm_crtc *crtc = &intel_crtc->base;
>>> - struct drm_i915_private *dev_priv = crtc->dev->dev_private;
>>> + struct drm_device *dev = crtc->dev;
>>> + struct drm_i915_private *dev_priv = dev->dev_private;
>>> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
>>> enum port port = intel_ddi_get_encoder_port(intel_encoder);
>>> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>>> b/drivers/gpu/drm/i915/intel_display.c
>>> index b8e0310..ea0f533 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -4991,6 +4991,7 @@ static void haswell_crtc_enable(struct drm_crtc
>>*crtc)
>>> struct drm_i915_private *dev_priv = dev->dev_private;
>>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>> struct intel_encoder *encoder;
>>> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>>> int pipe = intel_crtc->pipe;
>>>
>>> WARN_ON(!crtc->state->enable);
>>> @@ -5023,9 +5024,12 @@ static void haswell_crtc_enable(struct drm_crtc
>>*crtc)
>>> intel_crtc->active = true;
>>>
>>> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>>> - for_each_encoder_on_crtc(dev, crtc, encoder)
>>> + for_each_encoder_on_crtc(dev, crtc, encoder) {
>>> + if (encoder->pre_pll_enable)
>>> + encoder->pre_pll_enable(encoder);
>>> if (encoder->pre_enable)
>>> encoder->pre_enable(encoder);
>>> + }
>>>
>>> if (intel_crtc->config->has_pch_encoder) {
>>> intel_set_pch_fifo_underrun_reporting(dev_priv,
>>TRANSCODER_A, @@
>>> -5033,7 +5037,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>>> dev_priv->display.fdi_link_train(crtc);
>>> }
>>>
>>> - intel_ddi_enable_pipe_clock(intel_crtc);
>>> + if (!is_dsi)
>>> + intel_ddi_enable_pipe_clock(intel_crtc);
>>>
>>> if (INTEL_INFO(dev)->gen == 9)
>>> skylake_pfit_update(intel_crtc, 1); @@ -5049,7 +5054,8 @@
>>static
>>> void haswell_crtc_enable(struct drm_crtc *crtc)
>>> intel_crtc_load_lut(crtc);
>>>
>>> intel_ddi_set_pipe_settings(crtc);
>>> - intel_ddi_enable_transcoder_func(crtc);
>>> + if (!is_dsi)
>>> + intel_ddi_enable_transcoder_func(crtc);
>>>
>>> intel_update_watermarks(crtc);
>>> intel_enable_pipe(intel_crtc);
>>> @@ -5057,7 +5063,7 @@ static void haswell_crtc_enable(struct drm_crtc
>>*crtc)
>>> if (intel_crtc->config->has_pch_encoder)
>>> lpt_pch_enable(crtc);
>>>
>>> - if (intel_crtc->config->dp_encoder_is_mst)
>>> + if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
>>> intel_ddi_set_vc_payload_alloc(crtc, true);
>>>
>>> assert_vblank_disabled(crtc);
>>> @@ -5159,6 +5165,7 @@ static void haswell_crtc_disable(struct drm_crtc
>>*crtc)
>>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>> struct intel_encoder *encoder;
>>> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>>> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>>>
>>> if (!intel_crtc->active)
>>> return;
>>> @@ -5179,7 +5186,8 @@ static void haswell_crtc_disable(struct drm_crtc
>>*crtc)
>>> if (intel_crtc->config->dp_encoder_is_mst)
>>> intel_ddi_set_vc_payload_alloc(crtc, false);
>>>
>>> - intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>>> + if (!is_dsi)
>>> + intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>>>
>>> if (INTEL_INFO(dev)->gen == 9)
>>> skylake_pfit_update(intel_crtc, 0); @@ -5188,7 +5196,8 @@
>>static
>>> void haswell_crtc_disable(struct drm_crtc *crtc)
>>> else
>>> MISSING_CASE(INTEL_INFO(dev)->gen);
>>>
>>> - intel_ddi_disable_pipe_clock(intel_crtc);
>>> + if (!is_dsi)
>>> + intel_ddi_disable_pipe_clock(intel_crtc);
>>>
>>> if (intel_crtc->config->has_pch_encoder) {
>>> lpt_disable_pch_transcoder(dev_priv);
>>> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
>>> b/drivers/gpu/drm/i915/intel_opregion.c
>>> index 4813374..326aa6b 100644
>>> --- a/drivers/gpu/drm/i915/intel_opregion.c
>>> +++ b/drivers/gpu/drm/i915/intel_opregion.c
>>> @@ -335,7 +335,7 @@ int intel_opregion_notify_encoder(struct
>>intel_encoder *intel_encoder,
>>> return 0;
>>>
>>> port = intel_ddi_get_encoder_port(intel_encoder);
>>
>>My idea was that you'd only call this function on DDI (i.e. non-DSI) encoders. So
>>you'd have to add a check for DSI here.
>>
>
> Currently, I have implemented it as all other occurrences of this function. Even if it gets called for DSI,
> it will return PORT_INVALID. That case is handled below.
>
> But it would be better to check for DSI and avoid the call and an unnecessary Warning. Will change this.
>
> Please comment if the overall approach looks OK. Will implement accordingly.
>
> Thanks for all the suggestions and comments.
>
> Regards,
> Uma Shankar
>
>>BR,
>>Jani.
>>
>>> - if (port == PORT_E) {
>>> + if ((port == PORT_E) || (port == PORT_INVALID)) {
>>> port = 0;
>>> } else {
>>> parm |= 1 << port;
>>> @@ -356,6 +356,7 @@ int intel_opregion_notify_encoder(struct
>>intel_encoder *intel_encoder,
>>> type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
>>> break;
>>> case INTEL_OUTPUT_EDP:
>>> + case INTEL_OUTPUT_DSI:
>>> type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
>>> break;
>>> default:
>>> --
>>> 1.7.9.5
>>>
>>
>>--
>>Jani Nikula, Intel Open Source Technology Center
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v4 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-29 7:29 ` Jani Nikula
@ 2015-09-30 16:33 ` Shankar, Uma
2015-10-01 9:56 ` Jani Nikula
2015-09-30 17:03 ` [BXT MIPI PATCH v5 " Uma Shankar
1 sibling, 1 reply; 69+ messages in thread
From: Shankar, Uma @ 2015-09-30 16:33 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: Kumar, Shobhit
>-----Original Message-----
>From: Jani Nikula [mailto:jani.nikula@linux.intel.com]
>Sent: Tuesday, September 29, 2015 12:59 PM
>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank
>Subject: RE: [BXT MIPI PATCH v4 05/14] drm/i915/bxt: DSI encoder support in
>CRTC modeset
>
>On Mon, 28 Sep 2015, "Shankar, Uma" <uma.shankar@intel.com> wrote:
>>>-----Original Message-----
>>>From: Jani Nikula [mailto:jani.nikula@linux.intel.com]
>>>Sent: Monday, September 28, 2015 6:58 PM
>>>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>>>Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
>>>Subject: Re: [BXT MIPI PATCH v4 05/14] drm/i915/bxt: DSI encoder
>>>support in CRTC modeset
>>>
>>>On Wed, 23 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
>>>> From: Shashank Sharma <shashank.sharma@intel.com>
>>>>
>>>> SKL and BXT qualifies the HAS_DDI() check, and hence haswell modeset
>>>> functions are re-used for modeset sequence. But DDI interface
>>>> doesn't include support for DSI.
>>>> This patch adds:
>>>> 1. cases for DSI encoder, in those modeset functions and allows
>>>> a CRTC modeset
>>>> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
>>>> needs to be done as such in CRTC for DSI encoder, as PLL, clock
>>>> and and transcoder programming will be taken care in encoder's
>>>> pre_enable and pre_pll_enable function.
>>>>
>>>> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
>>>> encoder like DSI for platforms having HAS_DDI as true.
>>>>
>>>> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
>>>> encoder.
>>>>
>>>> v4: WARN_ON for invalid encoder is refactored as per Jani's suggestion.
>>>> Fixed the sequence for pre_pll_enable.
>>>>
>>>> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
>>>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>>>> drivers/gpu/drm/i915/intel_ddi.c | 21 ++++++++++++++++++++-
>>>> drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++------
>>>> drivers/gpu/drm/i915/intel_opregion.c | 3 ++-
>>>> 4 files changed, 38 insertions(+), 8 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>>> b/drivers/gpu/drm/i915/i915_drv.h index fd1de45..78d31c5 100644
>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>> @@ -142,6 +142,7 @@ enum plane {
>>>> #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)]
>>>> +
>>>> (s) + 'A')
>>>>
>>>> enum port {
>>>> + PORT_INVALID = -1,
>>>
>>>My idea was that you wouldn't add this. Maybe I wasn't clear enough.
>>>
>>>> PORT_A = 0,
>>>> PORT_B,
>>>> PORT_C,
>>>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>>>> b/drivers/gpu/drm/i915/intel_ddi.c
>>>> index cacb07b..8edb632 100644
>>>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>>>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>>>> @@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct
>>>intel_encoder *intel_encoder,
>>>> } else if (type == INTEL_OUTPUT_ANALOG) {
>>>> *dig_port = NULL;
>>>> *port = PORT_E;
>>>> + } else if (type == INTEL_OUTPUT_DSI) {
>>>> + *dig_port = NULL;
>>>> + *port = PORT_INVALID;
>>>> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
>>>
>>>My idea was that you'd only call this function on DDI (i.e. non-DSI)
>>>encoders. So you could do a warn here. Doesn't matter what you set
>>>*port to, it's going to be wrong anyway, and this is only slightly
>>>better than not oopsing on the BUG below.
>>>
>>>> } else {
>>>> DRM_ERROR("Invalid DDI encoder type %d\n", type);
>>>> BUG();
>>>> @@ -237,6 +241,15 @@ enum port intel_ddi_get_encoder_port(struct
>>>> intel_encoder *intel_encoder) {
>>>> struct intel_digital_port *dig_port;
>>>> enum port port;
>>>> + int type = intel_encoder->type;
>>>> +
>>>> + if (type == INTEL_OUTPUT_DSI) {
>>>> + port = PORT_INVALID;
>>>> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
>>>> + WARN_ON(1);
>>>> +
>>>> + return port;
>>>> + }
>>>
>>>Remove these.
>>>
>>
>> intel_ddi_get_encoder_port is the one getting called from multiple
>> locations. This expects an enum to be returned. We could either set
>> the *port in
>>
>> @@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct
>> intel_encoder *intel_encoder,
>> } else if (type == INTEL_OUTPUT_ANALOG) {
>> *dig_port = NULL;
>> *port = PORT_E;
>> + } else if (type == INTEL_OUTPUT_DSI) {
>> + *dig_port = NULL;
>> + *port = PORT_INVALID;
>> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
>>
>> And let this function return the PORT_INVALID with a WARN. Or we can
>initialize the port to PORT_INVALID and return that instead. Then I can remove
>these lines from here.
>> Also, If we try to avoid this function getting called from various locations, we
>will again end up to the original problem of spilled over DSI checks at multiple
>places in code.
>>
>> Please suggest which ever looks ok.
>
>I just sent two patches [1][2] to modify ddi_get_encoder_port a little. Rebase on
>top, and don't modify ddi_get_encoder_port() or
>intel_ddi_get_encoder_port() at all. Just make sure you don't call the functions
>for DSI. No need to add PORT_INVALID either.
>
>BR,
>Jani.
>
Thanks Jani. I will rebase and re-submit. Personally I feel this will be best approach as it will avoid the call itself.
However, only flip side is protection at multiple places in code for DSI.
Regards,
Uma Shankar
>[1] http://mid.gmane.org/1443511466-8017-1-git-send-email-
>jani.nikula@intel.com
>[2] http://mid.gmane.org/1443511466-8017-2-git-send-email-
>jani.nikula@intel.com
>
>>
>>>>
>>>> ddi_get_encoder_port(intel_encoder, &dig_port, &port);
>>>>
>>>> @@ -392,6 +405,11 @@ void intel_prepare_ddi(struct drm_device *dev)
>>>>
>>>> ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
>>>>
>>>
>>>My idea was that you'd only call this function on DDI (i.e. non-DSI)
>>>encoders. So you'd have to add a check for DSI here.
>>>
>>>> + if (port == PORT_INVALID) {
>>>> + WARN_ON(1);
>>>
>>>But this warn now makes me think we don't ever get here on with DSI.
>>>Don't warn for normal cases.
>>
>> Yes, you are right. This shouldn't be Warning, just a DSI protection should be
>fine. Will rectify this.
>>
>>>> + continue;
>>>> + }
>>>> +
>>>> if (visited[port])
>>>> continue;
>>>>
>>>> @@ -1779,7 +1797,8 @@ bool intel_ddi_get_hw_state(struct
>>>> intel_encoder *encoder, void intel_ddi_enable_pipe_clock(struct
>>>> intel_crtc
>>>> *intel_crtc) {
>>>> struct drm_crtc *crtc = &intel_crtc->base;
>>>> - struct drm_i915_private *dev_priv = crtc->dev->dev_private;
>>>> + struct drm_device *dev = crtc->dev;
>>>> + struct drm_i915_private *dev_priv = dev->dev_private;
>>>> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
>>>> enum port port = intel_ddi_get_encoder_port(intel_encoder);
>>>> enum transcoder cpu_transcoder =
>>>> intel_crtc->config->cpu_transcoder;
>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>>>> b/drivers/gpu/drm/i915/intel_display.c
>>>> index b8e0310..ea0f533 100644
>>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>>> @@ -4991,6 +4991,7 @@ static void haswell_crtc_enable(struct
>>>> drm_crtc
>>>*crtc)
>>>> struct drm_i915_private *dev_priv = dev->dev_private;
>>>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>>> struct intel_encoder *encoder;
>>>> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>>>> int pipe = intel_crtc->pipe;
>>>>
>>>> WARN_ON(!crtc->state->enable);
>>>> @@ -5023,9 +5024,12 @@ static void haswell_crtc_enable(struct
>>>> drm_crtc
>>>*crtc)
>>>> intel_crtc->active = true;
>>>>
>>>> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>>>> - for_each_encoder_on_crtc(dev, crtc, encoder)
>>>> + for_each_encoder_on_crtc(dev, crtc, encoder) {
>>>> + if (encoder->pre_pll_enable)
>>>> + encoder->pre_pll_enable(encoder);
>>>> if (encoder->pre_enable)
>>>> encoder->pre_enable(encoder);
>>>> + }
>>>>
>>>> if (intel_crtc->config->has_pch_encoder) {
>>>> intel_set_pch_fifo_underrun_reporting(dev_priv,
>>>TRANSCODER_A, @@
>>>> -5033,7 +5037,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>>>> dev_priv->display.fdi_link_train(crtc);
>>>> }
>>>>
>>>> - intel_ddi_enable_pipe_clock(intel_crtc);
>>>> + if (!is_dsi)
>>>> + intel_ddi_enable_pipe_clock(intel_crtc);
>>>>
>>>> if (INTEL_INFO(dev)->gen == 9)
>>>> skylake_pfit_update(intel_crtc, 1); @@ -5049,7 +5054,8 @@
>>>static
>>>> void haswell_crtc_enable(struct drm_crtc *crtc)
>>>> intel_crtc_load_lut(crtc);
>>>>
>>>> intel_ddi_set_pipe_settings(crtc);
>>>> - intel_ddi_enable_transcoder_func(crtc);
>>>> + if (!is_dsi)
>>>> + intel_ddi_enable_transcoder_func(crtc);
>>>>
>>>> intel_update_watermarks(crtc);
>>>> intel_enable_pipe(intel_crtc);
>>>> @@ -5057,7 +5063,7 @@ static void haswell_crtc_enable(struct
>>>> drm_crtc
>>>*crtc)
>>>> if (intel_crtc->config->has_pch_encoder)
>>>> lpt_pch_enable(crtc);
>>>>
>>>> - if (intel_crtc->config->dp_encoder_is_mst)
>>>> + if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
>>>> intel_ddi_set_vc_payload_alloc(crtc, true);
>>>>
>>>> assert_vblank_disabled(crtc);
>>>> @@ -5159,6 +5165,7 @@ static void haswell_crtc_disable(struct
>>>> drm_crtc
>>>*crtc)
>>>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>>> struct intel_encoder *encoder;
>>>> enum transcoder cpu_transcoder =
>>>> intel_crtc->config->cpu_transcoder;
>>>> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>>>>
>>>> if (!intel_crtc->active)
>>>> return;
>>>> @@ -5179,7 +5186,8 @@ static void haswell_crtc_disable(struct
>>>> drm_crtc
>>>*crtc)
>>>> if (intel_crtc->config->dp_encoder_is_mst)
>>>> intel_ddi_set_vc_payload_alloc(crtc, false);
>>>>
>>>> - intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>>>> + if (!is_dsi)
>>>> + intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>>>>
>>>> if (INTEL_INFO(dev)->gen == 9)
>>>> skylake_pfit_update(intel_crtc, 0); @@ -5188,7 +5196,8 @@
>>>static
>>>> void haswell_crtc_disable(struct drm_crtc *crtc)
>>>> else
>>>> MISSING_CASE(INTEL_INFO(dev)->gen);
>>>>
>>>> - intel_ddi_disable_pipe_clock(intel_crtc);
>>>> + if (!is_dsi)
>>>> + intel_ddi_disable_pipe_clock(intel_crtc);
>>>>
>>>> if (intel_crtc->config->has_pch_encoder) {
>>>> lpt_disable_pch_transcoder(dev_priv);
>>>> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
>>>> b/drivers/gpu/drm/i915/intel_opregion.c
>>>> index 4813374..326aa6b 100644
>>>> --- a/drivers/gpu/drm/i915/intel_opregion.c
>>>> +++ b/drivers/gpu/drm/i915/intel_opregion.c
>>>> @@ -335,7 +335,7 @@ int intel_opregion_notify_encoder(struct
>>>intel_encoder *intel_encoder,
>>>> return 0;
>>>>
>>>> port = intel_ddi_get_encoder_port(intel_encoder);
>>>
>>>My idea was that you'd only call this function on DDI (i.e. non-DSI)
>>>encoders. So you'd have to add a check for DSI here.
>>>
>>
>> Currently, I have implemented it as all other occurrences of this
>> function. Even if it gets called for DSI, it will return PORT_INVALID. That case is
>handled below.
>>
>> But it would be better to check for DSI and avoid the call and an unnecessary
>Warning. Will change this.
>>
>> Please comment if the overall approach looks OK. Will implement accordingly.
>>
>> Thanks for all the suggestions and comments.
>>
>> Regards,
>> Uma Shankar
>>
>>>BR,
>>>Jani.
>>>
>>>> - if (port == PORT_E) {
>>>> + if ((port == PORT_E) || (port == PORT_INVALID)) {
>>>> port = 0;
>>>> } else {
>>>> parm |= 1 << port;
>>>> @@ -356,6 +356,7 @@ int intel_opregion_notify_encoder(struct
>>>intel_encoder *intel_encoder,
>>>> type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
>>>> break;
>>>> case INTEL_OUTPUT_EDP:
>>>> + case INTEL_OUTPUT_DSI:
>>>> type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
>>>> break;
>>>> default:
>>>> --
>>>> 1.7.9.5
>>>>
>>>
>>>--
>>>Jani Nikula, Intel Open Source Technology Center
>
>--
>Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v5 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-29 7:29 ` Jani Nikula
2015-09-30 16:33 ` Shankar, Uma
@ 2015-09-30 17:03 ` Uma Shankar
2015-10-01 9:54 ` Jani Nikula
1 sibling, 1 reply; 69+ messages in thread
From: Uma Shankar @ 2015-09-30 17:03 UTC (permalink / raw)
To: intel-gfx; +Cc: shobhit.kumar
From: Shashank Sharma <shashank.sharma@intel.com>
SKL and BXT qualifies the HAS_DDI() check, and hence haswell
modeset functions are re-used for modeset sequence. But DDI
interface doesn't include support for DSI.
This patch adds:
1. cases for DSI encoder, in those modeset functions and allows
a CRTC modeset
2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
needs to be done as such in CRTC for DSI encoder, as PLL, clock
and and transcoder programming will be taken care in encoder's
pre_enable and pre_pll_enable function.
v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
encoder like DSI for platforms having HAS_DDI as true.
v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
encoder.
v4: WARN_ON for invalid encoder is refactored as per Jani's suggestion.
Fixed the sequence for pre_pll_enable.
v5: Protected DDI code paths in case of DSI encoder calls.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 83 ++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_display.c | 21 ++++++---
drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++-
drivers/gpu/drm/i915/intel_opregion.c | 9 +++-
5 files changed, 101 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fd1de45..f97a2a2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2482,6 +2482,7 @@ struct drm_i915_cmd_table {
INTEL_INFO(dev)->gen >= 9)
#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
+#define has_encoder_ddi(type) ((type) == (INTEL_OUTPUT_DSI) ? 0 : 1)
#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cacb07b..4abc13d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -390,8 +390,10 @@ void intel_prepare_ddi(struct drm_device *dev)
enum port port;
bool supports_hdmi;
- ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
+ if (intel_encoder->type == INTEL_OUTPUT_DSI)
+ continue;
+ ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
if (visited[port])
continue;
@@ -977,8 +979,16 @@ static void bxt_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
- enum port port = intel_ddi_get_encoder_port(encoder);
- uint32_t dpll = port;
+ enum port port;
+ uint32_t dpll;
+
+ if (!has_encoder_ddi(encoder->type)) {
+ DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
+ return;
+ }
+
+ port = intel_ddi_get_encoder_port(encoder);
+ dpll = port;
pipe_config->port_clock =
bxt_calc_pll_link(dev_priv, dpll);
@@ -1568,10 +1578,16 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
enum pipe pipe = intel_crtc->pipe;
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
- enum port port = intel_ddi_get_encoder_port(intel_encoder);
+ enum port port;
int type = intel_encoder->type;
uint32_t temp;
+ if (!has_encoder_ddi(type)) {
+ DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
+ return;
+ }
+
+ port = intel_ddi_get_encoder_port(intel_encoder);
/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
temp = TRANS_DDI_FUNC_ENABLE;
temp |= TRANS_DDI_SELECT_PORT(port);
@@ -1678,12 +1694,18 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *intel_encoder = intel_connector->encoder;
int type = intel_connector->base.connector_type;
- enum port port = intel_ddi_get_encoder_port(intel_encoder);
+ enum port port;
enum pipe pipe = 0;
enum transcoder cpu_transcoder;
enum intel_display_power_domain power_domain;
uint32_t tmp;
+ if (!has_encoder_ddi(type)) {
+ DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
+ return false;
+ }
+
+ port = intel_ddi_get_encoder_port(intel_encoder);
power_domain = intel_display_port_power_domain(intel_encoder);
if (!intel_display_power_is_enabled(dev_priv, power_domain))
return false;
@@ -1725,11 +1747,17 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
{
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- enum port port = intel_ddi_get_encoder_port(encoder);
+ enum port port;
enum intel_display_power_domain power_domain;
u32 tmp;
int i;
+ if (!has_encoder_ddi(encoder->type)) {
+ DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
+ return false;
+ }
+
+ port = intel_ddi_get_encoder_port(encoder);
power_domain = intel_display_port_power_domain(encoder);
if (!intel_display_power_is_enabled(dev_priv, power_domain))
return false;
@@ -1779,11 +1807,18 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
{
struct drm_crtc *crtc = &intel_crtc->base;
- struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
- enum port port = intel_ddi_get_encoder_port(intel_encoder);
+ enum port port;
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
+ if (!has_encoder_ddi(intel_encoder->type)) {
+ DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
+ return;
+ }
+
+ port = intel_ddi_get_encoder_port(intel_encoder);
if (cpu_transcoder != TRANSCODER_EDP)
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
TRANS_CLK_SEL_PORT(port));
@@ -1866,10 +1901,16 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
- enum port port = intel_ddi_get_encoder_port(intel_encoder);
+ enum port port;
int type = intel_encoder->type;
int hdmi_level;
+ if (!has_encoder_ddi(type)) {
+ DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
+ return;
+ }
+
+ port = intel_ddi_get_encoder_port(intel_encoder);
if (type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
intel_edp_panel_on(intel_dp);
@@ -1942,11 +1983,17 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
struct drm_encoder *encoder = &intel_encoder->base;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- enum port port = intel_ddi_get_encoder_port(intel_encoder);
+ enum port port;
int type = intel_encoder->type;
uint32_t val;
bool wait = false;
+ if (!has_encoder_ddi(type)) {
+ DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
+ return;
+ }
+
+ port = intel_ddi_get_encoder_port(intel_encoder);
val = I915_READ(DDI_BUF_CTL(port));
if (val & DDI_BUF_CTL_ENABLE) {
val &= ~DDI_BUF_CTL_ENABLE;
@@ -1983,9 +2030,15 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- enum port port = intel_ddi_get_encoder_port(intel_encoder);
+ enum port port;
int type = intel_encoder->type;
+ if (!has_encoder_ddi(type)) {
+ DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
+ return;
+ }
+
+ port = intel_ddi_get_encoder_port(intel_encoder);
if (type == INTEL_OUTPUT_HDMI) {
struct intel_digital_port *intel_dig_port =
enc_to_dig_port(encoder);
@@ -2729,8 +2782,14 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
int type = encoder->type;
- int port = intel_ddi_get_encoder_port(encoder);
+ int port;
+
+ if (!has_encoder_ddi(type)) {
+ DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
+ return false;
+ }
+ port = intel_ddi_get_encoder_port(encoder);
WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
if (port == PORT_A)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b8e0310..ea0f533 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4991,6 +4991,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
+ bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
int pipe = intel_crtc->pipe;
WARN_ON(!crtc->state->enable);
@@ -5023,9 +5024,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_crtc->active = true;
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- for_each_encoder_on_crtc(dev, crtc, encoder)
+ for_each_encoder_on_crtc(dev, crtc, encoder) {
+ if (encoder->pre_pll_enable)
+ encoder->pre_pll_enable(encoder);
if (encoder->pre_enable)
encoder->pre_enable(encoder);
+ }
if (intel_crtc->config->has_pch_encoder) {
intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
@@ -5033,7 +5037,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
dev_priv->display.fdi_link_train(crtc);
}
- intel_ddi_enable_pipe_clock(intel_crtc);
+ if (!is_dsi)
+ intel_ddi_enable_pipe_clock(intel_crtc);
if (INTEL_INFO(dev)->gen == 9)
skylake_pfit_update(intel_crtc, 1);
@@ -5049,7 +5054,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_crtc_load_lut(crtc);
intel_ddi_set_pipe_settings(crtc);
- intel_ddi_enable_transcoder_func(crtc);
+ if (!is_dsi)
+ intel_ddi_enable_transcoder_func(crtc);
intel_update_watermarks(crtc);
intel_enable_pipe(intel_crtc);
@@ -5057,7 +5063,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
if (intel_crtc->config->has_pch_encoder)
lpt_pch_enable(crtc);
- if (intel_crtc->config->dp_encoder_is_mst)
+ if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
intel_ddi_set_vc_payload_alloc(crtc, true);
assert_vblank_disabled(crtc);
@@ -5159,6 +5165,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
+ bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
if (!intel_crtc->active)
return;
@@ -5179,7 +5186,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
if (intel_crtc->config->dp_encoder_is_mst)
intel_ddi_set_vc_payload_alloc(crtc, false);
- intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
+ if (!is_dsi)
+ intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
if (INTEL_INFO(dev)->gen == 9)
skylake_pfit_update(intel_crtc, 0);
@@ -5188,7 +5196,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
else
MISSING_CASE(INTEL_INFO(dev)->gen);
- intel_ddi_disable_pipe_clock(intel_crtc);
+ if (!is_dsi)
+ intel_ddi_disable_pipe_clock(intel_crtc);
if (intel_crtc->config->has_pch_encoder) {
lpt_disable_pch_transcoder(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 600afdb..00327bc 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -172,8 +172,14 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
intel_mst->port = found->port;
if (intel_dp->active_mst_links == 0) {
- enum port port = intel_ddi_get_encoder_port(encoder);
+ enum port port;
+ if (!has_encoder_ddi(encoder->type)) {
+ DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
+ return;
+ }
+
+ port = intel_ddi_get_encoder_port(encoder);
/* FIXME: add support for SKL */
if (INTEL_INFO(dev)->gen < 9)
I915_WRITE(PORT_CLK_SEL(port),
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index 4813374..64b8bcd 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -334,8 +334,12 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
if (!HAS_DDI(dev))
return 0;
- port = intel_ddi_get_encoder_port(intel_encoder);
- if (port == PORT_E) {
+ if (!has_encoder_ddi(type))
+ port = 0;
+ else
+ port = intel_ddi_get_encoder_port(intel_encoder);
+
+ if (port == PORT_E) {
port = 0;
} else {
parm |= 1 << port;
@@ -356,6 +360,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
break;
case INTEL_OUTPUT_EDP:
+ case INTEL_OUTPUT_DSI:
type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
break;
default:
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v5 11/14] drm/i915/bxt: Modify BXT BLC according to VBT changes
2015-09-28 13:13 ` Jani Nikula
@ 2015-09-30 17:04 ` Uma Shankar
2015-10-01 10:16 ` Jani Nikula
2015-10-02 12:58 ` Daniel Vetter
0 siblings, 2 replies; 69+ messages in thread
From: Uma Shankar @ 2015-09-30 17:04 UTC (permalink / raw)
To: intel-gfx; +Cc: shobhit.kumar
From: Sunil Kamath <sunil.kamath@intel.com>
Latest VBT mentions which set of registers will be used for BLC,
as controller number field. Making use of this field in BXT
BLC implementation. Also, the registers are used in case control
pin indicates display DDI. Adding a check for this.
According to Bspec, BLC_PWM_*_2 uses the display utility pin for output.
To use backlight 2, enable the utility pin with mode = PWM
v2: Jani's review comments
addressed
- Add a prefix _ to BXT BLC registers definitions.
- Add "bxt only" comment for u8 controller
- Remove control_pin check for DDI controller
- Check for valid controller values
- Set pipe bits in UTIL_PIN_CTL
- Enable/Disable UTIL_PIN_CTL in enable/disable_backlight()
- If BLC 2 is used, read active_low_pwm from UTIL_PIN polarity
Satheesh's review comment addressed
- If UTIL PIN is already enabled, BIOS would have programmed it. No
need to disable and enable again.
v3: Jani's review comments
- add UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK
- Disable UTIL_PIN if controller 1 is used
- Mask out UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK before enabling
UTIL_PIN
- check valid controller value in intel_bios.c
- add backlight.util_pin_active_low
- disable util pin before enabling
v4: Change for BXT-PO branch:
Stubbed unwanted definition which was existing before
because of DC6 patch.
UTIL_PIN_MODE_PWM (0x1b << 24)
v2: Fixed Jani's review comment.
v3: Split the backight PWM frequency programming into separate patch,
in cases BIOS doesn't initializes it.
v4: Starting afresh and not modifying existing state for backlight, as
per Jani's recommendation.
v5: Fixed Jani's review comment wrt util pin enable
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++----
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_panel.c | 83 ++++++++++++++++++++++++++++--------
3 files changed, 88 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 88a16e2..519f764 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3512,17 +3512,29 @@ enum skl_disp_power_wells {
#define UTIL_PIN_CTL 0x48400
#define UTIL_PIN_ENABLE (1 << 31)
+#define UTIL_PIN_PIPE(x) ((x) << 29)
+#define UTIL_PIN_PIPE_MASK (3 << 29)
+#define UTIL_PIN_MODE_PWM (1 << 24)
+#define UTIL_PIN_MODE_MASK (0xf << 24)
+#define UTIL_PIN_POLARITY (1 << 22)
+
/* BXT backlight register definition. */
-#define BXT_BLC_PWM_CTL1 0xC8250
+#define _BXT_BLC_PWM_CTL1 0xC8250
#define BXT_BLC_PWM_ENABLE (1 << 31)
#define BXT_BLC_PWM_POLARITY (1 << 29)
-#define BXT_BLC_PWM_FREQ1 0xC8254
-#define BXT_BLC_PWM_DUTY1 0xC8258
-
-#define BXT_BLC_PWM_CTL2 0xC8350
-#define BXT_BLC_PWM_FREQ2 0xC8354
-#define BXT_BLC_PWM_DUTY2 0xC8358
-
+#define _BXT_BLC_PWM_FREQ1 0xC8254
+#define _BXT_BLC_PWM_DUTY1 0xC8258
+
+#define _BXT_BLC_PWM_CTL2 0xC8350
+#define _BXT_BLC_PWM_FREQ2 0xC8354
+#define _BXT_BLC_PWM_DUTY2 0xC8358
+
+#define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \
+ _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
+#define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \
+ _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
+#define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \
+ _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
#define PCH_GTC_CTL 0xe7000
#define PCH_GTC_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1059283..d8ca075 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -182,7 +182,9 @@ struct intel_panel {
bool enabled;
bool combination_mode; /* gen 2/4 only */
bool active_low_pwm;
+ bool util_pin_active_low; /* bxt+ */
struct backlight_device *device;
+ u8 controller; /* bxt+ only */
} backlight;
void (*backlight_power)(struct intel_connector *, bool enable);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 55aad23..0d21715 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -539,9 +539,10 @@ static u32 vlv_get_backlight(struct intel_connector *connector)
static u32 bxt_get_backlight(struct intel_connector *connector)
{
struct drm_device *dev = connector->base.dev;
+ struct intel_panel *panel = &connector->panel;
struct drm_i915_private *dev_priv = dev->dev_private;
- return I915_READ(BXT_BLC_PWM_DUTY1);
+ return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
}
static u32 intel_panel_get_backlight(struct intel_connector *connector)
@@ -628,8 +629,9 @@ static void bxt_set_backlight(struct intel_connector *connector, u32 level)
{
struct drm_device *dev = connector->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_panel *panel = &connector->panel;
- I915_WRITE(BXT_BLC_PWM_DUTY1, level);
+ I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
}
static void
@@ -761,12 +763,20 @@ static void bxt_disable_backlight(struct intel_connector *connector)
{
struct drm_device *dev = connector->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- u32 tmp;
+ struct intel_panel *panel = &connector->panel;
+ u32 tmp, val;
intel_panel_actually_set_backlight(connector, 0);
- tmp = I915_READ(BXT_BLC_PWM_CTL1);
- I915_WRITE(BXT_BLC_PWM_CTL1, tmp & ~BXT_BLC_PWM_ENABLE);
+ tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+ tmp & ~BXT_BLC_PWM_ENABLE);
+
+ if (panel->backlight.controller == 1) {
+ val = I915_READ(UTIL_PIN_CTL);
+ val &= ~UTIL_PIN_ENABLE;
+ I915_WRITE(UTIL_PIN_CTL, val);
+ }
}
void intel_panel_disable_backlight(struct intel_connector *connector)
@@ -988,16 +998,38 @@ static void bxt_enable_backlight(struct intel_connector *connector)
struct drm_device *dev = connector->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_panel *panel = &connector->panel;
- u32 pwm_ctl;
+ enum pipe pipe = intel_get_pipe_from_connector(connector);
+ u32 pwm_ctl, val;
+
+ /* To use 2nd set of backlight registers, utility pin has to be
+ * enabled with PWM mode.
+ * The field should only be changed when the utility pin is disabled
+ */
+ if (panel->backlight.controller == 1) {
+ val = I915_READ(UTIL_PIN_CTL);
+ if (val & UTIL_PIN_ENABLE) {
+ DRM_DEBUG_KMS("util pin already enabled\n");
+ val &= ~UTIL_PIN_ENABLE;
+ I915_WRITE(UTIL_PIN_CTL, val);
+ }
- pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
+ val = 0;
+ if (panel->backlight.util_pin_active_low)
+ val |= UTIL_PIN_POLARITY;
+ I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) |
+ UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
+ }
+
+ pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
DRM_DEBUG_KMS("backlight already enabled\n");
pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
- I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+ pwm_ctl);
}
- I915_WRITE(BXT_BLC_PWM_FREQ1, panel->backlight.max);
+ I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
+ panel->backlight.max);
intel_panel_actually_set_backlight(connector, panel->backlight.level);
@@ -1005,9 +1037,10 @@ static void bxt_enable_backlight(struct intel_connector *connector)
if (panel->backlight.active_low_pwm)
pwm_ctl |= BXT_BLC_PWM_POLARITY;
- I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
- POSTING_READ(BXT_BLC_PWM_CTL1);
- I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl | BXT_BLC_PWM_ENABLE);
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
+ POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+ pwm_ctl | BXT_BLC_PWM_ENABLE);
}
void intel_panel_enable_backlight(struct intel_connector *connector)
@@ -1370,12 +1403,28 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
struct intel_panel *panel = &connector->panel;
u32 pwm_ctl, val;
- pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
- panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
+ /*
+ * For BXT hard coding the Backlight controller to 0.
+ * TODO : Read the controller value from VBT and generalize
+ */
+ panel->backlight.controller = 0;
- panel->backlight.max = I915_READ(BXT_BLC_PWM_FREQ1);
- if (!panel->backlight.max)
- return -ENODEV;
+ pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+
+ /* Keeping the check if controller 1 is to be programmed.
+ * This will come into affect once the VBT parsing
+ * is fixed for controller selection, and controller 1 is used
+ * for a prticular display configuration.
+ */
+ if (panel->backlight.controller == 1) {
+ val = I915_READ(UTIL_PIN_CTL);
+ panel->backlight.util_pin_active_low =
+ val & UTIL_PIN_POLARITY;
+ }
+
+ panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
+ panel->backlight.max = I915_READ(
+ BXT_BLC_PWM_FREQ(panel->backlight.controller));
val = bxt_get_backlight(connector);
panel->backlight.level = intel_panel_compute_brightness(connector, val);
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v5 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-30 17:03 ` [BXT MIPI PATCH v5 " Uma Shankar
@ 2015-10-01 9:54 ` Jani Nikula
2015-10-01 16:22 ` Shankar, Uma
2015-10-01 16:53 ` Uma Shankar
0 siblings, 2 replies; 69+ messages in thread
From: Jani Nikula @ 2015-10-01 9:54 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Wed, 30 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> SKL and BXT qualifies the HAS_DDI() check, and hence haswell
> modeset functions are re-used for modeset sequence. But DDI
> interface doesn't include support for DSI.
> This patch adds:
> 1. cases for DSI encoder, in those modeset functions and allows
> a CRTC modeset
> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
> needs to be done as such in CRTC for DSI encoder, as PLL, clock
> and and transcoder programming will be taken care in encoder's
> pre_enable and pre_pll_enable function.
>
> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
> encoder like DSI for platforms having HAS_DDI as true.
>
> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
> encoder.
>
> v4: WARN_ON for invalid encoder is refactored as per Jani's suggestion.
> Fixed the sequence for pre_pll_enable.
>
> v5: Protected DDI code paths in case of DSI encoder calls.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_ddi.c | 83 ++++++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_display.c | 21 ++++++---
> drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++-
> drivers/gpu/drm/i915/intel_opregion.c | 9 +++-
> 5 files changed, 101 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fd1de45..f97a2a2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2482,6 +2482,7 @@ struct drm_i915_cmd_table {
> INTEL_INFO(dev)->gen >= 9)
>
> #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
> +#define has_encoder_ddi(type) ((type) == (INTEL_OUTPUT_DSI) ? 0 : 1)
Drop this change.
> #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
> #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
> IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cacb07b..4abc13d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -390,8 +390,10 @@ void intel_prepare_ddi(struct drm_device *dev)
> enum port port;
> bool supports_hdmi;
>
> - ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
> + if (intel_encoder->type == INTEL_OUTPUT_DSI)
> + continue;
>
This is good.
> + ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
> if (visited[port])
> continue;
>
> @@ -977,8 +979,16 @@ static void bxt_ddi_clock_get(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> - enum port port = intel_ddi_get_encoder_port(encoder);
> - uint32_t dpll = port;
> + enum port port;
> + uint32_t dpll;
> +
> + if (!has_encoder_ddi(encoder->type)) {
> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
> + return;
> + }
> +
> + port = intel_ddi_get_encoder_port(encoder);
> + dpll = port;
No. Drop this change.
Ask yourself, is it okay to call this function (bxt_ddi_clock_get) if
the encoder type is DSI.
No, it's not. We should not be here, at all, if encoder is DSI.
We have modified ddi_get_encoder_port (and therefore
intel_ddi_get_encoder_port) to emit a big warning if that function is
called on a DSI encoder.
So don't make those extra checks. We'll catch the bugs with the warning
in ddi_get_encoder_port. We'll fix the code paths, and move on.
We don't care if the function goes on and does something stupid because
we called it with the wrong preconditions. Similarly, we don't check
for, say, IS_GEN2() in DDI code, because that should not have
happened. The bug is somewhere else.
Now, there *are* valid code paths which will be called if encoder is
DSI. In those cases, we need to handle DSI gracefully and not call
ddi_get_encoder_port. For example intel_prepare_ddi above and
intel_opregion_notify_encoder below.
>
> pipe_config->port_clock =
> bxt_calc_pll_link(dev_priv, dpll);
> @@ -1568,10 +1578,16 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
> struct drm_i915_private *dev_priv = dev->dev_private;
> enum pipe pipe = intel_crtc->pipe;
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> - enum port port = intel_ddi_get_encoder_port(intel_encoder);
> + enum port port;
> int type = intel_encoder->type;
> uint32_t temp;
>
> + if (!has_encoder_ddi(type)) {
> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
> + return;
> + }
> +
> + port = intel_ddi_get_encoder_port(intel_encoder);
Drop this change.
> /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
> temp = TRANS_DDI_FUNC_ENABLE;
> temp |= TRANS_DDI_SELECT_PORT(port);
> @@ -1678,12 +1694,18 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_encoder *intel_encoder = intel_connector->encoder;
> int type = intel_connector->base.connector_type;
> - enum port port = intel_ddi_get_encoder_port(intel_encoder);
> + enum port port;
> enum pipe pipe = 0;
> enum transcoder cpu_transcoder;
> enum intel_display_power_domain power_domain;
> uint32_t tmp;
>
> + if (!has_encoder_ddi(type)) {
> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
> + return false;
> + }
> +
> + port = intel_ddi_get_encoder_port(intel_encoder);
Drop this change.
> power_domain = intel_display_port_power_domain(intel_encoder);
> if (!intel_display_power_is_enabled(dev_priv, power_domain))
> return false;
> @@ -1725,11 +1747,17 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> {
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - enum port port = intel_ddi_get_encoder_port(encoder);
> + enum port port;
> enum intel_display_power_domain power_domain;
> u32 tmp;
> int i;
>
> + if (!has_encoder_ddi(encoder->type)) {
> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
> + return false;
> + }
> +
> + port = intel_ddi_get_encoder_port(encoder);
Drop this change.
> power_domain = intel_display_port_power_domain(encoder);
> if (!intel_display_power_is_enabled(dev_priv, power_domain))
> return false;
> @@ -1779,11 +1807,18 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
> {
> struct drm_crtc *crtc = &intel_crtc->base;
> - struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
> - enum port port = intel_ddi_get_encoder_port(intel_encoder);
> + enum port port;
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>
> + if (!has_encoder_ddi(intel_encoder->type)) {
> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
> + return;
> + }
> +
> + port = intel_ddi_get_encoder_port(intel_encoder);
Drop this change.
> if (cpu_transcoder != TRANSCODER_EDP)
> I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> TRANS_CLK_SEL_PORT(port));
> @@ -1866,10 +1901,16 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
> struct drm_device *dev = encoder->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
> - enum port port = intel_ddi_get_encoder_port(intel_encoder);
> + enum port port;
> int type = intel_encoder->type;
> int hdmi_level;
>
> + if (!has_encoder_ddi(type)) {
> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
> + return;
> + }
> +
> + port = intel_ddi_get_encoder_port(intel_encoder);
Drop this change.
> if (type == INTEL_OUTPUT_EDP) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> intel_edp_panel_on(intel_dp);
> @@ -1942,11 +1983,17 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
> struct drm_encoder *encoder = &intel_encoder->base;
> struct drm_device *dev = encoder->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - enum port port = intel_ddi_get_encoder_port(intel_encoder);
> + enum port port;
> int type = intel_encoder->type;
> uint32_t val;
> bool wait = false;
>
> + if (!has_encoder_ddi(type)) {
> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
> + return;
> + }
> +
> + port = intel_ddi_get_encoder_port(intel_encoder);
Drop this change.
> val = I915_READ(DDI_BUF_CTL(port));
> if (val & DDI_BUF_CTL_ENABLE) {
> val &= ~DDI_BUF_CTL_ENABLE;
> @@ -1983,9 +2030,15 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct drm_device *dev = encoder->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - enum port port = intel_ddi_get_encoder_port(intel_encoder);
> + enum port port;
> int type = intel_encoder->type;
>
> + if (!has_encoder_ddi(type)) {
> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
> + return;
> + }
> +
> + port = intel_ddi_get_encoder_port(intel_encoder);
Drop this change.
> if (type == INTEL_OUTPUT_HDMI) {
> struct intel_digital_port *intel_dig_port =
> enc_to_dig_port(encoder);
> @@ -2729,8 +2782,14 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> int type = encoder->type;
> - int port = intel_ddi_get_encoder_port(encoder);
> + int port;
> +
> + if (!has_encoder_ddi(type)) {
> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
> + return false;
> + }
>
> + port = intel_ddi_get_encoder_port(encoder);
Drop this change.
> WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
>
> if (port == PORT_A)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b8e0310..ea0f533 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4991,6 +4991,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
> int pipe = intel_crtc->pipe;
>
> WARN_ON(!crtc->state->enable);
> @@ -5023,9 +5024,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> intel_crtc->active = true;
>
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> - for_each_encoder_on_crtc(dev, crtc, encoder)
> + for_each_encoder_on_crtc(dev, crtc, encoder) {
> + if (encoder->pre_pll_enable)
> + encoder->pre_pll_enable(encoder);
> if (encoder->pre_enable)
> encoder->pre_enable(encoder);
> + }
>
> if (intel_crtc->config->has_pch_encoder) {
> intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
> @@ -5033,7 +5037,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> dev_priv->display.fdi_link_train(crtc);
> }
>
> - intel_ddi_enable_pipe_clock(intel_crtc);
> + if (!is_dsi)
> + intel_ddi_enable_pipe_clock(intel_crtc);
>
> if (INTEL_INFO(dev)->gen == 9)
> skylake_pfit_update(intel_crtc, 1);
> @@ -5049,7 +5054,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> intel_crtc_load_lut(crtc);
>
> intel_ddi_set_pipe_settings(crtc);
> - intel_ddi_enable_transcoder_func(crtc);
> + if (!is_dsi)
> + intel_ddi_enable_transcoder_func(crtc);
>
> intel_update_watermarks(crtc);
> intel_enable_pipe(intel_crtc);
> @@ -5057,7 +5063,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->config->has_pch_encoder)
> lpt_pch_enable(crtc);
>
> - if (intel_crtc->config->dp_encoder_is_mst)
> + if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
> intel_ddi_set_vc_payload_alloc(crtc, true);
>
> assert_vblank_disabled(crtc);
> @@ -5159,6 +5165,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>
> if (!intel_crtc->active)
> return;
> @@ -5179,7 +5186,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> if (intel_crtc->config->dp_encoder_is_mst)
> intel_ddi_set_vc_payload_alloc(crtc, false);
>
> - intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
> + if (!is_dsi)
> + intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>
> if (INTEL_INFO(dev)->gen == 9)
> skylake_pfit_update(intel_crtc, 0);
> @@ -5188,7 +5196,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> else
> MISSING_CASE(INTEL_INFO(dev)->gen);
>
> - intel_ddi_disable_pipe_clock(intel_crtc);
> + if (!is_dsi)
> + intel_ddi_disable_pipe_clock(intel_crtc);
>
> if (intel_crtc->config->has_pch_encoder) {
> lpt_disable_pch_transcoder(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 600afdb..00327bc 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -172,8 +172,14 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
> intel_mst->port = found->port;
>
> if (intel_dp->active_mst_links == 0) {
> - enum port port = intel_ddi_get_encoder_port(encoder);
> + enum port port;
>
> + if (!has_encoder_ddi(encoder->type)) {
> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
> + return;
> + }
> +
> + port = intel_ddi_get_encoder_port(encoder);
Drop this change.
> /* FIXME: add support for SKL */
> if (INTEL_INFO(dev)->gen < 9)
> I915_WRITE(PORT_CLK_SEL(port),
> diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
> index 4813374..64b8bcd 100644
> --- a/drivers/gpu/drm/i915/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> @@ -334,8 +334,12 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
> if (!HAS_DDI(dev))
> return 0;
>
> - port = intel_ddi_get_encoder_port(intel_encoder);
> - if (port == PORT_E) {
> + if (!has_encoder_ddi(type))
This is good, but don't add extra wrapper (has_encoder_ddi) for the
encode type check.
> + port = 0;
> + else
> + port = intel_ddi_get_encoder_port(intel_encoder);
> +
> + if (port == PORT_E) {
> port = 0;
> } else {
> parm |= 1 << port;
> @@ -356,6 +360,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
> type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
> break;
> case INTEL_OUTPUT_EDP:
> + case INTEL_OUTPUT_DSI:
> type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
> break;
> default:
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v4 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-09-30 16:33 ` Shankar, Uma
@ 2015-10-01 9:56 ` Jani Nikula
0 siblings, 0 replies; 69+ messages in thread
From: Jani Nikula @ 2015-10-01 9:56 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx; +Cc: Kumar, Shobhit
On Wed, 30 Sep 2015, "Shankar, Uma" <uma.shankar@intel.com> wrote:
>>-----Original Message-----
>>From: Jani Nikula [mailto:jani.nikula@linux.intel.com]
>>Sent: Tuesday, September 29, 2015 12:59 PM
>>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>>Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank
>>Subject: RE: [BXT MIPI PATCH v4 05/14] drm/i915/bxt: DSI encoder support in
>>CRTC modeset
>>
>>I just sent two patches [1][2] to modify ddi_get_encoder_port a
>>little. Rebase on top, and don't modify ddi_get_encoder_port() or
>>intel_ddi_get_encoder_port() at all. Just make sure you don't call the
>>functions for DSI. No need to add PORT_INVALID either.
>>
>>BR,
>>Jani.
>>
>
> Thanks Jani. I will rebase and re-submit. Personally I feel this will
> be best approach as it will avoid the call itself. However, only flip
> side is protection at multiple places in code for DSI.
As I explain in my review, it is not necessary to add those checks
everywhere.
BR,
Jani.
>>[1] http://mid.gmane.org/1443511466-8017-1-git-send-email-
>>jani.nikula@intel.com
>>[2] http://mid.gmane.org/1443511466-8017-2-git-send-email-
>>jani.nikula@intel.com
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v5 11/14] drm/i915/bxt: Modify BXT BLC according to VBT changes
2015-09-30 17:04 ` [BXT MIPI PATCH v5 " Uma Shankar
@ 2015-10-01 10:16 ` Jani Nikula
2015-10-02 12:58 ` Daniel Vetter
1 sibling, 0 replies; 69+ messages in thread
From: Jani Nikula @ 2015-10-01 10:16 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Wed, 30 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Sunil Kamath <sunil.kamath@intel.com>
>
> Latest VBT mentions which set of registers will be used for BLC,
> as controller number field. Making use of this field in BXT
> BLC implementation. Also, the registers are used in case control
> pin indicates display DDI. Adding a check for this.
> According to Bspec, BLC_PWM_*_2 uses the display utility pin for output.
> To use backlight 2, enable the utility pin with mode = PWM
> v2: Jani's review comments
> addressed
> - Add a prefix _ to BXT BLC registers definitions.
> - Add "bxt only" comment for u8 controller
> - Remove control_pin check for DDI controller
> - Check for valid controller values
> - Set pipe bits in UTIL_PIN_CTL
> - Enable/Disable UTIL_PIN_CTL in enable/disable_backlight()
> - If BLC 2 is used, read active_low_pwm from UTIL_PIN polarity
> Satheesh's review comment addressed
> - If UTIL PIN is already enabled, BIOS would have programmed it. No
> need to disable and enable again.
> v3: Jani's review comments
> - add UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK
> - Disable UTIL_PIN if controller 1 is used
> - Mask out UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK before enabling
> UTIL_PIN
> - check valid controller value in intel_bios.c
> - add backlight.util_pin_active_low
> - disable util pin before enabling
> v4: Change for BXT-PO branch:
> Stubbed unwanted definition which was existing before
> because of DC6 patch.
> UTIL_PIN_MODE_PWM (0x1b << 24)
>
> v2: Fixed Jani's review comment.
>
> v3: Split the backight PWM frequency programming into separate patch,
> in cases BIOS doesn't initializes it.
>
> v4: Starting afresh and not modifying existing state for backlight, as
> per Jani's recommendation.
>
> v5: Fixed Jani's review comment wrt util pin enable
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Sunil Kamath <sunil.kamath@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++----
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> drivers/gpu/drm/i915/intel_panel.c | 83 ++++++++++++++++++++++++++++--------
> 3 files changed, 88 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 88a16e2..519f764 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3512,17 +3512,29 @@ enum skl_disp_power_wells {
> #define UTIL_PIN_CTL 0x48400
> #define UTIL_PIN_ENABLE (1 << 31)
>
> +#define UTIL_PIN_PIPE(x) ((x) << 29)
> +#define UTIL_PIN_PIPE_MASK (3 << 29)
> +#define UTIL_PIN_MODE_PWM (1 << 24)
> +#define UTIL_PIN_MODE_MASK (0xf << 24)
> +#define UTIL_PIN_POLARITY (1 << 22)
> +
> /* BXT backlight register definition. */
> -#define BXT_BLC_PWM_CTL1 0xC8250
> +#define _BXT_BLC_PWM_CTL1 0xC8250
> #define BXT_BLC_PWM_ENABLE (1 << 31)
> #define BXT_BLC_PWM_POLARITY (1 << 29)
> -#define BXT_BLC_PWM_FREQ1 0xC8254
> -#define BXT_BLC_PWM_DUTY1 0xC8258
> -
> -#define BXT_BLC_PWM_CTL2 0xC8350
> -#define BXT_BLC_PWM_FREQ2 0xC8354
> -#define BXT_BLC_PWM_DUTY2 0xC8358
> -
> +#define _BXT_BLC_PWM_FREQ1 0xC8254
> +#define _BXT_BLC_PWM_DUTY1 0xC8258
> +
> +#define _BXT_BLC_PWM_CTL2 0xC8350
> +#define _BXT_BLC_PWM_FREQ2 0xC8354
> +#define _BXT_BLC_PWM_DUTY2 0xC8358
> +
> +#define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \
> + _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
> +#define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \
> + _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
> +#define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \
> + _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
>
> #define PCH_GTC_CTL 0xe7000
> #define PCH_GTC_ENABLE (1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 1059283..d8ca075 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -182,7 +182,9 @@ struct intel_panel {
> bool enabled;
> bool combination_mode; /* gen 2/4 only */
> bool active_low_pwm;
> + bool util_pin_active_low; /* bxt+ */
> struct backlight_device *device;
> + u8 controller; /* bxt+ only */
> } backlight;
>
> void (*backlight_power)(struct intel_connector *, bool enable);
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 55aad23..0d21715 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -539,9 +539,10 @@ static u32 vlv_get_backlight(struct intel_connector *connector)
> static u32 bxt_get_backlight(struct intel_connector *connector)
> {
> struct drm_device *dev = connector->base.dev;
> + struct intel_panel *panel = &connector->panel;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - return I915_READ(BXT_BLC_PWM_DUTY1);
> + return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
> }
>
> static u32 intel_panel_get_backlight(struct intel_connector *connector)
> @@ -628,8 +629,9 @@ static void bxt_set_backlight(struct intel_connector *connector, u32 level)
> {
> struct drm_device *dev = connector->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_panel *panel = &connector->panel;
>
> - I915_WRITE(BXT_BLC_PWM_DUTY1, level);
> + I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
> }
>
> static void
> @@ -761,12 +763,20 @@ static void bxt_disable_backlight(struct intel_connector *connector)
> {
> struct drm_device *dev = connector->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - u32 tmp;
> + struct intel_panel *panel = &connector->panel;
> + u32 tmp, val;
>
> intel_panel_actually_set_backlight(connector, 0);
>
> - tmp = I915_READ(BXT_BLC_PWM_CTL1);
> - I915_WRITE(BXT_BLC_PWM_CTL1, tmp & ~BXT_BLC_PWM_ENABLE);
> + tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> + tmp & ~BXT_BLC_PWM_ENABLE);
> +
> + if (panel->backlight.controller == 1) {
> + val = I915_READ(UTIL_PIN_CTL);
> + val &= ~UTIL_PIN_ENABLE;
> + I915_WRITE(UTIL_PIN_CTL, val);
> + }
> }
>
> void intel_panel_disable_backlight(struct intel_connector *connector)
> @@ -988,16 +998,38 @@ static void bxt_enable_backlight(struct intel_connector *connector)
> struct drm_device *dev = connector->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_panel *panel = &connector->panel;
> - u32 pwm_ctl;
> + enum pipe pipe = intel_get_pipe_from_connector(connector);
> + u32 pwm_ctl, val;
> +
> + /* To use 2nd set of backlight registers, utility pin has to be
> + * enabled with PWM mode.
> + * The field should only be changed when the utility pin is disabled
> + */
> + if (panel->backlight.controller == 1) {
> + val = I915_READ(UTIL_PIN_CTL);
> + if (val & UTIL_PIN_ENABLE) {
> + DRM_DEBUG_KMS("util pin already enabled\n");
> + val &= ~UTIL_PIN_ENABLE;
> + I915_WRITE(UTIL_PIN_CTL, val);
> + }
>
> - pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
> + val = 0;
> + if (panel->backlight.util_pin_active_low)
> + val |= UTIL_PIN_POLARITY;
> + I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) |
> + UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
> + }
> +
> + pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
> DRM_DEBUG_KMS("backlight already enabled\n");
> pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
> - I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> + pwm_ctl);
> }
>
> - I915_WRITE(BXT_BLC_PWM_FREQ1, panel->backlight.max);
> + I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
> + panel->backlight.max);
>
> intel_panel_actually_set_backlight(connector, panel->backlight.level);
>
> @@ -1005,9 +1037,10 @@ static void bxt_enable_backlight(struct intel_connector *connector)
> if (panel->backlight.active_low_pwm)
> pwm_ctl |= BXT_BLC_PWM_POLARITY;
>
> - I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
> - POSTING_READ(BXT_BLC_PWM_CTL1);
> - I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl | BXT_BLC_PWM_ENABLE);
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
> + POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> + pwm_ctl | BXT_BLC_PWM_ENABLE);
> }
>
> void intel_panel_enable_backlight(struct intel_connector *connector)
> @@ -1370,12 +1403,28 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
> struct intel_panel *panel = &connector->panel;
> u32 pwm_ctl, val;
>
> - pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
> - panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
> + /*
> + * For BXT hard coding the Backlight controller to 0.
> + * TODO : Read the controller value from VBT and generalize
> + */
> + panel->backlight.controller = 0;
>
> - panel->backlight.max = I915_READ(BXT_BLC_PWM_FREQ1);
> - if (!panel->backlight.max)
> - return -ENODEV;
> + pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> +
> + /* Keeping the check if controller 1 is to be programmed.
> + * This will come into affect once the VBT parsing
> + * is fixed for controller selection, and controller 1 is used
> + * for a prticular display configuration.
> + */
> + if (panel->backlight.controller == 1) {
> + val = I915_READ(UTIL_PIN_CTL);
> + panel->backlight.util_pin_active_low =
> + val & UTIL_PIN_POLARITY;
> + }
> +
> + panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
> + panel->backlight.max = I915_READ(
> + BXT_BLC_PWM_FREQ(panel->backlight.controller));
>
> val = bxt_get_backlight(connector);
> panel->backlight.level = intel_panel_compute_brightness(connector, val);
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v5 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-10-01 9:54 ` Jani Nikula
@ 2015-10-01 16:22 ` Shankar, Uma
2015-10-01 16:53 ` Uma Shankar
1 sibling, 0 replies; 69+ messages in thread
From: Shankar, Uma @ 2015-10-01 16:22 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: Kumar, Shobhit
>-----Original Message-----
>From: Jani Nikula [mailto:jani.nikula@linux.intel.com]
>Sent: Thursday, October 1, 2015 3:24 PM
>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
>Subject: Re: [BXT MIPI PATCH v5 05/14] drm/i915/bxt: DSI encoder support in
>CRTC modeset
>
>On Wed, 30 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
>> From: Shashank Sharma <shashank.sharma@intel.com>
>>
>> SKL and BXT qualifies the HAS_DDI() check, and hence haswell modeset
>> functions are re-used for modeset sequence. But DDI interface doesn't
>> include support for DSI.
>> This patch adds:
>> 1. cases for DSI encoder, in those modeset functions and allows
>> a CRTC modeset
>> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
>> needs to be done as such in CRTC for DSI encoder, as PLL, clock
>> and and transcoder programming will be taken care in encoder's
>> pre_enable and pre_pll_enable function.
>>
>> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
>> encoder like DSI for platforms having HAS_DDI as true.
>>
>> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
>> encoder.
>>
>> v4: WARN_ON for invalid encoder is refactored as per Jani's suggestion.
>> Fixed the sequence for pre_pll_enable.
>>
>> v5: Protected DDI code paths in case of DSI encoder calls.
>>
>> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> drivers/gpu/drm/i915/intel_ddi.c | 83 ++++++++++++++++++++++++++++-
>----
>> drivers/gpu/drm/i915/intel_display.c | 21 ++++++---
>> drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++-
>> drivers/gpu/drm/i915/intel_opregion.c | 9 +++-
>> 5 files changed, 101 insertions(+), 21 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h index fd1de45..f97a2a2 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2482,6 +2482,7 @@ struct drm_i915_cmd_table {
>> INTEL_INFO(dev)->gen >= 9)
>>
>> #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
>> +#define has_encoder_ddi(type) ((type) == (INTEL_OUTPUT_DSI) ? 0 :
>> +1)
>
>Drop this change.
>
>> #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)-
>>has_fpga_dbg)
>> #define HAS_PSR(dev) (IS_HASWELL(dev) ||
>IS_BROADWELL(dev) || \
>> IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)
>|| \ diff --git
>> a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index cacb07b..4abc13d 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -390,8 +390,10 @@ void intel_prepare_ddi(struct drm_device *dev)
>> enum port port;
>> bool supports_hdmi;
>>
>> - ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
>> + if (intel_encoder->type == INTEL_OUTPUT_DSI)
>> + continue;
>>
>
>This is good.
>
>> + ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
>> if (visited[port])
>> continue;
>>
>> @@ -977,8 +979,16 @@ static void bxt_ddi_clock_get(struct intel_encoder
>*encoder,
>> struct intel_crtc_state *pipe_config) {
>> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>> - enum port port = intel_ddi_get_encoder_port(encoder);
>> - uint32_t dpll = port;
>> + enum port port;
>> + uint32_t dpll;
>> +
>> + if (!has_encoder_ddi(encoder->type)) {
>> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
>> + return;
>> + }
>> +
>> + port = intel_ddi_get_encoder_port(encoder);
>> + dpll = port;
>
>No. Drop this change.
>
>Ask yourself, is it okay to call this function (bxt_ddi_clock_get) if the encoder
>type is DSI.
>
>No, it's not. We should not be here, at all, if encoder is DSI.
>
>We have modified ddi_get_encoder_port (and therefore
>intel_ddi_get_encoder_port) to emit a big warning if that function is called on a
>DSI encoder.
>
>So don't make those extra checks. We'll catch the bugs with the warning in
>ddi_get_encoder_port. We'll fix the code paths, and move on.
>
>We don't care if the function goes on and does something stupid because we
>called it with the wrong preconditions. Similarly, we don't check for, say,
>IS_GEN2() in DDI code, because that should not have happened. The bug is
>somewhere else.
>
>Now, there *are* valid code paths which will be called if encoder is DSI. In those
>cases, we need to handle DSI gracefully and not call ddi_get_encoder_port. For
>example intel_prepare_ddi above and intel_opregion_notify_encoder below.
>
Ok got it. Will do the same.
Regards,
Uma Shankar
>>
>> pipe_config->port_clock =
>> bxt_calc_pll_link(dev_priv, dpll);
>> @@ -1568,10 +1578,16 @@ void intel_ddi_enable_transcoder_func(struct
>drm_crtc *crtc)
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> enum pipe pipe = intel_crtc->pipe;
>> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>> - enum port port = intel_ddi_get_encoder_port(intel_encoder);
>> + enum port port;
>> int type = intel_encoder->type;
>> uint32_t temp;
>>
>> + if (!has_encoder_ddi(type)) {
>> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
>> + return;
>> + }
>> +
>> + port = intel_ddi_get_encoder_port(intel_encoder);
>
>Drop this change.
>
>> /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
>> temp = TRANS_DDI_FUNC_ENABLE;
>> temp |= TRANS_DDI_SELECT_PORT(port); @@ -1678,12 +1694,18 @@
>bool
>> intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> struct intel_encoder *intel_encoder = intel_connector->encoder;
>> int type = intel_connector->base.connector_type;
>> - enum port port = intel_ddi_get_encoder_port(intel_encoder);
>> + enum port port;
>> enum pipe pipe = 0;
>> enum transcoder cpu_transcoder;
>> enum intel_display_power_domain power_domain;
>> uint32_t tmp;
>>
>> + if (!has_encoder_ddi(type)) {
>> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
>> + return false;
>> + }
>> +
>> + port = intel_ddi_get_encoder_port(intel_encoder);
>
>Drop this change.
>
>> power_domain = intel_display_port_power_domain(intel_encoder);
>> if (!intel_display_power_is_enabled(dev_priv, power_domain))
>> return false;
>> @@ -1725,11 +1747,17 @@ bool intel_ddi_get_hw_state(struct
>> intel_encoder *encoder, {
>> struct drm_device *dev = encoder->base.dev;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> - enum port port = intel_ddi_get_encoder_port(encoder);
>> + enum port port;
>> enum intel_display_power_domain power_domain;
>> u32 tmp;
>> int i;
>>
>> + if (!has_encoder_ddi(encoder->type)) {
>> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
>> + return false;
>> + }
>> +
>> + port = intel_ddi_get_encoder_port(encoder);
>
>Drop this change.
>
>> power_domain = intel_display_port_power_domain(encoder);
>> if (!intel_display_power_is_enabled(dev_priv, power_domain))
>> return false;
>> @@ -1779,11 +1807,18 @@ bool intel_ddi_get_hw_state(struct
>> intel_encoder *encoder, void intel_ddi_enable_pipe_clock(struct
>> intel_crtc *intel_crtc) {
>> struct drm_crtc *crtc = &intel_crtc->base;
>> - struct drm_i915_private *dev_priv = crtc->dev->dev_private;
>> + struct drm_device *dev = crtc->dev;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
>> - enum port port = intel_ddi_get_encoder_port(intel_encoder);
>> + enum port port;
>> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>>
>> + if (!has_encoder_ddi(intel_encoder->type)) {
>> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
>> + return;
>> + }
>> +
>> + port = intel_ddi_get_encoder_port(intel_encoder);
>
>Drop this change.
>
>> if (cpu_transcoder != TRANSCODER_EDP)
>> I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>> TRANS_CLK_SEL_PORT(port));
>> @@ -1866,10 +1901,16 @@ static void intel_ddi_pre_enable(struct
>intel_encoder *intel_encoder)
>> struct drm_device *dev = encoder->dev;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
>> - enum port port = intel_ddi_get_encoder_port(intel_encoder);
>> + enum port port;
>> int type = intel_encoder->type;
>> int hdmi_level;
>>
>> + if (!has_encoder_ddi(type)) {
>> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
>> + return;
>> + }
>> +
>> + port = intel_ddi_get_encoder_port(intel_encoder);
>
>Drop this change.
>
>> if (type == INTEL_OUTPUT_EDP) {
>> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> intel_edp_panel_on(intel_dp);
>> @@ -1942,11 +1983,17 @@ static void intel_ddi_post_disable(struct
>intel_encoder *intel_encoder)
>> struct drm_encoder *encoder = &intel_encoder->base;
>> struct drm_device *dev = encoder->dev;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> - enum port port = intel_ddi_get_encoder_port(intel_encoder);
>> + enum port port;
>> int type = intel_encoder->type;
>> uint32_t val;
>> bool wait = false;
>>
>> + if (!has_encoder_ddi(type)) {
>> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
>> + return;
>> + }
>> +
>> + port = intel_ddi_get_encoder_port(intel_encoder);
>
>Drop this change.
>
>> val = I915_READ(DDI_BUF_CTL(port));
>> if (val & DDI_BUF_CTL_ENABLE) {
>> val &= ~DDI_BUF_CTL_ENABLE;
>> @@ -1983,9 +2030,15 @@ static void intel_enable_ddi(struct intel_encoder
>*intel_encoder)
>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> struct drm_device *dev = encoder->dev;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> - enum port port = intel_ddi_get_encoder_port(intel_encoder);
>> + enum port port;
>> int type = intel_encoder->type;
>>
>> + if (!has_encoder_ddi(type)) {
>> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
>> + return;
>> + }
>> +
>> + port = intel_ddi_get_encoder_port(intel_encoder);
>
>Drop this change.
>
>> if (type == INTEL_OUTPUT_HDMI) {
>> struct intel_digital_port *intel_dig_port =
>> enc_to_dig_port(encoder);
>> @@ -2729,8 +2782,14 @@ static bool intel_ddi_compute_config(struct
>intel_encoder *encoder,
>> struct intel_crtc_state *pipe_config) {
>> int type = encoder->type;
>> - int port = intel_ddi_get_encoder_port(encoder);
>> + int port;
>> +
>> + if (!has_encoder_ddi(type)) {
>> + DRM_DEBUG_KMS("DDI func getting called for DSI?\n");
>> + return false;
>> + }
>>
>> + port = intel_ddi_get_encoder_port(encoder);
>
>Drop this change.
>
>> WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on
>unknown
>> output!\n");
>>
>> if (port == PORT_A)
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index b8e0310..ea0f533 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -4991,6 +4991,7 @@ static void haswell_crtc_enable(struct drm_crtc
>*crtc)
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> struct intel_encoder *encoder;
>> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>> int pipe = intel_crtc->pipe;
>>
>> WARN_ON(!crtc->state->enable);
>> @@ -5023,9 +5024,12 @@ static void haswell_crtc_enable(struct drm_crtc
>*crtc)
>> intel_crtc->active = true;
>>
>> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>> - for_each_encoder_on_crtc(dev, crtc, encoder)
>> + for_each_encoder_on_crtc(dev, crtc, encoder) {
>> + if (encoder->pre_pll_enable)
>> + encoder->pre_pll_enable(encoder);
>> if (encoder->pre_enable)
>> encoder->pre_enable(encoder);
>> + }
>>
>> if (intel_crtc->config->has_pch_encoder) {
>> intel_set_pch_fifo_underrun_reporting(dev_priv,
>TRANSCODER_A, @@
>> -5033,7 +5037,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>> dev_priv->display.fdi_link_train(crtc);
>> }
>>
>> - intel_ddi_enable_pipe_clock(intel_crtc);
>> + if (!is_dsi)
>> + intel_ddi_enable_pipe_clock(intel_crtc);
>>
>> if (INTEL_INFO(dev)->gen == 9)
>> skylake_pfit_update(intel_crtc, 1); @@ -5049,7 +5054,8 @@
>static
>> void haswell_crtc_enable(struct drm_crtc *crtc)
>> intel_crtc_load_lut(crtc);
>>
>> intel_ddi_set_pipe_settings(crtc);
>> - intel_ddi_enable_transcoder_func(crtc);
>> + if (!is_dsi)
>> + intel_ddi_enable_transcoder_func(crtc);
>>
>> intel_update_watermarks(crtc);
>> intel_enable_pipe(intel_crtc);
>> @@ -5057,7 +5063,7 @@ static void haswell_crtc_enable(struct drm_crtc
>*crtc)
>> if (intel_crtc->config->has_pch_encoder)
>> lpt_pch_enable(crtc);
>>
>> - if (intel_crtc->config->dp_encoder_is_mst)
>> + if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
>> intel_ddi_set_vc_payload_alloc(crtc, true);
>>
>> assert_vblank_disabled(crtc);
>> @@ -5159,6 +5165,7 @@ static void haswell_crtc_disable(struct drm_crtc
>*crtc)
>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> struct intel_encoder *encoder;
>> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>>
>> if (!intel_crtc->active)
>> return;
>> @@ -5179,7 +5186,8 @@ static void haswell_crtc_disable(struct drm_crtc
>*crtc)
>> if (intel_crtc->config->dp_encoder_is_mst)
>> intel_ddi_set_vc_payload_alloc(crtc, false);
>>
>> - intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>> + if (!is_dsi)
>> + intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>>
>> if (INTEL_INFO(dev)->gen == 9)
>> skylake_pfit_update(intel_crtc, 0); @@ -5188,7 +5196,8 @@
>static
>> void haswell_crtc_disable(struct drm_crtc *crtc)
>> else
>> MISSING_CASE(INTEL_INFO(dev)->gen);
>>
>> - intel_ddi_disable_pipe_clock(intel_crtc);
>> + if (!is_dsi)
>> + intel_ddi_disable_pipe_clock(intel_crtc);
>>
>> if (intel_crtc->config->has_pch_encoder) {
>> lpt_disable_pch_transcoder(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
>> b/drivers/gpu/drm/i915/intel_dp_mst.c
>> index 600afdb..00327bc 100644
>> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
>> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
>> @@ -172,8 +172,14 @@ static void intel_mst_pre_enable_dp(struct
>intel_encoder *encoder)
>> intel_mst->port = found->port;
>>
>> if (intel_dp->active_mst_links == 0) {
>> - enum port port = intel_ddi_get_encoder_port(encoder);
>> + enum port port;
>>
>> + if (!has_encoder_ddi(encoder->type)) {
>> + DRM_DEBUG_KMS("DDI func getting called for
>DSI?\n");
>> + return;
>> + }
>> +
>> + port = intel_ddi_get_encoder_port(encoder);
>
>Drop this change.
>
>> /* FIXME: add support for SKL */
>> if (INTEL_INFO(dev)->gen < 9)
>> I915_WRITE(PORT_CLK_SEL(port),
>> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
>> b/drivers/gpu/drm/i915/intel_opregion.c
>> index 4813374..64b8bcd 100644
>> --- a/drivers/gpu/drm/i915/intel_opregion.c
>> +++ b/drivers/gpu/drm/i915/intel_opregion.c
>> @@ -334,8 +334,12 @@ int intel_opregion_notify_encoder(struct
>intel_encoder *intel_encoder,
>> if (!HAS_DDI(dev))
>> return 0;
>>
>> - port = intel_ddi_get_encoder_port(intel_encoder);
>> - if (port == PORT_E) {
>> + if (!has_encoder_ddi(type))
>
>This is good, but don't add extra wrapper (has_encoder_ddi) for the encode type
>check.
>
>> + port = 0;
>> + else
>> + port = intel_ddi_get_encoder_port(intel_encoder);
>> +
>> + if (port == PORT_E) {
>> port = 0;
>> } else {
>> parm |= 1 << port;
>> @@ -356,6 +360,7 @@ int intel_opregion_notify_encoder(struct
>intel_encoder *intel_encoder,
>> type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
>> break;
>> case INTEL_OUTPUT_EDP:
>> + case INTEL_OUTPUT_DSI:
>> type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
>> break;
>> default:
>> --
>> 1.7.9.5
>>
>
>--
>Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* [BXT MIPI PATCH v5 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-10-01 9:54 ` Jani Nikula
2015-10-01 16:22 ` Shankar, Uma
@ 2015-10-01 16:53 ` Uma Shankar
2015-10-02 11:05 ` Jani Nikula
2015-10-02 12:34 ` Daniel Vetter
1 sibling, 2 replies; 69+ messages in thread
From: Uma Shankar @ 2015-10-01 16:53 UTC (permalink / raw)
To: intel-gfx; +Cc: shobhit.kumar
From: Shashank Sharma <shashank.sharma@intel.com>
SKL and BXT qualifies the HAS_DDI() check, and hence haswell
modeset functions are re-used for modeset sequence. But DDI
interface doesn't include support for DSI.
This patch adds:
1. cases for DSI encoder, in those modeset functions and allows
a CRTC modeset
2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
needs to be done as such in CRTC for DSI encoder, as PLL, clock
and and transcoder programming will be taken care in encoder's
pre_enable and pre_pll_enable function.
v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
encoder like DSI for platforms having HAS_DDI as true.
v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
encoder.
v4: WARN_ON for invalid encoder is refactored as per Jani's suggestion.
Fixed the sequence for pre_pll_enable.
v5: Protected DDI code paths in case of DSI encoder calls.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 7 +++++--
drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++------
drivers/gpu/drm/i915/intel_opregion.c | 9 +++++++--
3 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cacb07b..7b7f544 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -390,8 +390,10 @@ void intel_prepare_ddi(struct drm_device *dev)
enum port port;
bool supports_hdmi;
- ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
+ if (intel_encoder->type == INTEL_OUTPUT_DSI)
+ continue;
+ ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
if (visited[port])
continue;
@@ -1779,7 +1781,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
{
struct drm_crtc *crtc = &intel_crtc->base;
- struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
enum port port = intel_ddi_get_encoder_port(intel_encoder);
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b8e0310..ea0f533 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4991,6 +4991,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
+ bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
int pipe = intel_crtc->pipe;
WARN_ON(!crtc->state->enable);
@@ -5023,9 +5024,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_crtc->active = true;
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- for_each_encoder_on_crtc(dev, crtc, encoder)
+ for_each_encoder_on_crtc(dev, crtc, encoder) {
+ if (encoder->pre_pll_enable)
+ encoder->pre_pll_enable(encoder);
if (encoder->pre_enable)
encoder->pre_enable(encoder);
+ }
if (intel_crtc->config->has_pch_encoder) {
intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
@@ -5033,7 +5037,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
dev_priv->display.fdi_link_train(crtc);
}
- intel_ddi_enable_pipe_clock(intel_crtc);
+ if (!is_dsi)
+ intel_ddi_enable_pipe_clock(intel_crtc);
if (INTEL_INFO(dev)->gen == 9)
skylake_pfit_update(intel_crtc, 1);
@@ -5049,7 +5054,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_crtc_load_lut(crtc);
intel_ddi_set_pipe_settings(crtc);
- intel_ddi_enable_transcoder_func(crtc);
+ if (!is_dsi)
+ intel_ddi_enable_transcoder_func(crtc);
intel_update_watermarks(crtc);
intel_enable_pipe(intel_crtc);
@@ -5057,7 +5063,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
if (intel_crtc->config->has_pch_encoder)
lpt_pch_enable(crtc);
- if (intel_crtc->config->dp_encoder_is_mst)
+ if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
intel_ddi_set_vc_payload_alloc(crtc, true);
assert_vblank_disabled(crtc);
@@ -5159,6 +5165,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
+ bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
if (!intel_crtc->active)
return;
@@ -5179,7 +5186,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
if (intel_crtc->config->dp_encoder_is_mst)
intel_ddi_set_vc_payload_alloc(crtc, false);
- intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
+ if (!is_dsi)
+ intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
if (INTEL_INFO(dev)->gen == 9)
skylake_pfit_update(intel_crtc, 0);
@@ -5188,7 +5196,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
else
MISSING_CASE(INTEL_INFO(dev)->gen);
- intel_ddi_disable_pipe_clock(intel_crtc);
+ if (!is_dsi)
+ intel_ddi_disable_pipe_clock(intel_crtc);
if (intel_crtc->config->has_pch_encoder) {
lpt_disable_pch_transcoder(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index 4813374..db518ef 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -334,8 +334,12 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
if (!HAS_DDI(dev))
return 0;
- port = intel_ddi_get_encoder_port(intel_encoder);
- if (port == PORT_E) {
+ if (intel_encoder->type == INTEL_OUTPUT_DSI)
+ port = 0;
+ else
+ port = intel_ddi_get_encoder_port(intel_encoder);
+
+ if (port == PORT_E) {
port = 0;
} else {
parm |= 1 << port;
@@ -356,6 +360,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
break;
case INTEL_OUTPUT_EDP:
+ case INTEL_OUTPUT_DSI:
type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
break;
default:
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v5 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-10-01 16:53 ` Uma Shankar
@ 2015-10-02 11:05 ` Jani Nikula
2015-10-02 12:34 ` Daniel Vetter
1 sibling, 0 replies; 69+ messages in thread
From: Jani Nikula @ 2015-10-02 11:05 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: shobhit.kumar
On Thu, 01 Oct 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> SKL and BXT qualifies the HAS_DDI() check, and hence haswell
> modeset functions are re-used for modeset sequence. But DDI
> interface doesn't include support for DSI.
> This patch adds:
> 1. cases for DSI encoder, in those modeset functions and allows
> a CRTC modeset
> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
> needs to be done as such in CRTC for DSI encoder, as PLL, clock
> and and transcoder programming will be taken care in encoder's
> pre_enable and pre_pll_enable function.
>
> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
> encoder like DSI for platforms having HAS_DDI as true.
>
> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
> encoder.
>
> v4: WARN_ON for invalid encoder is refactored as per Jani's suggestion.
> Fixed the sequence for pre_pll_enable.
>
> v5: Protected DDI code paths in case of DSI encoder calls.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 7 +++++--
> drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++------
> drivers/gpu/drm/i915/intel_opregion.c | 9 +++++++--
> 3 files changed, 27 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cacb07b..7b7f544 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -390,8 +390,10 @@ void intel_prepare_ddi(struct drm_device *dev)
> enum port port;
> bool supports_hdmi;
>
> - ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
> + if (intel_encoder->type == INTEL_OUTPUT_DSI)
> + continue;
>
> + ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
> if (visited[port])
> continue;
>
> @@ -1779,7 +1781,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
> {
> struct drm_crtc *crtc = &intel_crtc->base;
> - struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
> enum port port = intel_ddi_get_encoder_port(intel_encoder);
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b8e0310..ea0f533 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4991,6 +4991,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
> int pipe = intel_crtc->pipe;
>
> WARN_ON(!crtc->state->enable);
> @@ -5023,9 +5024,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> intel_crtc->active = true;
>
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> - for_each_encoder_on_crtc(dev, crtc, encoder)
> + for_each_encoder_on_crtc(dev, crtc, encoder) {
> + if (encoder->pre_pll_enable)
> + encoder->pre_pll_enable(encoder);
> if (encoder->pre_enable)
> encoder->pre_enable(encoder);
> + }
>
> if (intel_crtc->config->has_pch_encoder) {
> intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
> @@ -5033,7 +5037,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> dev_priv->display.fdi_link_train(crtc);
> }
>
> - intel_ddi_enable_pipe_clock(intel_crtc);
> + if (!is_dsi)
> + intel_ddi_enable_pipe_clock(intel_crtc);
>
> if (INTEL_INFO(dev)->gen == 9)
> skylake_pfit_update(intel_crtc, 1);
> @@ -5049,7 +5054,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> intel_crtc_load_lut(crtc);
>
> intel_ddi_set_pipe_settings(crtc);
> - intel_ddi_enable_transcoder_func(crtc);
> + if (!is_dsi)
> + intel_ddi_enable_transcoder_func(crtc);
>
> intel_update_watermarks(crtc);
> intel_enable_pipe(intel_crtc);
> @@ -5057,7 +5063,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->config->has_pch_encoder)
> lpt_pch_enable(crtc);
>
> - if (intel_crtc->config->dp_encoder_is_mst)
> + if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
> intel_ddi_set_vc_payload_alloc(crtc, true);
>
> assert_vblank_disabled(crtc);
> @@ -5159,6 +5165,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>
> if (!intel_crtc->active)
> return;
> @@ -5179,7 +5186,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> if (intel_crtc->config->dp_encoder_is_mst)
> intel_ddi_set_vc_payload_alloc(crtc, false);
>
> - intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
> + if (!is_dsi)
> + intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>
> if (INTEL_INFO(dev)->gen == 9)
> skylake_pfit_update(intel_crtc, 0);
> @@ -5188,7 +5196,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> else
> MISSING_CASE(INTEL_INFO(dev)->gen);
>
> - intel_ddi_disable_pipe_clock(intel_crtc);
> + if (!is_dsi)
> + intel_ddi_disable_pipe_clock(intel_crtc);
>
> if (intel_crtc->config->has_pch_encoder) {
> lpt_disable_pch_transcoder(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
> index 4813374..db518ef 100644
> --- a/drivers/gpu/drm/i915/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> @@ -334,8 +334,12 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
> if (!HAS_DDI(dev))
> return 0;
>
> - port = intel_ddi_get_encoder_port(intel_encoder);
> - if (port == PORT_E) {
> + if (intel_encoder->type == INTEL_OUTPUT_DSI)
> + port = 0;
> + else
> + port = intel_ddi_get_encoder_port(intel_encoder);
> +
> + if (port == PORT_E) {
> port = 0;
> } else {
> parm |= 1 << port;
> @@ -356,6 +360,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
> type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
> break;
> case INTEL_OUTPUT_EDP:
> + case INTEL_OUTPUT_DSI:
> type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
> break;
> default:
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v5 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-10-01 16:53 ` Uma Shankar
2015-10-02 11:05 ` Jani Nikula
@ 2015-10-02 12:34 ` Daniel Vetter
2015-10-05 16:06 ` Shankar, Uma
1 sibling, 1 reply; 69+ messages in thread
From: Daniel Vetter @ 2015-10-02 12:34 UTC (permalink / raw)
To: Uma Shankar; +Cc: shobhit.kumar, intel-gfx
On Thu, Oct 01, 2015 at 10:23:49PM +0530, Uma Shankar wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> SKL and BXT qualifies the HAS_DDI() check, and hence haswell
> modeset functions are re-used for modeset sequence. But DDI
> interface doesn't include support for DSI.
> This patch adds:
> 1. cases for DSI encoder, in those modeset functions and allows
> a CRTC modeset
> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
> needs to be done as such in CRTC for DSI encoder, as PLL, clock
> and and transcoder programming will be taken care in encoder's
> pre_enable and pre_pll_enable function.
>
> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
> encoder like DSI for platforms having HAS_DDI as true.
>
> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
> encoder.
>
> v4: WARN_ON for invalid encoder is refactored as per Jani's suggestion.
> Fixed the sequence for pre_pll_enable.
>
> v5: Protected DDI code paths in case of DSI encoder calls.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Ok, after this patch we get stuff like this:
for_each_encoder_on_crtc(dev, crtc, encoder) {
if (encoder->pre_pll_enable)
encoder->pre_pll_enable(encoder);
if (encoder->pre_enable)
encoder->pre_enable(encoder);
}
if (intel_crtc->config->has_pch_encoder) {
intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
true);
dev_priv->display.fdi_link_train(crtc);
}
if (!is_dsi)
intel_ddi_enable_pipe_clock(intel_crtc);
1. Please remove pre_pll_enable again, we don't need 2 callbacks in
exactly the same spot. Yes this might mean that you need special bxt_
versions of that in the dsi encoder, we have that everywhere.
2. the has_pch_encoder is already something encoder-specific (it's
exclusively used by the HSW LPT CRT encoder). Now we have another one of
those for the !is_dsi case. These special-cases should be moved into the
encoder->pre_enable callbacks, that's what they're for.
I'm not going to block these patches are (18months is already ridiculous),
but I want this cleanup done. Uma, can you pls own this? If you can't do
it yourself please escalate to Indranil so he can find someone.
Thanks, Daniel
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 7 +++++--
> drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++------
> drivers/gpu/drm/i915/intel_opregion.c | 9 +++++++--
> 3 files changed, 27 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cacb07b..7b7f544 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -390,8 +390,10 @@ void intel_prepare_ddi(struct drm_device *dev)
> enum port port;
> bool supports_hdmi;
>
> - ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
> + if (intel_encoder->type == INTEL_OUTPUT_DSI)
> + continue;
>
> + ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
> if (visited[port])
> continue;
>
> @@ -1779,7 +1781,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
> {
> struct drm_crtc *crtc = &intel_crtc->base;
> - struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
> enum port port = intel_ddi_get_encoder_port(intel_encoder);
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b8e0310..ea0f533 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4991,6 +4991,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
> int pipe = intel_crtc->pipe;
>
> WARN_ON(!crtc->state->enable);
> @@ -5023,9 +5024,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> intel_crtc->active = true;
>
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> - for_each_encoder_on_crtc(dev, crtc, encoder)
> + for_each_encoder_on_crtc(dev, crtc, encoder) {
> + if (encoder->pre_pll_enable)
> + encoder->pre_pll_enable(encoder);
> if (encoder->pre_enable)
> encoder->pre_enable(encoder);
> + }
>
> if (intel_crtc->config->has_pch_encoder) {
> intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
> @@ -5033,7 +5037,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> dev_priv->display.fdi_link_train(crtc);
> }
>
> - intel_ddi_enable_pipe_clock(intel_crtc);
> + if (!is_dsi)
> + intel_ddi_enable_pipe_clock(intel_crtc);
>
> if (INTEL_INFO(dev)->gen == 9)
> skylake_pfit_update(intel_crtc, 1);
> @@ -5049,7 +5054,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> intel_crtc_load_lut(crtc);
>
> intel_ddi_set_pipe_settings(crtc);
> - intel_ddi_enable_transcoder_func(crtc);
> + if (!is_dsi)
> + intel_ddi_enable_transcoder_func(crtc);
>
> intel_update_watermarks(crtc);
> intel_enable_pipe(intel_crtc);
> @@ -5057,7 +5063,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->config->has_pch_encoder)
> lpt_pch_enable(crtc);
>
> - if (intel_crtc->config->dp_encoder_is_mst)
> + if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
> intel_ddi_set_vc_payload_alloc(crtc, true);
>
> assert_vblank_disabled(crtc);
> @@ -5159,6 +5165,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>
> if (!intel_crtc->active)
> return;
> @@ -5179,7 +5186,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> if (intel_crtc->config->dp_encoder_is_mst)
> intel_ddi_set_vc_payload_alloc(crtc, false);
>
> - intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
> + if (!is_dsi)
> + intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>
> if (INTEL_INFO(dev)->gen == 9)
> skylake_pfit_update(intel_crtc, 0);
> @@ -5188,7 +5196,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> else
> MISSING_CASE(INTEL_INFO(dev)->gen);
>
> - intel_ddi_disable_pipe_clock(intel_crtc);
> + if (!is_dsi)
> + intel_ddi_disable_pipe_clock(intel_crtc);
>
> if (intel_crtc->config->has_pch_encoder) {
> lpt_disable_pch_transcoder(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
> index 4813374..db518ef 100644
> --- a/drivers/gpu/drm/i915/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> @@ -334,8 +334,12 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
> if (!HAS_DDI(dev))
> return 0;
>
> - port = intel_ddi_get_encoder_port(intel_encoder);
> - if (port == PORT_E) {
> + if (intel_encoder->type == INTEL_OUTPUT_DSI)
> + port = 0;
> + else
> + port = intel_ddi_get_encoder_port(intel_encoder);
> +
> + if (port == PORT_E) {
> port = 0;
> } else {
> parm |= 1 << port;
> @@ -356,6 +360,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
> type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
> break;
> case INTEL_OUTPUT_EDP:
> + case INTEL_OUTPUT_DSI:
> type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
> break;
> default:
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v5 11/14] drm/i915/bxt: Modify BXT BLC according to VBT changes
2015-09-30 17:04 ` [BXT MIPI PATCH v5 " Uma Shankar
2015-10-01 10:16 ` Jani Nikula
@ 2015-10-02 12:58 ` Daniel Vetter
1 sibling, 0 replies; 69+ messages in thread
From: Daniel Vetter @ 2015-10-02 12:58 UTC (permalink / raw)
To: Uma Shankar; +Cc: shobhit.kumar, intel-gfx
On Wed, Sep 30, 2015 at 10:34:57PM +0530, Uma Shankar wrote:
> From: Sunil Kamath <sunil.kamath@intel.com>
>
> Latest VBT mentions which set of registers will be used for BLC,
> as controller number field. Making use of this field in BXT
> BLC implementation. Also, the registers are used in case control
> pin indicates display DDI. Adding a check for this.
> According to Bspec, BLC_PWM_*_2 uses the display utility pin for output.
> To use backlight 2, enable the utility pin with mode = PWM
> v2: Jani's review comments
> addressed
> - Add a prefix _ to BXT BLC registers definitions.
> - Add "bxt only" comment for u8 controller
> - Remove control_pin check for DDI controller
> - Check for valid controller values
> - Set pipe bits in UTIL_PIN_CTL
> - Enable/Disable UTIL_PIN_CTL in enable/disable_backlight()
> - If BLC 2 is used, read active_low_pwm from UTIL_PIN polarity
> Satheesh's review comment addressed
> - If UTIL PIN is already enabled, BIOS would have programmed it. No
> need to disable and enable again.
> v3: Jani's review comments
> - add UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK
> - Disable UTIL_PIN if controller 1 is used
> - Mask out UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK before enabling
> UTIL_PIN
> - check valid controller value in intel_bios.c
> - add backlight.util_pin_active_low
> - disable util pin before enabling
> v4: Change for BXT-PO branch:
> Stubbed unwanted definition which was existing before
> because of DC6 patch.
> UTIL_PIN_MODE_PWM (0x1b << 24)
>
> v2: Fixed Jani's review comment.
>
> v3: Split the backight PWM frequency programming into separate patch,
> in cases BIOS doesn't initializes it.
>
> v4: Starting afresh and not modifying existing state for backlight, as
> per Jani's recommendation.
>
> v5: Fixed Jani's review comment wrt util pin enable
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Sunil Kamath <sunil.kamath@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++----
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> drivers/gpu/drm/i915/intel_panel.c | 83 ++++++++++++++++++++++++++++--------
> 3 files changed, 88 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 88a16e2..519f764 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3512,17 +3512,29 @@ enum skl_disp_power_wells {
> #define UTIL_PIN_CTL 0x48400
> #define UTIL_PIN_ENABLE (1 << 31)
>
> +#define UTIL_PIN_PIPE(x) ((x) << 29)
> +#define UTIL_PIN_PIPE_MASK (3 << 29)
> +#define UTIL_PIN_MODE_PWM (1 << 24)
> +#define UTIL_PIN_MODE_MASK (0xf << 24)
> +#define UTIL_PIN_POLARITY (1 << 22)
> +
> /* BXT backlight register definition. */
> -#define BXT_BLC_PWM_CTL1 0xC8250
> +#define _BXT_BLC_PWM_CTL1 0xC8250
> #define BXT_BLC_PWM_ENABLE (1 << 31)
> #define BXT_BLC_PWM_POLARITY (1 << 29)
> -#define BXT_BLC_PWM_FREQ1 0xC8254
> -#define BXT_BLC_PWM_DUTY1 0xC8258
> -
> -#define BXT_BLC_PWM_CTL2 0xC8350
> -#define BXT_BLC_PWM_FREQ2 0xC8354
> -#define BXT_BLC_PWM_DUTY2 0xC8358
> -
> +#define _BXT_BLC_PWM_FREQ1 0xC8254
> +#define _BXT_BLC_PWM_DUTY1 0xC8258
> +
> +#define _BXT_BLC_PWM_CTL2 0xC8350
> +#define _BXT_BLC_PWM_FREQ2 0xC8354
> +#define _BXT_BLC_PWM_DUTY2 0xC8358
> +
> +#define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \
> + _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
> +#define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \
> + _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
> +#define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \
> + _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
>
> #define PCH_GTC_CTL 0xe7000
> #define PCH_GTC_ENABLE (1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 1059283..d8ca075 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -182,7 +182,9 @@ struct intel_panel {
> bool enabled;
> bool combination_mode; /* gen 2/4 only */
> bool active_low_pwm;
> + bool util_pin_active_low; /* bxt+ */
> struct backlight_device *device;
> + u8 controller; /* bxt+ only */
> } backlight;
>
> void (*backlight_power)(struct intel_connector *, bool enable);
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 55aad23..0d21715 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -539,9 +539,10 @@ static u32 vlv_get_backlight(struct intel_connector *connector)
> static u32 bxt_get_backlight(struct intel_connector *connector)
> {
> struct drm_device *dev = connector->base.dev;
> + struct intel_panel *panel = &connector->panel;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - return I915_READ(BXT_BLC_PWM_DUTY1);
> + return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
> }
>
> static u32 intel_panel_get_backlight(struct intel_connector *connector)
> @@ -628,8 +629,9 @@ static void bxt_set_backlight(struct intel_connector *connector, u32 level)
> {
> struct drm_device *dev = connector->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_panel *panel = &connector->panel;
>
> - I915_WRITE(BXT_BLC_PWM_DUTY1, level);
> + I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
> }
>
> static void
> @@ -761,12 +763,20 @@ static void bxt_disable_backlight(struct intel_connector *connector)
> {
> struct drm_device *dev = connector->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - u32 tmp;
> + struct intel_panel *panel = &connector->panel;
> + u32 tmp, val;
>
> intel_panel_actually_set_backlight(connector, 0);
>
> - tmp = I915_READ(BXT_BLC_PWM_CTL1);
> - I915_WRITE(BXT_BLC_PWM_CTL1, tmp & ~BXT_BLC_PWM_ENABLE);
> + tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> + tmp & ~BXT_BLC_PWM_ENABLE);
> +
> + if (panel->backlight.controller == 1) {
> + val = I915_READ(UTIL_PIN_CTL);
> + val &= ~UTIL_PIN_ENABLE;
> + I915_WRITE(UTIL_PIN_CTL, val);
> + }
> }
>
> void intel_panel_disable_backlight(struct intel_connector *connector)
> @@ -988,16 +998,38 @@ static void bxt_enable_backlight(struct intel_connector *connector)
> struct drm_device *dev = connector->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_panel *panel = &connector->panel;
> - u32 pwm_ctl;
> + enum pipe pipe = intel_get_pipe_from_connector(connector);
> + u32 pwm_ctl, val;
> +
> + /* To use 2nd set of backlight registers, utility pin has to be
> + * enabled with PWM mode.
> + * The field should only be changed when the utility pin is disabled
> + */
> + if (panel->backlight.controller == 1) {
> + val = I915_READ(UTIL_PIN_CTL);
> + if (val & UTIL_PIN_ENABLE) {
> + DRM_DEBUG_KMS("util pin already enabled\n");
> + val &= ~UTIL_PIN_ENABLE;
> + I915_WRITE(UTIL_PIN_CTL, val);
> + }
>
> - pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
> + val = 0;
> + if (panel->backlight.util_pin_active_low)
> + val |= UTIL_PIN_POLARITY;
> + I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) |
> + UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
> + }
> +
> + pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
> DRM_DEBUG_KMS("backlight already enabled\n");
> pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
> - I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> + pwm_ctl);
> }
>
> - I915_WRITE(BXT_BLC_PWM_FREQ1, panel->backlight.max);
> + I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
> + panel->backlight.max);
>
> intel_panel_actually_set_backlight(connector, panel->backlight.level);
>
> @@ -1005,9 +1037,10 @@ static void bxt_enable_backlight(struct intel_connector *connector)
> if (panel->backlight.active_low_pwm)
> pwm_ctl |= BXT_BLC_PWM_POLARITY;
>
> - I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
> - POSTING_READ(BXT_BLC_PWM_CTL1);
> - I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl | BXT_BLC_PWM_ENABLE);
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
> + POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> + pwm_ctl | BXT_BLC_PWM_ENABLE);
> }
>
> void intel_panel_enable_backlight(struct intel_connector *connector)
> @@ -1370,12 +1403,28 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
> struct intel_panel *panel = &connector->panel;
> u32 pwm_ctl, val;
>
> - pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
> - panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
> + /*
> + * For BXT hard coding the Backlight controller to 0.
> + * TODO : Read the controller value from VBT and generalize
> + */
> + panel->backlight.controller = 0;
>
> - panel->backlight.max = I915_READ(BXT_BLC_PWM_FREQ1);
> - if (!panel->backlight.max)
> - return -ENODEV;
There was a conflict here and removing that if check seemed accidental. So
I kept it.
> + pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> +
> + /* Keeping the check if controller 1 is to be programmed.
> + * This will come into affect once the VBT parsing
> + * is fixed for controller selection, and controller 1 is used
> + * for a prticular display configuration.
> + */
> + if (panel->backlight.controller == 1) {
> + val = I915_READ(UTIL_PIN_CTL);
> + panel->backlight.util_pin_active_low =
> + val & UTIL_PIN_POLARITY;
> + }
> +
> + panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
> + panel->backlight.max = I915_READ(
> + BXT_BLC_PWM_FREQ(panel->backlight.controller));
This isn't how we break lines. Fixed while applying.
-Daniel
>
> val = bxt_get_backlight(connector);
> panel->backlight.level = intel_panel_compute_brightness(connector, val);
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v3 13/14] drm/i915/bxt: Remove DSP CLK_GATE programming for BXT
2015-09-18 13:38 ` Jani Nikula
@ 2015-10-02 13:02 ` Daniel Vetter
0 siblings, 0 replies; 69+ messages in thread
From: Daniel Vetter @ 2015-10-02 13:02 UTC (permalink / raw)
To: Jani Nikula; +Cc: shobhit.kumar, intel-gfx
On Fri, Sep 18, 2015 at 04:38:27PM +0300, Jani Nikula wrote:
> On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> > DSP CLK_GATE registers are specific to BYT and CHT.
> > Avoid programming the same for BXT platform.
> >
> > v2: Rebased on latest drm nightly branch.
> >
> > v3: Fixed Jani's review comments
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Merged everything in this series to dinq, with the exception of two
backlight-related patches which seem superseeded.
I'll expect follow-up work to clean up the encoder callback code
organization.
-Daniel
>
>
> > ---
> > drivers/gpu/drm/i915/intel_dsi.c | 8 +++++---
> > 1 file changed, 5 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> > index 6a0071f..08bade2 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -631,9 +631,11 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
> >
> > intel_dsi_clear_device_ready(encoder);
> >
> > - val = I915_READ(DSPCLK_GATE_D);
> > - val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
> > - I915_WRITE(DSPCLK_GATE_D, val);
> > + if (!IS_BROXTON(dev_priv->dev)) {
> > + val = I915_READ(DSPCLK_GATE_D);
> > + val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
> > + I915_WRITE(DSPCLK_GATE_D, val);
> > + }
> >
> > drm_panel_unprepare(intel_dsi->panel);
> >
> > --
> > 1.7.9.5
> >
>
> --
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v5 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-10-02 12:34 ` Daniel Vetter
@ 2015-10-05 16:06 ` Shankar, Uma
2015-10-06 6:05 ` Jani Nikula
0 siblings, 1 reply; 69+ messages in thread
From: Shankar, Uma @ 2015-10-05 16:06 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Kumar, Shobhit, intel-gfx
>-----Original Message-----
>From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
>Sent: Friday, October 2, 2015 6:05 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Kumar, Shobhit
>Subject: Re: [Intel-gfx] [BXT MIPI PATCH v5 05/14] drm/i915/bxt: DSI encoder
>support in CRTC modeset
>
>On Thu, Oct 01, 2015 at 10:23:49PM +0530, Uma Shankar wrote:
>> From: Shashank Sharma <shashank.sharma@intel.com>
>>
>> SKL and BXT qualifies the HAS_DDI() check, and hence haswell modeset
>> functions are re-used for modeset sequence. But DDI interface doesn't
>> include support for DSI.
>> This patch adds:
>> 1. cases for DSI encoder, in those modeset functions and allows
>> a CRTC modeset
>> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
>> needs to be done as such in CRTC for DSI encoder, as PLL, clock
>> and and transcoder programming will be taken care in encoder's
>> pre_enable and pre_pll_enable function.
>>
>> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
>> encoder like DSI for platforms having HAS_DDI as true.
>>
>> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
>> encoder.
>>
>> v4: WARN_ON for invalid encoder is refactored as per Jani's suggestion.
>> Fixed the sequence for pre_pll_enable.
>>
>> v5: Protected DDI code paths in case of DSI encoder calls.
>>
>> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>
>Ok, after this patch we get stuff like this:
>
> for_each_encoder_on_crtc(dev, crtc, encoder) {
> if (encoder->pre_pll_enable)
> encoder->pre_pll_enable(encoder);
> if (encoder->pre_enable)
> encoder->pre_enable(encoder);
> }
>
> if (intel_crtc->config->has_pch_encoder) {
> intel_set_pch_fifo_underrun_reporting(dev_priv,
>TRANSCODER_A,
> true);
> dev_priv->display.fdi_link_train(crtc);
> }
>
> if (!is_dsi)
> intel_ddi_enable_pipe_clock(intel_crtc);
>
>1. Please remove pre_pll_enable again, we don't need 2 callbacks in exactly the
>same spot. Yes this might mean that you need special bxt_ versions of that in the
>dsi encoder, we have that everywhere.
>
>2. the has_pch_encoder is already something encoder-specific (it's exclusively
>used by the HSW LPT CRT encoder). Now we have another one of those for the
>!is_dsi case. These special-cases should be moved into the
>encoder->pre_enable callbacks, that's what they're for.
>
>I'm not going to block these patches are (18months is already ridiculous), but I
>want this cleanup done. Uma, can you pls own this? If you can't do it yourself
>please escalate to Indranil so he can find someone.
>
>Thanks, Daniel
>
Hi Daniel,
I will discuss with Indranil and will get this done.
Thanks for your support in getting the video mode patches merged.
Regards,
Uma Shankar
>> ---
>> drivers/gpu/drm/i915/intel_ddi.c | 7 +++++--
>> drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++------
>> drivers/gpu/drm/i915/intel_opregion.c | 9 +++++++--
>> 3 files changed, 27 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>> b/drivers/gpu/drm/i915/intel_ddi.c
>> index cacb07b..7b7f544 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -390,8 +390,10 @@ void intel_prepare_ddi(struct drm_device *dev)
>> enum port port;
>> bool supports_hdmi;
>>
>> - ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
>> + if (intel_encoder->type == INTEL_OUTPUT_DSI)
>> + continue;
>>
>> + ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
>> if (visited[port])
>> continue;
>>
>> @@ -1779,7 +1781,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder
>> *encoder, void intel_ddi_enable_pipe_clock(struct intel_crtc
>> *intel_crtc) {
>> struct drm_crtc *crtc = &intel_crtc->base;
>> - struct drm_i915_private *dev_priv = crtc->dev->dev_private;
>> + struct drm_device *dev = crtc->dev;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
>> enum port port = intel_ddi_get_encoder_port(intel_encoder);
>> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index b8e0310..ea0f533 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -4991,6 +4991,7 @@ static void haswell_crtc_enable(struct drm_crtc
>*crtc)
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> struct intel_encoder *encoder;
>> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>> int pipe = intel_crtc->pipe;
>>
>> WARN_ON(!crtc->state->enable);
>> @@ -5023,9 +5024,12 @@ static void haswell_crtc_enable(struct drm_crtc
>*crtc)
>> intel_crtc->active = true;
>>
>> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>> - for_each_encoder_on_crtc(dev, crtc, encoder)
>> + for_each_encoder_on_crtc(dev, crtc, encoder) {
>> + if (encoder->pre_pll_enable)
>> + encoder->pre_pll_enable(encoder);
>> if (encoder->pre_enable)
>> encoder->pre_enable(encoder);
>> + }
>>
>> if (intel_crtc->config->has_pch_encoder) {
>> intel_set_pch_fifo_underrun_reporting(dev_priv,
>TRANSCODER_A, @@
>> -5033,7 +5037,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>> dev_priv->display.fdi_link_train(crtc);
>> }
>>
>> - intel_ddi_enable_pipe_clock(intel_crtc);
>> + if (!is_dsi)
>> + intel_ddi_enable_pipe_clock(intel_crtc);
>>
>> if (INTEL_INFO(dev)->gen == 9)
>> skylake_pfit_update(intel_crtc, 1); @@ -5049,7 +5054,8 @@
>static
>> void haswell_crtc_enable(struct drm_crtc *crtc)
>> intel_crtc_load_lut(crtc);
>>
>> intel_ddi_set_pipe_settings(crtc);
>> - intel_ddi_enable_transcoder_func(crtc);
>> + if (!is_dsi)
>> + intel_ddi_enable_transcoder_func(crtc);
>>
>> intel_update_watermarks(crtc);
>> intel_enable_pipe(intel_crtc);
>> @@ -5057,7 +5063,7 @@ static void haswell_crtc_enable(struct drm_crtc
>*crtc)
>> if (intel_crtc->config->has_pch_encoder)
>> lpt_pch_enable(crtc);
>>
>> - if (intel_crtc->config->dp_encoder_is_mst)
>> + if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
>> intel_ddi_set_vc_payload_alloc(crtc, true);
>>
>> assert_vblank_disabled(crtc);
>> @@ -5159,6 +5165,7 @@ static void haswell_crtc_disable(struct drm_crtc
>*crtc)
>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> struct intel_encoder *encoder;
>> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>>
>> if (!intel_crtc->active)
>> return;
>> @@ -5179,7 +5186,8 @@ static void haswell_crtc_disable(struct drm_crtc
>*crtc)
>> if (intel_crtc->config->dp_encoder_is_mst)
>> intel_ddi_set_vc_payload_alloc(crtc, false);
>>
>> - intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>> + if (!is_dsi)
>> + intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>>
>> if (INTEL_INFO(dev)->gen == 9)
>> skylake_pfit_update(intel_crtc, 0); @@ -5188,7 +5196,8 @@
>static
>> void haswell_crtc_disable(struct drm_crtc *crtc)
>> else
>> MISSING_CASE(INTEL_INFO(dev)->gen);
>>
>> - intel_ddi_disable_pipe_clock(intel_crtc);
>> + if (!is_dsi)
>> + intel_ddi_disable_pipe_clock(intel_crtc);
>>
>> if (intel_crtc->config->has_pch_encoder) {
>> lpt_disable_pch_transcoder(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
>> b/drivers/gpu/drm/i915/intel_opregion.c
>> index 4813374..db518ef 100644
>> --- a/drivers/gpu/drm/i915/intel_opregion.c
>> +++ b/drivers/gpu/drm/i915/intel_opregion.c
>> @@ -334,8 +334,12 @@ int intel_opregion_notify_encoder(struct
>intel_encoder *intel_encoder,
>> if (!HAS_DDI(dev))
>> return 0;
>>
>> - port = intel_ddi_get_encoder_port(intel_encoder);
>> - if (port == PORT_E) {
>> + if (intel_encoder->type == INTEL_OUTPUT_DSI)
>> + port = 0;
>> + else
>> + port = intel_ddi_get_encoder_port(intel_encoder);
>> +
>> + if (port == PORT_E) {
>> port = 0;
>> } else {
>> parm |= 1 << port;
>> @@ -356,6 +360,7 @@ int intel_opregion_notify_encoder(struct
>intel_encoder *intel_encoder,
>> type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
>> break;
>> case INTEL_OUTPUT_EDP:
>> + case INTEL_OUTPUT_DSI:
>> type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
>> break;
>> default:
>> --
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Daniel Vetter
>Software Engineer, Intel Corporation
>http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [BXT MIPI PATCH v5 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset
2015-10-05 16:06 ` Shankar, Uma
@ 2015-10-06 6:05 ` Jani Nikula
0 siblings, 0 replies; 69+ messages in thread
From: Jani Nikula @ 2015-10-06 6:05 UTC (permalink / raw)
To: Shankar, Uma, Daniel Vetter; +Cc: Kumar, Shobhit, intel-gfx
On Mon, 05 Oct 2015, "Shankar, Uma" <uma.shankar@intel.com> wrote:
>>-----Original Message-----
>>From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
>>Sent: Friday, October 2, 2015 6:05 PM
>>To: Shankar, Uma
>>Cc: intel-gfx@lists.freedesktop.org; Kumar, Shobhit
>>Subject: Re: [Intel-gfx] [BXT MIPI PATCH v5 05/14] drm/i915/bxt: DSI encoder
>>support in CRTC modeset
>>
>>On Thu, Oct 01, 2015 at 10:23:49PM +0530, Uma Shankar wrote:
>>> From: Shashank Sharma <shashank.sharma@intel.com>
>>>
>>> SKL and BXT qualifies the HAS_DDI() check, and hence haswell modeset
>>> functions are re-used for modeset sequence. But DDI interface doesn't
>>> include support for DSI.
>>> This patch adds:
>>> 1. cases for DSI encoder, in those modeset functions and allows
>>> a CRTC modeset
>>> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
>>> needs to be done as such in CRTC for DSI encoder, as PLL, clock
>>> and and transcoder programming will be taken care in encoder's
>>> pre_enable and pre_pll_enable function.
>>>
>>> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
>>> encoder like DSI for platforms having HAS_DDI as true.
>>>
>>> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
>>> encoder.
>>>
>>> v4: WARN_ON for invalid encoder is refactored as per Jani's suggestion.
>>> Fixed the sequence for pre_pll_enable.
>>>
>>> v5: Protected DDI code paths in case of DSI encoder calls.
>>>
>>> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
>>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>>
>>Ok, after this patch we get stuff like this:
>>
>> for_each_encoder_on_crtc(dev, crtc, encoder) {
>> if (encoder->pre_pll_enable)
>> encoder->pre_pll_enable(encoder);
>> if (encoder->pre_enable)
>> encoder->pre_enable(encoder);
>> }
>>
>> if (intel_crtc->config->has_pch_encoder) {
>> intel_set_pch_fifo_underrun_reporting(dev_priv,
>>TRANSCODER_A,
>> true);
>> dev_priv->display.fdi_link_train(crtc);
>> }
>>
>> if (!is_dsi)
>> intel_ddi_enable_pipe_clock(intel_crtc);
>>
>>1. Please remove pre_pll_enable again, we don't need 2 callbacks in exactly the
>>same spot. Yes this might mean that you need special bxt_ versions of that in the
>>dsi encoder, we have that everywhere.
>>
>>2. the has_pch_encoder is already something encoder-specific (it's exclusively
>>used by the HSW LPT CRT encoder). Now we have another one of those for the
>>!is_dsi case. These special-cases should be moved into the
>>encoder->pre_enable callbacks, that's what they're for.
>>
>>I'm not going to block these patches are (18months is already ridiculous), but I
>>want this cleanup done. Uma, can you pls own this? If you can't do it yourself
>>please escalate to Indranil so he can find someone.
>>
>>Thanks, Daniel
>>
>
> Hi Daniel,
> I will discuss with Indranil and will get this done.
>
> Thanks for your support in getting the video mode patches merged.
I'll do the cleanups, don't worry about it.
BR,
Jani.
>
> Regards,
> Uma Shankar
>
>>> ---
>>> drivers/gpu/drm/i915/intel_ddi.c | 7 +++++--
>>> drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++------
>>> drivers/gpu/drm/i915/intel_opregion.c | 9 +++++++--
>>> 3 files changed, 27 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>>> b/drivers/gpu/drm/i915/intel_ddi.c
>>> index cacb07b..7b7f544 100644
>>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>>> @@ -390,8 +390,10 @@ void intel_prepare_ddi(struct drm_device *dev)
>>> enum port port;
>>> bool supports_hdmi;
>>>
>>> - ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
>>> + if (intel_encoder->type == INTEL_OUTPUT_DSI)
>>> + continue;
>>>
>>> + ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
>>> if (visited[port])
>>> continue;
>>>
>>> @@ -1779,7 +1781,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder
>>> *encoder, void intel_ddi_enable_pipe_clock(struct intel_crtc
>>> *intel_crtc) {
>>> struct drm_crtc *crtc = &intel_crtc->base;
>>> - struct drm_i915_private *dev_priv = crtc->dev->dev_private;
>>> + struct drm_device *dev = crtc->dev;
>>> + struct drm_i915_private *dev_priv = dev->dev_private;
>>> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
>>> enum port port = intel_ddi_get_encoder_port(intel_encoder);
>>> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>>> b/drivers/gpu/drm/i915/intel_display.c
>>> index b8e0310..ea0f533 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -4991,6 +4991,7 @@ static void haswell_crtc_enable(struct drm_crtc
>>*crtc)
>>> struct drm_i915_private *dev_priv = dev->dev_private;
>>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>> struct intel_encoder *encoder;
>>> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>>> int pipe = intel_crtc->pipe;
>>>
>>> WARN_ON(!crtc->state->enable);
>>> @@ -5023,9 +5024,12 @@ static void haswell_crtc_enable(struct drm_crtc
>>*crtc)
>>> intel_crtc->active = true;
>>>
>>> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>>> - for_each_encoder_on_crtc(dev, crtc, encoder)
>>> + for_each_encoder_on_crtc(dev, crtc, encoder) {
>>> + if (encoder->pre_pll_enable)
>>> + encoder->pre_pll_enable(encoder);
>>> if (encoder->pre_enable)
>>> encoder->pre_enable(encoder);
>>> + }
>>>
>>> if (intel_crtc->config->has_pch_encoder) {
>>> intel_set_pch_fifo_underrun_reporting(dev_priv,
>>TRANSCODER_A, @@
>>> -5033,7 +5037,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>>> dev_priv->display.fdi_link_train(crtc);
>>> }
>>>
>>> - intel_ddi_enable_pipe_clock(intel_crtc);
>>> + if (!is_dsi)
>>> + intel_ddi_enable_pipe_clock(intel_crtc);
>>>
>>> if (INTEL_INFO(dev)->gen == 9)
>>> skylake_pfit_update(intel_crtc, 1); @@ -5049,7 +5054,8 @@
>>static
>>> void haswell_crtc_enable(struct drm_crtc *crtc)
>>> intel_crtc_load_lut(crtc);
>>>
>>> intel_ddi_set_pipe_settings(crtc);
>>> - intel_ddi_enable_transcoder_func(crtc);
>>> + if (!is_dsi)
>>> + intel_ddi_enable_transcoder_func(crtc);
>>>
>>> intel_update_watermarks(crtc);
>>> intel_enable_pipe(intel_crtc);
>>> @@ -5057,7 +5063,7 @@ static void haswell_crtc_enable(struct drm_crtc
>>*crtc)
>>> if (intel_crtc->config->has_pch_encoder)
>>> lpt_pch_enable(crtc);
>>>
>>> - if (intel_crtc->config->dp_encoder_is_mst)
>>> + if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
>>> intel_ddi_set_vc_payload_alloc(crtc, true);
>>>
>>> assert_vblank_disabled(crtc);
>>> @@ -5159,6 +5165,7 @@ static void haswell_crtc_disable(struct drm_crtc
>>*crtc)
>>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>> struct intel_encoder *encoder;
>>> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>>> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>>>
>>> if (!intel_crtc->active)
>>> return;
>>> @@ -5179,7 +5186,8 @@ static void haswell_crtc_disable(struct drm_crtc
>>*crtc)
>>> if (intel_crtc->config->dp_encoder_is_mst)
>>> intel_ddi_set_vc_payload_alloc(crtc, false);
>>>
>>> - intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>>> + if (!is_dsi)
>>> + intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>>>
>>> if (INTEL_INFO(dev)->gen == 9)
>>> skylake_pfit_update(intel_crtc, 0); @@ -5188,7 +5196,8 @@
>>static
>>> void haswell_crtc_disable(struct drm_crtc *crtc)
>>> else
>>> MISSING_CASE(INTEL_INFO(dev)->gen);
>>>
>>> - intel_ddi_disable_pipe_clock(intel_crtc);
>>> + if (!is_dsi)
>>> + intel_ddi_disable_pipe_clock(intel_crtc);
>>>
>>> if (intel_crtc->config->has_pch_encoder) {
>>> lpt_disable_pch_transcoder(dev_priv);
>>> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
>>> b/drivers/gpu/drm/i915/intel_opregion.c
>>> index 4813374..db518ef 100644
>>> --- a/drivers/gpu/drm/i915/intel_opregion.c
>>> +++ b/drivers/gpu/drm/i915/intel_opregion.c
>>> @@ -334,8 +334,12 @@ int intel_opregion_notify_encoder(struct
>>intel_encoder *intel_encoder,
>>> if (!HAS_DDI(dev))
>>> return 0;
>>>
>>> - port = intel_ddi_get_encoder_port(intel_encoder);
>>> - if (port == PORT_E) {
>>> + if (intel_encoder->type == INTEL_OUTPUT_DSI)
>>> + port = 0;
>>> + else
>>> + port = intel_ddi_get_encoder_port(intel_encoder);
>>> +
>>> + if (port == PORT_E) {
>>> port = 0;
>>> } else {
>>> parm |= 1 << port;
>>> @@ -356,6 +360,7 @@ int intel_opregion_notify_encoder(struct
>>intel_encoder *intel_encoder,
>>> type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
>>> break;
>>> case INTEL_OUTPUT_EDP:
>>> + case INTEL_OUTPUT_DSI:
>>> type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
>>> break;
>>> default:
>>> --
>>> 1.7.9.5
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>--
>>Daniel Vetter
>>Software Engineer, Intel Corporation
>>http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 69+ messages in thread
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2015-09-01 14:11 [BXT MIPI PATCH v3 00/14] MIPI DSI Support for BXT Uma Shankar
2015-09-01 14:11 ` [BXT MIPI PATCH v3 01/14] drm/i915/bxt: Initialize MIPI " Uma Shankar
2015-09-18 12:17 ` Jani Nikula
2015-09-23 8:08 ` Daniel Vetter
2015-09-01 14:11 ` [BXT MIPI PATCH v3 02/14] drm/i915/bxt: Enable BXT DSI PLL Uma Shankar
2015-09-18 12:32 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 03/14] drm/i915/bxt: Disable DSI PLL for BXT Uma Shankar
2015-09-18 12:57 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 04/14] drm/i915/bxt: DSI prepare changes " Uma Shankar
2015-09-18 13:05 ` Jani Nikula
2015-09-23 8:16 ` Daniel Vetter
2015-09-01 14:11 ` [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset Uma Shankar
2015-09-18 14:18 ` Jani Nikula
2015-09-21 10:41 ` Shankar, Uma
2015-09-23 8:15 ` Daniel Vetter
2015-09-23 12:43 ` Jani Nikula
2015-09-23 13:11 ` Daniel Vetter
2015-09-23 14:44 ` Shankar, Uma
2015-09-23 12:53 ` Jani Nikula
2015-09-23 14:49 ` Shankar, Uma
2015-09-23 17:03 ` Shankar, Uma
2015-09-23 17:53 ` [BXT MIPI PATCH v4 " Uma Shankar
2015-09-28 13:28 ` Jani Nikula
2015-09-28 16:57 ` Shankar, Uma
2015-09-29 7:29 ` Jani Nikula
2015-09-30 16:33 ` Shankar, Uma
2015-10-01 9:56 ` Jani Nikula
2015-09-30 17:03 ` [BXT MIPI PATCH v5 " Uma Shankar
2015-10-01 9:54 ` Jani Nikula
2015-10-01 16:22 ` Shankar, Uma
2015-10-01 16:53 ` Uma Shankar
2015-10-02 11:05 ` Jani Nikula
2015-10-02 12:34 ` Daniel Vetter
2015-10-05 16:06 ` Shankar, Uma
2015-10-06 6:05 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 06/14] drm/i915/bxt: DSI enable for BXT Uma Shankar
2015-09-18 13:17 ` Jani Nikula
2015-09-21 9:33 ` Shankar, Uma
2015-09-01 14:11 ` [BXT MIPI PATCH v3 07/14] drm/i915/bxt: Program Tx Rx and Dphy clocks Uma Shankar
2015-09-18 13:27 ` Jani Nikula
2015-09-21 10:11 ` Shankar, Uma
2015-09-23 17:57 ` [BXT MIPI PATCH v4 " Uma Shankar
2015-09-28 13:04 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 08/14] drm/i915/bxt: DSI disable and post-disable Uma Shankar
2015-09-18 13:29 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 09/14] drm/i915/bxt: get_hw_state for BXT Uma Shankar
2015-09-18 13:30 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 10/14] drm/i915/bxt: get DSI pixelclock Uma Shankar
2015-09-18 13:30 ` Jani Nikula
2015-09-01 14:11 ` [BXT MIPI PATCH v3 11/14] drm/i915/bxt: Modify BXT BLC according to VBT changes Uma Shankar
2015-09-18 13:51 ` Jani Nikula
2015-09-21 10:26 ` Shankar, Uma
2015-09-23 17:59 ` [BXT MIPI PATCH v4 " Uma Shankar
2015-09-28 13:13 ` Jani Nikula
2015-09-30 17:04 ` [BXT MIPI PATCH v5 " Uma Shankar
2015-10-01 10:16 ` Jani Nikula
2015-10-02 12:58 ` Daniel Vetter
2015-09-01 14:11 ` [BXT MIPI PATCH v3 12/14] drm/i915/bxt: Program Backlight PWM frequency Uma Shankar
2015-09-18 13:33 ` Jani Nikula
2015-09-21 10:18 ` Shankar, Uma
2015-09-01 14:11 ` [BXT MIPI PATCH v3 13/14] drm/i915/bxt: Remove DSP CLK_GATE programming for BXT Uma Shankar
2015-09-18 13:38 ` Jani Nikula
2015-10-02 13:02 ` Daniel Vetter
2015-09-01 14:11 ` [BXT MIPI PATCH v3 14/14] drm/i915: Added BXT DSI backlight support Uma Shankar
2015-09-18 13:37 ` Jani Nikula
2015-09-21 10:22 ` Shankar, Uma
2015-09-23 18:00 ` [BXT MIPI PATCH v4 " Uma Shankar
2015-09-24 16:58 ` Ville Syrjälä
2015-09-25 10:15 ` Shankar, Uma
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