* [U-Boot] [PATCH v2 1/7] MIPS: move create_tlb() in an proper header: mipsregs.h
2018-10-09 11:58 [U-Boot] [PATCH v2 0/7] Add support for the SoCs found in Microsemi switches Gregory CLEMENT
@ 2018-10-09 11:58 ` Gregory CLEMENT
2018-10-09 11:58 ` [U-Boot] [PATCH v2 2/7] MIPS: Allow to prefetch and lock instructions into cache Gregory CLEMENT
` (5 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Gregory CLEMENT @ 2018-10-09 11:58 UTC (permalink / raw)
To: u-boot
Export create_tlb() as an inline function in mipsregs.h. It allows to
remove the declaration of the function from the board files.
Then it will allow also to use this function very early in the boot when
the stack is not usable.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/cpu/cpu.c | 10 ----------
arch/mips/include/asm/mipsregs.h | 11 +++++++++++
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
index 5c56ab0289..a403ff729b 100644
--- a/arch/mips/cpu/cpu.c
+++ b/arch/mips/cpu/cpu.c
@@ -28,16 +28,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
}
#endif
-void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-{
- write_c0_entrylo0(low0);
- write_c0_pagemask(pagemask);
- write_c0_entrylo1(low1);
- write_c0_entryhi(hi);
- write_c0_index(index);
- tlb_write_indexed();
-}
-
int arch_cpu_init(void)
{
mips_cache_probe();
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 48fa1f1f7f..930562ebb2 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2005,6 +2005,17 @@ static inline unsigned int get_ebase_cpunum(void)
return read_c0_ebase() & 0x3ff;
}
+static inline void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0,
+ u32 low1)
+{
+ write_c0_entrylo0(low0);
+ write_c0_pagemask(pagemask);
+ write_c0_entrylo1(low1);
+ write_c0_entryhi(hi);
+ write_c0_index(index);
+ tlb_write_indexed();
+}
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_MIPSREGS_H */
--
2.19.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v2 2/7] MIPS: Allow to prefetch and lock instructions into cache
2018-10-09 11:58 [U-Boot] [PATCH v2 0/7] Add support for the SoCs found in Microsemi switches Gregory CLEMENT
2018-10-09 11:58 ` [U-Boot] [PATCH v2 1/7] MIPS: move create_tlb() in an proper header: mipsregs.h Gregory CLEMENT
@ 2018-10-09 11:58 ` Gregory CLEMENT
2018-10-09 11:58 ` [U-Boot] [PATCH v2 3/7] MSCC: add support for Ocelot SoCs Gregory CLEMENT
` (4 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Gregory CLEMENT @ 2018-10-09 11:58 UTC (permalink / raw)
To: u-boot
This path add a new helper allowing to prefetch and lock instructions
into cache. This is useful very early in the boot when no RAM is
available yet.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/include/asm/cacheops.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 3161875441..98b67ccc8e 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -19,6 +19,25 @@ static inline void mips_cache(int op, const volatile void *addr)
#endif
}
+#define MIPS32_WHICH_ICACHE 0x0
+#define MIPS32_FETCH_AND_LOCK 0x7
+
+#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2))
+
+/* Prefetch and lock instructions into cache */
+static inline void icache_lock(void *func, size_t len)
+{
+ int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1;
+
+ for (i = 0; i < lines; i++) {
+ asm volatile (" cache %0, %1(%2)"
+ : /* No Output */
+ : "I" ICACHE_LOAD_LOCK,
+ "n" (i * ARCH_DMA_MINALIGN),
+ "r" (func)
+ : /* No Clobbers */);
+ }
+}
#endif /* !__ASSEMBLY__ */
/*
--
2.19.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v2 3/7] MSCC: add support for Ocelot SoCs
2018-10-09 11:58 [U-Boot] [PATCH v2 0/7] Add support for the SoCs found in Microsemi switches Gregory CLEMENT
2018-10-09 11:58 ` [U-Boot] [PATCH v2 1/7] MIPS: move create_tlb() in an proper header: mipsregs.h Gregory CLEMENT
2018-10-09 11:58 ` [U-Boot] [PATCH v2 2/7] MIPS: Allow to prefetch and lock instructions into cache Gregory CLEMENT
@ 2018-10-09 11:58 ` Gregory CLEMENT
2018-10-28 18:50 ` Daniel Schwierzeck
2018-10-09 11:58 ` [U-Boot] [PATCH v2 4/7] MSCC: add support for Luton SoCs Gregory CLEMENT
` (3 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Gregory CLEMENT @ 2018-10-09 11:58 UTC (permalink / raw)
To: u-boot
This family of SoCs are found in the Microsemi Switches solution and have
already a support in the linux kernel.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/Kconfig | 6 +
arch/mips/Makefile | 1 +
arch/mips/mach-mscc/Kconfig | 69 ++
arch/mips/mach-mscc/Makefile | 5 +
arch/mips/mach-mscc/cpu.c | 42 ++
arch/mips/mach-mscc/dram.c | 61 ++
arch/mips/mach-mscc/include/ioremap.h | 51 ++
arch/mips/mach-mscc/include/mach/common.h | 27 +
arch/mips/mach-mscc/include/mach/ddr.h | 680 ++++++++++++++++++
.../mach-mscc/include/mach/ocelot/ocelot.h | 35 +
.../include/mach/ocelot/ocelot_devcpu_gcb.h | 21 +
.../include/mach/ocelot/ocelot_icpu_cfg.h | 274 +++++++
arch/mips/mach-mscc/include/mach/tlb.h | 55 ++
arch/mips/mach-mscc/lowlevel_init.S | 23 +
arch/mips/mach-mscc/reset.c | 36 +
15 files changed, 1386 insertions(+)
create mode 100644 arch/mips/mach-mscc/Kconfig
create mode 100644 arch/mips/mach-mscc/Makefile
create mode 100644 arch/mips/mach-mscc/cpu.c
create mode 100644 arch/mips/mach-mscc/dram.c
create mode 100644 arch/mips/mach-mscc/include/ioremap.h
create mode 100644 arch/mips/mach-mscc/include/mach/common.h
create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h
create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h
create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h
create mode 100644 arch/mips/mach-mscc/lowlevel_init.S
create mode 100644 arch/mips/mach-mscc/reset.c
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 071dea04ec..da479f2172 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -59,6 +59,11 @@ config ARCH_ATH79
select OF_CONTROL
imply CMD_DM
+config ARCH_MSCC
+ bool "Support MSCC VCore-III"
+ select OF_CONTROL
+ select DM
+
config ARCH_BMIPS
bool "Support BMIPS SoCs"
select CLK
@@ -135,6 +140,7 @@ source "board/imgtec/xilfpga/Kconfig"
source "board/micronas/vct/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
+source "arch/mips/mach-mscc/Kconfig"
source "arch/mips/mach-bmips/Kconfig"
source "arch/mips/mach-pic32/Kconfig"
source "arch/mips/mach-mt7620/Kconfig"
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 802244a06e..124e93fa26 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -15,6 +15,7 @@ machine-$(CONFIG_ARCH_ATH79) += ath79
machine-$(CONFIG_ARCH_BMIPS) += bmips
machine-$(CONFIG_MACH_PIC32) += pic32
machine-$(CONFIG_ARCH_MT7620) += mt7620
+machine-$(CONFIG_ARCH_MSCC) += mscc
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
libs-y += $(machdirs)
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
new file mode 100644
index 0000000000..7f1b270207
--- /dev/null
+++ b/arch/mips/mach-mscc/Kconfig
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+menu "MSCC VCore-III platforms"
+ depends on ARCH_MSCC
+
+config SOC_VCOREIII
+ select MIPS_TUNE_24KC
+ select ROM_EXCEPTION_VECTORS
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
+ select SUPPORTS_LITTLE_ENDIAN
+ bool
+
+config SYS_SOC
+ default "mscc"
+
+config SOC_OCELOT
+ bool
+ select SOC_VCOREIII
+ help
+ This supports MSCC Ocelot family of SOCs.
+
+config SYS_CONFIG_NAME
+ default "vcoreiii"
+
+choice
+ prompt "Board select"
+
+config TARGET_OCELOT_PCB120
+ bool "MSCC PCB120 Reference Board (aka VSC5635EV)"
+ select SOC_OCELOT
+ help
+ When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
+ ocelot_pcb120
+
+config TARGET_OCELOT_PCB123
+ bool "MSCC PCB123 Reference Board (aka VSC7514EV))"
+ select SOC_OCELOT
+ help
+ When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
+ ocelot_pcb123
+
+endchoice
+
+choice
+ prompt "DDR type"
+
+config DDRTYPE_H5TQ4G63MFR
+ bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)"
+
+config DDRTYPE_MT41K256M16
+ bool "Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16)"
+
+config DDRTYPE_H5TQ1G63BFA
+ bool "Hynix H5TQ1G63BFA (1Gbit DDR3, x16)"
+
+config DDRTYPE_MT41J128M16HA
+ bool "Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16)"
+
+config DDRTYPE_MT41K128M16JT
+ bool "Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16)"
+
+config DDRTYPE_MT47H128M8HQ
+ bool "Micron MT47H128M8-3 (1Gbit, DDR-533 at CL4 @ 4.80ns 16Mbisx8x8)"
+
+endchoice
+
+endmenu
diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
new file mode 100644
index 0000000000..d14ec33838
--- /dev/null
+++ b/arch/mips/mach-mscc/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+CFLAGS_cpu.o += -finline-limit=64000
+
+obj-y += cpu.o dram.o reset.o lowlevel_init.o
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
new file mode 100644
index 0000000000..0c8f7933cd
--- /dev/null
+++ b/arch/mips/mach-mscc/cpu.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/types.h>
+
+#include <mach/tlb.h>
+#include <mach/ddr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* NOTE: lowlevel_init() function does not have access to the
+ * stack. Thus, all called functions must be inlined, and (any) local
+ * variables must be kept in registers.
+ */
+void vcoreiii_tlb_init(void)
+{
+ register int tlbix = 0;
+
+ /*
+ * Unlike most of the MIPS based SoCs, the IO register address
+ * are not in KSEG0. The mainline linux kernel built in legacy
+ * mode needs to access some of the registers very early in
+ * the boot and make the assumption that the bootloader has
+ * already configured them, so we have to match this
+ * expectation.
+ */
+ create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW,
+ MMU_REGIO_RW);
+}
+
+int mach_cpu_init(void)
+{
+ /* Speed up NOR flash access */
+ writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
+ ICPU_SPI_MST_CFG_CLK_DIV(9), REG_CFG(ICPU_SPI_MST_CFG));
+ return 0;
+}
diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
new file mode 100644
index 0000000000..b82961f773
--- /dev/null
+++ b/arch/mips/mach-mscc/dram.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/types.h>
+
+#include <mach/tlb.h>
+#include <mach/ddr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int vcoreiii_ddr_init(void)
+{
+ int res;
+
+ if (!(readl(REG_CFG(ICPU_MEMCTRL_STAT))
+ & ICPU_MEMCTRL_STAT_INIT_DONE)) {
+ hal_vcoreiii_init_memctl();
+ hal_vcoreiii_wait_memctl();
+ if (hal_vcoreiii_init_dqs() != 0 ||
+ hal_vcoreiii_train_bytelane(0) != 0
+ || hal_vcoreiii_train_bytelane(1) != 0
+ )
+ hal_vcoreiii_ddr_failed();
+ }
+#if (CONFIG_SYS_TEXT_BASE != 0x20000000)
+ res = dram_check();
+ if (res == 0)
+ hal_vcoreiii_ddr_verified();
+ else
+ hal_vcoreiii_ddr_failed();
+
+ /* Clear boot-mode and read-back to activate/verify */
+ clrbits_le32(REG_CFG(ICPU_GENERAL_CTRL),
+ ICPU_GENERAL_CTRL_BOOT_MODE_ENA);
+ readl(REG_CFG(ICPU_GENERAL_CTRL));
+#else
+ res = 0;
+#endif
+ return res;
+}
+
+int print_cpuinfo(void)
+{
+ printf("MSCC VCore-III MIPS 24Kec\n");
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ while (vcoreiii_ddr_init())
+ ;
+
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ return 0;
+}
diff --git a/arch/mips/mach-mscc/include/ioremap.h b/arch/mips/mach-mscc/include/ioremap.h
new file mode 100644
index 0000000000..8ea5c65ce3
--- /dev/null
+++ b/arch/mips/mach-mscc/include/ioremap.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef __ASM_MACH_MSCC_IOREMAP_H
+#define __ASM_MACH_MSCC_IOREMAP_H
+
+#include <linux/types.h>
+#include <mach/common.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
+ phys_addr_t size)
+{
+ return phys_addr;
+}
+
+static inline int is_vcoreiii_internal_registers(phys_addr_t offset)
+{
+#if defined(CONFIG_ARCH_MSCC)
+ if ((offset >= MSCC_IO_ORIGIN1_OFFSET &&
+ offset < (MSCC_IO_ORIGIN1_OFFSET + MSCC_IO_ORIGIN1_SIZE)) ||
+ (offset >= MSCC_IO_ORIGIN2_OFFSET &&
+ offset < (MSCC_IO_ORIGIN2_OFFSET + MSCC_IO_ORIGIN2_SIZE)))
+ return 1;
+#endif
+
+ return 0;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+ unsigned long flags)
+{
+ if (is_vcoreiii_internal_registers(offset))
+ return (void __iomem *)offset;
+
+ return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+ return is_vcoreiii_internal_registers((unsigned long)addr);
+}
+
+#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
+
+#endif /* __ASM_MACH_MSCC_IOREMAP_H */
diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h
new file mode 100644
index 0000000000..41887097f9
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef __ASM_MACH_COMMON_H
+#define __ASM_MACH_COMMON_H
+
+// Stick to using register offsets - matching readl()/writel() prototypes
+#define MSCC_IOREG(t, o) ((void *)MSCC_IOADDR(t, o))
+
+#if defined(CONFIG_SOC_OCELOT)
+#include <mach/ocelot/ocelot.h>
+#include <mach/ocelot/ocelot_devcpu_gcb.h>
+#include <mach/ocelot/ocelot_icpu_cfg.h>
+#else
+#error Unsupported platform
+#endif
+
+#define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */
+#define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */
+#define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */
+#define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */
+
+#define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */
+
+#endif /* __ASM_MACH_COMMON_H */
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h
new file mode 100644
index 0000000000..c089af8e33
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -0,0 +1,680 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef __ASM_MACH_DDR_H
+#define __ASM_MACH_DDR_H
+
+#include <asm/cacheops.h>
+#include <asm/io.h>
+#include <asm/reboot.h>
+#include <mach/common.h>
+
+#define MIPS_VCOREIII_MEMORY_DDR3
+#define MIPS_VCOREIII_DDR_SIZE CONFIG_SYS_SDRAM_SIZE
+
+#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) /* Serval1 Refboard */
+
+/* Hynix H5TQ1G63BFA (1Gbit DDR3, x16) @ 3.20ns */
+#define VC3_MPAR_bank_addr_cnt 3
+#define VC3_MPAR_row_addr_cnt 13
+#define VC3_MPAR_col_addr_cnt 10
+#define VC3_MPAR_tREFI 2437
+#define VC3_MPAR_tRAS_min 12
+#define VC3_MPAR_CL 6
+#define VC3_MPAR_tWTR 4
+#define VC3_MPAR_tRC 16
+#define VC3_MPR_tFAW 16
+#define VC3_MPAR_tRP 5
+#define VC3_MPAR_tRRD 4
+#define VC3_MPAR_tRCD 5
+#define VC3_MPAR_tMRD 4
+#define VC3_MPAR_tRFC 35
+#define VC3_MPAR_CWL 5
+#define VC3_MPAR_tXPR 38
+#define VC3_MPAR_tMOD 12
+#define VC3_MPAR_tDLLK 512
+#define VC3_MPAR_tWR 5
+
+#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) /* Validation board */
+
+/* Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16) @ 3.20ns */
+#define VC3_MPAR_bank_addr_cnt 3
+#define VC3_MPAR_row_addr_cnt 14
+#define VC3_MPAR_col_addr_cnt 10
+#define VC3_MPAR_tREFI 2437
+#define VC3_MPAR_tRAS_min 12
+#define VC3_MPAR_CL 5
+#define VC3_MPAR_tWTR 4
+#define VC3_MPAR_tRC 16
+#define VC3_MPAR_tFAW 16
+#define VC3_MPAR_tRP 5
+#define VC3_MPAR_tRRD 4
+#define VC3_MPAR_tRCD 5
+#define VC3_MPAR_tMRD 4
+#define VC3_MPAR_tRFC 50
+#define VC3_MPAR_CWL 5
+#define VC3_MPAR_tXPR 54
+#define VC3_MPAR_tMOD 12
+#define VC3_MPAR_tDLLK 512
+#define VC3_MPAR_tWR 5
+
+#elif defined(CONFIG_DDRTYPE_MT41K256M16) /* JR2 Validation board */
+
+/* Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16) @ 3.20ns */
+#define VC3_MPAR_bank_addr_cnt 3
+#define VC3_MPAR_row_addr_cnt 15
+#define VC3_MPAR_col_addr_cnt 10
+#define VC3_MPAR_tREFI 2437
+#define VC3_MPAR_tRAS_min 12
+#define VC3_MPAR_CL 5
+#define VC3_MPAR_tWTR 4
+#define VC3_MPAR_tRC 16
+#define VC3_MPAR_tFAW 16
+#define VC3_MPAR_tRP 5
+#define VC3_MPAR_tRRD 4
+#define VC3_MPAR_tRCD 5
+#define VC3_MPAR_tMRD 4
+#define VC3_MPAR_tRFC 82
+#define VC3_MPAR_CWL 5
+#define VC3_MPAR_tXPR 85
+#define VC3_MPAR_tMOD 12
+#define VC3_MPAR_tDLLK 512
+#define VC3_MPAR_tWR 5
+
+#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) /* JR2 Reference board */
+
+/* Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16) - 2kb pages @ 3.20ns */
+#define VC3_MPAR_bank_addr_cnt 3
+#define VC3_MPAR_row_addr_cnt 15
+#define VC3_MPAR_col_addr_cnt 10
+#define VC3_MPAR_tREFI 2437
+#define VC3_MPAR_tRAS_min 12
+#define VC3_MPAR_CL 6
+#define VC3_MPAR_tWTR 4
+#define VC3_MPAR_tRC 17
+#define VC3_MPAR_tFAW 16
+#define VC3_MPAR_tRP 5
+#define VC3_MPAR_tRRD 4
+#define VC3_MPAR_tRCD 5
+#define VC3_MPAR_tMRD 4
+#define VC3_MPAR_tRFC 82
+#define VC3_MPAR_CWL 5
+#define VC3_MPAR_tXPR 85
+#define VC3_MPAR_tMOD 12
+#define VC3_MPAR_tDLLK 512
+#define VC3_MPAR_tWR 5
+
+#elif defined(CONFIG_DDRTYPE_MT41K128M16JT)
+
+/* Micron Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16) @ 3.20ns */
+#define VC3_MPAR_bank_addr_cnt 3
+#define VC3_MPAR_row_addr_cnt 14
+#define VC3_MPAR_col_addr_cnt 10
+#define VC3_MPAR_tREFI 2437
+#define VC3_MPAR_tRAS_min 12
+#define VC3_MPAR_CL 6
+#define VC3_MPAR_tWTR 4
+#define VC3_MPAR_tRC 16
+#define VC3_MPAR_tFAW 16
+#define VC3_MPAR_tRP 5
+#define VC3_MPAR_tRRD 4
+#define VC3_MPAR_tRCD 5
+#define VC3_MPAR_tMRD 4
+#define VC3_MPAR_tRFC 82
+#define VC3_MPAR_CWL 5
+#define VC3_MPAR_tXPR 85
+#define VC3_MPAR_tMOD 12
+#define VC3_MPAR_tDLLK 512
+#define VC3_MPAR_tWR 5
+
+#elif defined(CONFIG_DDRTYPE_MT47H128M8HQ) /* Luton10/26 Refboards */
+
+/* Micron 1Gb MT47H128M8-3 16Meg x 8 x 8 banks, DDR-533 at CL4 @ 4.80ns */
+#define VC3_MPAR_bank_addr_cnt 3
+#define VC3_MPAR_row_addr_cnt 14
+#define VC3_MPAR_col_addr_cnt 10
+#define VC3_MPAR_tREFI 1625
+#define VC3_MPAR_tRAS_min 9
+#define VC3_MPAR_CL 4
+#define VC3_MPAR_tWTR 2
+#define VC3_MPAR_tRC 12
+#define VC3_MPAR_tFAW 8
+#define VC3_MPAR_tRP 4
+#define VC3_MPAR_tRRD 2
+#define VC3_MPAR_tRCD 4
+
+#define VC3_MPAR_tRPA 4
+#define VC3_MPAR_tRP 4
+
+#define VC3_MPAR_tMRD 2
+#define VC3_MPAR_tRFC 27
+
+#define VC3_MPAR__400_ns_dly 84
+
+#define VC3_MPAR_tWR 4
+#undef MIPS_VCOREIII_MEMORY_DDR3
+#else
+
+#error Unknown DDR system configuration - please add!
+
+#endif
+
+#ifdef CONFIG_SOC_OCELOT
+#define MIPS_VCOREIII_MEMORY_16BIT 1
+#endif
+
+#define MIPS_VCOREIII_MEMORY_SSTL_ODT 7
+#define MIPS_VCOREIII_MEMORY_SSTL_DRIVE 7
+#define VCOREIII_DDR_DQS_MODE_CALIBRATE
+
+#ifdef MIPS_VCOREIII_MEMORY_16BIT
+#define VC3_MPAR_16BIT 1
+#else
+#define VC3_MPAR_16BIT 0
+#endif
+
+#ifdef MIPS_VCOREIII_MEMORY_DDR3
+#define VC3_MPAR_DDR3_MODE 1 /* DDR3 */
+#define VC3_MPAR_BURST_LENGTH 8 /* Always 8 (1) for DDR3 */
+#ifdef MIPS_VCOREIII_MEMORY_16BIT
+#define VC3_MPAR_BURST_SIZE 1 /* Always 1 for DDR3/16bit */
+#else
+#define VC3_MPAR_BURST_SIZE 0
+#endif
+#else
+#define VC3_MPAR_DDR3_MODE 0 /* DDR2 */
+#ifdef MIPS_VCOREIII_MEMORY_16BIT
+#define VC3_MPAR_BURST_LENGTH 4 /* in DDR2 16-bit mode, use burstlen 4 */
+#else
+#define VC3_MPAR_BURST_LENGTH 8 /* For 8-bit IF we must run burst-8 */
+#endif
+#define VC3_MPAR_BURST_SIZE 0 /* Always 0 for DDR2 */
+#endif
+
+#define VC3_MPAR_RL VC3_MPAR_CL
+#if !defined(MIPS_VCOREIII_MEMORY_DDR3)
+#define VC3_MPAR_WL (VC3_MPAR_RL - 1)
+#define VC3_MPAR_MD VC3_MPAR_tMRD
+#define VC3_MPAR_ID VC3_MPAR__400_ns_dly
+#define VC3_MPAR_SD VC3_MPAR_tXSRD
+#define VC3_MPAR_OW (VC3_MPAR_WL - 2)
+#define VC3_MPAR_OR (VC3_MPAR_WL - 3)
+#define VC3_MPAR_RP (VC3_MPAR_bank_addr_cnt < 3 ? VC3_MPAR_tRP : VC3_MPAR_tRPA)
+#define VC3_MPAR_FAW (VC3_MPAR_bank_addr_cnt < 3 ? 1 : VC3_MPAR_tFAW)
+#define VC3_MPAR_BL (VC3_MPAR_BURST_LENGTH == 4 ? 2 : 4)
+#define MSCC_MEMPARM_MR0 \
+ (VC3_MPAR_BURST_LENGTH == 8 ? 3 : 2) | (VC3_MPAR_CL << 4) | \
+ ((VC3_MPAR_tWR - 1) << 9)
+/* DLL-on, Full-OD, AL=0, RTT=off, nDQS-on, RDQS-off, out-en */
+#define MSCC_MEMPARM_MR1 0x382
+#define MSCC_MEMPARM_MR2 0
+#define MSCC_MEMPARM_MR3 0
+#else
+#define VC3_MPAR_WL VC3_MPAR_CWL
+#define VC3_MPAR_MD VC3_MPAR_tMOD
+#define VC3_MPAR_ID VC3_MPAR_tXPR
+#define VC3_MPAR_SD VC3_MPAR_tDLLK
+#define VC3_MPAR_OW 2
+#define VC3_MPAR_OR 2
+#define VC3_MPAR_RP VC3_MPAR_tRP
+#define VC3_MPAR_FAW VC3_MPAR_tFAW
+#define VC3_MPAR_BL 4
+#define MSCC_MEMPARM_MR0 ((VC3_MPAR_RL - 4) << 4) | ((VC3_MPAR_tWR - 4) << 9)
+/* ODT_RTT: “0x0040” for 120ohm, and “0x0004” for 60ohm. */
+#define MSCC_MEMPARM_MR1 0x0040
+#define MSCC_MEMPARM_MR2 ((VC3_MPAR_WL - 5) << 3)
+#define MSCC_MEMPARM_MR3 0
+#endif /* MIPS_VCOREIII_MEMORY_DDR3 */
+
+#define MSCC_MEMPARM_MEMCFG \
+ ((MIPS_VCOREIII_DDR_SIZE > SZ_512M) ? \
+ ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS : 0) | \
+ (VC3_MPAR_16BIT ? ICPU_MEMCTRL_CFG_DDR_WIDTH : 0) | \
+ (VC3_MPAR_DDR3_MODE ? ICPU_MEMCTRL_CFG_DDR_MODE : 0) | \
+ (VC3_MPAR_BURST_SIZE ? ICPU_MEMCTRL_CFG_BURST_SIZE : 0) | \
+ (VC3_MPAR_BURST_LENGTH == 8 ? ICPU_MEMCTRL_CFG_BURST_LEN : 0) | \
+ (VC3_MPAR_bank_addr_cnt == 3 ? ICPU_MEMCTRL_CFG_BANK_CNT : 0) | \
+ ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(VC3_MPAR_row_addr_cnt - 1) | \
+ ICPU_MEMCTRL_CFG_MSB_COL_ADDR(VC3_MPAR_col_addr_cnt - 1)
+
+#ifdef CONFIG_SOC_OCELOT
+#define MSCC_MEMPARM_PERIOD \
+ ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(8) | \
+ ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
+
+#define MSCC_MEMPARM_TIMING0 \
+ ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(VC3_MPAR_RL + VC3_MPAR_BL + 1 - \
+ VC3_MPAR_WL) | \
+ ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(VC3_MPAR_BL - 1) | \
+ ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(VC3_MPAR_BL) | \
+ ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(VC3_MPAR_tRAS_min - 1) | \
+ ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(VC3_MPAR_WL + \
+ VC3_MPAR_BL + \
+ VC3_MPAR_tWR - 1) | \
+ ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(VC3_MPAR_BL - 1) | \
+ ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(VC3_MPAR_WL - 1) | \
+ ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(VC3_MPAR_RL - 3)
+
+#define MSCC_MEMPARM_TIMING1 \
+ ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(VC3_MPAR_tRC - 1) | \
+ ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(VC3_MPAR_FAW - 1) | \
+ ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(VC3_MPAR_RP - 1) | \
+ ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(VC3_MPAR_tRRD - 1) | \
+ ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(VC3_MPAR_tRCD - 1) | \
+ ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(VC3_MPAR_WL + \
+ VC3_MPAR_BL + \
+ VC3_MPAR_tWTR - 1)
+
+#define MSCC_MEMPARM_TIMING2 \
+ ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(VC3_MPAR_RP - 1) | \
+ ICPU_MEMCTRL_TIMING2_MDSET_DLY(VC3_MPAR_MD - 1) | \
+ ICPU_MEMCTRL_TIMING2_REF_DLY(VC3_MPAR_tRFC - 1) | \
+ ICPU_MEMCTRL_TIMING2_INIT_DLY(VC3_MPAR_ID - 1)
+
+#define MSCC_MEMPARM_TIMING3 \
+ ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(VC3_MPAR_WL + \
+ VC3_MPAR_tWTR - 1) |\
+ ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(VC3_MPAR_OR - 1) | \
+ ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(VC3_MPAR_OW - 1) | \
+ ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(VC3_MPAR_RL - 3)
+
+#else
+#define MSCC_MEMPARM_PERIOD \
+ ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(1) | \
+ ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
+
+#define MSCC_MEMPARM_TIMING0 \
+ ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(VC3_MPAR_tRAS_min - 1) | \
+ ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(VC3_MPAR_CL + \
+ (VC3_MPAR_BURST_LENGTH == 8 ? 2 : 0) + \
+ VC3_MPAR_tWR) | \
+ ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(VC3_MPAR_BURST_LENGTH == 8 ? 3 : 1) | \
+ ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(VC3_MPAR_CL - 3) | \
+ ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(VC3_MPAR_CL - 3)
+
+#define MSCC_MEMPARM_TIMING1 \
+ ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(VC3_MPAR_tRC - 1) | \
+ ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(VC3_MPAR_tFAW - 1) | \
+ ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(VC3_MPAR_tRP - 1) | \
+ ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(VC3_MPAR_tRRD - 1) | \
+ ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(VC3_MPAR_tRCD - 1) | \
+ ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(VC3_MPAR_CL + \
+ (VC3_MPAR_BURST_LENGTH == 8 ? 2 : 0) + \
+ VC3_MPAR_tWTR)
+#define MSCC_MEMPARM_TIMING2 \
+ ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(VC3_MPAR_tRPA - 1) | \
+ ICPU_MEMCTRL_TIMING2_MDSET_DLY(VC3_MPAR_tMRD - 1) | \
+ ICPU_MEMCTRL_TIMING2_REF_DLY(VC3_MPAR_tRFC - 1) | \
+ ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY(VC3_MPAR__400_ns_dly)
+
+#define MSCC_MEMPARM_TIMING3 \
+ ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(VC3_MPAR_CL - 1) | \
+ ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(VC3_MPAR_CL - 1) | \
+ ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(VC3_MPAR_CL - 1)
+
+#endif
+
+enum {
+ DDR_TRAIN_OK,
+ DDR_TRAIN_CONTINUE,
+ DDR_TRAIN_ERROR,
+};
+
+/*
+ * We actually have very few 'pause' possibilities apart from
+ * these assembly nops (at this very early stage).
+ */
+#define PAUSE() asm volatile("nop; nop; nop; nop; nop; nop; nop; nop")
+
+/* NB: Assumes inlining as no stack is available! */
+static inline void set_dly(u32 bytelane, u32 dly)
+{
+ register u32 r = readl(REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane)));
+
+ r &= ~ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M;
+ r |= ICPU_MEMCTRL_DQS_DLY_DQS_DLY(dly);
+ writel(r, REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane)));
+}
+
+static inline bool incr_dly(u32 bytelane)
+{
+ register u32 r = readl(REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane)));
+
+ if (ICPU_MEMCTRL_DQS_DLY_DQS_DLY(r) < 31) {
+ writel(r + 1, REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane)));
+ return true;
+ }
+
+ return false;
+}
+
+static inline bool adjust_dly(int adjust)
+{
+ register u32 r = readl(REG_CFG(ICPU_MEMCTRL_DQS_DLY(0)));
+
+ if (ICPU_MEMCTRL_DQS_DLY_DQS_DLY(r) < 31) {
+ writel(r + adjust, REG_CFG(ICPU_MEMCTRL_DQS_DLY(0)));
+ return true;
+ }
+
+ return false;
+}
+
+/* NB: Assumes inlining as no stack is available! */
+static inline void center_dly(u32 bytelane, u32 start)
+{
+ register u32 r = readl(REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane))) - start;
+
+ writel(start + (r >> 1), REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane)));
+}
+
+static inline void memphy_soft_reset(void)
+{
+ setbits_le32(REG_CFG(ICPU_MEMPHY_CFG), ICPU_MEMPHY_CFG_PHY_FIFO_RST);
+ PAUSE();
+ clrbits_le32(REG_CFG(ICPU_MEMPHY_CFG), ICPU_MEMPHY_CFG_PHY_FIFO_RST);
+ PAUSE();
+}
+
+#ifdef CONFIG_SOC_OCELOT
+static u8 training_data[] = { 0xfe, 0x11, 0x33, 0x55, 0x77, 0x99, 0xbb, 0xdd };
+
+static inline void sleep_100ns(u32 val)
+{
+ /* Set the timer tick generator to 100 ns */
+ writel(VCOREIII_TIMER_DIVIDER - 1, REG_CFG(ICPU_TIMER_TICK_DIV));
+
+ /* Set the timer value */
+ writel(val, REG_CFG(ICPU_TIMER_VALUE(0)));
+
+ /* Enable timer 0 for one-shot */
+ writel(ICPU_TIMER_CTRL_ONE_SHOT_ENA | ICPU_TIMER_CTRL_TIMER_ENA,
+ REG_CFG(ICPU_TIMER_CTRL(0)));
+
+ /* Wait for timer 0 to reach 0 */
+ while (readl(REG_CFG(ICPU_TIMER_VALUE(0))) != 0)
+ ;
+}
+
+static inline void hal_vcoreiii_ddr_reset_assert(void)
+{
+ /* DDR has reset pin on GPIO 19 toggle Low-High to release */
+ setbits_le32(REG_GCB(PERF_GPIO_OE), BIT(19));
+ writel(BIT(19), REG_GCB(PERF_GPIO_OUT_CLR));
+ sleep_100ns(10000);
+}
+
+static inline void hal_vcoreiii_ddr_reset_release(void)
+{
+ /* DDR has reset pin on GPIO 19 toggle Low-High to release */
+ setbits_le32(REG_GCB(PERF_GPIO_OE), BIT(19));
+ writel(BIT(19), REG_GCB(PERF_GPIO_OUT_SET));
+ sleep_100ns(10000);
+}
+
+/*
+ * DDR memory sanity checking failed, tally and do hard reset
+ *
+ * NB: Assumes inlining as no stack is available!
+ */
+static inline void hal_vcoreiii_ddr_failed(void)
+{
+ register u32 reset;
+
+ writel(readl(REG_CFG(ICPU_GPR(6))) + 1, REG_CFG(ICPU_GPR(6)));
+
+ clrbits_le32(REG_GCB(PERF_GPIO_OE), BIT(19));
+
+ /* Jump to reset - does not return */
+ reset = KSEG0ADDR(_machine_restart);
+ /* Reset while running from cache */
+ icache_lock((void *)reset, 128);
+ asm volatile ("jr %0"::"r" (reset));
+
+ panic("DDR init failed\n");
+}
+
+/*
+ * DDR memory sanity checking done, possibly enable ECC.
+ *
+ * NB: Assumes inlining as no stack is available!
+ */
+static inline void hal_vcoreiii_ddr_verified(void)
+{
+#ifdef MIPS_VCOREIII_MEMORY_ECC
+ /* Finally, enable ECC */
+ register u32 val = readl(REG_CFG(ICPU_MEMCTRL_CFG));
+
+ val |= ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA;
+ val &= ~ICPU_MEMCTRL_CFG_BURST_SIZE;
+
+ writel(val, REG_CFG(ICPU_MEMCTRL_CFG));
+#endif
+
+ /* Reset Status register - sticky bits */
+ writel(readl(REG_CFG(ICPU_MEMCTRL_STAT)), REG_CFG(ICPU_MEMCTRL_STAT));
+}
+
+/* NB: Assumes inlining as no stack is available! */
+static inline int look_for(u32 bytelane)
+{
+ register u32 i;
+
+ /* Reset FIFO in case any previous access failed */
+ for (i = 0; i < sizeof(training_data); i++) {
+ register u32 byte;
+
+ memphy_soft_reset();
+ /* Reset sticky bits */
+ writel(readl(REG_CFG(ICPU_MEMCTRL_STAT)),
+ REG_CFG(ICPU_MEMCTRL_STAT));
+ /* Read data */
+ byte = ((volatile u8 *)MSCC_DDR_TO)[bytelane + (i * 4)];
+ if (readl(REG_CFG(ICPU_MEMCTRL_STAT)) &
+ (ICPU_MEMCTRL_STAT_RDATA_MASKED |
+ ICPU_MEMCTRL_STAT_RDATA_DUMMY)) {
+ /* Noise on the line */
+ goto read_error;
+ }
+ /* If mismatch, increment DQS - if possible */
+ if (byte != training_data[i]) {
+ read_error:
+ if (!incr_dly(bytelane))
+ return DDR_TRAIN_ERROR;
+ return DDR_TRAIN_CONTINUE;
+ }
+ }
+ return DDR_TRAIN_OK;
+}
+
+/* NB: Assumes inlining as no stack is available! */
+static inline int look_past(u32 bytelane)
+{
+ register u32 i;
+
+ /* Reset FIFO in case any previous access failed */
+ for (i = 0; i < sizeof(training_data); i++) {
+ register u32 byte;
+
+ memphy_soft_reset();
+ /* Ack sticky bits */
+ writel(readl(REG_CFG(ICPU_MEMCTRL_STAT)),
+ REG_CFG(ICPU_MEMCTRL_STAT));
+ byte = ((volatile u8 *)MSCC_DDR_TO)[bytelane + (i * 4)];
+ if (readl(REG_CFG(ICPU_MEMCTRL_STAT)) &
+ (ICPU_MEMCTRL_STAT_RDATA_MASKED |
+ ICPU_MEMCTRL_STAT_RDATA_DUMMY)) {
+ /* Noise on the line */
+ goto read_error;
+ }
+ /* Bail out when we see first mismatch */
+ if (byte != training_data[i]) {
+ read_error:
+ return DDR_TRAIN_OK;
+ }
+ }
+ /* All data compares OK, increase DQS and retry */
+ if (!incr_dly(bytelane))
+ return DDR_TRAIN_ERROR;
+
+ return DDR_TRAIN_CONTINUE;
+}
+
+static inline int hal_vcoreiii_train_bytelane(u32 bytelane)
+{
+ register int res;
+ register u32 dqs_s;
+
+ set_dly(bytelane, 0); // Start training@DQS=0
+ while ((res = look_for(bytelane)) == DDR_TRAIN_CONTINUE)
+ ;
+ if (res != DDR_TRAIN_OK)
+ return res;
+
+ dqs_s = readl(REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane)));
+ while ((res = look_past(bytelane)) == DDR_TRAIN_CONTINUE)
+ ;
+ if (res != DDR_TRAIN_OK)
+ return res;
+ /* Reset FIFO - for good measure */
+ memphy_soft_reset();
+ /* Adjust to center [dqs_s;cur] */
+ center_dly(bytelane, dqs_s);
+ return DDR_TRAIN_OK;
+}
+
+/* This algorithm is converted from the TCL training algorithm used
+ * during silicon simulation.
+ * NB: Assumes inlining as no stack is available!
+ */
+static inline int hal_vcoreiii_init_dqs(void)
+{
+#define MAX_DQS 32
+ register u32 i, j;
+
+ for (i = 0; i < MAX_DQS; i++) {
+ set_dly(0, i); // Byte-lane 0
+ for (j = 0; j < MAX_DQS; j++) {
+ register u32 __attribute__ ((unused)) byte;
+ set_dly(1, j); // Byte-lane 1
+ /* Reset FIFO in case any previous access failed */
+ memphy_soft_reset();
+ writel(readl(REG_CFG(ICPU_MEMCTRL_STAT)),
+ REG_CFG(ICPU_MEMCTRL_STAT));
+ byte = ((volatile u8 *)MSCC_DDR_TO)[0];
+ byte = ((volatile u8 *)MSCC_DDR_TO)[1];
+ if (!(readl(REG_CFG(ICPU_MEMCTRL_STAT)) &
+ (ICPU_MEMCTRL_STAT_RDATA_MASKED |
+ ICPU_MEMCTRL_STAT_RDATA_DUMMY)))
+ return 0;
+ }
+ }
+ return -1;
+}
+
+static inline int dram_check(void)
+{
+#define DDR ((volatile u32 *) MSCC_DDR_TO)
+ register u32 i;
+
+ for (i = 0; i < 8; i++) {
+ DDR[i] = ~i;
+ if (DDR[i] != ~i)
+ return 1;
+ }
+ return 0;
+}
+/*
+ * NB: Called *early* to init memory controller - assumes inlining as
+ * no stack is available!
+ */
+static inline void hal_vcoreiii_init_memctl(void)
+{
+ /* Ensure DDR is in reset */
+ hal_vcoreiii_ddr_reset_assert();
+
+ /* Wait maybe not needed, but ... */
+ PAUSE();
+
+ /* Drop sys ctl memory controller forced reset */
+ clrbits_le32(REG_CFG(ICPU_RESET), ICPU_RESET_MEM_RST_FORCE);
+
+ PAUSE();
+
+ /* Drop Reset, enable SSTL */
+ writel(ICPU_MEMPHY_CFG_PHY_SSTL_ENA, REG_CFG(ICPU_MEMPHY_CFG));
+ PAUSE();
+
+ /* Start the automatic SSTL output and ODT drive-strength calibration */
+ writel(ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(MIPS_VCOREIII_MEMORY_SSTL_ODT) |
+ /* drive strength */
+ ICPU_MEMPHY_ZCAL_ZCAL_PROG(MIPS_VCOREIII_MEMORY_SSTL_DRIVE) |
+ /* Start calibration process */
+ ICPU_MEMPHY_ZCAL_ZCAL_ENA, REG_CFG(ICPU_MEMPHY_ZCAL));
+
+ /* Wait for ZCAL to clear */
+ while (readl(REG_CFG(ICPU_MEMPHY_ZCAL)) & ICPU_MEMPHY_ZCAL_ZCAL_ENA)
+ ;
+
+ /* Check no ZCAL_ERR */
+ if (readl(REG_CFG(ICPU_MEMPHY_ZCAL_STAT))
+ & ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR)
+ hal_vcoreiii_ddr_failed();
+
+ /* Drive CL, CK, ODT */
+ setbits_le32(REG_CFG(ICPU_MEMPHY_CFG), ICPU_MEMPHY_CFG_PHY_ODT_OE |
+ ICPU_MEMPHY_CFG_PHY_CK_OE | ICPU_MEMPHY_CFG_PHY_CL_OE);
+
+ /* Initialize memory controller */
+ writel(MSCC_MEMPARM_MEMCFG, REG_CFG(ICPU_MEMCTRL_CFG));
+ writel(MSCC_MEMPARM_PERIOD, REG_CFG(ICPU_MEMCTRL_REF_PERIOD));
+
+
+ writel(MSCC_MEMPARM_TIMING0, REG_CFG(ICPU_MEMCTRL_TIMING0));
+
+ writel(MSCC_MEMPARM_TIMING1, REG_CFG(ICPU_MEMCTRL_TIMING1));
+ writel(MSCC_MEMPARM_TIMING2, REG_CFG(ICPU_MEMCTRL_TIMING2));
+ writel(MSCC_MEMPARM_TIMING3, REG_CFG(ICPU_MEMCTRL_TIMING3));
+ writel(MSCC_MEMPARM_MR0, REG_CFG(ICPU_MEMCTRL_MR0_VAL));
+ writel(MSCC_MEMPARM_MR1, REG_CFG(ICPU_MEMCTRL_MR1_VAL));
+ writel(MSCC_MEMPARM_MR2, REG_CFG(ICPU_MEMCTRL_MR2_VAL));
+ writel(MSCC_MEMPARM_MR3, REG_CFG(ICPU_MEMCTRL_MR3_VAL));
+
+ /* Termination setup - enable ODT */
+ writel(ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA |
+ /* Assert ODT0 for any write */
+ ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(3),
+ REG_CFG(ICPU_MEMCTRL_TERMRES_CTRL));
+
+ /* Release Reset from DDR */
+ hal_vcoreiii_ddr_reset_release();
+
+ writel(readl(REG_CFG(ICPU_GPR(7))) + 1, REG_CFG(ICPU_GPR(7)));
+}
+
+static inline void hal_vcoreiii_wait_memctl(void)
+{
+ /* Now, rip it! */
+ writel(ICPU_MEMCTRL_CTRL_INITIALIZE, REG_CFG(ICPU_MEMCTRL_CTRL));
+
+ while (!(readl(REG_CFG(ICPU_MEMCTRL_STAT))
+ & ICPU_MEMCTRL_STAT_INIT_DONE))
+ ;
+
+ /* Settle...? */
+ sleep_100ns(10000);
+
+ /* Establish data contents in DDR RAM for training */
+
+ __raw_writel(0xcacafefe, ((void __iomem *)MSCC_DDR_TO));
+ __raw_writel(0x22221111, ((void __iomem *)MSCC_DDR_TO + 0x4));
+ __raw_writel(0x44443333, ((void __iomem *)MSCC_DDR_TO + 0x8));
+ __raw_writel(0x66665555, ((void __iomem *)MSCC_DDR_TO + 0xC));
+ __raw_writel(0x88887777, ((void __iomem *)MSCC_DDR_TO + 0x10));
+ __raw_writel(0xaaaa9999, ((void __iomem *)MSCC_DDR_TO + 0x14));
+ __raw_writel(0xccccbbbb, ((void __iomem *)MSCC_DDR_TO + 0x18));
+ __raw_writel(0xeeeedddd, ((void __iomem *)MSCC_DDR_TO + 0x1C));
+}
+#endif /* __ASM_MACH_DDR_H */
diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
new file mode 100644
index 0000000000..75b25bae62
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Microsemi Ocelot Switch driver
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_OCELOT_H_
+#define _MSCC_OCELOT_H_
+
+#include <linux/bitops.h>
+#include <dm.h>
+
+/*
+ * Target offset base(s)
+ */
+#define MSCC_IO_ORIGIN1_OFFSET 0x70000000
+#define MSCC_IO_ORIGIN1_SIZE 0x00200000
+#define MSCC_IO_ORIGIN2_OFFSET 0x71000000
+#define MSCC_IO_ORIGIN2_SIZE 0x01000000
+#ifndef MSCC_IO_OFFSET1
+#define MSCC_IO_OFFSET1(offset) (MSCC_IO_ORIGIN1_OFFSET + offset)
+#endif
+#ifndef MSCC_IO_OFFSET2
+#define MSCC_IO_OFFSET2(offset) (MSCC_IO_ORIGIN2_OFFSET + offset)
+#endif
+#define BASE_CFG 0x70000000
+#define BASE_UART 0x70100000
+#define BASE_DEVCPU_GCB 0x71070000
+
+#define REG_OFFSET(t, o) ((volatile unsigned long *)(t + (o)))
+#define REG_CFG(x) REG_OFFSET(BASE_CFG, x)
+#define REG_GCB(x) REG_OFFSET(BASE_DEVCPU_GCB, x)
+
+#endif
diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
new file mode 100644
index 0000000000..f8aa97ba26
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_OCELOT_DEVCPU_GCB_H_
+#define _MSCC_OCELOT_DEVCPU_GCB_H_
+
+#define PERF_SOFT_RST 0x8
+
+#define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2)
+#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)
+#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
+
+#define PERF_GPIO_OUT_SET 0x34
+
+#define PERF_GPIO_OUT_CLR 0x38
+
+#define PERF_GPIO_OE 0x44
+
+#endif
diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h
new file mode 100644
index 0000000000..04cf70bec3
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h
@@ -0,0 +1,274 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_OCELOT_ICPU_CFG_H_
+#define _MSCC_OCELOT_ICPU_CFG_H_
+
+#define ICPU_GPR(x) (0x4 * (x))
+#define ICPU_GPR_RSZ 0x4
+
+#define ICPU_RESET 0x20
+
+#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
+#define ICPU_RESET_CORE_RST_PROTECT BIT(2)
+#define ICPU_RESET_CORE_RST_FORCE BIT(1)
+#define ICPU_RESET_MEM_RST_FORCE BIT(0)
+
+#define ICPU_GENERAL_CTRL 0x24
+
+#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(14)
+#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(13)
+#define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12)
+#define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(11)
+#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ADDR_SEL BIT(10)
+#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(9)
+#define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(8)
+#define ICPU_GENERAL_CTRL_IF_PI_MST_ENA BIT(7)
+#define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(6)
+#define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4))
+#define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4)
+#define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
+#define ICPU_GENERAL_CTRL_SSI_MST_CONTENTION BIT(3)
+#define ICPU_GENERAL_CTRL_CPU_BE_ENA BIT(2)
+#define ICPU_GENERAL_CTRL_CPU_DIS BIT(1)
+#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0)
+#define ICPU_SPI_MST_CFG 0x3c
+
+#define ICPU_SPI_MST_CFG_A32B_ENA BIT(11)
+#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10)
+#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
+#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
+#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
+#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
+#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
+
+#define ICPU_SW_MODE 0x50
+
+#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
+#define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
+#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11)
+#define ICPU_SW_MODE_SW_SPI_SDO BIT(10)
+#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9)
+#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
+#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
+#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
+#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1))
+#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1)
+#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1)
+#define ICPU_SW_MODE_SW_SPI_SDI BIT(0)
+
+#define ICPU_INTR_ENA 0x88
+
+#define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x))
+#define ICPU_DST_INTR_MAP_RSZ 0x4
+
+#define ICPU_DST_INTR_IDENT 0xa8
+#define ICPU_DST_INTR_IDENT_RSZ 0x4
+
+#define ICPU_TIMER_TICK_DIV 0xe8
+#define ICPU_TIMER_VALUE(x) (0xec + 0x4 * (x))
+
+#define ICPU_TIMER_CTRL(x) (0x104 + 0x4 * (x))
+#define ICPU_TIMER_CTRL_MAX_FREQ_ENA BIT(3)
+#define ICPU_TIMER_CTRL_ONE_SHOT_ENA BIT(2)
+#define ICPU_TIMER_CTRL_TIMER_ENA BIT(1)
+#define ICPU_TIMER_CTRL_FORCE_RELOAD BIT(0)
+
+#define ICPU_MEMCTRL_CTRL 0x110
+#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3)
+#define ICPU_MEMCTRL_CTRL_MDSET BIT(2)
+#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1)
+#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0)
+
+#define ICPU_MEMCTRL_CFG 0x114
+
+#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16)
+#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15)
+#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14)
+#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13)
+#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12)
+#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11)
+#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10)
+#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9)
+#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8)
+#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_STAT 0x118
+
+#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5)
+#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4)
+#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3)
+#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2)
+#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1)
+#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0)
+
+#define ICPU_MEMCTRL_REF_PERIOD 0x11c
+
+#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16))
+#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16)
+#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16)
+#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0))
+#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0)
+
+#define ICPU_MEMCTRL_TIMING0 0x124
+
+#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28))
+#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28)
+#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
+#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24))
+#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24)
+#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
+#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20))
+#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20)
+#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20)
+#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16))
+#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16)
+#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12))
+#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12)
+#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
+#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8))
+#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8)
+#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_TIMING1 0x128
+
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24))
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24)
+#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16))
+#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16)
+#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12))
+#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12)
+#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8))
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_TIMING2 0x12c
+
+#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28))
+#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28)
+#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
+#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24))
+#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24)
+#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
+#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16))
+#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16)
+#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0))
+#define ICPU_MEMCTRL_TIMING2_INIT_DLY_M GENMASK(15, 0)
+
+#define ICPU_MEMCTRL_TIMING3 0x130
+
+#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16))
+#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16)
+#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12))
+#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12)
+#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
+#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8))
+#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8)
+#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_MR0_VAL 0x138
+
+#define ICPU_MEMCTRL_MR1_VAL 0x13c
+
+#define ICPU_MEMCTRL_MR2_VAL 0x140
+
+#define ICPU_MEMCTRL_MR3_VAL 0x144
+
+#define ICPU_MEMCTRL_TERMRES_CTRL 0x148
+
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7))
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2))
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2)
+#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1)
+#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0)
+
+#define ICPU_MEMCTRL_DQS_DLY(x) (0x150 + 0x4 * (x))
+#define ICPU_MEMCTRL_DQS_DLY_RSZ 0x4
+
+#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8))
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5))
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0))
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0)
+
+#define ICPU_MEMPHY_CFG 0x160
+
+#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10)
+#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9)
+#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8)
+#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7)
+#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6)
+#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5)
+#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4)
+#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3)
+#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2)
+#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1)
+#define ICPU_MEMPHY_CFG_PHY_RST BIT(0)
+
+#define ICPU_MEMPHY_ZCAL 0x188
+
+#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5))
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1))
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1)
+#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0)
+
+#define ICPU_MEMPHY_ZCAL_STAT 0x18c
+
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL(x) (((x) << 12) & GENMASK(31, 12))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_M GENMASK(31, 12)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_X(x) (((x) & GENMASK(31, 12)) >> 12)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU(x) (((x) << 8) & GENMASK(9, 8))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_M GENMASK(9, 8)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_X(x) (((x) & GENMASK(9, 8)) >> 8)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD(x) (((x) << 6) & GENMASK(7, 6))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_M GENMASK(7, 6)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_X(x) (((x) & GENMASK(7, 6)) >> 6)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU(x) (((x) << 4) & GENMASK(5, 4))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_M GENMASK(5, 4)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_X(x) (((x) & GENMASK(5, 4)) >> 4)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD(x) (((x) << 2) & GENMASK(3, 2))
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_M GENMASK(3, 2)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_X(x) (((x) & GENMASK(3, 2)) >> 2)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR BIT(1)
+#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_DONE BIT(0)
+#endif
diff --git a/arch/mips/mach-mscc/include/mach/tlb.h b/arch/mips/mach-mscc/include/mach/tlb.h
new file mode 100644
index 0000000000..fdb554f551
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/tlb.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef __ASM_MACH_TLB_H
+#define __ASM_MACH_TLB_H
+
+#include <asm/mipsregs.h>
+#include <mach/common.h>
+#include <linux/sizes.h>
+
+#define TLB_HI_MASK 0xffffe000
+#define TLB_LO_MASK 0x3fffffff /* Masks off Fill bits */
+#define TLB_LO_SHIFT 6 /* PFN Start bit */
+
+#define PAGEMASK_SHIFT 13
+
+#define MMU_PAGE_CACHED (3 << 3) /* C(5:3) Cache Coherency Attributes */
+#define MMU_PAGE_UNCACHED (2 << 3) /* C(5:3) Cache Coherency Attributes */
+#define MMU_PAGE_DIRTY BIT(2) /* = Writeable */
+#define MMU_PAGE_VALID BIT(1)
+#define MMU_PAGE_GLOBAL BIT(0)
+#define MMU_REGIO_RO_C (MMU_PAGE_CACHED | MMU_PAGE_VALID | MMU_PAGE_GLOBAL)
+#define MMU_REGIO_RO (MMU_PAGE_UNCACHED | MMU_PAGE_VALID | MMU_PAGE_GLOBAL)
+#define MMU_REGIO_RW (MMU_PAGE_DIRTY | MMU_REGIO_RO)
+#define MMU_REGIO_INVAL (MMU_PAGE_GLOBAL)
+
+#define TLB_COUNT_MASK GENMASK(5, 0)
+#define TLB_COUNT_OFF 25
+
+static inline u32 get_tlb_count(void)
+{
+ register u32 config1;
+
+ config1 = read_c0_config1();
+ config1 >>= TLB_COUNT_OFF;
+ config1 &= TLB_COUNT_MASK;
+
+ return 1 + config1;
+}
+
+static inline void create_tlb(int index, u32 offset, u32 size, u32 tlb_attrib1,
+ u32 tlb_attrib2)
+{
+ register u32 tlb_mask, tlb_lo0, tlb_lo1;
+
+ tlb_mask = ((size >> 12) - 1) << PAGEMASK_SHIFT;
+ tlb_lo0 = tlb_attrib1 | (offset >> TLB_LO_SHIFT);
+ tlb_lo1 = tlb_attrib2 | ((offset + size) >> TLB_LO_SHIFT);
+
+ write_one_tlb(index, tlb_mask, offset & TLB_HI_MASK,
+ tlb_lo0 & TLB_LO_MASK, tlb_lo1 & TLB_LO_MASK);
+}
+#endif /* __ASM_MACH_TLB_H */
diff --git a/arch/mips/mach-mscc/lowlevel_init.S b/arch/mips/mach-mscc/lowlevel_init.S
new file mode 100644
index 0000000000..e6dc9427e1
--- /dev/null
+++ b/arch/mips/mach-mscc/lowlevel_init.S
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+
+ .set noreorder
+ .extern vcoreiii_tlb_init
+
+LEAF(lowlevel_init)
+ /*
+ * As we have no stack yet, we can assume the restricted
+ * luxury of the sX-registers without saving them
+ */
+ move s0,ra
+
+ jal vcoreiii_tlb_init
+ nop
+ jr s0
+ nop
+ END(lowlevel_init)
diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c
new file mode 100644
index 0000000000..c4215ba228
--- /dev/null
+++ b/arch/mips/mach-mscc/reset.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+
+#include <asm/sections.h>
+#include <asm/io.h>
+
+#include <asm/reboot.h>
+
+void _machine_restart(void)
+{
+ register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
+ (void)readl(REG_GCB(PERF_SOFT_RST));
+
+ /*
+ * Make sure VCore is NOT protected from reset
+ */
+ clrbits_le32(REG_CFG(ICPU_RESET), ICPU_RESET_CORE_RST_PROTECT);
+
+ /*
+ * Change to SPI bitbang for SPI reset workaround...
+ */
+ writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) |
+ ICPU_SW_MODE_SW_PIN_CTRL_MODE, REG_CFG(ICPU_SW_MODE));
+
+ /*
+ * Do the global reset
+ */
+ writel(resetbits, REG_GCB(PERF_SOFT_RST));
+
+ while (1)
+ ; /* NOP */
+}
--
2.19.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v2 3/7] MSCC: add support for Ocelot SoCs
2018-10-09 11:58 ` [U-Boot] [PATCH v2 3/7] MSCC: add support for Ocelot SoCs Gregory CLEMENT
@ 2018-10-28 18:50 ` Daniel Schwierzeck
2018-11-30 14:48 ` Gregory CLEMENT
0 siblings, 1 reply; 12+ messages in thread
From: Daniel Schwierzeck @ 2018-10-28 18:50 UTC (permalink / raw)
To: u-boot
Am 09.10.18 um 13:58 schrieb Gregory CLEMENT:
> This family of SoCs are found in the Microsemi Switches solution and have
> already a support in the linux kernel.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> arch/mips/Kconfig | 6 +
> arch/mips/Makefile | 1 +
> arch/mips/mach-mscc/Kconfig | 69 ++
> arch/mips/mach-mscc/Makefile | 5 +
> arch/mips/mach-mscc/cpu.c | 42 ++
> arch/mips/mach-mscc/dram.c | 61 ++
> arch/mips/mach-mscc/include/ioremap.h | 51 ++
> arch/mips/mach-mscc/include/mach/common.h | 27 +
> arch/mips/mach-mscc/include/mach/ddr.h | 680 ++++++++++++++++++
> .../mach-mscc/include/mach/ocelot/ocelot.h | 35 +
> .../include/mach/ocelot/ocelot_devcpu_gcb.h | 21 +
> .../include/mach/ocelot/ocelot_icpu_cfg.h | 274 +++++++
> arch/mips/mach-mscc/include/mach/tlb.h | 55 ++
> arch/mips/mach-mscc/lowlevel_init.S | 23 +
> arch/mips/mach-mscc/reset.c | 36 +
> 15 files changed, 1386 insertions(+)
> create mode 100644 arch/mips/mach-mscc/Kconfig
> create mode 100644 arch/mips/mach-mscc/Makefile
> create mode 100644 arch/mips/mach-mscc/cpu.c
> create mode 100644 arch/mips/mach-mscc/dram.c
> create mode 100644 arch/mips/mach-mscc/include/ioremap.h
> create mode 100644 arch/mips/mach-mscc/include/mach/common.h
> create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h
> create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
> create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
> create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h
> create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h
> create mode 100644 arch/mips/mach-mscc/lowlevel_init.S
> create mode 100644 arch/mips/mach-mscc/reset.c
there are still some style issues and checkpatch.pl warnings in all
patches. Please fix.
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 071dea04ec..da479f2172 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -59,6 +59,11 @@ config ARCH_ATH79
> select OF_CONTROL
> imply CMD_DM
>
> +config ARCH_MSCC
> + bool "Support MSCC VCore-III"
> + select OF_CONTROL
> + select DM
> +
> config ARCH_BMIPS
> bool "Support BMIPS SoCs"
> select CLK
> @@ -135,6 +140,7 @@ source "board/imgtec/xilfpga/Kconfig"
> source "board/micronas/vct/Kconfig"
> source "board/qemu-mips/Kconfig"
> source "arch/mips/mach-ath79/Kconfig"
> +source "arch/mips/mach-mscc/Kconfig"
> source "arch/mips/mach-bmips/Kconfig"
> source "arch/mips/mach-pic32/Kconfig"
> source "arch/mips/mach-mt7620/Kconfig"
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index 802244a06e..124e93fa26 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -15,6 +15,7 @@ machine-$(CONFIG_ARCH_ATH79) += ath79
> machine-$(CONFIG_ARCH_BMIPS) += bmips
> machine-$(CONFIG_MACH_PIC32) += pic32
> machine-$(CONFIG_ARCH_MT7620) += mt7620
> +machine-$(CONFIG_ARCH_MSCC) += mscc
>
> machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
> libs-y += $(machdirs)
> diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
> new file mode 100644
> index 0000000000..7f1b270207
> --- /dev/null
> +++ b/arch/mips/mach-mscc/Kconfig
> @@ -0,0 +1,69 @@
> +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +menu "MSCC VCore-III platforms"
> + depends on ARCH_MSCC
> +
> +config SOC_VCOREIII
> + select MIPS_TUNE_24KC
> + select ROM_EXCEPTION_VECTORS
> + select SUPPORTS_BIG_ENDIAN
> + select SUPPORTS_CPU_MIPS32_R1
> + select SUPPORTS_CPU_MIPS32_R2
> + select SUPPORTS_LITTLE_ENDIAN
> + bool
> +
> +config SYS_SOC
> + default "mscc"
> +
> +config SOC_OCELOT
> + bool
> + select SOC_VCOREIII
> + help
> + This supports MSCC Ocelot family of SOCs.
> +
> +config SYS_CONFIG_NAME
> + default "vcoreiii"
> +
> +choice
> + prompt "Board select"
> +
> +config TARGET_OCELOT_PCB120
> + bool "MSCC PCB120 Reference Board (aka VSC5635EV)"
> + select SOC_OCELOT
> + help
> + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
> + ocelot_pcb120
> +
> +config TARGET_OCELOT_PCB123
> + bool "MSCC PCB123 Reference Board (aka VSC7514EV))"
> + select SOC_OCELOT
> + help
> + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
> + ocelot_pcb123
> +
> +endchoice
> +
> +choice
> + prompt "DDR type"
> +
> +config DDRTYPE_H5TQ4G63MFR
> + bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)"
> +
> +config DDRTYPE_MT41K256M16
> + bool "Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16)"
> +
> +config DDRTYPE_H5TQ1G63BFA
> + bool "Hynix H5TQ1G63BFA (1Gbit DDR3, x16)"
> +
> +config DDRTYPE_MT41J128M16HA
> + bool "Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16)"
> +
> +config DDRTYPE_MT41K128M16JT
> + bool "Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16)"
> +
> +config DDRTYPE_MT47H128M8HQ
> + bool "Micron MT47H128M8-3 (1Gbit, DDR-533 at CL4 @ 4.80ns 16Mbisx8x8)"
> +
> +endchoice
> +
> +endmenu
> diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
> new file mode 100644
> index 0000000000..d14ec33838
> --- /dev/null
> +++ b/arch/mips/mach-mscc/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +CFLAGS_cpu.o += -finline-limit=64000
> +
> +obj-y += cpu.o dram.o reset.o lowlevel_init.o
> diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
> new file mode 100644
> index 0000000000..0c8f7933cd
> --- /dev/null
> +++ b/arch/mips/mach-mscc/cpu.c
> @@ -0,0 +1,42 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#include <common.h>
> +
> +#include <asm/io.h>
> +#include <asm/types.h>
> +
> +#include <mach/tlb.h>
> +#include <mach/ddr.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* NOTE: lowlevel_init() function does not have access to the
> + * stack. Thus, all called functions must be inlined, and (any) local
> + * variables must be kept in registers.
> + */
> +void vcoreiii_tlb_init(void)
> +{
> + register int tlbix = 0;
> +
> + /*
> + * Unlike most of the MIPS based SoCs, the IO register address
> + * are not in KSEG0. The mainline linux kernel built in legacy
> + * mode needs to access some of the registers very early in
> + * the boot and make the assumption that the bootloader has
> + * already configured them, so we have to match this
> + * expectation.
> + */
> + create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW,
> + MMU_REGIO_RW);
> +}
> +
> +int mach_cpu_init(void)
> +{
> + /* Speed up NOR flash access */
> + writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
> + ICPU_SPI_MST_CFG_CLK_DIV(9), REG_CFG(ICPU_SPI_MST_CFG));
> + return 0;
> +}
> diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
> new file mode 100644
> index 0000000000..b82961f773
> --- /dev/null
> +++ b/arch/mips/mach-mscc/dram.c
> @@ -0,0 +1,61 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#include <common.h>
> +
> +#include <asm/io.h>
> +#include <asm/types.h>
> +
> +#include <mach/tlb.h>
> +#include <mach/ddr.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int vcoreiii_ddr_init(void)
> +{
> + int res;
> +
> + if (!(readl(REG_CFG(ICPU_MEMCTRL_STAT))
> + & ICPU_MEMCTRL_STAT_INIT_DONE)) {
> + hal_vcoreiii_init_memctl();
> + hal_vcoreiii_wait_memctl();
> + if (hal_vcoreiii_init_dqs() != 0 ||
> + hal_vcoreiii_train_bytelane(0) != 0
> + || hal_vcoreiii_train_bytelane(1) != 0
> + )
> + hal_vcoreiii_ddr_failed();
> + }
> +#if (CONFIG_SYS_TEXT_BASE != 0x20000000)
> + res = dram_check();
> + if (res == 0)
> + hal_vcoreiii_ddr_verified();
> + else
> + hal_vcoreiii_ddr_failed();
> +
> + /* Clear boot-mode and read-back to activate/verify */
> + clrbits_le32(REG_CFG(ICPU_GENERAL_CTRL),
> + ICPU_GENERAL_CTRL_BOOT_MODE_ENA);
> + readl(REG_CFG(ICPU_GENERAL_CTRL));
> +#else
> + res = 0;
> +#endif
> + return res;
> +}
> +
> +int print_cpuinfo(void)
> +{
> + printf("MSCC VCore-III MIPS 24Kec\n");
> +
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + while (vcoreiii_ddr_init())
> + ;
> +
> + gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
> + return 0;
> +}
> diff --git a/arch/mips/mach-mscc/include/ioremap.h b/arch/mips/mach-mscc/include/ioremap.h
> new file mode 100644
> index 0000000000..8ea5c65ce3
> --- /dev/null
> +++ b/arch/mips/mach-mscc/include/ioremap.h
> @@ -0,0 +1,51 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#ifndef __ASM_MACH_MSCC_IOREMAP_H
> +#define __ASM_MACH_MSCC_IOREMAP_H
> +
> +#include <linux/types.h>
> +#include <mach/common.h>
> +
> +/*
> + * Allow physical addresses to be fixed up to help peripherals located
> + * outside the low 32-bit range -- generic pass-through version.
> + */
> +static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
> + phys_addr_t size)
> +{
> + return phys_addr;
> +}
> +
> +static inline int is_vcoreiii_internal_registers(phys_addr_t offset)
> +{
> +#if defined(CONFIG_ARCH_MSCC)
> + if ((offset >= MSCC_IO_ORIGIN1_OFFSET &&
> + offset < (MSCC_IO_ORIGIN1_OFFSET + MSCC_IO_ORIGIN1_SIZE)) ||
> + (offset >= MSCC_IO_ORIGIN2_OFFSET &&
> + offset < (MSCC_IO_ORIGIN2_OFFSET + MSCC_IO_ORIGIN2_SIZE)))
> + return 1;
> +#endif
> +
> + return 0;
> +}
> +
> +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
> + unsigned long flags)
> +{
> + if (is_vcoreiii_internal_registers(offset))
> + return (void __iomem *)offset;
> +
> + return NULL;
> +}
> +
> +static inline int plat_iounmap(const volatile void __iomem *addr)
> +{
> + return is_vcoreiii_internal_registers((unsigned long)addr);
> +}
> +
> +#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
> +
> +#endif /* __ASM_MACH_MSCC_IOREMAP_H */
> diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h
> new file mode 100644
> index 0000000000..41887097f9
> --- /dev/null
> +++ b/arch/mips/mach-mscc/include/mach/common.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#ifndef __ASM_MACH_COMMON_H
> +#define __ASM_MACH_COMMON_H
> +
> +// Stick to using register offsets - matching readl()/writel() prototypes
> +#define MSCC_IOREG(t, o) ((void *)MSCC_IOADDR(t, o))
> +
> +#if defined(CONFIG_SOC_OCELOT)
> +#include <mach/ocelot/ocelot.h>
> +#include <mach/ocelot/ocelot_devcpu_gcb.h>
> +#include <mach/ocelot/ocelot_icpu_cfg.h>
> +#else
> +#error Unsupported platform
> +#endif
> +
> +#define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */
> +#define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */
> +#define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */
> +#define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */
> +
> +#define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */
> +
> +#endif /* __ASM_MACH_COMMON_H */
> diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h
> new file mode 100644
> index 0000000000..c089af8e33
> --- /dev/null
> +++ b/arch/mips/mach-mscc/include/mach/ddr.h
> @@ -0,0 +1,680 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#ifndef __ASM_MACH_DDR_H
> +#define __ASM_MACH_DDR_H
> +
> +#include <asm/cacheops.h>
> +#include <asm/io.h>
> +#include <asm/reboot.h>
> +#include <mach/common.h>
> +
> +#define MIPS_VCOREIII_MEMORY_DDR3
> +#define MIPS_VCOREIII_DDR_SIZE CONFIG_SYS_SDRAM_SIZE
> +
> +#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) /* Serval1 Refboard */
> +
> +/* Hynix H5TQ1G63BFA (1Gbit DDR3, x16) @ 3.20ns */
> +#define VC3_MPAR_bank_addr_cnt 3
> +#define VC3_MPAR_row_addr_cnt 13
> +#define VC3_MPAR_col_addr_cnt 10
> +#define VC3_MPAR_tREFI 2437
> +#define VC3_MPAR_tRAS_min 12
> +#define VC3_MPAR_CL 6
> +#define VC3_MPAR_tWTR 4
> +#define VC3_MPAR_tRC 16
> +#define VC3_MPR_tFAW 16
> +#define VC3_MPAR_tRP 5
> +#define VC3_MPAR_tRRD 4
> +#define VC3_MPAR_tRCD 5
> +#define VC3_MPAR_tMRD 4
> +#define VC3_MPAR_tRFC 35
> +#define VC3_MPAR_CWL 5
> +#define VC3_MPAR_tXPR 38
> +#define VC3_MPAR_tMOD 12
> +#define VC3_MPAR_tDLLK 512
> +#define VC3_MPAR_tWR 5
> +
> +#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) /* Validation board */
> +
> +/* Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16) @ 3.20ns */
> +#define VC3_MPAR_bank_addr_cnt 3
> +#define VC3_MPAR_row_addr_cnt 14
> +#define VC3_MPAR_col_addr_cnt 10
> +#define VC3_MPAR_tREFI 2437
> +#define VC3_MPAR_tRAS_min 12
> +#define VC3_MPAR_CL 5
> +#define VC3_MPAR_tWTR 4
> +#define VC3_MPAR_tRC 16
> +#define VC3_MPAR_tFAW 16
> +#define VC3_MPAR_tRP 5
> +#define VC3_MPAR_tRRD 4
> +#define VC3_MPAR_tRCD 5
> +#define VC3_MPAR_tMRD 4
> +#define VC3_MPAR_tRFC 50
> +#define VC3_MPAR_CWL 5
> +#define VC3_MPAR_tXPR 54
> +#define VC3_MPAR_tMOD 12
> +#define VC3_MPAR_tDLLK 512
> +#define VC3_MPAR_tWR 5
> +
> +#elif defined(CONFIG_DDRTYPE_MT41K256M16) /* JR2 Validation board */
> +
> +/* Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16) @ 3.20ns */
> +#define VC3_MPAR_bank_addr_cnt 3
> +#define VC3_MPAR_row_addr_cnt 15
> +#define VC3_MPAR_col_addr_cnt 10
> +#define VC3_MPAR_tREFI 2437
> +#define VC3_MPAR_tRAS_min 12
> +#define VC3_MPAR_CL 5
> +#define VC3_MPAR_tWTR 4
> +#define VC3_MPAR_tRC 16
> +#define VC3_MPAR_tFAW 16
> +#define VC3_MPAR_tRP 5
> +#define VC3_MPAR_tRRD 4
> +#define VC3_MPAR_tRCD 5
> +#define VC3_MPAR_tMRD 4
> +#define VC3_MPAR_tRFC 82
> +#define VC3_MPAR_CWL 5
> +#define VC3_MPAR_tXPR 85
> +#define VC3_MPAR_tMOD 12
> +#define VC3_MPAR_tDLLK 512
> +#define VC3_MPAR_tWR 5
> +
> +#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) /* JR2 Reference board */
> +
> +/* Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16) - 2kb pages @ 3.20ns */
> +#define VC3_MPAR_bank_addr_cnt 3
> +#define VC3_MPAR_row_addr_cnt 15
> +#define VC3_MPAR_col_addr_cnt 10
> +#define VC3_MPAR_tREFI 2437
> +#define VC3_MPAR_tRAS_min 12
> +#define VC3_MPAR_CL 6
> +#define VC3_MPAR_tWTR 4
> +#define VC3_MPAR_tRC 17
> +#define VC3_MPAR_tFAW 16
> +#define VC3_MPAR_tRP 5
> +#define VC3_MPAR_tRRD 4
> +#define VC3_MPAR_tRCD 5
> +#define VC3_MPAR_tMRD 4
> +#define VC3_MPAR_tRFC 82
> +#define VC3_MPAR_CWL 5
> +#define VC3_MPAR_tXPR 85
> +#define VC3_MPAR_tMOD 12
> +#define VC3_MPAR_tDLLK 512
> +#define VC3_MPAR_tWR 5
> +
> +#elif defined(CONFIG_DDRTYPE_MT41K128M16JT)
> +
> +/* Micron Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16) @ 3.20ns */
> +#define VC3_MPAR_bank_addr_cnt 3
> +#define VC3_MPAR_row_addr_cnt 14
> +#define VC3_MPAR_col_addr_cnt 10
> +#define VC3_MPAR_tREFI 2437
> +#define VC3_MPAR_tRAS_min 12
> +#define VC3_MPAR_CL 6
> +#define VC3_MPAR_tWTR 4
> +#define VC3_MPAR_tRC 16
> +#define VC3_MPAR_tFAW 16
> +#define VC3_MPAR_tRP 5
> +#define VC3_MPAR_tRRD 4
> +#define VC3_MPAR_tRCD 5
> +#define VC3_MPAR_tMRD 4
> +#define VC3_MPAR_tRFC 82
> +#define VC3_MPAR_CWL 5
> +#define VC3_MPAR_tXPR 85
> +#define VC3_MPAR_tMOD 12
> +#define VC3_MPAR_tDLLK 512
> +#define VC3_MPAR_tWR 5
> +
> +#elif defined(CONFIG_DDRTYPE_MT47H128M8HQ) /* Luton10/26 Refboards */
> +
> +/* Micron 1Gb MT47H128M8-3 16Meg x 8 x 8 banks, DDR-533 at CL4 @ 4.80ns */
> +#define VC3_MPAR_bank_addr_cnt 3
> +#define VC3_MPAR_row_addr_cnt 14
> +#define VC3_MPAR_col_addr_cnt 10
> +#define VC3_MPAR_tREFI 1625
> +#define VC3_MPAR_tRAS_min 9
> +#define VC3_MPAR_CL 4
> +#define VC3_MPAR_tWTR 2
> +#define VC3_MPAR_tRC 12
> +#define VC3_MPAR_tFAW 8
> +#define VC3_MPAR_tRP 4
> +#define VC3_MPAR_tRRD 2
> +#define VC3_MPAR_tRCD 4
> +
> +#define VC3_MPAR_tRPA 4
> +#define VC3_MPAR_tRP 4
> +
> +#define VC3_MPAR_tMRD 2
> +#define VC3_MPAR_tRFC 27
> +
> +#define VC3_MPAR__400_ns_dly 84
> +
> +#define VC3_MPAR_tWR 4
> +#undef MIPS_VCOREIII_MEMORY_DDR3
> +#else
> +
> +#error Unknown DDR system configuration - please add!
> +
> +#endif
> +
> +#ifdef CONFIG_SOC_OCELOT
> +#define MIPS_VCOREIII_MEMORY_16BIT 1
> +#endif
> +
> +#define MIPS_VCOREIII_MEMORY_SSTL_ODT 7
> +#define MIPS_VCOREIII_MEMORY_SSTL_DRIVE 7
> +#define VCOREIII_DDR_DQS_MODE_CALIBRATE
> +
> +#ifdef MIPS_VCOREIII_MEMORY_16BIT
> +#define VC3_MPAR_16BIT 1
> +#else
> +#define VC3_MPAR_16BIT 0
> +#endif
> +
> +#ifdef MIPS_VCOREIII_MEMORY_DDR3
> +#define VC3_MPAR_DDR3_MODE 1 /* DDR3 */
> +#define VC3_MPAR_BURST_LENGTH 8 /* Always 8 (1) for DDR3 */
> +#ifdef MIPS_VCOREIII_MEMORY_16BIT
> +#define VC3_MPAR_BURST_SIZE 1 /* Always 1 for DDR3/16bit */
> +#else
> +#define VC3_MPAR_BURST_SIZE 0
> +#endif
> +#else
> +#define VC3_MPAR_DDR3_MODE 0 /* DDR2 */
> +#ifdef MIPS_VCOREIII_MEMORY_16BIT
> +#define VC3_MPAR_BURST_LENGTH 4 /* in DDR2 16-bit mode, use burstlen 4 */
> +#else
> +#define VC3_MPAR_BURST_LENGTH 8 /* For 8-bit IF we must run burst-8 */
> +#endif
> +#define VC3_MPAR_BURST_SIZE 0 /* Always 0 for DDR2 */
> +#endif
> +
> +#define VC3_MPAR_RL VC3_MPAR_CL
> +#if !defined(MIPS_VCOREIII_MEMORY_DDR3)
> +#define VC3_MPAR_WL (VC3_MPAR_RL - 1)
> +#define VC3_MPAR_MD VC3_MPAR_tMRD
> +#define VC3_MPAR_ID VC3_MPAR__400_ns_dly
> +#define VC3_MPAR_SD VC3_MPAR_tXSRD
> +#define VC3_MPAR_OW (VC3_MPAR_WL - 2)
> +#define VC3_MPAR_OR (VC3_MPAR_WL - 3)
> +#define VC3_MPAR_RP (VC3_MPAR_bank_addr_cnt < 3 ? VC3_MPAR_tRP : VC3_MPAR_tRPA)
> +#define VC3_MPAR_FAW (VC3_MPAR_bank_addr_cnt < 3 ? 1 : VC3_MPAR_tFAW)
> +#define VC3_MPAR_BL (VC3_MPAR_BURST_LENGTH == 4 ? 2 : 4)
> +#define MSCC_MEMPARM_MR0 \
> + (VC3_MPAR_BURST_LENGTH == 8 ? 3 : 2) | (VC3_MPAR_CL << 4) | \
> + ((VC3_MPAR_tWR - 1) << 9)
> +/* DLL-on, Full-OD, AL=0, RTT=off, nDQS-on, RDQS-off, out-en */
> +#define MSCC_MEMPARM_MR1 0x382
> +#define MSCC_MEMPARM_MR2 0
> +#define MSCC_MEMPARM_MR3 0
> +#else
> +#define VC3_MPAR_WL VC3_MPAR_CWL
> +#define VC3_MPAR_MD VC3_MPAR_tMOD
> +#define VC3_MPAR_ID VC3_MPAR_tXPR
> +#define VC3_MPAR_SD VC3_MPAR_tDLLK
> +#define VC3_MPAR_OW 2
> +#define VC3_MPAR_OR 2
> +#define VC3_MPAR_RP VC3_MPAR_tRP
> +#define VC3_MPAR_FAW VC3_MPAR_tFAW
> +#define VC3_MPAR_BL 4
> +#define MSCC_MEMPARM_MR0 ((VC3_MPAR_RL - 4) << 4) | ((VC3_MPAR_tWR - 4) << 9)
> +/* ODT_RTT: “0x0040” for 120ohm, and “0x0004” for 60ohm. */
> +#define MSCC_MEMPARM_MR1 0x0040
> +#define MSCC_MEMPARM_MR2 ((VC3_MPAR_WL - 5) << 3)
> +#define MSCC_MEMPARM_MR3 0
> +#endif /* MIPS_VCOREIII_MEMORY_DDR3 */
> +
> +#define MSCC_MEMPARM_MEMCFG \
> + ((MIPS_VCOREIII_DDR_SIZE > SZ_512M) ? \
> + ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS : 0) | \
> + (VC3_MPAR_16BIT ? ICPU_MEMCTRL_CFG_DDR_WIDTH : 0) | \
> + (VC3_MPAR_DDR3_MODE ? ICPU_MEMCTRL_CFG_DDR_MODE : 0) | \
> + (VC3_MPAR_BURST_SIZE ? ICPU_MEMCTRL_CFG_BURST_SIZE : 0) | \
> + (VC3_MPAR_BURST_LENGTH == 8 ? ICPU_MEMCTRL_CFG_BURST_LEN : 0) | \
> + (VC3_MPAR_bank_addr_cnt == 3 ? ICPU_MEMCTRL_CFG_BANK_CNT : 0) | \
> + ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(VC3_MPAR_row_addr_cnt - 1) | \
> + ICPU_MEMCTRL_CFG_MSB_COL_ADDR(VC3_MPAR_col_addr_cnt - 1)
> +
> +#ifdef CONFIG_SOC_OCELOT
> +#define MSCC_MEMPARM_PERIOD \
> + ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(8) | \
> + ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
> +
> +#define MSCC_MEMPARM_TIMING0 \
> + ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(VC3_MPAR_RL + VC3_MPAR_BL + 1 - \
> + VC3_MPAR_WL) | \
> + ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(VC3_MPAR_BL - 1) | \
> + ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(VC3_MPAR_BL) | \
> + ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(VC3_MPAR_tRAS_min - 1) | \
> + ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(VC3_MPAR_WL + \
> + VC3_MPAR_BL + \
> + VC3_MPAR_tWR - 1) | \
> + ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(VC3_MPAR_BL - 1) | \
> + ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(VC3_MPAR_WL - 1) | \
> + ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(VC3_MPAR_RL - 3)
> +
> +#define MSCC_MEMPARM_TIMING1 \
> + ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(VC3_MPAR_tRC - 1) | \
> + ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(VC3_MPAR_FAW - 1) | \
> + ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(VC3_MPAR_RP - 1) | \
> + ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(VC3_MPAR_tRRD - 1) | \
> + ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(VC3_MPAR_tRCD - 1) | \
> + ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(VC3_MPAR_WL + \
> + VC3_MPAR_BL + \
> + VC3_MPAR_tWTR - 1)
> +
> +#define MSCC_MEMPARM_TIMING2 \
> + ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(VC3_MPAR_RP - 1) | \
> + ICPU_MEMCTRL_TIMING2_MDSET_DLY(VC3_MPAR_MD - 1) | \
> + ICPU_MEMCTRL_TIMING2_REF_DLY(VC3_MPAR_tRFC - 1) | \
> + ICPU_MEMCTRL_TIMING2_INIT_DLY(VC3_MPAR_ID - 1)
> +
> +#define MSCC_MEMPARM_TIMING3 \
> + ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(VC3_MPAR_WL + \
> + VC3_MPAR_tWTR - 1) |\
> + ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(VC3_MPAR_OR - 1) | \
> + ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(VC3_MPAR_OW - 1) | \
> + ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(VC3_MPAR_RL - 3)
> +
> +#else
> +#define MSCC_MEMPARM_PERIOD \
> + ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(1) | \
> + ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
> +
> +#define MSCC_MEMPARM_TIMING0 \
> + ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(VC3_MPAR_tRAS_min - 1) | \
> + ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(VC3_MPAR_CL + \
> + (VC3_MPAR_BURST_LENGTH == 8 ? 2 : 0) + \
> + VC3_MPAR_tWR) | \
> + ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(VC3_MPAR_BURST_LENGTH == 8 ? 3 : 1) | \
> + ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(VC3_MPAR_CL - 3) | \
> + ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(VC3_MPAR_CL - 3)
> +
> +#define MSCC_MEMPARM_TIMING1 \
> + ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(VC3_MPAR_tRC - 1) | \
> + ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(VC3_MPAR_tFAW - 1) | \
> + ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(VC3_MPAR_tRP - 1) | \
> + ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(VC3_MPAR_tRRD - 1) | \
> + ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(VC3_MPAR_tRCD - 1) | \
> + ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(VC3_MPAR_CL + \
> + (VC3_MPAR_BURST_LENGTH == 8 ? 2 : 0) + \
> + VC3_MPAR_tWTR)
> +#define MSCC_MEMPARM_TIMING2 \
> + ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(VC3_MPAR_tRPA - 1) | \
> + ICPU_MEMCTRL_TIMING2_MDSET_DLY(VC3_MPAR_tMRD - 1) | \
> + ICPU_MEMCTRL_TIMING2_REF_DLY(VC3_MPAR_tRFC - 1) | \
> + ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY(VC3_MPAR__400_ns_dly)
> +
> +#define MSCC_MEMPARM_TIMING3 \
> + ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(VC3_MPAR_CL - 1) | \
> + ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(VC3_MPAR_CL - 1) | \
> + ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(VC3_MPAR_CL - 1)
> +
> +#endif
> +
> +enum {
> + DDR_TRAIN_OK,
> + DDR_TRAIN_CONTINUE,
> + DDR_TRAIN_ERROR,
> +};
> +
> +/*
> + * We actually have very few 'pause' possibilities apart from
> + * these assembly nops (at this very early stage).
> + */
> +#define PAUSE() asm volatile("nop; nop; nop; nop; nop; nop; nop; nop")
> +
> +/* NB: Assumes inlining as no stack is available! */
> +static inline void set_dly(u32 bytelane, u32 dly)
> +{
> + register u32 r = readl(REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane)));
> +
> + r &= ~ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M;
> + r |= ICPU_MEMCTRL_DQS_DLY_DQS_DLY(dly);
> + writel(r, REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane)));
> +}
> +
> +static inline bool incr_dly(u32 bytelane)
> +{
> + register u32 r = readl(REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane)));
> +
> + if (ICPU_MEMCTRL_DQS_DLY_DQS_DLY(r) < 31) {
> + writel(r + 1, REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane)));
> + return true;
> + }
> +
> + return false;
> +}
> +
> +static inline bool adjust_dly(int adjust)
> +{
> + register u32 r = readl(REG_CFG(ICPU_MEMCTRL_DQS_DLY(0)));
> +
> + if (ICPU_MEMCTRL_DQS_DLY_DQS_DLY(r) < 31) {
> + writel(r + adjust, REG_CFG(ICPU_MEMCTRL_DQS_DLY(0)));
> + return true;
> + }
> +
> + return false;
> +}
> +
> +/* NB: Assumes inlining as no stack is available! */
> +static inline void center_dly(u32 bytelane, u32 start)
> +{
> + register u32 r = readl(REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane))) - start;
> +
> + writel(start + (r >> 1), REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane)));
> +}
> +
> +static inline void memphy_soft_reset(void)
> +{
> + setbits_le32(REG_CFG(ICPU_MEMPHY_CFG), ICPU_MEMPHY_CFG_PHY_FIFO_RST);
> + PAUSE();
> + clrbits_le32(REG_CFG(ICPU_MEMPHY_CFG), ICPU_MEMPHY_CFG_PHY_FIFO_RST);
> + PAUSE();
> +}
> +
> +#ifdef CONFIG_SOC_OCELOT
> +static u8 training_data[] = { 0xfe, 0x11, 0x33, 0x55, 0x77, 0x99, 0xbb, 0xdd };
> +
> +static inline void sleep_100ns(u32 val)
> +{
> + /* Set the timer tick generator to 100 ns */
> + writel(VCOREIII_TIMER_DIVIDER - 1, REG_CFG(ICPU_TIMER_TICK_DIV));
> +
> + /* Set the timer value */
> + writel(val, REG_CFG(ICPU_TIMER_VALUE(0)));
> +
> + /* Enable timer 0 for one-shot */
> + writel(ICPU_TIMER_CTRL_ONE_SHOT_ENA | ICPU_TIMER_CTRL_TIMER_ENA,
> + REG_CFG(ICPU_TIMER_CTRL(0)));
> +
> + /* Wait for timer 0 to reach 0 */
> + while (readl(REG_CFG(ICPU_TIMER_VALUE(0))) != 0)
> + ;
> +}
> +
> +static inline void hal_vcoreiii_ddr_reset_assert(void)
> +{
> + /* DDR has reset pin on GPIO 19 toggle Low-High to release */
> + setbits_le32(REG_GCB(PERF_GPIO_OE), BIT(19));
> + writel(BIT(19), REG_GCB(PERF_GPIO_OUT_CLR));
> + sleep_100ns(10000);
> +}
> +
> +static inline void hal_vcoreiii_ddr_reset_release(void)
> +{
> + /* DDR has reset pin on GPIO 19 toggle Low-High to release */
> + setbits_le32(REG_GCB(PERF_GPIO_OE), BIT(19));
> + writel(BIT(19), REG_GCB(PERF_GPIO_OUT_SET));
> + sleep_100ns(10000);
> +}
> +
> +/*
> + * DDR memory sanity checking failed, tally and do hard reset
> + *
> + * NB: Assumes inlining as no stack is available!
> + */
> +static inline void hal_vcoreiii_ddr_failed(void)
> +{
> + register u32 reset;
> +
> + writel(readl(REG_CFG(ICPU_GPR(6))) + 1, REG_CFG(ICPU_GPR(6)));
> +
> + clrbits_le32(REG_GCB(PERF_GPIO_OE), BIT(19));
> +
> + /* Jump to reset - does not return */
> + reset = KSEG0ADDR(_machine_restart);
> + /* Reset while running from cache */
> + icache_lock((void *)reset, 128);
> + asm volatile ("jr %0"::"r" (reset));
why do you need to move to KSEG0 and to lock the cache line? Do you run
the whole lowlevel code in KSEG1 space?
I guess the SoC maps the SPI flash to some executable buffer from where
U-Boot is started. If the I-Cache works on this buffer, you could move
your text base to KSEG0 space and run fully cached after I-Caches have
been initialised.
> +
> + panic("DDR init failed\n");
> +}
> +
> +/*
> + * DDR memory sanity checking done, possibly enable ECC.
> + *
> + * NB: Assumes inlining as no stack is available!
> + */
> +static inline void hal_vcoreiii_ddr_verified(void)
> +{
> +#ifdef MIPS_VCOREIII_MEMORY_ECC
> + /* Finally, enable ECC */
> + register u32 val = readl(REG_CFG(ICPU_MEMCTRL_CFG));
> +
> + val |= ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA;
> + val &= ~ICPU_MEMCTRL_CFG_BURST_SIZE;
> +
> + writel(val, REG_CFG(ICPU_MEMCTRL_CFG));
> +#endif
> +
> + /* Reset Status register - sticky bits */
> + writel(readl(REG_CFG(ICPU_MEMCTRL_STAT)), REG_CFG(ICPU_MEMCTRL_STAT));
> +}
> +
> +/* NB: Assumes inlining as no stack is available! */
> +static inline int look_for(u32 bytelane)
> +{
> + register u32 i;
> +
> + /* Reset FIFO in case any previous access failed */
> + for (i = 0; i < sizeof(training_data); i++) {
> + register u32 byte;
> +
> + memphy_soft_reset();
> + /* Reset sticky bits */
> + writel(readl(REG_CFG(ICPU_MEMCTRL_STAT)),
> + REG_CFG(ICPU_MEMCTRL_STAT));
> + /* Read data */
> + byte = ((volatile u8 *)MSCC_DDR_TO)[bytelane + (i * 4)];
> + if (readl(REG_CFG(ICPU_MEMCTRL_STAT)) &
> + (ICPU_MEMCTRL_STAT_RDATA_MASKED |
> + ICPU_MEMCTRL_STAT_RDATA_DUMMY)) {
> + /* Noise on the line */
> + goto read_error;
> + }
> + /* If mismatch, increment DQS - if possible */
> + if (byte != training_data[i]) {
> + read_error:
> + if (!incr_dly(bytelane))
> + return DDR_TRAIN_ERROR;
> + return DDR_TRAIN_CONTINUE;
> + }
> + }
> + return DDR_TRAIN_OK;
> +}
> +
> +/* NB: Assumes inlining as no stack is available! */
> +static inline int look_past(u32 bytelane)
> +{
> + register u32 i;
> +
> + /* Reset FIFO in case any previous access failed */
> + for (i = 0; i < sizeof(training_data); i++) {
> + register u32 byte;
> +
> + memphy_soft_reset();
> + /* Ack sticky bits */
> + writel(readl(REG_CFG(ICPU_MEMCTRL_STAT)),
> + REG_CFG(ICPU_MEMCTRL_STAT));
> + byte = ((volatile u8 *)MSCC_DDR_TO)[bytelane + (i * 4)];
> + if (readl(REG_CFG(ICPU_MEMCTRL_STAT)) &
> + (ICPU_MEMCTRL_STAT_RDATA_MASKED |
> + ICPU_MEMCTRL_STAT_RDATA_DUMMY)) {
> + /* Noise on the line */
> + goto read_error;
> + }
> + /* Bail out when we see first mismatch */
> + if (byte != training_data[i]) {
> + read_error:
> + return DDR_TRAIN_OK;
> + }
> + }
> + /* All data compares OK, increase DQS and retry */
> + if (!incr_dly(bytelane))
> + return DDR_TRAIN_ERROR;
> +
> + return DDR_TRAIN_CONTINUE;
> +}
> +
> +static inline int hal_vcoreiii_train_bytelane(u32 bytelane)
> +{
> + register int res;
> + register u32 dqs_s;
> +
> + set_dly(bytelane, 0); // Start training at DQS=0
> + while ((res = look_for(bytelane)) == DDR_TRAIN_CONTINUE)
> + ;
> + if (res != DDR_TRAIN_OK)
> + return res;
> +
> + dqs_s = readl(REG_CFG(ICPU_MEMCTRL_DQS_DLY(bytelane)));
> + while ((res = look_past(bytelane)) == DDR_TRAIN_CONTINUE)
> + ;
> + if (res != DDR_TRAIN_OK)
> + return res;
> + /* Reset FIFO - for good measure */
> + memphy_soft_reset();
> + /* Adjust to center [dqs_s;cur] */
> + center_dly(bytelane, dqs_s);
> + return DDR_TRAIN_OK;
> +}
> +
> +/* This algorithm is converted from the TCL training algorithm used
> + * during silicon simulation.
> + * NB: Assumes inlining as no stack is available!
> + */
> +static inline int hal_vcoreiii_init_dqs(void)
> +{
> +#define MAX_DQS 32
> + register u32 i, j;
> +
> + for (i = 0; i < MAX_DQS; i++) {
> + set_dly(0, i); // Byte-lane 0
> + for (j = 0; j < MAX_DQS; j++) {
> + register u32 __attribute__ ((unused)) byte;
> + set_dly(1, j); // Byte-lane 1
> + /* Reset FIFO in case any previous access failed */
> + memphy_soft_reset();
> + writel(readl(REG_CFG(ICPU_MEMCTRL_STAT)),
> + REG_CFG(ICPU_MEMCTRL_STAT));
> + byte = ((volatile u8 *)MSCC_DDR_TO)[0];
> + byte = ((volatile u8 *)MSCC_DDR_TO)[1];
> + if (!(readl(REG_CFG(ICPU_MEMCTRL_STAT)) &
> + (ICPU_MEMCTRL_STAT_RDATA_MASKED |
> + ICPU_MEMCTRL_STAT_RDATA_DUMMY)))
> + return 0;
> + }
> + }
> + return -1;
> +}
> +
> +static inline int dram_check(void)
> +{
> +#define DDR ((volatile u32 *) MSCC_DDR_TO)
> + register u32 i;
> +
> + for (i = 0; i < 8; i++) {
> + DDR[i] = ~i;
> + if (DDR[i] != ~i)
> + return 1;
> + }
> + return 0;
> +}
> +/*
> + * NB: Called *early* to init memory controller - assumes inlining as
> + * no stack is available!
> + */
> +static inline void hal_vcoreiii_init_memctl(void)
> +{
> + /* Ensure DDR is in reset */
> + hal_vcoreiii_ddr_reset_assert();
> +
> + /* Wait maybe not needed, but ... */
> + PAUSE();
> +
> + /* Drop sys ctl memory controller forced reset */
> + clrbits_le32(REG_CFG(ICPU_RESET), ICPU_RESET_MEM_RST_FORCE);
> +
> + PAUSE();
> +
> + /* Drop Reset, enable SSTL */
> + writel(ICPU_MEMPHY_CFG_PHY_SSTL_ENA, REG_CFG(ICPU_MEMPHY_CFG));
> + PAUSE();
> +
> + /* Start the automatic SSTL output and ODT drive-strength calibration */
> + writel(ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(MIPS_VCOREIII_MEMORY_SSTL_ODT) |
> + /* drive strength */
> + ICPU_MEMPHY_ZCAL_ZCAL_PROG(MIPS_VCOREIII_MEMORY_SSTL_DRIVE) |
> + /* Start calibration process */
> + ICPU_MEMPHY_ZCAL_ZCAL_ENA, REG_CFG(ICPU_MEMPHY_ZCAL));
> +
> + /* Wait for ZCAL to clear */
> + while (readl(REG_CFG(ICPU_MEMPHY_ZCAL)) & ICPU_MEMPHY_ZCAL_ZCAL_ENA)
> + ;
> +
> + /* Check no ZCAL_ERR */
> + if (readl(REG_CFG(ICPU_MEMPHY_ZCAL_STAT))
> + & ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR)
> + hal_vcoreiii_ddr_failed();
> +
> + /* Drive CL, CK, ODT */
> + setbits_le32(REG_CFG(ICPU_MEMPHY_CFG), ICPU_MEMPHY_CFG_PHY_ODT_OE |
> + ICPU_MEMPHY_CFG_PHY_CK_OE | ICPU_MEMPHY_CFG_PHY_CL_OE);
> +
> + /* Initialize memory controller */
> + writel(MSCC_MEMPARM_MEMCFG, REG_CFG(ICPU_MEMCTRL_CFG));
> + writel(MSCC_MEMPARM_PERIOD, REG_CFG(ICPU_MEMCTRL_REF_PERIOD));
> +
> +
> + writel(MSCC_MEMPARM_TIMING0, REG_CFG(ICPU_MEMCTRL_TIMING0));
> +
> + writel(MSCC_MEMPARM_TIMING1, REG_CFG(ICPU_MEMCTRL_TIMING1));
> + writel(MSCC_MEMPARM_TIMING2, REG_CFG(ICPU_MEMCTRL_TIMING2));
> + writel(MSCC_MEMPARM_TIMING3, REG_CFG(ICPU_MEMCTRL_TIMING3));
> + writel(MSCC_MEMPARM_MR0, REG_CFG(ICPU_MEMCTRL_MR0_VAL));
> + writel(MSCC_MEMPARM_MR1, REG_CFG(ICPU_MEMCTRL_MR1_VAL));
> + writel(MSCC_MEMPARM_MR2, REG_CFG(ICPU_MEMCTRL_MR2_VAL));
> + writel(MSCC_MEMPARM_MR3, REG_CFG(ICPU_MEMCTRL_MR3_VAL));
> +
> + /* Termination setup - enable ODT */
> + writel(ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA |
> + /* Assert ODT0 for any write */
> + ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(3),
> + REG_CFG(ICPU_MEMCTRL_TERMRES_CTRL));
> +
> + /* Release Reset from DDR */
> + hal_vcoreiii_ddr_reset_release();
> +
> + writel(readl(REG_CFG(ICPU_GPR(7))) + 1, REG_CFG(ICPU_GPR(7)));
> +}
> +
> +static inline void hal_vcoreiii_wait_memctl(void)
> +{
> + /* Now, rip it! */
> + writel(ICPU_MEMCTRL_CTRL_INITIALIZE, REG_CFG(ICPU_MEMCTRL_CTRL));
> +
> + while (!(readl(REG_CFG(ICPU_MEMCTRL_STAT))
> + & ICPU_MEMCTRL_STAT_INIT_DONE))
> + ;
> +
> + /* Settle...? */
> + sleep_100ns(10000);
> +
> + /* Establish data contents in DDR RAM for training */
> +
> + __raw_writel(0xcacafefe, ((void __iomem *)MSCC_DDR_TO));
> + __raw_writel(0x22221111, ((void __iomem *)MSCC_DDR_TO + 0x4));
> + __raw_writel(0x44443333, ((void __iomem *)MSCC_DDR_TO + 0x8));
> + __raw_writel(0x66665555, ((void __iomem *)MSCC_DDR_TO + 0xC));
> + __raw_writel(0x88887777, ((void __iomem *)MSCC_DDR_TO + 0x10));
> + __raw_writel(0xaaaa9999, ((void __iomem *)MSCC_DDR_TO + 0x14));
> + __raw_writel(0xccccbbbb, ((void __iomem *)MSCC_DDR_TO + 0x18));
> + __raw_writel(0xeeeedddd, ((void __iomem *)MSCC_DDR_TO + 0x1C));
> +}
> +#endif /* __ASM_MACH_DDR_H */
> diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
> new file mode 100644
> index 0000000000..75b25bae62
> --- /dev/null
> +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Microsemi Ocelot Switch driver
> + *
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#ifndef _MSCC_OCELOT_H_
> +#define _MSCC_OCELOT_H_
> +
> +#include <linux/bitops.h>
> +#include <dm.h>
> +
> +/*
> + * Target offset base(s)
> + */
> +#define MSCC_IO_ORIGIN1_OFFSET 0x70000000
> +#define MSCC_IO_ORIGIN1_SIZE 0x00200000
> +#define MSCC_IO_ORIGIN2_OFFSET 0x71000000
> +#define MSCC_IO_ORIGIN2_SIZE 0x01000000
> +#ifndef MSCC_IO_OFFSET1
> +#define MSCC_IO_OFFSET1(offset) (MSCC_IO_ORIGIN1_OFFSET + offset)
> +#endif
> +#ifndef MSCC_IO_OFFSET2
> +#define MSCC_IO_OFFSET2(offset) (MSCC_IO_ORIGIN2_OFFSET + offset)
> +#endif
> +#define BASE_CFG 0x70000000
> +#define BASE_UART 0x70100000
> +#define BASE_DEVCPU_GCB 0x71070000
> +
> +#define REG_OFFSET(t, o) ((volatile unsigned long *)(t + (o)))
> +#define REG_CFG(x) REG_OFFSET(BASE_CFG, x)
> +#define REG_GCB(x) REG_OFFSET(BASE_DEVCPU_GCB, x)
this look like oldschool vendor SDK macros and checkpatch is complaining
about it ;)
I would prefer if you establish mappings in lowlevel code like this:
void __iomem *base = ioremap_nocache(BASE_CFG, 0);
writel(VAL, base + OFFSET);
> +
> +#endif
> diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
> new file mode 100644
> index 0000000000..f8aa97ba26
> --- /dev/null
> +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#ifndef _MSCC_OCELOT_DEVCPU_GCB_H_
> +#define _MSCC_OCELOT_DEVCPU_GCB_H_
> +
> +#define PERF_SOFT_RST 0x8
> +
> +#define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2)
> +#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)
> +#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
> +
> +#define PERF_GPIO_OUT_SET 0x34
> +
> +#define PERF_GPIO_OUT_CLR 0x38
> +
> +#define PERF_GPIO_OE 0x44
> +
> +#endif
> diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h
> new file mode 100644
> index 0000000000..04cf70bec3
> --- /dev/null
> +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h
> @@ -0,0 +1,274 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#ifndef _MSCC_OCELOT_ICPU_CFG_H_
> +#define _MSCC_OCELOT_ICPU_CFG_H_
> +
> +#define ICPU_GPR(x) (0x4 * (x))
> +#define ICPU_GPR_RSZ 0x4
> +
> +#define ICPU_RESET 0x20
> +
> +#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
> +#define ICPU_RESET_CORE_RST_PROTECT BIT(2)
> +#define ICPU_RESET_CORE_RST_FORCE BIT(1)
> +#define ICPU_RESET_MEM_RST_FORCE BIT(0)
> +
> +#define ICPU_GENERAL_CTRL 0x24
> +
> +#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(14)
> +#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(13)
> +#define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12)
> +#define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(11)
> +#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ADDR_SEL BIT(10)
> +#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(9)
> +#define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(8)
> +#define ICPU_GENERAL_CTRL_IF_PI_MST_ENA BIT(7)
> +#define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(6)
> +#define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4))
> +#define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4)
> +#define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
> +#define ICPU_GENERAL_CTRL_SSI_MST_CONTENTION BIT(3)
> +#define ICPU_GENERAL_CTRL_CPU_BE_ENA BIT(2)
> +#define ICPU_GENERAL_CTRL_CPU_DIS BIT(1)
> +#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0)
> +#define ICPU_SPI_MST_CFG 0x3c
> +
> +#define ICPU_SPI_MST_CFG_A32B_ENA BIT(11)
> +#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10)
> +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
> +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
> +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
> +#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
> +#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
> +
> +#define ICPU_SW_MODE 0x50
> +
> +#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
> +#define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
> +#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11)
> +#define ICPU_SW_MODE_SW_SPI_SDO BIT(10)
> +#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9)
> +#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
> +#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
> +#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
> +#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1))
> +#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1)
> +#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1)
> +#define ICPU_SW_MODE_SW_SPI_SDI BIT(0)
> +
> +#define ICPU_INTR_ENA 0x88
> +
> +#define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x))
> +#define ICPU_DST_INTR_MAP_RSZ 0x4
> +
> +#define ICPU_DST_INTR_IDENT 0xa8
> +#define ICPU_DST_INTR_IDENT_RSZ 0x4
> +
> +#define ICPU_TIMER_TICK_DIV 0xe8
> +#define ICPU_TIMER_VALUE(x) (0xec + 0x4 * (x))
> +
> +#define ICPU_TIMER_CTRL(x) (0x104 + 0x4 * (x))
> +#define ICPU_TIMER_CTRL_MAX_FREQ_ENA BIT(3)
> +#define ICPU_TIMER_CTRL_ONE_SHOT_ENA BIT(2)
> +#define ICPU_TIMER_CTRL_TIMER_ENA BIT(1)
> +#define ICPU_TIMER_CTRL_FORCE_RELOAD BIT(0)
> +
> +#define ICPU_MEMCTRL_CTRL 0x110
> +#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3)
> +#define ICPU_MEMCTRL_CTRL_MDSET BIT(2)
> +#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1)
> +#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0)
> +
> +#define ICPU_MEMCTRL_CFG 0x114
> +
> +#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16)
> +#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15)
> +#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14)
> +#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13)
> +#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12)
> +#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11)
> +#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10)
> +#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9)
> +#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8)
> +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4))
> +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4)
> +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4)
> +#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0))
> +#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0)
> +
> +#define ICPU_MEMCTRL_STAT 0x118
> +
> +#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5)
> +#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4)
> +#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3)
> +#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2)
> +#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1)
> +#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0)
> +
> +#define ICPU_MEMCTRL_REF_PERIOD 0x11c
> +
> +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16))
> +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16)
> +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16)
> +#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0))
> +#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0)
> +
> +#define ICPU_MEMCTRL_TIMING0 0x124
> +
> +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28))
> +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28)
> +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
> +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24))
> +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24)
> +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
> +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20))
> +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20)
> +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20)
> +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16))
> +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16)
> +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
> +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12))
> +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12)
> +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
> +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8))
> +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8)
> +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
> +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4))
> +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4)
> +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
> +#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0))
> +#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0)
> +
> +#define ICPU_MEMCTRL_TIMING1 0x128
> +
> +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24))
> +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24)
> +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24)
> +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16))
> +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16)
> +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
> +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12))
> +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12)
> +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
> +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8))
> +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8)
> +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
> +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4))
> +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4)
> +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
> +#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0))
> +#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0)
> +
> +#define ICPU_MEMCTRL_TIMING2 0x12c
> +
> +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28))
> +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28)
> +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
> +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24))
> +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24)
> +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
> +#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16))
> +#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16)
> +#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
> +#define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0))
> +#define ICPU_MEMCTRL_TIMING2_INIT_DLY_M GENMASK(15, 0)
> +
> +#define ICPU_MEMCTRL_TIMING3 0x130
> +
> +#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16))
> +#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16)
> +#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
> +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12))
> +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12)
> +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
> +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8))
> +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8)
> +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
> +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4))
> +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4)
> +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
> +#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0))
> +#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0)
> +
> +#define ICPU_MEMCTRL_MR0_VAL 0x138
> +
> +#define ICPU_MEMCTRL_MR1_VAL 0x13c
> +
> +#define ICPU_MEMCTRL_MR2_VAL 0x140
> +
> +#define ICPU_MEMCTRL_MR3_VAL 0x144
> +
> +#define ICPU_MEMCTRL_TERMRES_CTRL 0x148
> +
> +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11)
> +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7))
> +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7)
> +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7)
> +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6)
> +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2))
> +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2)
> +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2)
> +#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1)
> +#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0)
> +
> +#define ICPU_MEMCTRL_DQS_DLY(x) (0x150 + 0x4 * (x))
> +#define ICPU_MEMCTRL_DQS_DLY_RSZ 0x4
> +
> +#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11)
> +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8))
> +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8)
> +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8)
> +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5))
> +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5)
> +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5)
> +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0))
> +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0)
> +
> +#define ICPU_MEMPHY_CFG 0x160
> +
> +#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10)
> +#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9)
> +#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8)
> +#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7)
> +#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6)
> +#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5)
> +#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4)
> +#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3)
> +#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2)
> +#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1)
> +#define ICPU_MEMPHY_CFG_PHY_RST BIT(0)
> +
> +#define ICPU_MEMPHY_ZCAL 0x188
> +
> +#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9)
> +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5))
> +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5)
> +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5)
> +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1))
> +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1)
> +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1)
> +#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0)
> +
> +#define ICPU_MEMPHY_ZCAL_STAT 0x18c
> +
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL(x) (((x) << 12) & GENMASK(31, 12))
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_M GENMASK(31, 12)
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_X(x) (((x) & GENMASK(31, 12)) >> 12)
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU(x) (((x) << 8) & GENMASK(9, 8))
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_M GENMASK(9, 8)
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_X(x) (((x) & GENMASK(9, 8)) >> 8)
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD(x) (((x) << 6) & GENMASK(7, 6))
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_M GENMASK(7, 6)
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_X(x) (((x) & GENMASK(7, 6)) >> 6)
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU(x) (((x) << 4) & GENMASK(5, 4))
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_M GENMASK(5, 4)
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_X(x) (((x) & GENMASK(5, 4)) >> 4)
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD(x) (((x) << 2) & GENMASK(3, 2))
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_M GENMASK(3, 2)
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_X(x) (((x) & GENMASK(3, 2)) >> 2)
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR BIT(1)
> +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_DONE BIT(0)
> +#endif
> diff --git a/arch/mips/mach-mscc/include/mach/tlb.h b/arch/mips/mach-mscc/include/mach/tlb.h
> new file mode 100644
> index 0000000000..fdb554f551
> --- /dev/null
> +++ b/arch/mips/mach-mscc/include/mach/tlb.h
> @@ -0,0 +1,55 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#ifndef __ASM_MACH_TLB_H
> +#define __ASM_MACH_TLB_H
> +
> +#include <asm/mipsregs.h>
> +#include <mach/common.h>
> +#include <linux/sizes.h>
> +
> +#define TLB_HI_MASK 0xffffe000
> +#define TLB_LO_MASK 0x3fffffff /* Masks off Fill bits */
> +#define TLB_LO_SHIFT 6 /* PFN Start bit */
> +
> +#define PAGEMASK_SHIFT 13
> +
> +#define MMU_PAGE_CACHED (3 << 3) /* C(5:3) Cache Coherency Attributes */
> +#define MMU_PAGE_UNCACHED (2 << 3) /* C(5:3) Cache Coherency Attributes */
> +#define MMU_PAGE_DIRTY BIT(2) /* = Writeable */
> +#define MMU_PAGE_VALID BIT(1)
> +#define MMU_PAGE_GLOBAL BIT(0)
> +#define MMU_REGIO_RO_C (MMU_PAGE_CACHED | MMU_PAGE_VALID | MMU_PAGE_GLOBAL)
> +#define MMU_REGIO_RO (MMU_PAGE_UNCACHED | MMU_PAGE_VALID | MMU_PAGE_GLOBAL)
> +#define MMU_REGIO_RW (MMU_PAGE_DIRTY | MMU_REGIO_RO)
> +#define MMU_REGIO_INVAL (MMU_PAGE_GLOBAL)
> +
> +#define TLB_COUNT_MASK GENMASK(5, 0)
> +#define TLB_COUNT_OFF 25
> +
> +static inline u32 get_tlb_count(void)
> +{
> + register u32 config1;
> +
> + config1 = read_c0_config1();
> + config1 >>= TLB_COUNT_OFF;
> + config1 &= TLB_COUNT_MASK;
> +
> + return 1 + config1;
> +}
> +
> +static inline void create_tlb(int index, u32 offset, u32 size, u32 tlb_attrib1,
> + u32 tlb_attrib2)
> +{
> + register u32 tlb_mask, tlb_lo0, tlb_lo1;
> +
> + tlb_mask = ((size >> 12) - 1) << PAGEMASK_SHIFT;
> + tlb_lo0 = tlb_attrib1 | (offset >> TLB_LO_SHIFT);
> + tlb_lo1 = tlb_attrib2 | ((offset + size) >> TLB_LO_SHIFT);
> +
> + write_one_tlb(index, tlb_mask, offset & TLB_HI_MASK,
> + tlb_lo0 & TLB_LO_MASK, tlb_lo1 & TLB_LO_MASK);
> +}
> +#endif /* __ASM_MACH_TLB_H */
> diff --git a/arch/mips/mach-mscc/lowlevel_init.S b/arch/mips/mach-mscc/lowlevel_init.S
> new file mode 100644
> index 0000000000..e6dc9427e1
> --- /dev/null
> +++ b/arch/mips/mach-mscc/lowlevel_init.S
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#include <asm/asm.h>
> +#include <asm/regdef.h>
> +
> + .set noreorder
> + .extern vcoreiii_tlb_init
> +
> +LEAF(lowlevel_init)
> + /*
> + * As we have no stack yet, we can assume the restricted
> + * luxury of the sX-registers without saving them
> + */
> + move s0,ra
> +
> + jal vcoreiii_tlb_init
> + nop
> + jr s0
> + nop
> + END(lowlevel_init)
> diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c
> new file mode 100644
> index 0000000000..c4215ba228
> --- /dev/null
> +++ b/arch/mips/mach-mscc/reset.c
> @@ -0,0 +1,36 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#include <common.h>
> +
> +#include <asm/sections.h>
> +#include <asm/io.h>
> +
> +#include <asm/reboot.h>
> +
> +void _machine_restart(void)
> +{
> + register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
> + (void)readl(REG_GCB(PERF_SOFT_RST));
> +
> + /*
> + * Make sure VCore is NOT protected from reset
> + */
> + clrbits_le32(REG_CFG(ICPU_RESET), ICPU_RESET_CORE_RST_PROTECT);
> +
> + /*
> + * Change to SPI bitbang for SPI reset workaround...
> + */
> + writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) |
> + ICPU_SW_MODE_SW_PIN_CTRL_MODE, REG_CFG(ICPU_SW_MODE));
> +
> + /*
> + * Do the global reset
> + */
> + writel(resetbits, REG_GCB(PERF_SOFT_RST));
> +
> + while (1)
> + ; /* NOP */
> +}
>
is it possible to add a reset controller driver?
--
- Daniel
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^ permalink raw reply [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v2 3/7] MSCC: add support for Ocelot SoCs
2018-10-28 18:50 ` Daniel Schwierzeck
@ 2018-11-30 14:48 ` Gregory CLEMENT
0 siblings, 0 replies; 12+ messages in thread
From: Gregory CLEMENT @ 2018-11-30 14:48 UTC (permalink / raw)
To: u-boot
Hi Daniel,
On dim., oct. 28 2018, Daniel Schwierzeck <daniel.schwierzeck@gmail.com> wrote:
> Am 09.10.18 um 13:58 schrieb Gregory CLEMENT:
>> This family of SoCs are found in the Microsemi Switches solution and have
>> already a support in the linux kernel.
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>> arch/mips/Kconfig | 6 +
>> arch/mips/Makefile | 1 +
>> arch/mips/mach-mscc/Kconfig | 69 ++
>> arch/mips/mach-mscc/Makefile | 5 +
>> arch/mips/mach-mscc/cpu.c | 42 ++
>> arch/mips/mach-mscc/dram.c | 61 ++
>> arch/mips/mach-mscc/include/ioremap.h | 51 ++
>> arch/mips/mach-mscc/include/mach/common.h | 27 +
>> arch/mips/mach-mscc/include/mach/ddr.h | 680 ++++++++++++++++++
>> .../mach-mscc/include/mach/ocelot/ocelot.h | 35 +
>> .../include/mach/ocelot/ocelot_devcpu_gcb.h | 21 +
>> .../include/mach/ocelot/ocelot_icpu_cfg.h | 274 +++++++
>> arch/mips/mach-mscc/include/mach/tlb.h | 55 ++
>> arch/mips/mach-mscc/lowlevel_init.S | 23 +
>> arch/mips/mach-mscc/reset.c | 36 +
>> 15 files changed, 1386 insertions(+)
>> create mode 100644 arch/mips/mach-mscc/Kconfig
>> create mode 100644 arch/mips/mach-mscc/Makefile
>> create mode 100644 arch/mips/mach-mscc/cpu.c
>> create mode 100644 arch/mips/mach-mscc/dram.c
>> create mode 100644 arch/mips/mach-mscc/include/ioremap.h
>> create mode 100644 arch/mips/mach-mscc/include/mach/common.h
>> create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h
>> create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
>> create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
>> create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h
>> create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h
>> create mode 100644 arch/mips/mach-mscc/lowlevel_init.S
>> create mode 100644 arch/mips/mach-mscc/reset.c
>
> there are still some style issues and checkpatch.pl warnings in all
> patches. Please fix.
Actually there was a lot of warning no relevant such as:
- the ones about the "line over 80 character" in the headers, but
splitting the register definition in multiple line woul just make the
file less readbale
- the ones about "please write a paragraph that describes the config
symbol fully" fro the RAM choice, but the title give engough
information.
- the ones about "Use of volatile is usually wrong", but here we really
want to be sure that value will be really read from the memory that
we are testing.
- the one about "Avoid CamelCase", here the rational is to use a small
"t" in the naem of a register, as it make prefectly sens to use it to
indicate time: VC3_MPAR_tXSRD
And in the middle of them there were a few real issues that I indeed
missed and that I fixed now.
>
>> +/*
>> + * DDR memory sanity checking failed, tally and do hard reset
>> + *
>> + * NB: Assumes inlining as no stack is available!
>> + */
>> +static inline void hal_vcoreiii_ddr_failed(void)
>> +{
>> + register u32 reset;
>> +
>> + writel(readl(REG_CFG(ICPU_GPR(6))) + 1, REG_CFG(ICPU_GPR(6)));
>> +
>> + clrbits_le32(REG_GCB(PERF_GPIO_OE), BIT(19));
>> +
>> + /* Jump to reset - does not return */
>> + reset = KSEG0ADDR(_machine_restart);
>> + /* Reset while running from cache */
>> + icache_lock((void *)reset, 128);
>> + asm volatile ("jr %0"::"r" (reset));
>
> why do you need to move to KSEG0 and to lock the cache line? Do you run
> the whole lowlevel code in KSEG1 space?
Yes the vector code of this platform is not located in KSEG0 actually it
started at address 0x40000000 so in KUSEG.
Gregory
>
> I guess the SoC maps the SPI flash to some executable buffer from where
> U-Boot is started. If the I-Cache works on this buffer, you could move
> your text base to KSEG0 space and run fully cached after I-Caches have
> been initialised.
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 4/7] MSCC: add support for Luton SoCs
2018-10-09 11:58 [U-Boot] [PATCH v2 0/7] Add support for the SoCs found in Microsemi switches Gregory CLEMENT
` (2 preceding siblings ...)
2018-10-09 11:58 ` [U-Boot] [PATCH v2 3/7] MSCC: add support for Ocelot SoCs Gregory CLEMENT
@ 2018-10-09 11:58 ` Gregory CLEMENT
2018-10-09 11:58 ` [U-Boot] [PATCH v2 5/7] MSCC: add board support for the Ocelots based evaluation boards Gregory CLEMENT
` (2 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Gregory CLEMENT @ 2018-10-09 11:58 UTC (permalink / raw)
To: u-boot
As the Ocelots SoCs, this family of SoCs are found in the Microsemi
Switches solution.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/mach-mscc/Kconfig | 13 +
arch/mips/mach-mscc/Makefile | 1 +
arch/mips/mach-mscc/cpu.c | 13 +
arch/mips/mach-mscc/dram.c | 2 +
arch/mips/mach-mscc/include/mach/common.h | 4 +
arch/mips/mach-mscc/include/mach/ddr.h | 114 +++++++-
.../mips/mach-mscc/include/mach/luton/luton.h | 37 +++
.../include/mach/luton/luton_devcpu_gcb.h | 14 +
.../include/mach/luton/luton_icpu_cfg.h | 245 ++++++++++++++++++
arch/mips/mach-mscc/lowlevel_init.S | 7 +
arch/mips/mach-mscc/lowlevel_init_luton.S | 62 +++++
11 files changed, 508 insertions(+), 4 deletions(-)
create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h
create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h
create mode 100644 arch/mips/mach-mscc/lowlevel_init_luton.S
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index 7f1b270207..a8cace0e79 100644
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -21,6 +21,12 @@ config SOC_OCELOT
help
This supports MSCC Ocelot family of SOCs.
+config SOC_LUTON
+ bool
+ select SOC_VCOREIII
+ help
+ This supports MSCC Luton family of SOCs.
+
config SYS_CONFIG_NAME
default "vcoreiii"
@@ -41,6 +47,13 @@ config TARGET_OCELOT_PCB123
When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
ocelot_pcb123
+config TARGET_LUTON_PCB091
+ bool "MSCC PCB091 Reference Board"
+ select SOC_LUTON
+ select MSCC_BITBANG_SPI_GPIO
+ help
+ When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
+ luton_pcb091
endchoice
choice
diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
index d14ec33838..6c60f26ca4 100644
--- a/arch/mips/mach-mscc/Makefile
+++ b/arch/mips/mach-mscc/Makefile
@@ -3,3 +3,4 @@
CFLAGS_cpu.o += -finline-limit=64000
obj-y += cpu.o dram.o reset.o lowlevel_init.o
+obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
index 0c8f7933cd..562b2cf5f9 100644
--- a/arch/mips/mach-mscc/cpu.c
+++ b/arch/mips/mach-mscc/cpu.c
@@ -31,12 +31,25 @@ void vcoreiii_tlb_init(void)
*/
create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW,
MMU_REGIO_RW);
+#ifdef CONFIG_SOC_LUTON
+ create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW,
+ MMU_REGIO_RW);
+#endif
}
int mach_cpu_init(void)
{
/* Speed up NOR flash access */
+#ifdef CONFIG_SOC_LUTON
+ writel(ICPU_PI_MST_CFG_TRISTATE_CTRL +
+ ICPU_PI_MST_CFG_CLK_DIV(4), REG_CFG(ICPU_PI_MST_CFG));
+
+ writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
+ ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
+ ICPU_SPI_MST_CFG_CLK_DIV(9), REG_CFG(ICPU_SPI_MST_CFG));
+#else
writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), REG_CFG(ICPU_SPI_MST_CFG));
+#endif
return 0;
}
diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
index b82961f773..5ee141ab77 100644
--- a/arch/mips/mach-mscc/dram.c
+++ b/arch/mips/mach-mscc/dram.c
@@ -23,7 +23,9 @@ int vcoreiii_ddr_init(void)
hal_vcoreiii_wait_memctl();
if (hal_vcoreiii_init_dqs() != 0 ||
hal_vcoreiii_train_bytelane(0) != 0
+#ifdef CONFIG_SOC_OCELOT
|| hal_vcoreiii_train_bytelane(1) != 0
+#endif
)
hal_vcoreiii_ddr_failed();
}
diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h
index 41887097f9..4ba1f7974c 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -13,6 +13,10 @@
#include <mach/ocelot/ocelot.h>
#include <mach/ocelot/ocelot_devcpu_gcb.h>
#include <mach/ocelot/ocelot_icpu_cfg.h>
+#elif defined(CONFIG_SOC_LUTON)
+#include <mach/luton/luton.h>
+#include <mach/luton/luton_devcpu_gcb.h>
+#include <mach/luton/luton_icpu_cfg.h>
#else
#error Unsupported platform
#endif
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h
index c089af8e33..51ea65b573 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -586,6 +586,99 @@ static inline int dram_check(void)
}
return 0;
}
+#else /* Luton */
+
+static inline void sleep_100ns(u32 val)
+{
+}
+
+static inline void hal_vcoreiii_ddr_reset_assert(void)
+{
+ setbits_le32(REG_CFG(ICPU_MEMPHY_CFG), ICPU_MEMPHY_CFG_PHY_RST);
+ setbits_le32(REG_CFG(ICPU_RESET), ICPU_RESET_MEM_RST_FORCE);
+}
+
+static inline void hal_vcoreiii_ddr_reset_release(void)
+{
+}
+
+static inline void hal_vcoreiii_ddr_failed(void)
+{
+ register u32 memphy_cfg = readl(REG_CFG(ICPU_MEMPHY_CFG));
+
+ /* Do a fifo reset and start over */
+ writel(memphy_cfg | ICPU_MEMPHY_CFG_PHY_FIFO_RST,
+ REG_CFG(ICPU_MEMPHY_CFG));
+ writel(memphy_cfg & ~ICPU_MEMPHY_CFG_PHY_FIFO_RST,
+ REG_CFG(ICPU_MEMPHY_CFG));
+ writel(memphy_cfg | ICPU_MEMPHY_CFG_PHY_FIFO_RST,
+ REG_CFG(ICPU_MEMPHY_CFG));
+}
+
+static inline void hal_vcoreiii_ddr_verified(void)
+{
+}
+
+static inline int look_for(u32 data)
+{
+ register u32 byte = ((volatile u8 *)MSCC_DDR_TO)[0];
+
+ if (data != byte) {
+ if (!incr_dly(0))
+ return DDR_TRAIN_ERROR;
+ return DDR_TRAIN_CONTINUE;
+ }
+
+ return DDR_TRAIN_OK;
+}
+
+/* This algorithm is converted from the TCL training algorithm used
+ * during silicon simulation.
+ * NB: Assumes inlining as no stack is available!
+ */
+static inline int hal_vcoreiii_train_bytelane(u32 bytelane)
+{
+ register int res;
+
+ set_dly(bytelane, 0); // Start training at DQS=0
+ while ((res = look_for(0xff)) == DDR_TRAIN_CONTINUE)
+ ;
+ if (res != DDR_TRAIN_OK)
+ return res;
+
+ set_dly(bytelane, 0); // Start training at DQS=0
+ while ((res = look_for(0x00)) == DDR_TRAIN_CONTINUE)
+
+ ;
+
+ if (res != DDR_TRAIN_OK)
+ return res;
+
+ adjust_dly(-3);
+
+ return DDR_TRAIN_OK;
+}
+
+static inline int hal_vcoreiii_init_dqs(void)
+{
+ return 0;
+}
+
+static inline int dram_check(void)
+{
+#define DDR ((volatile u32 *) MSCC_DDR_TO)
+ register u32 i;
+
+ for (i = 0; i < 8; i++) {
+ DDR[i] = ~i;
+ if (DDR[i] != ~i)
+ return 1;
+ }
+
+ return 0;
+}
+#endif
+
/*
* NB: Called *early* to init memory controller - assumes inlining as
* no stack is available!
@@ -617,12 +710,12 @@ static inline void hal_vcoreiii_init_memctl(void)
/* Wait for ZCAL to clear */
while (readl(REG_CFG(ICPU_MEMPHY_ZCAL)) & ICPU_MEMPHY_ZCAL_ZCAL_ENA)
;
-
+#ifdef CONFIG_SOC_OCELOT
/* Check no ZCAL_ERR */
if (readl(REG_CFG(ICPU_MEMPHY_ZCAL_STAT))
& ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR)
hal_vcoreiii_ddr_failed();
-
+#endif
/* Drive CL, CK, ODT */
setbits_le32(REG_CFG(ICPU_MEMPHY_CFG), ICPU_MEMPHY_CFG_PHY_ODT_OE |
ICPU_MEMPHY_CFG_PHY_CK_OE | ICPU_MEMPHY_CFG_PHY_CL_OE);
@@ -631,8 +724,12 @@ static inline void hal_vcoreiii_init_memctl(void)
writel(MSCC_MEMPARM_MEMCFG, REG_CFG(ICPU_MEMCTRL_CFG));
writel(MSCC_MEMPARM_PERIOD, REG_CFG(ICPU_MEMCTRL_REF_PERIOD));
-
+#ifdef CONFIG_SOC_OCELOT
writel(MSCC_MEMPARM_TIMING0, REG_CFG(ICPU_MEMCTRL_TIMING0));
+#else /* Luton */
+ clrbits_le32(REG_CFG(ICPU_MEMCTRL_TIMING0), ((1 << 20) - 1));
+ setbits_le32(REG_CFG(ICPU_MEMCTRL_TIMING0), MSCC_MEMPARM_TIMING0);
+#endif
writel(MSCC_MEMPARM_TIMING1, REG_CFG(ICPU_MEMCTRL_TIMING1));
writel(MSCC_MEMPARM_TIMING2, REG_CFG(ICPU_MEMCTRL_TIMING2));
@@ -642,6 +739,7 @@ static inline void hal_vcoreiii_init_memctl(void)
writel(MSCC_MEMPARM_MR2, REG_CFG(ICPU_MEMCTRL_MR2_VAL));
writel(MSCC_MEMPARM_MR3, REG_CFG(ICPU_MEMCTRL_MR3_VAL));
+#ifdef CONFIG_SOC_OCELOT
/* Termination setup - enable ODT */
writel(ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA |
/* Assert ODT0 for any write */
@@ -652,6 +750,11 @@ static inline void hal_vcoreiii_init_memctl(void)
hal_vcoreiii_ddr_reset_release();
writel(readl(REG_CFG(ICPU_GPR(7))) + 1, REG_CFG(ICPU_GPR(7)));
+#else /* Luton */
+ /* Termination setup - disable ODT */
+ writel(0, REG_CFG(ICPU_MEMCTRL_TERMRES_CTRL));
+
+#endif
}
static inline void hal_vcoreiii_wait_memctl(void)
@@ -665,7 +768,7 @@ static inline void hal_vcoreiii_wait_memctl(void)
/* Settle...? */
sleep_100ns(10000);
-
+#ifdef CONFIG_SOC_OCELOT
/* Establish data contents in DDR RAM for training */
__raw_writel(0xcacafefe, ((void __iomem *)MSCC_DDR_TO));
@@ -676,5 +779,8 @@ static inline void hal_vcoreiii_wait_memctl(void)
__raw_writel(0xaaaa9999, ((void __iomem *)MSCC_DDR_TO + 0x14));
__raw_writel(0xccccbbbb, ((void __iomem *)MSCC_DDR_TO + 0x18));
__raw_writel(0xeeeedddd, ((void __iomem *)MSCC_DDR_TO + 0x1C));
+#else
+ __raw_writel(0xff, ((void __iomem *)MSCC_DDR_TO));
+#endif
}
#endif /* __ASM_MACH_DDR_H */
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton.h b/arch/mips/mach-mscc/include/mach/luton/luton.h
new file mode 100644
index 0000000000..b6e1090a2f
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/luton/luton.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Microsemi Ocelot Switch driver
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_OCELOT_H_
+#define _MSCC_OCELOT_H_
+
+#include <linux/bitops.h>
+#include <dm.h>
+
+/*
+ * Target offset base(s)
+ */
+#define MSCC_IO_ORIGIN1_OFFSET 0x60000000
+#define MSCC_IO_ORIGIN1_SIZE 0x01000000
+#define MSCC_IO_ORIGIN2_OFFSET 0x70000000
+#define MSCC_IO_ORIGIN2_SIZE 0x00200000
+#ifndef MSCC_IO_OFFSET1
+#define MSCC_IO_OFFSET1(offset) (MSCC_IO_ORIGIN1_OFFSET + offset)
+#endif
+#ifndef MSCC_IO_OFFSET2
+#define MSCC_IO_OFFSET2(offset) (MSCC_IO_ORIGIN2_OFFSET + offset)
+#endif
+#define BASE_CFG 0x70000000
+#define BASE_UART 0x70100000
+#define BASE_DEVCPU_GCB 0x60070000
+#define BASE_MACRO 0x600a0000
+
+#define REG_OFFSET(t, o) ((volatile unsigned long *)(t + (o)))
+#define REG_CFG(x) REG_OFFSET(BASE_CFG, x)
+#define REG_GCB(x) REG_OFFSET(BASE_DEVCPU_GCB, x)
+#define REG_MACRO(x) REG_OFFSET(BASE_MACRO, x)
+
+#endif
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
new file mode 100644
index 0000000000..8c0b612325
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_OCELOT_DEVCPU_GCB_H_
+#define _MSCC_OCELOT_DEVCPU_GCB_H_
+
+#define PERF_SOFT_RST 0x90
+
+#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)
+#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
+
+#endif
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h
new file mode 100644
index 0000000000..9233f037bb
--- /dev/null
+++ b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h
@@ -0,0 +1,245 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_OCELOT_ICPU_CFG_H_
+#define _MSCC_OCELOT_ICPU_CFG_H_
+
+#define ICPU_GPR(x) (0x4 * (x))
+#define ICPU_GPR_RSZ 0x4
+
+#define ICPU_RESET 0x20
+
+#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
+#define ICPU_RESET_CORE_RST_PROTECT BIT(2)
+#define ICPU_RESET_CORE_RST_FORCE BIT(1)
+#define ICPU_RESET_MEM_RST_FORCE BIT(0)
+
+#define ICPU_GENERAL_CTRL 0x24
+
+#define ICPU_GENERAL_CTRL_SWC_CLEAR_IF BIT(6)
+#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(5)
+#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(4)
+#define ICPU_GENERAL_CTRL_IF_MASTER_DIS BIT(3)
+#define ICPU_GENERAL_CTRL_IF_MASTER_SPI_ENA BIT(2)
+#define ICPU_GENERAL_CTRL_IF_MASTER_PI_ENA BIT(1)
+
+#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0)
+
+#define ICPU_PI_MST_CFG 0x2c
+
+#define ICPU_PI_MST_CFG_ATE_MODE_DIS BIT(7)
+#define ICPU_PI_MST_CFG_CLK_POL BIT(6)
+#define ICPU_PI_MST_CFG_TRISTATE_CTRL BIT(5)
+#define ICPU_PI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
+#define ICPU_PI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
+
+#define ICPU_SPI_MST_CFG 0x50
+
+#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10)
+#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
+#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
+#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
+#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
+#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
+
+#define ICPU_SW_MODE 0x64
+
+#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
+#define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
+#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11)
+#define ICPU_SW_MODE_SW_SPI_SDO BIT(10)
+#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9)
+#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
+#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
+#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
+#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1))
+#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1)
+#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1)
+#define ICPU_SW_MODE_SW_SPI_SDI BIT(0)
+
+#define ICPU_INTR_ENA 0x88
+
+#define ICPU_INTR_IRQ0_ENA 0x98
+#define ICPU_INTR_IRQ0_ENA_IRQ0_ENA BIT(0)
+
+#define ICPU_MEMCTRL_CTRL 0x234
+
+#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3)
+#define ICPU_MEMCTRL_CTRL_MDSET BIT(2)
+#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1)
+#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0)
+
+#define ICPU_MEMCTRL_CFG 0x238
+
+#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16)
+#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15)
+#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14)
+#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13)
+#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12)
+#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11)
+#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10)
+#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9)
+#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8)
+#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_STAT 0x23C
+
+#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5)
+#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4)
+#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3)
+#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2)
+#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1)
+#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0)
+
+#define ICPU_MEMCTRL_REF_PERIOD 0x240
+
+#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16))
+#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16)
+#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16)
+#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0))
+#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0)
+
+#define ICPU_MEMCTRL_TIMING0 0x248
+
+#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28))
+#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28)
+#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
+#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24))
+#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24)
+#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
+#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20))
+#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20)
+#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20)
+#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16))
+#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16)
+#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12))
+#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12)
+#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
+#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8))
+#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8)
+#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_TIMING1 0x24c
+
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24))
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24)
+#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16))
+#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16)
+#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12))
+#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12)
+#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8))
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_TIMING2 0x250
+
+#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28))
+#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28)
+#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
+#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24))
+#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24)
+#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
+#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16))
+#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16)
+#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY(x) ((x) & GENMASK(15, 0))
+#define ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY_M GENMASK(15, 0)
+
+#define ICPU_MEMCTRL_TIMING3 0x254
+
+#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16))
+#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16)
+#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
+#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12))
+#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12)
+#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
+#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8))
+#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8)
+#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
+#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4))
+#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4)
+#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
+#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0))
+#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0)
+
+#define ICPU_MEMCTRL_MR0_VAL 0x258
+
+#define ICPU_MEMCTRL_MR1_VAL 0x25c
+
+#define ICPU_MEMCTRL_MR2_VAL 0x260
+
+#define ICPU_MEMCTRL_MR3_VAL 0x264
+
+#define ICPU_MEMCTRL_TERMRES_CTRL 0x268
+
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7))
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2))
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2)
+#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2)
+#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1)
+#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0)
+
+#define ICPU_MEMCTRL_DQS_DLY(x) (0x270)
+
+#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8))
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5))
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5)
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0))
+#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0)
+
+#define ICPU_MEMPHY_CFG 0x278
+
+#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10)
+#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9)
+#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8)
+#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7)
+#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6)
+#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5)
+#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4)
+#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3)
+#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2)
+#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1)
+#define ICPU_MEMPHY_CFG_PHY_RST BIT(0)
+#define ICPU_MEMPHY_DQ_DLY_TRM 0x180
+#define ICPU_MEMPHY_DQ_DLY_TRM_RSZ 0x4
+
+#define ICPU_MEMPHY_ZCAL 0x294
+
+#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5))
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1))
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1)
+#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1)
+#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0)
+
+#endif
diff --git a/arch/mips/mach-mscc/lowlevel_init.S b/arch/mips/mach-mscc/lowlevel_init.S
index e6dc9427e1..a2776fa54e 100644
--- a/arch/mips/mach-mscc/lowlevel_init.S
+++ b/arch/mips/mach-mscc/lowlevel_init.S
@@ -8,6 +8,9 @@
.set noreorder
.extern vcoreiii_tlb_init
+#ifdef CONFIG_SOC_LUTON
+ .extern pll_init
+#endif
LEAF(lowlevel_init)
/*
@@ -18,6 +21,10 @@ LEAF(lowlevel_init)
jal vcoreiii_tlb_init
nop
+#ifdef CONFIG_SOC_LUTON
+ jal pll_init
+ nop
+#endif
jr s0
nop
END(lowlevel_init)
diff --git a/arch/mips/mach-mscc/lowlevel_init_luton.S b/arch/mips/mach-mscc/lowlevel_init_luton.S
new file mode 100644
index 0000000000..6b298a99da
--- /dev/null
+++ b/arch/mips/mach-mscc/lowlevel_init_luton.S
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+
+#define BASE_MACRO 0x600a0000
+#define REG_OFFSET(t, o) (t + (o*4))
+#define REG_MACRO(x) REG_OFFSET(BASE_MACRO, x)
+#define BIT(nr) (1 << (nr))
+
+#define MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0 REG_MACRO(6)
+#define MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS BIT(0)
+#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 REG_MACRO(2)
+#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0 REG_MACRO(0)
+#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV (0x3F << 6)
+#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV_ENC(x) (x << 6)
+
+ .set noreorder
+LEAF(pll_init)
+ /* Make sure PLL is locked */
+ lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0
+ andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS
+ bne v1, zero, 1f
+ nop
+
+ /* Black magic from frontend */
+ li v1, 0x00610400
+ sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
+
+ li v1, 0x00610c00
+ sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
+
+ li v1, 0x00610800
+ sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
+
+ li v1, 0x00610000
+ sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
+
+ /* Wait for lock */
+2: lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0
+ andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS
+ # Keep looping if zero (no lock bit yet)
+ beq v1, zero, 2b
+ nop
+
+ /* Setup PLL CPU clock divider for 416MHz */
+1: lw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0
+
+ /* Keep reserved bits */
+ li v1, ~MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV
+ and v0, v0, v1
+
+ /* Set code 6 ~ 416.66 MHz */
+ ori v0, v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV_ENC(6)
+
+ sw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0
+ jr ra
+ nop
+ END(pll_init)
--
2.19.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v2 5/7] MSCC: add board support for the Ocelots based evaluation boards
2018-10-09 11:58 [U-Boot] [PATCH v2 0/7] Add support for the SoCs found in Microsemi switches Gregory CLEMENT
` (3 preceding siblings ...)
2018-10-09 11:58 ` [U-Boot] [PATCH v2 4/7] MSCC: add support for Luton SoCs Gregory CLEMENT
@ 2018-10-09 11:58 ` Gregory CLEMENT
2018-10-09 11:58 ` [U-Boot] [PATCH v2 6/7] MSCC: add board support for the Luton based evaluation board Gregory CLEMENT
2018-10-09 11:58 ` [U-Boot] [PATCH v2 7/7] MIPS: bootm: Add support for Vcore III linux kernel Gregory CLEMENT
6 siblings, 0 replies; 12+ messages in thread
From: Gregory CLEMENT @ 2018-10-09 11:58 UTC (permalink / raw)
To: u-boot
Adding the support for 2 boards sharing common code for Ocelot chip:
PCB120 and PCB123
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/dts/mscc,ocelot.dtsi | 132 +++++++++++++++++++++++++++
arch/mips/dts/mscc,ocelot_pcb.dtsi | 33 +++++++
arch/mips/dts/ocelot_pcb120.dts | 12 +++
arch/mips/dts/ocelot_pcb123.dts | 12 +++
arch/mips/mach-mscc/Kconfig | 2 +
board/mscc/ocelot/Kconfig | 14 +++
board/mscc/ocelot/Makefile | 4 +
board/mscc/ocelot/ocelot.c | 48 ++++++++++
configs/mscc_ocelot_defconfig | 57 ++++++++++++
configs/mscc_ocelot_pcb120_defconfig | 56 ++++++++++++
include/configs/vcoreiii.h | 77 ++++++++++++++++
11 files changed, 447 insertions(+)
create mode 100644 arch/mips/dts/mscc,ocelot.dtsi
create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi
create mode 100644 arch/mips/dts/ocelot_pcb120.dts
create mode 100644 arch/mips/dts/ocelot_pcb123.dts
create mode 100644 board/mscc/ocelot/Kconfig
create mode 100644 board/mscc/ocelot/Makefile
create mode 100644 board/mscc/ocelot/ocelot.c
create mode 100644 configs/mscc_ocelot_defconfig
create mode 100644 configs/mscc_ocelot_pcb120_defconfig
create mode 100644 include/configs/vcoreiii.h
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
new file mode 100644
index 0000000000..81afdffd4b
--- /dev/null
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,ocelot";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <&cpu_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpuintc: interrupt-controller at 0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <500000000>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x70000000 0x2000000>;
+
+ interrupt-parent = <&intc>;
+
+ cpu_ctrl: syscon at 0 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x0 0x2c>;
+ };
+
+ intc: interrupt-controller at 70 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ uart0: serial at 100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100000 0x20>;
+ interrupts = <6>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial at 100800 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100800 0x20>;
+ interrupts = <7>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ spi0: spi-master at 101000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x101000 0x40>;
+ num-chipselect = <4>;
+ bus-num = <0>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ spi-max-frequency = <18000000>; /* input clock */
+ clocks = <&ahb_clk>;
+
+ status = "disabled";
+ };
+
+ reset at 1070008 {
+ compatible = "mscc,ocelot-chip-reset";
+ reg = <0x1070008 0x4>;
+ };
+
+ gpio: pinctrl at 1070034 {
+ compatible = "mscc,ocelot-pinctrl";
+ reg = <0x1070034 0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 22>;
+
+ uart_pins: uart-pins {
+ pins = "GPIO_6", "GPIO_7";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+ pins = "GPIO_12", "GPIO_13";
+ function = "uart2";
+ };
+ };
+ };
+};
diff --git a/arch/mips/dts/mscc,ocelot_pcb.dtsi b/arch/mips/dts/mscc,ocelot_pcb.dtsi
new file mode 100644
index 0000000000..90f4156469
--- /dev/null
+++ b/arch/mips/dts/mscc,ocelot_pcb.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,ocelot.dtsi"
+
+/ {
+ compatible = "mscc,ocelot";
+
+ aliases {
+ spi0 = &spi0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ spi-flash at 0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <18000000>; /* input clock */
+ reg = <0>; /* CS0 */
+ };
+};
diff --git a/arch/mips/dts/ocelot_pcb120.dts b/arch/mips/dts/ocelot_pcb120.dts
new file mode 100644
index 0000000000..47d305a614
--- /dev/null
+++ b/arch/mips/dts/ocelot_pcb120.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,ocelot_pcb.dtsi"
+
+/ {
+ model = "Ocelot PCB120 Reference Board";
+ compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
+};
diff --git a/arch/mips/dts/ocelot_pcb123.dts b/arch/mips/dts/ocelot_pcb123.dts
new file mode 100644
index 0000000000..17d8d326ce
--- /dev/null
+++ b/arch/mips/dts/ocelot_pcb123.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,ocelot_pcb.dtsi"
+
+/ {
+ model = "Ocelot PCB123 Reference Board";
+ compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
+};
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index a8cace0e79..fc806fc1f3 100644
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -79,4 +79,6 @@ config DDRTYPE_MT47H128M8HQ
endchoice
+source "board/mscc/ocelot/Kconfig"
+
endmenu
diff --git a/board/mscc/ocelot/Kconfig b/board/mscc/ocelot/Kconfig
new file mode 100644
index 0000000000..9ddc0880b1
--- /dev/null
+++ b/board/mscc/ocelot/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config SYS_VENDOR
+ default "mscc"
+
+if SOC_OCELOT
+
+config SYS_BOARD
+ default "ocelot"
+
+config SYS_CONFIG_NAME
+ default "ocelot"
+
+endif
diff --git a/board/mscc/ocelot/Makefile b/board/mscc/ocelot/Makefile
new file mode 100644
index 0000000000..9f28c81268
--- /dev/null
+++ b/board/mscc/ocelot/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_OCELOT) := ocelot.o
+
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
new file mode 100644
index 0000000000..6f28cfc2b8
--- /dev/null
+++ b/board/mscc/ocelot/ocelot.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <environment.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void external_cs_manage(struct udevice *dev, bool enable)
+{
+ u32 cs = spi_chip_select(dev);
+ /* IF_SI0_OWNER, select the owner of the SI interface
+ * Encoding: 0: SI Slave
+ * 1: SI Boot Master
+ * 2: SI Master Controller
+ */
+ if (!enable) {
+ writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
+ ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), REG_CFG(ICPU_SW_MODE));
+ clrsetbits_le32(REG_CFG(ICPU_GENERAL_CTRL),
+ ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
+ ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
+ } else {
+ writel(0, REG_CFG(ICPU_SW_MODE));
+ clrsetbits_le32(REG_CFG(ICPU_GENERAL_CTRL),
+ ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
+ ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
+ }
+}
+
+int board_early_init_r(void)
+{
+ /* Prepare SPI controller to be used in master mode */
+ writel(0, REG_CFG(ICPU_SW_MODE));
+ clrsetbits_le32(REG_CFG(ICPU_GENERAL_CTRL),
+ ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
+ ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+ return 0;
+}
diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig
new file mode 100644
index 0000000000..eb0566189a
--- /dev/null
+++ b/configs/mscc_ocelot_defconfig
@@ -0,0 +1,57 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_MSCC=y
+CONFIG_TARGET_OCELOT_PCB123=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123"
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_LOGLEVEL=7
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_SYS_PROMPT="pcb123 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+# CONFIG_NET_TFTP_VARS is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)"
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_EMBED=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_LZMA=y
diff --git a/configs/mscc_ocelot_pcb120_defconfig b/configs/mscc_ocelot_pcb120_defconfig
new file mode 100644
index 0000000000..40cdec45f1
--- /dev/null
+++ b/configs/mscc_ocelot_pcb120_defconfig
@@ -0,0 +1,56 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_MSCC=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb120"
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_LOGLEVEL=7
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_SYS_PROMPT="pcb120 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+# CONFIG_NET_TFTP_VARS is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)"
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_EMBED=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_LZMA=y
diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h
new file mode 100644
index 0000000000..38110a233e
--- /dev/null
+++ b/include/configs/vcoreiii.h
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef __VCOREIII_H
+#define __VCOREIII_H
+
+#include <linux/sizes.h>
+
+/* Onboard devices */
+
+#define CONFIG_SYS_MALLOC_LEN 0xF0000
+#define CONFIG_SYS_LOAD_ADDR 0x00100000
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+
+#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */
+#ifdef CONFIG_SOC_LUTON
+#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333
+#else
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
+#endif
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
+
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_OFFSET (1024 * 1024)
+#define CONFIG_ENV_SIZE (256 * 1024)
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
+#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
+#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT)
+#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M)
+#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16)
+#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M)
+#else
+#error Unknown DDR size - please add!
+#endif
+
+#define CONFIG_CONS_INDEX 1
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - SZ_1M)
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#if defined (CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
+#define VCOREIII_DEFAULT_MTD_ENV \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+ "mtdids="CONFIG_MTDIDS_DEFAULT "\0"
+#else
+#define VCOREIII_DEFAULT_MTD_ENV // Go away
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ VCOREIII_DEFAULT_MTD_ENV \
+ "loadaddr=0x81000000" "\0" \
+ "spi_image_off=0x00100000" "\0" \
+ "console=ttyS0,115200" "\0" \
+ "setup=setenv bootargs console=${console} ${mtdparts} ${bootargs_extra}" "\0" \
+ "spiboot=run setup; sf probe; sf read ${loadaddr} ${spi_image_off} 0x600000; bootm ${loadaddr}" "\0" \
+ "ubootfile=u-boot.bin" "\0" \
+ "update=sf probe;mtdparts;dhcp ${loadaddr} ${ubootfile};" \
+ "sf erase UBoot 0x100000;sf write ${loadaddr} UBoot ${filesize}" "\0" \
+ "bootcmd=run spiboot"
+
+#endif /* __VCOREIII_H */
--
2.19.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v2 6/7] MSCC: add board support for the Luton based evaluation board
2018-10-09 11:58 [U-Boot] [PATCH v2 0/7] Add support for the SoCs found in Microsemi switches Gregory CLEMENT
` (4 preceding siblings ...)
2018-10-09 11:58 ` [U-Boot] [PATCH v2 5/7] MSCC: add board support for the Ocelots based evaluation boards Gregory CLEMENT
@ 2018-10-09 11:58 ` Gregory CLEMENT
2018-10-09 11:58 ` [U-Boot] [PATCH v2 7/7] MIPS: bootm: Add support for Vcore III linux kernel Gregory CLEMENT
6 siblings, 0 replies; 12+ messages in thread
From: Gregory CLEMENT @ 2018-10-09 11:58 UTC (permalink / raw)
To: u-boot
Adding the support for the Luton boards PCB91 which share common code with
the Ocelots boards, including board code, device tree and configuration.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/dts/luton_pcb091.dts | 36 ++++++++++++++
arch/mips/dts/mscc,luton.dtsi | 87 ++++++++++++++++++++++++++++++++++
arch/mips/mach-mscc/Kconfig | 2 +
board/mscc/luton/Kconfig | 14 ++++++
board/mscc/luton/Makefile | 3 ++
board/mscc/luton/luton.c | 28 +++++++++++
configs/mscc_luton_defconfig | 66 ++++++++++++++++++++++++++
7 files changed, 236 insertions(+)
create mode 100644 arch/mips/dts/luton_pcb091.dts
create mode 100644 arch/mips/dts/mscc,luton.dtsi
create mode 100644 board/mscc/luton/Kconfig
create mode 100644 board/mscc/luton/Makefile
create mode 100644 board/mscc/luton/luton.c
create mode 100644 configs/mscc_luton_defconfig
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
new file mode 100644
index 0000000000..b5e0df8d04
--- /dev/null
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,luton.dtsi"
+
+/ {
+ model = "Luton PCB091 Reference Board";
+ compatible = "mscc,luton-pcb091", "mscc,luton";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ spi-flash at 0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <18000000>; /* input clock */
+ reg = <0>; /* CS0 */
+ };
+};
+
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
new file mode 100644
index 0000000000..6a4ad2a5be
--- /dev/null
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,luton";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <208333333>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x60000000 0x10200000>;
+
+ uart0: serial at 10100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+
+ compatible = "ns16550a";
+ reg = <0x10100000 0x20>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ gpio: pinctrl at 70068 {
+ compatible = "mscc,luton-pinctrl";
+ reg = <0x70068 0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 32>;
+
+ uart_pins: uart-pins {
+ pins = "GPIO_30", "GPIO_31";
+ function = "uart";
+ };
+
+ };
+
+ gpio_spi_bitbang: gpio at 10000064 {
+ compatible = "mscc,spi-bitbang-gpio";
+ reg = <0x10000064 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ };
+
+ spi0: spi-bitbang {
+ compatible = "spi-gpio";
+ status = "okay";
+ gpio-sck = <&gpio_spi_bitbang 6 0>;
+ gpio-miso = <&gpio_spi_bitbang 0 0>;
+ gpio-mosi = <&gpio_spi_bitbang 5 0>;
+ cs-gpios = <&gpio_spi_bitbang 1 0>;
+ num-chipselects = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index fc806fc1f3..0e35b77c9d 100644
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -81,4 +81,6 @@ endchoice
source "board/mscc/ocelot/Kconfig"
+source "board/mscc/luton/Kconfig"
+
endmenu
diff --git a/board/mscc/luton/Kconfig b/board/mscc/luton/Kconfig
new file mode 100644
index 0000000000..e1199808d5
--- /dev/null
+++ b/board/mscc/luton/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+if SOC_LUTON
+
+config SYS_VENDOR
+ default "mscc"
+
+config SYS_BOARD
+ default "luton"
+
+config SYS_CONFIG_NAME
+ default "luton"
+
+endif
diff --git a/board/mscc/luton/Makefile b/board/mscc/luton/Makefile
new file mode 100644
index 0000000000..b27f7c7739
--- /dev/null
+++ b/board/mscc/luton/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_LUTON) := luton.o
diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c
new file mode 100644
index 0000000000..6be55d4c46
--- /dev/null
+++ b/board/mscc/luton/luton.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MSCC_GPIO_ALT0 0x88
+#define MSCC_GPIO_ALT1 0x8C
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_debug_uart_init(void)
+{
+ /* too early for the pinctrl driver, so configure the UART pins here */
+ setbits_le32(REG_GCB(MSCC_GPIO_ALT0), BIT(30) | BIT(31));
+}
+
+int board_early_init_r(void)
+{
+ /* Prepare SPI controller to be used in master mode */
+ writel(0, REG_CFG(ICPU_SW_MODE));
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+ return 0;
+}
diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig
new file mode 100644
index 0000000000..47fe12b6ee
--- /dev/null
+++ b/configs/mscc_luton_defconfig
@@ -0,0 +1,66 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0x70100000
+CONFIG_DEBUG_UART_CLOCK=208333333
+CONFIG_ARCH_MSCC=y
+CONFIG_TARGET_LUTON_PCB091=y
+CONFIG_DDRTYPE_MT47H128M8HQ=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_LOGLEVEL=7
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_SYS_PROMPT="pcb091 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+# CONFIG_NET_TFTP_VARS is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m at 1m(linux)"
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_EMBED=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_LZMA=y
+CONFIG_XZ=y
--
2.19.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v2 7/7] MIPS: bootm: Add support for Vcore III linux kernel
2018-10-09 11:58 [U-Boot] [PATCH v2 0/7] Add support for the SoCs found in Microsemi switches Gregory CLEMENT
` (5 preceding siblings ...)
2018-10-09 11:58 ` [U-Boot] [PATCH v2 6/7] MSCC: add board support for the Luton based evaluation board Gregory CLEMENT
@ 2018-10-09 11:58 ` Gregory CLEMENT
2018-10-28 17:54 ` Daniel Schwierzeck
6 siblings, 1 reply; 12+ messages in thread
From: Gregory CLEMENT @ 2018-10-09 11:58 UTC (permalink / raw)
To: u-boot
The kernels built for the Vcore III linux kernel have different
expectation in the way the data were passed.
Unlike with yamon, the command line is expected to be a single string
passed in argv[1]. An other expectation is that the arguments are located
in the cached address space.
However, like yamon, they expect that rd_start and rd_size was passed by
the bootloader in the command line of the kernel, and besides that it
also wait for the root=/dev/ram0.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/lib/bootm.c | 77 ++++++++++++++++++++++++++++++++-----------
1 file changed, 57 insertions(+), 20 deletions(-)
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index deca5189e3..803d5e1de3 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -15,6 +15,11 @@ DECLARE_GLOBAL_DATA_PTR;
#define LINUX_MAX_ENVS 256
#define LINUX_MAX_ARGS 256
+enum legacy_boot_type {
+ LEGACY_BOOT_YAML,
+ LEGACY_BOOT_VCORE,
+};
+
static int linux_argc;
static char **linux_argv;
static char *linux_argp;
@@ -44,22 +49,46 @@ void arch_lmb_reserve(struct lmb *lmb)
lmb_reserve(lmb, sp, gd->ram_top - sp);
}
-static void linux_cmdline_init(void)
+static void linux_cmdline_init(enum legacy_boot_type boot_type)
{
+ switch (boot_type) {
+ /*
+ * Vcore III linux kernels expect arguments in the cached
+ * address space. They also expect the command line being a
+ * single string in the first argument
+ */
+ case LEGACY_BOOT_VCORE:
+ linux_argv = (char **)(gd->bd->bi_boot_params);
+ linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
+ linux_argv[1] = linux_argp;
+ break;
+ case LEGACY_BOOT_YAML:
+ /* fallthrough */
+ default:
+ linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
+ linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
+ }
linux_argc = 1;
- linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
linux_argv[0] = 0;
- linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
}
-static void linux_cmdline_set(const char *value, size_t len)
+static void linux_cmdline_set(const char *value, size_t len,
+ enum legacy_boot_type boot_type)
{
- linux_argv[linux_argc] = linux_argp;
memcpy(linux_argp, value, len);
- linux_argp[len] = 0;
-
+ switch (boot_type) {
+ case LEGACY_BOOT_VCORE:
+ linux_argv[linux_argc] = linux_argp;
+ linux_argp[len] = 0;
+ linux_argc++;
+ case LEGACY_BOOT_YAML:
+ /* fallthrough */
+ default:
+ linux_argp[len] = ' ';
+ linux_argp[len + 1] = 0;
+ linux_argc = 2;
+ }
linux_argp += len + 1;
- linux_argc++;
}
static void linux_cmdline_dump(void)
@@ -73,12 +102,11 @@ static void linux_cmdline_dump(void)
debug(" arg %03d: %s\n", i, linux_argv[i]);
}
-static void linux_cmdline_legacy(bootm_headers_t *images)
+static void linux_cmdline_legacy(bootm_headers_t *images,
+ enum legacy_boot_type boot_type)
{
const char *bootargs, *next, *quote;
-
- linux_cmdline_init();
-
+ linux_cmdline_init(boot_type);
bootargs = env_get("bootargs");
if (!bootargs)
return;
@@ -104,7 +132,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
if (!next)
next = bootargs + strlen(bootargs);
- linux_cmdline_set(bootargs, next - bootargs);
+ linux_cmdline_set(bootargs, next - bootargs, boot_type);
if (*next)
next++;
@@ -113,7 +141,8 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
}
}
-static void linux_cmdline_append(bootm_headers_t *images)
+static void linux_cmdline_append(bootm_headers_t *images,
+ enum legacy_boot_type boot_type)
{
char buf[24];
ulong mem, rd_start, rd_size;
@@ -121,7 +150,7 @@ static void linux_cmdline_append(bootm_headers_t *images)
/* append mem */
mem = gd->ram_size >> 20;
sprintf(buf, "mem=%luM", mem);
- linux_cmdline_set(buf, strlen(buf));
+ linux_cmdline_set(buf, strlen(buf), boot_type);
/* append rd_start and rd_size */
rd_start = images->initrd_start;
@@ -129,9 +158,13 @@ static void linux_cmdline_append(bootm_headers_t *images)
if (rd_size) {
sprintf(buf, "rd_start=0x%08lX", rd_start);
- linux_cmdline_set(buf, strlen(buf));
+ linux_cmdline_set(buf, strlen(buf), boot_type);
sprintf(buf, "rd_size=0x%lX", rd_size);
- linux_cmdline_set(buf, strlen(buf));
+ linux_cmdline_set(buf, strlen(buf), boot_type);
+ if (boot_type == LEGACY_BOOT_VCORE) {
+ sprintf(buf, "root=/dev/ram0");
+ linux_cmdline_set(buf, strlen(buf), boot_type);
+ }
}
}
@@ -276,11 +309,15 @@ static void boot_prep_linux(bootm_headers_t *images)
boot_reloc_fdt(images);
boot_setup_fdt(images);
} else {
- if (CONFIG_IS_ENABLED(MIPS_BOOT_CMDLINE_LEGACY)) {
- linux_cmdline_legacy(images);
+ if (CONFIG_IS_ENABLED(SOC_VCOREIII)) {
+ linux_cmdline_legacy(images, LEGACY_BOOT_VCORE);
+ linux_cmdline_append(images, LEGACY_BOOT_VCORE);
+ linux_cmdline_dump();
+ } else if (CONFIG_IS_ENABLED(MIPS_BOOT_CMDLINE_LEGACY)) {
+ linux_cmdline_legacy(images, 0);
if (!CONFIG_IS_ENABLED(MIPS_BOOT_ENV_LEGACY))
- linux_cmdline_append(images);
+ linux_cmdline_append(images, LEGACY_BOOT_YAML);
linux_cmdline_dump();
}
--
2.19.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v2 7/7] MIPS: bootm: Add support for Vcore III linux kernel
2018-10-09 11:58 ` [U-Boot] [PATCH v2 7/7] MIPS: bootm: Add support for Vcore III linux kernel Gregory CLEMENT
@ 2018-10-28 17:54 ` Daniel Schwierzeck
2018-11-30 14:16 ` Gregory CLEMENT
0 siblings, 1 reply; 12+ messages in thread
From: Daniel Schwierzeck @ 2018-10-28 17:54 UTC (permalink / raw)
To: u-boot
Hi Gregory,
sorry for the late response.
Am 09.10.18 um 13:58 schrieb Gregory CLEMENT:
> The kernels built for the Vcore III linux kernel have different
> expectation in the way the data were passed.
>
> Unlike with yamon, the command line is expected to be a single string
> passed in argv[1]. An other expectation is that the arguments are located
> in the cached address space.
I'm still not convinced whether this patch is necessary. As far as I
understand, you can boot a mainline kernel with the device-tree blob way
or with the legacy way. The latter makes sense when booting a mainline
kernel with Redboot. But what's the use case for booting a mainline
kernel in mainline U-Boot in the legacy way? Do you still want to boot
out-of-tree legacy kernels with mainline U-Boot?
Apart from this is this single cmdline string specific to Redboot or
only to Microsemi? The former would be acceptable for a generic patch to
emulate a Redboot interface (similar to the YAMON one). But this should
be configurable for the user via Kconfig. You could enable this by
default with an "imply MIPS_BOOT_CMDLINE_REDBOOT" in your SoC/board
specific Kconfig part.
>
> However, like yamon, they expect that rd_start and rd_size was passed by
> the bootloader in the command line of the kernel, and besides that it
> also wait for the root=/dev/ram0.
Who exactly needs "root=/dev/ram0"? Normally the generic MIPS setup code
only needs "rd_start" and "rd_size" from cmdline respectively
"linux,initrd-start" and "linux,initrd-end" from the device-tree blob.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> arch/mips/lib/bootm.c | 77 ++++++++++++++++++++++++++++++++-----------
> 1 file changed, 57 insertions(+), 20 deletions(-)
>
> diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
> index deca5189e3..803d5e1de3 100644
> --- a/arch/mips/lib/bootm.c
> +++ b/arch/mips/lib/bootm.c
> @@ -15,6 +15,11 @@ DECLARE_GLOBAL_DATA_PTR;
> #define LINUX_MAX_ENVS 256
> #define LINUX_MAX_ARGS 256
>
> +enum legacy_boot_type {
> + LEGACY_BOOT_YAML,
> + LEGACY_BOOT_VCORE,
> +};
> +
> static int linux_argc;
> static char **linux_argv;
> static char *linux_argp;
> @@ -44,22 +49,46 @@ void arch_lmb_reserve(struct lmb *lmb)
> lmb_reserve(lmb, sp, gd->ram_top - sp);
> }
>
> -static void linux_cmdline_init(void)
> +static void linux_cmdline_init(enum legacy_boot_type boot_type)
> {
> + switch (boot_type) {
> + /*
> + * Vcore III linux kernels expect arguments in the cached
> + * address space. They also expect the command line being a
> + * single string in the first argument
> + */
> + case LEGACY_BOOT_VCORE:
> + linux_argv = (char **)(gd->bd->bi_boot_params);
> + linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
> + linux_argv[1] = linux_argp;
> + break;
> + case LEGACY_BOOT_YAML:
> + /* fallthrough */
> + default:
> + linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
> + linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
> + }
> linux_argc = 1;
> - linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
> linux_argv[0] = 0;
> - linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
> }
>
> -static void linux_cmdline_set(const char *value, size_t len)
> +static void linux_cmdline_set(const char *value, size_t len,
> + enum legacy_boot_type boot_type)
> {
> - linux_argv[linux_argc] = linux_argp;
> memcpy(linux_argp, value, len);
> - linux_argp[len] = 0;
> -
> + switch (boot_type) {
> + case LEGACY_BOOT_VCORE:
> + linux_argv[linux_argc] = linux_argp;
> + linux_argp[len] = 0;
> + linux_argc++;
> + case LEGACY_BOOT_YAML:
> + /* fallthrough */
> + default:
> + linux_argp[len] = ' ';
> + linux_argp[len + 1] = 0;
> + linux_argc = 2;
> + }
> linux_argp += len + 1;
> - linux_argc++;
> }
>
> static void linux_cmdline_dump(void)
> @@ -73,12 +102,11 @@ static void linux_cmdline_dump(void)
> debug(" arg %03d: %s\n", i, linux_argv[i]);
> }
>
> -static void linux_cmdline_legacy(bootm_headers_t *images)
> +static void linux_cmdline_legacy(bootm_headers_t *images,
> + enum legacy_boot_type boot_type)
> {
> const char *bootargs, *next, *quote;
> -
> - linux_cmdline_init();
> -
> + linux_cmdline_init(boot_type);
> bootargs = env_get("bootargs");
> if (!bootargs)
> return;
> @@ -104,7 +132,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
> if (!next)
> next = bootargs + strlen(bootargs);
>
> - linux_cmdline_set(bootargs, next - bootargs);
> + linux_cmdline_set(bootargs, next - bootargs, boot_type);
>
> if (*next)
> next++;
> @@ -113,7 +141,8 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
> }
> }
>
> -static void linux_cmdline_append(bootm_headers_t *images)
> +static void linux_cmdline_append(bootm_headers_t *images,
> + enum legacy_boot_type boot_type)
> {
> char buf[24];
> ulong mem, rd_start, rd_size;
> @@ -121,7 +150,7 @@ static void linux_cmdline_append(bootm_headers_t *images)
> /* append mem */
> mem = gd->ram_size >> 20;
> sprintf(buf, "mem=%luM", mem);
> - linux_cmdline_set(buf, strlen(buf));
> + linux_cmdline_set(buf, strlen(buf), boot_type);
>
> /* append rd_start and rd_size */
> rd_start = images->initrd_start;
> @@ -129,9 +158,13 @@ static void linux_cmdline_append(bootm_headers_t *images)
>
> if (rd_size) {
> sprintf(buf, "rd_start=0x%08lX", rd_start);
> - linux_cmdline_set(buf, strlen(buf));
> + linux_cmdline_set(buf, strlen(buf), boot_type);
> sprintf(buf, "rd_size=0x%lX", rd_size);
> - linux_cmdline_set(buf, strlen(buf));
> + linux_cmdline_set(buf, strlen(buf), boot_type);
> + if (boot_type == LEGACY_BOOT_VCORE) {
> + sprintf(buf, "root=/dev/ram0");
> + linux_cmdline_set(buf, strlen(buf), boot_type);
> + }
> }
> }
>
> @@ -276,11 +309,15 @@ static void boot_prep_linux(bootm_headers_t *images)
> boot_reloc_fdt(images);
> boot_setup_fdt(images);
> } else {
> - if (CONFIG_IS_ENABLED(MIPS_BOOT_CMDLINE_LEGACY)) {
> - linux_cmdline_legacy(images);
> + if (CONFIG_IS_ENABLED(SOC_VCOREIII)) {
> + linux_cmdline_legacy(images, LEGACY_BOOT_VCORE);
> + linux_cmdline_append(images, LEGACY_BOOT_VCORE);
> + linux_cmdline_dump();
> + } else if (CONFIG_IS_ENABLED(MIPS_BOOT_CMDLINE_LEGACY)) {
> + linux_cmdline_legacy(images, 0);
>
> if (!CONFIG_IS_ENABLED(MIPS_BOOT_ENV_LEGACY))
> - linux_cmdline_append(images);
> + linux_cmdline_append(images, LEGACY_BOOT_YAML);
>
> linux_cmdline_dump();
> }
>
--
- Daniel
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^ permalink raw reply [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v2 7/7] MIPS: bootm: Add support for Vcore III linux kernel
2018-10-28 17:54 ` Daniel Schwierzeck
@ 2018-11-30 14:16 ` Gregory CLEMENT
0 siblings, 0 replies; 12+ messages in thread
From: Gregory CLEMENT @ 2018-11-30 14:16 UTC (permalink / raw)
To: u-boot
Hi Daniel,
On dim., oct. 28 2018, Daniel Schwierzeck <daniel.schwierzeck@gmail.com> wrote:
> Hi Gregory,
>
> sorry for the late response.
>
> Am 09.10.18 um 13:58 schrieb Gregory CLEMENT:
>> The kernels built for the Vcore III linux kernel have different
>> expectation in the way the data were passed.
>>
>> Unlike with yamon, the command line is expected to be a single string
>> passed in argv[1]. An other expectation is that the arguments are located
>> in the cached address space.
>
> I'm still not convinced whether this patch is necessary. As far as I
> understand, you can boot a mainline kernel with the device-tree blob way
> or with the legacy way. The latter makes sense when booting a mainline
> kernel with Redboot. But what's the use case for booting a mainline
> kernel in mainline U-Boot in the legacy way? Do you still want to boot
> out-of-tree legacy kernels with mainline U-Boot?
Currently there is only redboot which is used , but there is already
mainline kernel in legacy format. The purpose of it, is to be able to
switch from reboot to u-Boot but still being able to boot the mainline
kernel currently used.
As a bonus it could also allow to boot old out of tree kernel, but I
don't think it is something planed.
>
> Apart from this is this single cmdline string specific to Redboot or
> only to Microsemi? The former would be acceptable for a generic patch to
Actually I don't know.
> emulate a Redboot interface (similar to the YAMON one). But this should
> be configurable for the user via Kconfig. You could enable this by
> default with an "imply MIPS_BOOT_CMDLINE_REDBOOT" in your SoC/board
> specific Kconfig part.
>
>>
>> However, like yamon, they expect that rd_start and rd_size was passed by
>> the bootloader in the command line of the kernel, and besides that it
>> also wait for the root=/dev/ram0.
>
> Who exactly needs "root=/dev/ram0"? Normally the generic MIPS setup code
> only needs "rd_start" and "rd_size" from cmdline respectively
> "linux,initrd-start" and "linux,initrd-end" from the device-tree blob.
If it is a problem I think that we can use a U-boot script to take care
of this value.
Gregory
>
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>> arch/mips/lib/bootm.c | 77 ++++++++++++++++++++++++++++++++-----------
>> 1 file changed, 57 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
>> index deca5189e3..803d5e1de3 100644
>> --- a/arch/mips/lib/bootm.c
>> +++ b/arch/mips/lib/bootm.c
>> @@ -15,6 +15,11 @@ DECLARE_GLOBAL_DATA_PTR;
>> #define LINUX_MAX_ENVS 256
>> #define LINUX_MAX_ARGS 256
>>
>> +enum legacy_boot_type {
>> + LEGACY_BOOT_YAML,
>> + LEGACY_BOOT_VCORE,
>> +};
>> +
>> static int linux_argc;
>> static char **linux_argv;
>> static char *linux_argp;
>> @@ -44,22 +49,46 @@ void arch_lmb_reserve(struct lmb *lmb)
>> lmb_reserve(lmb, sp, gd->ram_top - sp);
>> }
>>
>> -static void linux_cmdline_init(void)
>> +static void linux_cmdline_init(enum legacy_boot_type boot_type)
>> {
>> + switch (boot_type) {
>> + /*
>> + * Vcore III linux kernels expect arguments in the cached
>> + * address space. They also expect the command line being a
>> + * single string in the first argument
>> + */
>> + case LEGACY_BOOT_VCORE:
>> + linux_argv = (char **)(gd->bd->bi_boot_params);
>> + linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
>> + linux_argv[1] = linux_argp;
>> + break;
>> + case LEGACY_BOOT_YAML:
>> + /* fallthrough */
>> + default:
>> + linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
>> + linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
>> + }
>> linux_argc = 1;
>> - linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
>> linux_argv[0] = 0;
>> - linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
>> }
>>
>> -static void linux_cmdline_set(const char *value, size_t len)
>> +static void linux_cmdline_set(const char *value, size_t len,
>> + enum legacy_boot_type boot_type)
>> {
>> - linux_argv[linux_argc] = linux_argp;
>> memcpy(linux_argp, value, len);
>> - linux_argp[len] = 0;
>> -
>> + switch (boot_type) {
>> + case LEGACY_BOOT_VCORE:
>> + linux_argv[linux_argc] = linux_argp;
>> + linux_argp[len] = 0;
>> + linux_argc++;
>> + case LEGACY_BOOT_YAML:
>> + /* fallthrough */
>> + default:
>> + linux_argp[len] = ' ';
>> + linux_argp[len + 1] = 0;
>> + linux_argc = 2;
>> + }
>> linux_argp += len + 1;
>> - linux_argc++;
>> }
>>
>> static void linux_cmdline_dump(void)
>> @@ -73,12 +102,11 @@ static void linux_cmdline_dump(void)
>> debug(" arg %03d: %s\n", i, linux_argv[i]);
>> }
>>
>> -static void linux_cmdline_legacy(bootm_headers_t *images)
>> +static void linux_cmdline_legacy(bootm_headers_t *images,
>> + enum legacy_boot_type boot_type)
>> {
>> const char *bootargs, *next, *quote;
>> -
>> - linux_cmdline_init();
>> -
>> + linux_cmdline_init(boot_type);
>> bootargs = env_get("bootargs");
>> if (!bootargs)
>> return;
>> @@ -104,7 +132,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
>> if (!next)
>> next = bootargs + strlen(bootargs);
>>
>> - linux_cmdline_set(bootargs, next - bootargs);
>> + linux_cmdline_set(bootargs, next - bootargs, boot_type);
>>
>> if (*next)
>> next++;
>> @@ -113,7 +141,8 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
>> }
>> }
>>
>> -static void linux_cmdline_append(bootm_headers_t *images)
>> +static void linux_cmdline_append(bootm_headers_t *images,
>> + enum legacy_boot_type boot_type)
>> {
>> char buf[24];
>> ulong mem, rd_start, rd_size;
>> @@ -121,7 +150,7 @@ static void linux_cmdline_append(bootm_headers_t *images)
>> /* append mem */
>> mem = gd->ram_size >> 20;
>> sprintf(buf, "mem=%luM", mem);
>> - linux_cmdline_set(buf, strlen(buf));
>> + linux_cmdline_set(buf, strlen(buf), boot_type);
>>
>> /* append rd_start and rd_size */
>> rd_start = images->initrd_start;
>> @@ -129,9 +158,13 @@ static void linux_cmdline_append(bootm_headers_t *images)
>>
>> if (rd_size) {
>> sprintf(buf, "rd_start=0x%08lX", rd_start);
>> - linux_cmdline_set(buf, strlen(buf));
>> + linux_cmdline_set(buf, strlen(buf), boot_type);
>> sprintf(buf, "rd_size=0x%lX", rd_size);
>> - linux_cmdline_set(buf, strlen(buf));
>> + linux_cmdline_set(buf, strlen(buf), boot_type);
>> + if (boot_type == LEGACY_BOOT_VCORE) {
>> + sprintf(buf, "root=/dev/ram0");
>> + linux_cmdline_set(buf, strlen(buf), boot_type);
>> + }
>> }
>> }
>>
>> @@ -276,11 +309,15 @@ static void boot_prep_linux(bootm_headers_t *images)
>> boot_reloc_fdt(images);
>> boot_setup_fdt(images);
>> } else {
>> - if (CONFIG_IS_ENABLED(MIPS_BOOT_CMDLINE_LEGACY)) {
>> - linux_cmdline_legacy(images);
>> + if (CONFIG_IS_ENABLED(SOC_VCOREIII)) {
>> + linux_cmdline_legacy(images, LEGACY_BOOT_VCORE);
>> + linux_cmdline_append(images, LEGACY_BOOT_VCORE);
>> + linux_cmdline_dump();
>> + } else if (CONFIG_IS_ENABLED(MIPS_BOOT_CMDLINE_LEGACY)) {
>> + linux_cmdline_legacy(images, 0);
>>
>> if (!CONFIG_IS_ENABLED(MIPS_BOOT_ENV_LEGACY))
>> - linux_cmdline_append(images);
>> + linux_cmdline_append(images, LEGACY_BOOT_YAML);
>>
>> linux_cmdline_dump();
>> }
>>
>
> --
> - Daniel
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 12+ messages in thread