Re: [PATCH 08/16] drm/i915: Don't read out port_clock on CHV when DPLL is disabled

[Jani Nikula <jani.nikula@linux.intel.com>]

On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Check whether the DPLL is even enabled before readoing out the dividers
> and trying to derive port_clock on CHV. We already did this on VLV.
>
> Also remove the comment "MIPI" comment from the VLV code since we call
> this function whenever the pipe is enabled.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_display.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 98aae3914e9e..3e6b5fb140ad 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7969,8 +7969,8 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
>  	u32 mdiv;
>  	int refclk = 100000;
>  
> -	/* In case of MIPI DPLL will not even be used */
> -	if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
> +	/* In case of DSI, DPLL will not be used */
> +	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
>  		return;
>  
>  	mutex_lock(&dev_priv->sb_lock);
> @@ -8066,6 +8066,10 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
>  	u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
>  	int refclk = 100000;
>  
> +	/* In case of DSI, DPLL will not be used */
> +	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
> +		return;
> +
>  	mutex_lock(&dev_priv->sb_lock);
>  	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
>  	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));

-- 
Jani Nikula, Intel Open Source Technology Center
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