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* [PATCH] drm/i915: BDW Fix Halo PCI IDs marked as ULT.
@ 2015-01-19 21:57 Rodrigo Vivi
  2015-01-20  0:16 ` Rodrigo Vivi
  0 siblings, 1 reply; 4+ messages in thread
From: Rodrigo Vivi @ 2015-01-19 21:57 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi, Xion Zhang, Guo Jinxian, Jani Nikula, Stable

BDW with PCI-IDs ended in "2" aren't ULT, but HALO.
Let's fix it and at least allow VGA to work on this units.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87220
Cc: Xion Zhang <xiong.y.zhang@intel.com>
Cc: Guo Jinxian <jinxianx.guo@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Stable <stable@vger.kernel.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0be7d40..11e9b76 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2292,7 +2292,6 @@ struct drm_i915_cmd_table {
 #define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
 				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
-				 ((INTEL_DEVID(dev) & 0xf) == 0x2  || \
 				 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
 				 (INTEL_DEVID(dev) & 0xf) == 0xe))
 #define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH] drm/i915: BDW Fix Halo PCI IDs marked as ULT.
  2015-01-19 21:57 [PATCH] drm/i915: BDW Fix Halo PCI IDs marked as ULT Rodrigo Vivi
@ 2015-01-20  0:16 ` Rodrigo Vivi
  2015-01-20 10:36   ` shuang.he
  2015-01-21 19:12   ` Jani Nikula
  0 siblings, 2 replies; 4+ messages in thread
From: Rodrigo Vivi @ 2015-01-20  0:16 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi, Xion Zhang, Guo Jinxian, Jani Nikula, Stable

BDW with PCI-IDs ended in "2" aren't ULT, but HALO.
Let's fix it and at least allow VGA to work on this units.

v2: forgot ammend and v1 doesn't compile

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87220
Cc: Xion Zhang <xiong.y.zhang@intel.com>
Cc: Guo Jinxian <jinxianx.guo@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Stable <stable@vger.kernel.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0be7d40..276320e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2292,8 +2292,7 @@ struct drm_i915_cmd_table {
 #define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
 				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
-				 ((INTEL_DEVID(dev) & 0xf) == 0x2  || \
-				 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
+				 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||	\
 				 (INTEL_DEVID(dev) & 0xf) == 0xe))
 #define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
 				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: BDW Fix Halo PCI IDs marked as ULT.
  2015-01-20  0:16 ` Rodrigo Vivi
@ 2015-01-20 10:36   ` shuang.he
  2015-01-21 19:12   ` Jani Nikula
  1 sibling, 0 replies; 4+ messages in thread
From: shuang.he @ 2015-01-20 10:36 UTC (permalink / raw)
  To: shuang.he, ethan.gao, intel-gfx, rodrigo.vivi

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5609
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -1              353/353              352/353
ILK                 -1              200/200              199/200
SNB                                  400/422              400/422
IVB                 -11              487/487              476/487
BYT                                  296/296              296/296
HSW              +21                 487/508              508/508
BDW                                  401/402              401/402
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt_gen3_render_linear_blits      PASS(6, M25M23)      CRASH(1, M23)
*ILK  igt_gem_concurrent_blit_gtt-bcs-overwrite-source      PASS(2, M26M37)      NO_RESULT(1, M37)
*IVB  igt_kms_cursor_crc_cursor-128x128-onscreen      PASS(2, M4M34)      TIMEOUT(1, M34)
*IVB  igt_kms_cursor_crc_cursor-128x128-random      PASS(2, M4M34)      TIMEOUT(1, M34)
*IVB  igt_kms_cursor_crc_cursor-128x128-sliding      PASS(2, M4M34)      TIMEOUT(1, M34)
*IVB  igt_kms_cursor_crc_cursor-256x256-offscreen      PASS(2, M4M34)      TIMEOUT(1, M34)
*IVB  igt_kms_cursor_crc_cursor-256x256-onscreen      PASS(2, M4M34)      TIMEOUT(1, M34)
*IVB  igt_kms_cursor_crc_cursor-256x256-sliding      PASS(2, M4M34)      TIMEOUT(1, M34)
*IVB  igt_kms_cursor_crc_cursor-64x64-offscreen      PASS(2, M4M34)      TIMEOUT(1, M34)
*IVB  igt_kms_cursor_crc_cursor-64x64-onscreen      PASS(2, M4M34)      TIMEOUT(1, M34)
*IVB  igt_kms_cursor_crc_cursor-64x64-random      PASS(2, M4M34)      TIMEOUT(1, M34)
*IVB  igt_kms_cursor_crc_cursor-64x64-sliding      PASS(2, M4M34)      TIMEOUT(1, M34)
*IVB  igt_kms_cursor_crc_cursor-size-change      PASS(2, M4M34)      TIMEOUT(1, M34)
 HSW  igt_kms_cursor_crc_cursor-size-change      NSPT(1, M19)TIMEOUT(1, M40)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_kms_fence_pin_leak      NSPT(1, M19)DMESG_WARN(1, M40)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(1, M19)TIMEOUT(1, M40)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(1, M19)TIMEOUT(1, M40)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_lpsp_non-edp      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_cursor      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_cursor-dpms      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_dpms-mode-unset-non-lpsp      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_dpms-non-lpsp      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_drm-resources-equal      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_fences      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_fences-dpms      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_gem-execbuf      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_gem-mmap-cpu      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_gem-mmap-gtt      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_gem-pread      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_i2c      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_modeset-non-lpsp      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_pci-d3-state      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_rte      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M40)
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: BDW Fix Halo PCI IDs marked as ULT.
  2015-01-20  0:16 ` Rodrigo Vivi
  2015-01-20 10:36   ` shuang.he
@ 2015-01-21 19:12   ` Jani Nikula
  1 sibling, 0 replies; 4+ messages in thread
From: Jani Nikula @ 2015-01-21 19:12 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi, Xion Zhang, Guo Jinxian, Stable

On Tue, 20 Jan 2015, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> BDW with PCI-IDs ended in "2" aren't ULT, but HALO.
> Let's fix it and at least allow VGA to work on this units.
>
> v2: forgot ammend and v1 doesn't compile
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87220
> Cc: Xion Zhang <xiong.y.zhang@intel.com>
> Cc: Guo Jinxian <jinxianx.guo@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Stable <stable@vger.kernel.org>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Pushed to drm-intel-fixes, thanks for the patch.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0be7d40..276320e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2292,8 +2292,7 @@ struct drm_i915_cmd_table {
>  #define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
>  				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
>  #define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
> -				 ((INTEL_DEVID(dev) & 0xf) == 0x2  || \
> -				 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
> +				 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||	\
>  				 (INTEL_DEVID(dev) & 0xf) == 0xe))
>  #define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
>  				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
> -- 
> 2.1.0
>

-- 
Jani Nikula, Intel Open Source Technology Center

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2015-01-21 19:12 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-01-19 21:57 [PATCH] drm/i915: BDW Fix Halo PCI IDs marked as ULT Rodrigo Vivi
2015-01-20  0:16 ` Rodrigo Vivi
2015-01-20 10:36   ` shuang.he
2015-01-21 19:12   ` Jani Nikula

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