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From: "Björn Töpel" <bjorn@kernel.org>
To: Andy Chiu <andy.chiu@sifive.com>,
	linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	anup@brainfault.org, atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: Kefeng Wang <wangkefeng.wang@huawei.com>,
	guoren@linux.alibaba.com, David Hildenbrand <david@redhat.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	"Jason A. Donenfeld" <Jason@zx2c4.com>,
	Joey Gouly <joey.gouly@arm.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Guo Ren <guoren@kernel.org>, Jisheng Zhang <jszhang@kernel.org>,
	greentime.hu@sifive.com, Albert Ou <aou@eecs.berkeley.edu>,
	Stefan Roesch <shr@devkernel.io>,
	vineetg@rivosinc.com, Josh Triplett <josh@joshtriplett.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Heiko Stuebner <heiko.stuebner@vrull.eu>,
	Jordy Zomer <jordyzomer@google.com>,
	Ondrej Mosnacek <omosnace@redhat.com>,
	Vincent Chen <vincent.chen@sifive.com>,
	"Eric W. Biederman" <ebiederm@xmission.com>,
	Andy Chiu <andy.chiu@sifive.com>,
	Andrew Morton <akpm@linux-foundation.org>
Subject: Re: [PATCH -next v19 20/24] riscv: Add prctl controls for userspace vector management
Date: Mon, 15 May 2023 13:38:20 +0200	[thread overview]
Message-ID: <87ttwdhljn.fsf@all.your.base.are.belong.to.us> (raw)
In-Reply-To: <20230509103033.11285-21-andy.chiu@sifive.com>

Andy Chiu <andy.chiu@sifive.com> writes:

> This patch add two riscv-specific prctls, to allow usespace control the
> use of vector unit:

A more general question; I know that it's only x86 that implements
arch_prctl(), and that arm64 added the SVE prctl kernel/sys.c -- but is
there a reason not to have an arch-specific prctl for riscv?

>  * PR_RISCV_V_SET_CONTROL: control the permission to use Vector at next,
>    or all following execve for a thread. Turning off a thread's Vector
>    live is not possible since libraries may have registered ifunc that
>    may execute Vector instructions.
>  * PR_RISCV_V_GET_CONTROL: get the same permission setting for the
>    current thread, and the setting for following execve(s).
>
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
> Reviewed-by: Vincent Chen <vincent.chen@sifive.com>
> ---
>  arch/riscv/include/asm/processor.h |  13 ++++
>  arch/riscv/include/asm/vector.h    |   4 ++
>  arch/riscv/kernel/process.c        |   1 +
>  arch/riscv/kernel/vector.c         | 108 +++++++++++++++++++++++++++++
>  arch/riscv/kvm/vcpu.c              |   2 +
>  include/uapi/linux/prctl.h         |  11 +++
>  kernel/sys.c                       |  12 ++++
>  7 files changed, 151 insertions(+)
>
> diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> index 38ded8c5f207..79261da74cfd 100644
> --- a/arch/riscv/include/asm/processor.h
> +++ b/arch/riscv/include/asm/processor.h
> @@ -40,6 +40,7 @@ struct thread_struct {
>  	unsigned long s[12];	/* s[0]: frame pointer */
>  	struct __riscv_d_ext_state fstate;
>  	unsigned long bad_cause;
> +	unsigned long vstate_ctrl;
>  	struct __riscv_v_ext_state vstate;
>  };
>  
> @@ -83,6 +84,18 @@ extern void riscv_fill_hwcap(void);
>  extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
>  
>  extern unsigned long signal_minsigstksz __ro_after_init;
> +
> +#ifdef CONFIG_RISCV_ISA_V
> +/* Userspace interface for PR_RISCV_V_{SET,GET}_VS prctl()s: */
> +#define RISCV_V_SET_CONTROL(arg)	riscv_v_vstate_ctrl_set_current(arg)
> +#define RISCV_V_GET_CONTROL()		riscv_v_vstate_ctrl_get_current()
> +extern unsigned int riscv_v_vstate_ctrl_set_current(unsigned long arg);
> +extern unsigned int riscv_v_vstate_ctrl_get_current(void);
> +#else /* !CONFIG_RISCV_ISA_V */
> +#define RISCV_V_SET_CONTROL(arg)	(-EINVAL)
> +#define RISCV_V_GET_CONTROL()		(-EINVAL)

The else-clause is not needed (see my comment below for kernel/sys.c),
and can be removed.

> +#endif /* CONFIG_RISCV_ISA_V */
> +
>  #endif /* __ASSEMBLY__ */
>  
>  #endif /* _ASM_RISCV_PROCESSOR_H */

> diff --git a/kernel/sys.c b/kernel/sys.c
> index 339fee3eff6a..412d2c126060 100644
> --- a/kernel/sys.c
> +++ b/kernel/sys.c
> @@ -140,6 +140,12 @@
>  #ifndef GET_TAGGED_ADDR_CTRL
>  # define GET_TAGGED_ADDR_CTRL()		(-EINVAL)
>  #endif
> +#ifndef PR_RISCV_V_SET_CONTROL
> +# define PR_RISCV_V_SET_CONTROL(a)	(-EINVAL)
> +#endif
> +#ifndef PR_RISCV_V_GET_CONTROL
> +# define PR_RISCV_V_GET_CONTROL()	(-EINVAL)

Both SET/GET above should be RISCV_V_{SET,GET}_CONTROL (without the
prefix "PR_"), and nothing else, otherwise...

> +#endif
>  
>  /*
>   * this is where the system-wide overflow UID and GID are defined, for
> @@ -2708,6 +2714,12 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3,
>  		error = !!test_bit(MMF_VM_MERGE_ANY, &me->mm->flags);
>  		break;
>  #endif
> +	case PR_RISCV_V_SET_CONTROL:
> +		error = RISCV_V_SET_CONTROL(arg2);
> +		break;
> +	case PR_RISCV_V_GET_CONTROL:
> +		error = RISCV_V_GET_CONTROL();
> +		break;


...the case here will be weird. ;-)


Björn

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WARNING: multiple messages have this Message-ID (diff)
From: "Björn Töpel" <bjorn@kernel.org>
To: Andy Chiu <andy.chiu@sifive.com>,
	linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	anup@brainfault.org, atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: Kefeng Wang <wangkefeng.wang@huawei.com>,
	guoren@linux.alibaba.com, David Hildenbrand <david@redhat.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	"Jason A. Donenfeld" <Jason@zx2c4.com>,
	Joey Gouly <joey.gouly@arm.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Guo Ren <guoren@kernel.org>, Jisheng Zhang <jszhang@kernel.org>,
	greentime.hu@sifive.com, Albert Ou <aou@eecs.berkeley.edu>,
	Stefan Roesch <shr@devkernel.io>,
	vineetg@rivosinc.com, Josh Triplett <josh@joshtriplett.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Heiko Stuebner <heiko.stuebner@vrull.eu>,
	Jordy Zomer <jordyzomer@google.com>,
	Ondrej Mosnacek <omosnace@redhat.com>,
	Vincent Chen <vincent.chen@sifive.com>,
	"Eric W. Biederman" <ebiederm@xmission.com>,
	Andy Chiu <andy.chiu@sifive.com>,
	Andrew Morton <akpm@linux-foundation.org>
Subject: Re: [PATCH -next v19 20/24] riscv: Add prctl controls for userspace vector management
Date: Mon, 15 May 2023 13:38:20 +0200	[thread overview]
Message-ID: <87ttwdhljn.fsf@all.your.base.are.belong.to.us> (raw)
In-Reply-To: <20230509103033.11285-21-andy.chiu@sifive.com>

Andy Chiu <andy.chiu@sifive.com> writes:

> This patch add two riscv-specific prctls, to allow usespace control the
> use of vector unit:

A more general question; I know that it's only x86 that implements
arch_prctl(), and that arm64 added the SVE prctl kernel/sys.c -- but is
there a reason not to have an arch-specific prctl for riscv?

>  * PR_RISCV_V_SET_CONTROL: control the permission to use Vector at next,
>    or all following execve for a thread. Turning off a thread's Vector
>    live is not possible since libraries may have registered ifunc that
>    may execute Vector instructions.
>  * PR_RISCV_V_GET_CONTROL: get the same permission setting for the
>    current thread, and the setting for following execve(s).
>
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
> Reviewed-by: Vincent Chen <vincent.chen@sifive.com>
> ---
>  arch/riscv/include/asm/processor.h |  13 ++++
>  arch/riscv/include/asm/vector.h    |   4 ++
>  arch/riscv/kernel/process.c        |   1 +
>  arch/riscv/kernel/vector.c         | 108 +++++++++++++++++++++++++++++
>  arch/riscv/kvm/vcpu.c              |   2 +
>  include/uapi/linux/prctl.h         |  11 +++
>  kernel/sys.c                       |  12 ++++
>  7 files changed, 151 insertions(+)
>
> diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> index 38ded8c5f207..79261da74cfd 100644
> --- a/arch/riscv/include/asm/processor.h
> +++ b/arch/riscv/include/asm/processor.h
> @@ -40,6 +40,7 @@ struct thread_struct {
>  	unsigned long s[12];	/* s[0]: frame pointer */
>  	struct __riscv_d_ext_state fstate;
>  	unsigned long bad_cause;
> +	unsigned long vstate_ctrl;
>  	struct __riscv_v_ext_state vstate;
>  };
>  
> @@ -83,6 +84,18 @@ extern void riscv_fill_hwcap(void);
>  extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
>  
>  extern unsigned long signal_minsigstksz __ro_after_init;
> +
> +#ifdef CONFIG_RISCV_ISA_V
> +/* Userspace interface for PR_RISCV_V_{SET,GET}_VS prctl()s: */
> +#define RISCV_V_SET_CONTROL(arg)	riscv_v_vstate_ctrl_set_current(arg)
> +#define RISCV_V_GET_CONTROL()		riscv_v_vstate_ctrl_get_current()
> +extern unsigned int riscv_v_vstate_ctrl_set_current(unsigned long arg);
> +extern unsigned int riscv_v_vstate_ctrl_get_current(void);
> +#else /* !CONFIG_RISCV_ISA_V */
> +#define RISCV_V_SET_CONTROL(arg)	(-EINVAL)
> +#define RISCV_V_GET_CONTROL()		(-EINVAL)

The else-clause is not needed (see my comment below for kernel/sys.c),
and can be removed.

> +#endif /* CONFIG_RISCV_ISA_V */
> +
>  #endif /* __ASSEMBLY__ */
>  
>  #endif /* _ASM_RISCV_PROCESSOR_H */

> diff --git a/kernel/sys.c b/kernel/sys.c
> index 339fee3eff6a..412d2c126060 100644
> --- a/kernel/sys.c
> +++ b/kernel/sys.c
> @@ -140,6 +140,12 @@
>  #ifndef GET_TAGGED_ADDR_CTRL
>  # define GET_TAGGED_ADDR_CTRL()		(-EINVAL)
>  #endif
> +#ifndef PR_RISCV_V_SET_CONTROL
> +# define PR_RISCV_V_SET_CONTROL(a)	(-EINVAL)
> +#endif
> +#ifndef PR_RISCV_V_GET_CONTROL
> +# define PR_RISCV_V_GET_CONTROL()	(-EINVAL)

Both SET/GET above should be RISCV_V_{SET,GET}_CONTROL (without the
prefix "PR_"), and nothing else, otherwise...

> +#endif
>  
>  /*
>   * this is where the system-wide overflow UID and GID are defined, for
> @@ -2708,6 +2714,12 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3,
>  		error = !!test_bit(MMF_VM_MERGE_ANY, &me->mm->flags);
>  		break;
>  #endif
> +	case PR_RISCV_V_SET_CONTROL:
> +		error = RISCV_V_SET_CONTROL(arg2);
> +		break;
> +	case PR_RISCV_V_GET_CONTROL:
> +		error = RISCV_V_GET_CONTROL();
> +		break;


...the case here will be weird. ;-)


Björn

  parent reply	other threads:[~2023-05-15 11:38 UTC|newest]

Thread overview: 110+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-09 10:30 [PATCH -next v19 00/24] riscv: Add vector ISA support Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 01/24] riscv: Rename __switch_to_aux() -> fpu Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-11 22:56   ` Palmer Dabbelt
2023-05-11 22:56     ` Palmer Dabbelt
2023-05-16  2:47     ` Andy Chiu
2023-05-16  2:47       ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 02/24] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-11 22:56   ` Palmer Dabbelt
2023-05-11 22:56     ` Palmer Dabbelt
2023-05-09 10:30 ` [PATCH -next v19 03/24] riscv: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_V Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-09 11:05   ` Heiko Stübner
2023-05-09 11:05     ` Heiko Stübner
2023-05-09 16:41     ` Andy Chiu
2023-05-09 16:41       ` Andy Chiu
2023-05-09 17:32       ` Evan Green
2023-05-09 17:32         ` Evan Green
2023-05-09 17:59         ` Palmer Dabbelt
2023-05-09 17:59           ` Palmer Dabbelt
2023-05-09 18:29           ` Evan Green
2023-05-09 18:29             ` Evan Green
2023-05-11 22:36             ` Palmer Dabbelt
2023-05-11 22:36               ` Palmer Dabbelt
2023-05-09 10:30 ` [PATCH -next v19 04/24] riscv: Add new csr defines related to vector extension Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-11 22:56   ` Palmer Dabbelt
2023-05-11 22:56     ` Palmer Dabbelt
2023-05-16  3:15     ` Andy Chiu
2023-05-16  3:15       ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 05/24] riscv: Clear vector regfile on bootup Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-11 22:56   ` Palmer Dabbelt
2023-05-11 22:56     ` Palmer Dabbelt
2023-05-09 10:30 ` [PATCH -next v19 06/24] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-11 22:56   ` Palmer Dabbelt
2023-05-11 22:56     ` Palmer Dabbelt
2023-05-09 10:30 ` [PATCH -next v19 07/24] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-11 22:56   ` Palmer Dabbelt
2023-05-11 22:56     ` Palmer Dabbelt
2023-05-09 10:30 ` [PATCH -next v19 08/24] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-11 22:56   ` Palmer Dabbelt
2023-05-11 22:56     ` Palmer Dabbelt
2023-05-09 10:30 ` [PATCH -next v19 09/24] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 10/24] riscv: Add task switch support for vector Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 11/24] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 12/24] riscv: Add ptrace vector support Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 13/24] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 14/24] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 15/24] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 16/24] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 17/24] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 18/24] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 19/24] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 20/24] riscv: Add prctl controls for userspace vector management Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-09 11:14   ` Heiko Stübner
2023-05-09 11:14     ` Heiko Stübner
2023-05-09 16:11     ` Andy Chiu
2023-05-09 16:11       ` Andy Chiu
2023-05-09 17:58     ` Palmer Dabbelt
2023-05-09 17:58       ` Palmer Dabbelt
2023-05-15 11:38   ` Björn Töpel [this message]
2023-05-15 11:38     ` Björn Töpel
2023-05-16  7:13     ` Andy Chiu
2023-05-16  7:13       ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 21/24] riscv: Add sysctl to set the default vector rule for new processes Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-15 11:42   ` Björn Töpel
2023-05-15 11:42     ` Björn Töpel
2023-05-09 10:30 ` [PATCH -next v19 22/24] riscv: detect assembler support for .option arch Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 23/24] riscv: Enable Vector code to be built Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-09 12:34   ` Conor Dooley
2023-05-09 12:34     ` Conor Dooley
2023-05-09 16:04     ` Andy Chiu
2023-05-09 16:04       ` Andy Chiu
2023-05-09 16:53       ` Conor Dooley
2023-05-09 16:53         ` Conor Dooley
2023-05-09 20:59         ` Palmer Dabbelt
2023-05-09 20:59           ` Palmer Dabbelt
2023-05-09 21:06           ` Conor Dooley
2023-05-09 21:06             ` Conor Dooley
2023-05-15 12:04             ` Conor Dooley
2023-05-15 12:04               ` Conor Dooley
2023-05-09 22:14   ` kernel test robot
2023-05-09 22:14     ` kernel test robot
2023-05-09 10:30 ` [PATCH -next v19 24/24] riscv: Add documentation for Vector Andy Chiu
2023-05-09 10:30   ` Andy Chiu
2023-05-15 11:41   ` Björn Töpel
2023-05-15 11:41     ` Björn Töpel
2023-05-09 20:59 ` [PATCH -next v19 00/24] riscv: Add vector ISA support Palmer Dabbelt
2023-05-09 20:59   ` Palmer Dabbelt

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