From: Fabiano Rosas <farosas@linux.ibm.com> To: Nicholas Piggin <npiggin@gmail.com>, kvm-ppc@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, Nicholas Piggin <npiggin@gmail.com> Subject: Re: [RFC PATCH 2/9] KVM: PPC: Book3S 64: Move GUEST_MODE_SKIP test into KVM Date: Fri, 12 Feb 2021 17:33:02 -0300 [thread overview] Message-ID: <87tuqhxc01.fsf@linux.ibm.com> (raw) In-Reply-To: <20210202030313.3509446-3-npiggin@gmail.com> Nicholas Piggin <npiggin@gmail.com> writes: > Move the GUEST_MODE_SKIP logic into KVM code. This is quite a KVM > internal detail that has no real need to be in common handlers. LGTM, > > (XXX: Need to confirm CBE handlers etc) Do these interrupts exist only in Cell? I see that they set HSRRs and MSR_HV, but CPU_FTRS_CELL does not contain CPU_HVMODE. So I don't get why they use the KVM macros. And for the instruction_breakpoint (0x1300) I think it would help if we could at least restrict when it is built. But I don't know what ISA/processor version it is from. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- > arch/powerpc/kernel/exceptions-64s.S | 64 ---------------------------- > arch/powerpc/kvm/book3s_64_entry.S | 50 ++++++++++++++++++---- > 2 files changed, 42 insertions(+), 72 deletions(-) > > diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S > index 65659ea3cec4..e6f7fc7c61a1 100644 > --- a/arch/powerpc/kernel/exceptions-64s.S > +++ b/arch/powerpc/kernel/exceptions-64s.S > @@ -133,7 +133,6 @@ name: > #define IBRANCH_TO_COMMON .L_IBRANCH_TO_COMMON_\name\() /* ENTRY branch to common */ > #define IREALMODE_COMMON .L_IREALMODE_COMMON_\name\() /* Common runs in realmode */ > #define IMASK .L_IMASK_\name\() /* IRQ soft-mask bit */ > -#define IKVM_SKIP .L_IKVM_SKIP_\name\() /* Generate KVM skip handler */ > #define IKVM_REAL .L_IKVM_REAL_\name\() /* Real entry tests KVM */ > #define __IKVM_REAL(name) .L_IKVM_REAL_ ## name > #define IKVM_VIRT .L_IKVM_VIRT_\name\() /* Virt entry tests KVM */ > @@ -191,9 +190,6 @@ do_define_int n > .ifndef IMASK > IMASK=0 > .endif > - .ifndef IKVM_SKIP > - IKVM_SKIP=0 > - .endif > .ifndef IKVM_REAL > IKVM_REAL=0 > .endif > @@ -254,15 +250,10 @@ do_define_int n > .balign IFETCH_ALIGN_BYTES > \name\()_kvm: > > - .if IKVM_SKIP > - cmpwi r10,KVM_GUEST_MODE_SKIP > - beq 89f > - .else > BEGIN_FTR_SECTION > ld r10,IAREA+EX_CFAR(r13) > std r10,HSTATE_CFAR(r13) > END_FTR_SECTION_IFSET(CPU_FTR_CFAR) > - .endif > > ld r10,IAREA+EX_CTR(r13) > mtctr r10 > @@ -289,27 +280,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) > ori r12,r12,(IVEC) > .endif > b kvmppc_interrupt > - > - .if IKVM_SKIP > -89: mtocrf 0x80,r9 > - ld r10,IAREA+EX_CTR(r13) > - mtctr r10 > - ld r9,IAREA+EX_R9(r13) > - ld r10,IAREA+EX_R10(r13) > - ld r11,IAREA+EX_R11(r13) > - ld r12,IAREA+EX_R12(r13) > - .if IHSRR_IF_HVMODE > - BEGIN_FTR_SECTION > - b kvmppc_skip_Hinterrupt > - FTR_SECTION_ELSE > - b kvmppc_skip_interrupt > - ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) > - .elseif IHSRR > - b kvmppc_skip_Hinterrupt > - .else > - b kvmppc_skip_interrupt > - .endif > - .endif > .endm > > #else > @@ -1128,7 +1098,6 @@ INT_DEFINE_BEGIN(machine_check) > ISET_RI=0 > IDAR=1 > IDSISR=1 > - IKVM_SKIP=1 > IKVM_REAL=1 > INT_DEFINE_END(machine_check) > > @@ -1419,7 +1388,6 @@ INT_DEFINE_BEGIN(data_access) > IVEC=0x300 > IDAR=1 > IDSISR=1 > - IKVM_SKIP=1 > IKVM_REAL=1 > INT_DEFINE_END(data_access) > > @@ -1469,7 +1437,6 @@ INT_DEFINE_BEGIN(data_access_slb) > IAREA=PACA_EXSLB > IRECONCILE=0 > IDAR=1 > - IKVM_SKIP=1 > IKVM_REAL=1 > INT_DEFINE_END(data_access_slb) > > @@ -2116,7 +2083,6 @@ INT_DEFINE_BEGIN(h_data_storage) > IHSRR=1 > IDAR=1 > IDSISR=1 > - IKVM_SKIP=1 > IKVM_REAL=1 > IKVM_VIRT=1 > INT_DEFINE_END(h_data_storage) > @@ -2573,7 +2539,6 @@ EXC_VIRT_NONE(0x5100, 0x100) > INT_DEFINE_BEGIN(cbe_system_error) > IVEC=0x1200 > IHSRR=1 > - IKVM_SKIP=1 > IKVM_REAL=1 > INT_DEFINE_END(cbe_system_error) > > @@ -2598,7 +2563,6 @@ EXC_VIRT_NONE(0x5200, 0x100) > INT_DEFINE_BEGIN(instruction_breakpoint) > IVEC=0x1300 > #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE > - IKVM_SKIP=1 > IKVM_REAL=1 > #endif > INT_DEFINE_END(instruction_breakpoint) > @@ -2744,7 +2708,6 @@ EXC_COMMON_BEGIN(denorm_exception_common) > INT_DEFINE_BEGIN(cbe_maintenance) > IVEC=0x1600 > IHSRR=1 > - IKVM_SKIP=1 > IKVM_REAL=1 > INT_DEFINE_END(cbe_maintenance) > > @@ -2797,7 +2760,6 @@ EXC_COMMON_BEGIN(altivec_assist_common) > INT_DEFINE_BEGIN(cbe_thermal) > IVEC=0x1800 > IHSRR=1 > - IKVM_SKIP=1 > IKVM_REAL=1 > INT_DEFINE_END(cbe_thermal) > > @@ -3081,32 +3043,6 @@ EXPORT_SYMBOL(do_uaccess_flush) > MASKED_INTERRUPT > MASKED_INTERRUPT hsrr=1 > > -#ifdef CONFIG_KVM_BOOK3S_64_HANDLER > -kvmppc_skip_interrupt: > - /* > - * Here all GPRs are unchanged from when the interrupt happened > - * except for r13, which is saved in SPRG_SCRATCH0. > - */ > - mfspr r13, SPRN_SRR0 > - addi r13, r13, 4 > - mtspr SPRN_SRR0, r13 > - GET_SCRATCH0(r13) > - RFI_TO_KERNEL > - b . > - > -kvmppc_skip_Hinterrupt: > - /* > - * Here all GPRs are unchanged from when the interrupt happened > - * except for r13, which is saved in SPRG_SCRATCH0. > - */ > - mfspr r13, SPRN_HSRR0 > - addi r13, r13, 4 > - mtspr SPRN_HSRR0, r13 > - GET_SCRATCH0(r13) > - HRFI_TO_KERNEL > - b . > -#endif > - > /* > * Relocation-on interrupts: A subset of the interrupts can be delivered > * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering > diff --git a/arch/powerpc/kvm/book3s_64_entry.S b/arch/powerpc/kvm/book3s_64_entry.S > index 22e34b95f478..8e7216f3c3ee 100644 > --- a/arch/powerpc/kvm/book3s_64_entry.S > +++ b/arch/powerpc/kvm/book3s_64_entry.S > @@ -1,9 +1,10 @@ > +#include <asm/asm-offsets.h> > #include <asm/cache.h> > -#include <asm/ppc_asm.h> > +#include <asm/exception-64s.h> > #include <asm/kvm_asm.h> > -#include <asm/reg.h> > -#include <asm/asm-offsets.h> > #include <asm/kvm_book3s_asm.h> > +#include <asm/ppc_asm.h> > +#include <asm/reg.h> > > /* > * We come here from the first-level interrupt handlers. > @@ -18,17 +19,50 @@ kvmppc_interrupt: > * guest R12 saved in shadow VCPU SCRATCH0 > * guest R13 saved in SPRN_SCRATCH0 > */ > + std r9,HSTATE_SCRATCH2(r13) > + lbz r9,HSTATE_IN_GUEST(r13) > + cmpwi r9,KVM_GUEST_MODE_SKIP > + beq maybe_skip > +no_skip: > #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE > - std r9, HSTATE_SCRATCH2(r13) > - lbz r9, HSTATE_IN_GUEST(r13) > - cmpwi r9, KVM_GUEST_MODE_HOST_HV > + cmpwi r9,KVM_GUEST_MODE_HOST_HV > beq kvmppc_bad_host_intr > #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE > - cmpwi r9, KVM_GUEST_MODE_GUEST > - ld r9, HSTATE_SCRATCH2(r13) > + cmpwi r9,KVM_GUEST_MODE_GUEST > + ld r9,HSTATE_SCRATCH2(r13) > beq kvmppc_interrupt_pr > #endif > b kvmppc_interrupt_hv > #else > b kvmppc_interrupt_pr > #endif > + > +maybe_skip: > + cmpwi r12,0x200 > + beq 1f > + cmpwi r12,0x300 > + beq 1f > + cmpwi r12,0x380 > + beq 1f > +#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE > + /* XXX: cbe stuff? instruction breakpoint? */ > + cmpwi r12,0xe02 > + beq 2f > +#endif > + b no_skip > +1: mfspr r9,SPRN_SRR0 > + addi r9,r9,4 > + mtspr SPRN_SRR0,r9 > + ld r12,HSTATE_SCRATCH0(r13) > + ld r9,HSTATE_SCRATCH2(r13) > + GET_SCRATCH0(r13) > + RFI_TO_KERNEL > +#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE > +2: mfspr r9,SPRN_HSRR0 > + addi r9,r9,4 > + mtspr SPRN_HSRR0,r9 > + ld r12,HSTATE_SCRATCH0(r13) > + ld r9,HSTATE_SCRATCH2(r13) > + GET_SCRATCH0(r13) > + HRFI_TO_KERNEL > +#endif
WARNING: multiple messages have this Message-ID (diff)
From: Fabiano Rosas <farosas@linux.ibm.com> To: Nicholas Piggin <npiggin@gmail.com>, kvm-ppc@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, Nicholas Piggin <npiggin@gmail.com> Subject: Re: [RFC PATCH 2/9] KVM: PPC: Book3S 64: Move GUEST_MODE_SKIP test into KVM Date: Fri, 12 Feb 2021 20:33:02 +0000 [thread overview] Message-ID: <87tuqhxc01.fsf@linux.ibm.com> (raw) In-Reply-To: <20210202030313.3509446-3-npiggin@gmail.com> Nicholas Piggin <npiggin@gmail.com> writes: > Move the GUEST_MODE_SKIP logic into KVM code. This is quite a KVM > internal detail that has no real need to be in common handlers. LGTM, > > (XXX: Need to confirm CBE handlers etc) Do these interrupts exist only in Cell? I see that they set HSRRs and MSR_HV, but CPU_FTRS_CELL does not contain CPU_HVMODE. So I don't get why they use the KVM macros. And for the instruction_breakpoint (0x1300) I think it would help if we could at least restrict when it is built. But I don't know what ISA/processor version it is from. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- > arch/powerpc/kernel/exceptions-64s.S | 64 ---------------------------- > arch/powerpc/kvm/book3s_64_entry.S | 50 ++++++++++++++++++---- > 2 files changed, 42 insertions(+), 72 deletions(-) > > diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S > index 65659ea3cec4..e6f7fc7c61a1 100644 > --- a/arch/powerpc/kernel/exceptions-64s.S > +++ b/arch/powerpc/kernel/exceptions-64s.S > @@ -133,7 +133,6 @@ name: > #define IBRANCH_TO_COMMON .L_IBRANCH_TO_COMMON_\name\() /* ENTRY branch to common */ > #define IREALMODE_COMMON .L_IREALMODE_COMMON_\name\() /* Common runs in realmode */ > #define IMASK .L_IMASK_\name\() /* IRQ soft-mask bit */ > -#define IKVM_SKIP .L_IKVM_SKIP_\name\() /* Generate KVM skip handler */ > #define IKVM_REAL .L_IKVM_REAL_\name\() /* Real entry tests KVM */ > #define __IKVM_REAL(name) .L_IKVM_REAL_ ## name > #define IKVM_VIRT .L_IKVM_VIRT_\name\() /* Virt entry tests KVM */ > @@ -191,9 +190,6 @@ do_define_int n > .ifndef IMASK > IMASK=0 > .endif > - .ifndef IKVM_SKIP > - IKVM_SKIP=0 > - .endif > .ifndef IKVM_REAL > IKVM_REAL=0 > .endif > @@ -254,15 +250,10 @@ do_define_int n > .balign IFETCH_ALIGN_BYTES > \name\()_kvm: > > - .if IKVM_SKIP > - cmpwi r10,KVM_GUEST_MODE_SKIP > - beq 89f > - .else > BEGIN_FTR_SECTION > ld r10,IAREA+EX_CFAR(r13) > std r10,HSTATE_CFAR(r13) > END_FTR_SECTION_IFSET(CPU_FTR_CFAR) > - .endif > > ld r10,IAREA+EX_CTR(r13) > mtctr r10 > @@ -289,27 +280,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) > ori r12,r12,(IVEC) > .endif > b kvmppc_interrupt > - > - .if IKVM_SKIP > -89: mtocrf 0x80,r9 > - ld r10,IAREA+EX_CTR(r13) > - mtctr r10 > - ld r9,IAREA+EX_R9(r13) > - ld r10,IAREA+EX_R10(r13) > - ld r11,IAREA+EX_R11(r13) > - ld r12,IAREA+EX_R12(r13) > - .if IHSRR_IF_HVMODE > - BEGIN_FTR_SECTION > - b kvmppc_skip_Hinterrupt > - FTR_SECTION_ELSE > - b kvmppc_skip_interrupt > - ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) > - .elseif IHSRR > - b kvmppc_skip_Hinterrupt > - .else > - b kvmppc_skip_interrupt > - .endif > - .endif > .endm > > #else > @@ -1128,7 +1098,6 @@ INT_DEFINE_BEGIN(machine_check) > ISET_RI=0 > IDAR=1 > IDSISR=1 > - IKVM_SKIP=1 > IKVM_REAL=1 > INT_DEFINE_END(machine_check) > > @@ -1419,7 +1388,6 @@ INT_DEFINE_BEGIN(data_access) > IVEC=0x300 > IDAR=1 > IDSISR=1 > - IKVM_SKIP=1 > IKVM_REAL=1 > INT_DEFINE_END(data_access) > > @@ -1469,7 +1437,6 @@ INT_DEFINE_BEGIN(data_access_slb) > IAREA=PACA_EXSLB > IRECONCILE=0 > IDAR=1 > - IKVM_SKIP=1 > IKVM_REAL=1 > INT_DEFINE_END(data_access_slb) > > @@ -2116,7 +2083,6 @@ INT_DEFINE_BEGIN(h_data_storage) > IHSRR=1 > IDAR=1 > IDSISR=1 > - IKVM_SKIP=1 > IKVM_REAL=1 > IKVM_VIRT=1 > INT_DEFINE_END(h_data_storage) > @@ -2573,7 +2539,6 @@ EXC_VIRT_NONE(0x5100, 0x100) > INT_DEFINE_BEGIN(cbe_system_error) > IVEC=0x1200 > IHSRR=1 > - IKVM_SKIP=1 > IKVM_REAL=1 > INT_DEFINE_END(cbe_system_error) > > @@ -2598,7 +2563,6 @@ EXC_VIRT_NONE(0x5200, 0x100) > INT_DEFINE_BEGIN(instruction_breakpoint) > IVEC=0x1300 > #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE > - IKVM_SKIP=1 > IKVM_REAL=1 > #endif > INT_DEFINE_END(instruction_breakpoint) > @@ -2744,7 +2708,6 @@ EXC_COMMON_BEGIN(denorm_exception_common) > INT_DEFINE_BEGIN(cbe_maintenance) > IVEC=0x1600 > IHSRR=1 > - IKVM_SKIP=1 > IKVM_REAL=1 > INT_DEFINE_END(cbe_maintenance) > > @@ -2797,7 +2760,6 @@ EXC_COMMON_BEGIN(altivec_assist_common) > INT_DEFINE_BEGIN(cbe_thermal) > IVEC=0x1800 > IHSRR=1 > - IKVM_SKIP=1 > IKVM_REAL=1 > INT_DEFINE_END(cbe_thermal) > > @@ -3081,32 +3043,6 @@ EXPORT_SYMBOL(do_uaccess_flush) > MASKED_INTERRUPT > MASKED_INTERRUPT hsrr=1 > > -#ifdef CONFIG_KVM_BOOK3S_64_HANDLER > -kvmppc_skip_interrupt: > - /* > - * Here all GPRs are unchanged from when the interrupt happened > - * except for r13, which is saved in SPRG_SCRATCH0. > - */ > - mfspr r13, SPRN_SRR0 > - addi r13, r13, 4 > - mtspr SPRN_SRR0, r13 > - GET_SCRATCH0(r13) > - RFI_TO_KERNEL > - b . > - > -kvmppc_skip_Hinterrupt: > - /* > - * Here all GPRs are unchanged from when the interrupt happened > - * except for r13, which is saved in SPRG_SCRATCH0. > - */ > - mfspr r13, SPRN_HSRR0 > - addi r13, r13, 4 > - mtspr SPRN_HSRR0, r13 > - GET_SCRATCH0(r13) > - HRFI_TO_KERNEL > - b . > -#endif > - > /* > * Relocation-on interrupts: A subset of the interrupts can be delivered > * with IR=1/DR=1, if AIL=2 and MSR.HV won't be changed by delivering > diff --git a/arch/powerpc/kvm/book3s_64_entry.S b/arch/powerpc/kvm/book3s_64_entry.S > index 22e34b95f478..8e7216f3c3ee 100644 > --- a/arch/powerpc/kvm/book3s_64_entry.S > +++ b/arch/powerpc/kvm/book3s_64_entry.S > @@ -1,9 +1,10 @@ > +#include <asm/asm-offsets.h> > #include <asm/cache.h> > -#include <asm/ppc_asm.h> > +#include <asm/exception-64s.h> > #include <asm/kvm_asm.h> > -#include <asm/reg.h> > -#include <asm/asm-offsets.h> > #include <asm/kvm_book3s_asm.h> > +#include <asm/ppc_asm.h> > +#include <asm/reg.h> > > /* > * We come here from the first-level interrupt handlers. > @@ -18,17 +19,50 @@ kvmppc_interrupt: > * guest R12 saved in shadow VCPU SCRATCH0 > * guest R13 saved in SPRN_SCRATCH0 > */ > + std r9,HSTATE_SCRATCH2(r13) > + lbz r9,HSTATE_IN_GUEST(r13) > + cmpwi r9,KVM_GUEST_MODE_SKIP > + beq maybe_skip > +no_skip: > #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE > - std r9, HSTATE_SCRATCH2(r13) > - lbz r9, HSTATE_IN_GUEST(r13) > - cmpwi r9, KVM_GUEST_MODE_HOST_HV > + cmpwi r9,KVM_GUEST_MODE_HOST_HV > beq kvmppc_bad_host_intr > #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE > - cmpwi r9, KVM_GUEST_MODE_GUEST > - ld r9, HSTATE_SCRATCH2(r13) > + cmpwi r9,KVM_GUEST_MODE_GUEST > + ld r9,HSTATE_SCRATCH2(r13) > beq kvmppc_interrupt_pr > #endif > b kvmppc_interrupt_hv > #else > b kvmppc_interrupt_pr > #endif > + > +maybe_skip: > + cmpwi r12,0x200 > + beq 1f > + cmpwi r12,0x300 > + beq 1f > + cmpwi r12,0x380 > + beq 1f > +#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE > + /* XXX: cbe stuff? instruction breakpoint? */ > + cmpwi r12,0xe02 > + beq 2f > +#endif > + b no_skip > +1: mfspr r9,SPRN_SRR0 > + addi r9,r9,4 > + mtspr SPRN_SRR0,r9 > + ld r12,HSTATE_SCRATCH0(r13) > + ld r9,HSTATE_SCRATCH2(r13) > + GET_SCRATCH0(r13) > + RFI_TO_KERNEL > +#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE > +2: mfspr r9,SPRN_HSRR0 > + addi r9,r9,4 > + mtspr SPRN_HSRR0,r9 > + ld r12,HSTATE_SCRATCH0(r13) > + ld r9,HSTATE_SCRATCH2(r13) > + GET_SCRATCH0(r13) > + HRFI_TO_KERNEL > +#endif
next prev parent reply other threads:[~2021-02-12 20:34 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-02 3:03 [RFC PATCH 0/9] KVM: PPC: Book3S: C-ify the P9 entry/exit code Nicholas Piggin 2021-02-02 3:03 ` Nicholas Piggin 2021-02-02 3:03 ` [RFC PATCH 1/9] KVM: PPC: Book3S 64: move KVM interrupt entry to a common entry point Nicholas Piggin 2021-02-02 3:03 ` Nicholas Piggin 2021-02-05 21:28 ` Fabiano Rosas 2021-02-05 21:28 ` Fabiano Rosas 2021-02-19 5:18 ` Daniel Axtens 2021-02-19 5:18 ` Daniel Axtens 2021-02-19 8:03 ` Nicholas Piggin 2021-02-19 8:03 ` Nicholas Piggin 2021-02-02 3:03 ` [RFC PATCH 2/9] KVM: PPC: Book3S 64: Move GUEST_MODE_SKIP test into KVM Nicholas Piggin 2021-02-02 3:03 ` Nicholas Piggin 2021-02-12 20:33 ` Fabiano Rosas [this message] 2021-02-12 20:33 ` Fabiano Rosas 2021-02-19 7:53 ` Nicholas Piggin 2021-02-19 7:53 ` Nicholas Piggin 2021-02-19 6:03 ` Daniel Axtens 2021-02-19 6:03 ` Daniel Axtens 2021-02-19 7:56 ` Nicholas Piggin 2021-02-19 7:56 ` Nicholas Piggin 2021-02-02 3:03 ` [RFC PATCH 3/9] KVM: PPC: Book3S 64: add hcall interrupt handler Nicholas Piggin 2021-02-02 3:03 ` Nicholas Piggin 2021-02-12 20:33 ` Fabiano Rosas 2021-02-12 20:33 ` Fabiano Rosas 2021-02-02 3:03 ` [RFC PATCH 4/9] KVM: PPC: Book3S HV: Move hcall early register setup to KVM Nicholas Piggin 2021-02-02 3:03 ` Nicholas Piggin 2021-02-02 3:03 ` [RFC PATCH 5/9] powerpc/64s: Remove EXSLB interrupt save area Nicholas Piggin 2021-02-02 3:03 ` Nicholas Piggin 2021-02-02 3:03 ` [RFC PATCH 6/9] KVM: PPC: Book3S HV: Move interrupt early register setup to KVM Nicholas Piggin 2021-02-02 3:03 ` Nicholas Piggin 2021-02-02 3:03 ` [RFC PATCH 7/9] KVM: PPC: Book3S HV: move bad_host_intr check to HV handler Nicholas Piggin 2021-02-02 3:03 ` Nicholas Piggin 2021-02-02 3:03 ` [RFC PATCH 8/9] KVM: PPC: Book3S HV: Minimise hcall handler calling convention differences Nicholas Piggin 2021-02-02 3:03 ` Nicholas Piggin 2021-02-02 3:03 ` [RFC PATCH 9/9] KVM: PPC: Book3S HV: Implement the rest of the P9 entry/exit handling in C Nicholas Piggin 2021-02-02 3:03 ` Nicholas Piggin
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=87tuqhxc01.fsf@linux.ibm.com \ --to=farosas@linux.ibm.com \ --cc=kvm-ppc@vger.kernel.org \ --cc=linuxppc-dev@lists.ozlabs.org \ --cc=npiggin@gmail.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.