[PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff

[PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff

[Rodrigo Vivi]

This exactly same approach was already used from gen9
to gen10 and from gen10 to gen11. Let's also use it
for gen11+.

Let's first assume that we inherit a similar platform
and than we apply the differences on top.

Different from the previous attempts this will be
done this time with coccinelle. We obviously need to
exclude some case that is really exclusive for gen11
like  PCH, Firmware, and few others. Luckly this was
easy to filter by selecting the files we are touching
with coccinelle as exposed below:

spatch -sp_file gen11\+.cocci --in-place i915_perf.c \
       intel_bios.c intel_cdclk.c intel_ddi.c \
       intel_device_info.c intel_display.c intel_dpll_mgr.c \
       intel_dsi_vbt.c intel_hdmi.c intel_mocs.c intel_color.c

@noticelake@ expression e; @@
-!IS_ICELAKE(e)
+INTEL_GEN(e) < 11
@notgen11@ expression e; @@
-!IS_GEN(e, 11)
+INTEL_GEN(e) < 11
@icelake@ expression e; @@
-IS_ICELAKE(e)
+INTEL_GEN(e) >= 11
@gen11@ expression e; @@
-IS_GEN(e, 11)
+INTEL_GEN(e) >= 11

No functional change.

v2: Remove intel_lrc.c per Tvrtko request since those were w/a
    for ICL hw issuea and media related configuration.

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c         |  2 +-
 drivers/gpu/drm/i915/intel_bios.c        |  4 ++--
 drivers/gpu/drm/i915/intel_cdclk.c       |  6 +++---
 drivers/gpu/drm/i915/intel_color.c       |  2 +-
 drivers/gpu/drm/i915/intel_ddi.c         | 18 +++++++++---------
 drivers/gpu/drm/i915/intel_device_info.c |  2 +-
 drivers/gpu/drm/i915/intel_display.c     | 18 +++++++++---------
 drivers/gpu/drm/i915/intel_dpll_mgr.c    |  2 +-
 drivers/gpu/drm/i915/intel_dsi_vbt.c     |  6 +++---
 drivers/gpu/drm/i915/intel_hdmi.c        |  4 ++--
 drivers/gpu/drm/i915/intel_mocs.c        |  2 +-
 11 files changed, 33 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e19a89e4df64..9b0292a38865 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2881,7 +2881,7 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
 
 	sysfs_attr_init(&dev_priv->perf.oa.test_config.sysfs_metric_id.attr);
 
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		i915_perf_load_test_config_icl(dev_priv);
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		i915_perf_load_test_config_cnl(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index b508d8a735e0..48c62bea92cd 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -2093,8 +2093,8 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
 		dvo_port = child->dvo_port;
 
 		if (dvo_port == DVO_PORT_MIPIA ||
-		    (dvo_port == DVO_PORT_MIPIB && IS_ICELAKE(dev_priv)) ||
-		    (dvo_port == DVO_PORT_MIPIC && !IS_ICELAKE(dev_priv))) {
+		    (dvo_port == DVO_PORT_MIPIB && INTEL_GEN(dev_priv) >= 11) ||
+		    (dvo_port == DVO_PORT_MIPIC && INTEL_GEN(dev_priv) < 11)) {
 			if (port)
 				*port = dvo_port - DVO_PORT_MIPIA;
 			return true;
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 5d266538036d..7e5132772477 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2560,7 +2560,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 {
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		if (dev_priv->cdclk.hw.ref == 24000)
 			dev_priv->max_cdclk_freq = 648000;
 		else
@@ -2744,7 +2744,7 @@ void intel_update_rawclk(struct drm_i915_private *dev_priv)
  */
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		dev_priv->display.set_cdclk = icl_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
 	} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2773,7 +2773,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 			vlv_modeset_calc_cdclk;
 	}
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		dev_priv->display.get_cdclk = icl_get_cdclk;
 	else if (IS_CANNONLAKE(dev_priv))
 		dev_priv->display.get_cdclk = cnl_get_cdclk;
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index da7a07d5ccea..0173967ed593 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -841,7 +841,7 @@ void intel_color_init(struct intel_crtc *crtc)
 
 		dev_priv->display.color_commit = i9xx_color_commit;
 	} else {
-		if (IS_ICELAKE(dev_priv))
+		if (INTEL_GEN(dev_priv) >= 11)
 			dev_priv->display.load_luts = icl_load_luts;
 		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
 			dev_priv->display.load_luts = glk_load_luts;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7e3b4e8fdf3a..69aa0d148795 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -851,7 +851,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
 
 	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		if (intel_port_is_combophy(dev_priv, port))
 			icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
 						0, &n_entries);
@@ -1678,7 +1678,7 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		icl_ddi_clock_get(encoder, pipe_config);
 	else if (IS_CANNONLAKE(dev_priv))
 		cnl_ddi_clock_get(encoder, pipe_config);
@@ -2225,7 +2225,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 	enum port port = encoder->port;
 	int n_entries;
 
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		if (intel_port_is_combophy(dev_priv, port))
 			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
 						intel_dp->link_rate, &n_entries);
@@ -2698,7 +2698,7 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp)
 	struct intel_encoder *encoder = &dport->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
 					level, encoder->type);
 	else if (IS_CANNONLAKE(dev_priv))
@@ -2867,7 +2867,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 
 	mutex_lock(&dev_priv->dpll_lock);
 
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		if (!intel_port_is_combophy(dev_priv, port))
 			I915_WRITE(DDI_CLK_SEL(port),
 				   icl_pll_to_ddi_clk_sel(encoder, crtc_state));
@@ -2909,7 +2909,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		if (!intel_port_is_combophy(dev_priv, port))
 			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
 	} else if (IS_CANNONLAKE(dev_priv)) {
@@ -3126,7 +3126,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	icl_program_mg_dp_mode(dig_port);
 	icl_disable_phy_clock_gating(dig_port);
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
 					level, encoder->type);
 	else if (IS_CANNONLAKE(dev_priv))
@@ -3175,7 +3175,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
 	icl_program_mg_dp_mode(dig_port);
 	icl_disable_phy_clock_gating(dig_port);
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
 					level, INTEL_OUTPUT_HDMI);
 	else if (IS_CANNONLAKE(dev_priv))
@@ -3711,7 +3711,7 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
 					 struct intel_crtc_state *crtc_state)
 {
-	if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
+	if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 1;
 	else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 2;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 2c1b46cfd6d3..aac19b1c419c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -740,7 +740,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 
-	if (IS_GEN(dev_priv, 11))
+	if (INTEL_GEN(dev_priv) >= 11)
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_sprites[pipe] = 6;
 	else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 963b4bd69dbb..7ef1d3054cb1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5035,10 +5035,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 	/* range checks */
 	if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
 	    dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
-	    (IS_GEN(dev_priv, 11) &&
+	    (INTEL_GEN(dev_priv) >= 11 &&
 	     (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
 	      dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
-	    (!IS_GEN(dev_priv, 11) &&
+	    (INTEL_GEN(dev_priv) < 11 &&
 	     (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
 	      dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H)))	{
 		DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
@@ -6139,7 +6139,7 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
 	if (port == PORT_NONE)
 		return false;
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		return port <= PORT_B;
 
 	return false;
@@ -6147,7 +6147,7 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
 
 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
 {
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		return port >= PORT_C && port <= PORT_F;
 
 	return false;
@@ -9568,7 +9568,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
 		to_intel_atomic_state(crtc_state->base.state);
 
 	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
-	    IS_ICELAKE(dev_priv)) {
+	    INTEL_GEN(dev_priv) >= 11) {
 		struct intel_encoder *encoder =
 			intel_get_crtc_new_encoder(state, crtc_state);
 
@@ -9711,7 +9711,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
 	enum transcoder panel_transcoder;
 	u32 tmp;
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		panel_transcoder_mask |=
 			BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
 
@@ -9847,7 +9847,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
 
 	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		icelake_get_ddi_pll(dev_priv, port, pipe_config);
 	else if (IS_CANNONLAKE(dev_priv))
 		cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
@@ -9910,7 +9910,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 		goto out;
 
 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
-	    IS_ICELAKE(dev_priv)) {
+	    INTEL_GEN(dev_priv) >= 11) {
 		haswell_get_ddi_port_state(crtc, pipe_config);
 		intel_get_pipe_timings(crtc, pipe_config);
 	}
@@ -14658,7 +14658,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv))
 		return;
 
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index e4ec73d415d9..b3fb221c2532 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -3259,7 +3259,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
 	const struct dpll_info *dpll_info;
 	int i;
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		dpll_mgr = &icl_pll_mgr;
 	else if (IS_CANNONLAKE(dev_priv))
 		dpll_mgr = &cnl_pll_mgr;
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 06a11c35a784..d1e00e4c7726 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -194,7 +194,7 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
 		break;
 	}
 
-	if (!IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) < 11)
 		vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
 
 out:
@@ -365,7 +365,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	/* pull up/down */
 	value = *data++ & 1;
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
 	else if (IS_VALLEYVIEW(dev_priv))
 		vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
@@ -890,7 +890,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 
 	intel_dsi->burst_mode_ratio = burst_mode_ratio;
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		icl_dphy_param_init(intel_dsi);
 	else
 		vlv_dphy_param_init(intel_dsi);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index cd422a7b4da0..5ccb305a6e1c 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2206,7 +2206,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
 
 	/* Display Wa_1405510057:icl */
 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
-	    bpc == 10 && IS_ICELAKE(dev_priv) &&
+	    bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
 	    (adjusted_mode->crtc_hblank_end -
 	     adjusted_mode->crtc_hblank_start) % 8 == 2)
 		return false;
@@ -2500,7 +2500,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool force)
 
 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
 
-	if (IS_ICELAKE(dev_priv) &&
+	if (INTEL_GEN(dev_priv) >= 11 &&
 	    !intel_digital_port_connected(encoder))
 		goto out;
 
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 80dcc08222d0..274ba78500c0 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -252,7 +252,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 {
 	bool result = false;
 
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		table->size  = ARRAY_SIZE(icelake_mocs_table);
 		table->table = icelake_mocs_table;
 		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
-- 
2.20.1

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[PATCH 2/3] drm/i915: Move PCH_NOP to -1

[Rodrigo Vivi]

So we can later use PCH >= comparisons. The ultimate goal
is to make it easier for us to introduce a new platform
with south display engine on PCH just by reusing the previous
one.

Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4ffe19ec698..8a57cdde5385 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -524,6 +524,7 @@ struct i915_psr {
 };
 
 enum intel_pch {
+	PCH_NOP = -1,	/* PCH without south display */
 	PCH_NONE = 0,	/* No PCH present */
 	PCH_IBX,	/* Ibexpeak PCH */
 	PCH_CPT,	/* Cougarpoint/Pantherpoint PCH */
@@ -532,7 +533,6 @@ enum intel_pch {
 	PCH_KBP,        /* Kaby Lake PCH */
 	PCH_CNP,        /* Cannon Lake PCH */
 	PCH_ICP,	/* Ice Lake PCH */
-	PCH_NOP,	/* PCH without south display */
 };
 
 enum intel_sbi_destination {
-- 
2.20.1

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[PATCH 3/3] drm/i915: Start using comparative INTEL_PCH_TYPE

[Rodrigo Vivi]

In order to make it easier to bring up new platforms
without having to take care about all corner cases
that was previously taken care for previous platforms
we already use comparative INTEL_GEN statements.

Let's start doing the same with PCH.

The only caveats are:
 - less-than comparisons need to be avoided or done with
   attention and check > PCH_NONE as well.
 - It is not necessarily a chronological order, but a matter
   of south display compatibility/inheritance.

v2: Rebased on top of Jani's clean-up which removed the
    need for less-than comparison

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h    | 6 ++++++
 drivers/gpu/drm/i915/i915_irq.c    | 7 ++-----
 drivers/gpu/drm/i915/intel_cdclk.c | 2 +-
 drivers/gpu/drm/i915/intel_dp.c    | 3 +--
 drivers/gpu/drm/i915/intel_panel.c | 5 ++---
 5 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8a57cdde5385..9a93accbb2e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -523,6 +523,12 @@ struct i915_psr {
 	u16 su_x_granularity;
 };
 
+/*
+ * Sorted by south display engine compatibility.
+ * If the new PCH comes with a south display engine that is not
+ * inherited from the latest item, please do not add it to the
+ * end. Instead, add it right after its "parent" PCH.
+ */
 enum intel_pch {
 	PCH_NOP = -1,	/* PCH without south display */
 	PCH_NONE = 0,	/* No PCH present */
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1f4e984ce42f..c823d2e76852 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2831,9 +2831,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 
 			if (HAS_PCH_ICP(dev_priv))
 				icp_irq_handler(dev_priv, iir);
-			else if (HAS_PCH_SPT(dev_priv) ||
-				 HAS_PCH_KBP(dev_priv) ||
-				 HAS_PCH_CNP(dev_priv))
+			else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
 				spt_irq_handler(dev_priv, iir);
 			else
 				cpt_irq_handler(dev_priv, iir);
@@ -4621,8 +4619,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->disable_vblank = gen8_disable_vblank;
 		if (IS_GEN9_LP(dev_priv))
 			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
-		else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
-			 HAS_PCH_CNP(dev_priv))
+		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
 			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
 		else
 			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 7e5132772477..9d236e4ed26a 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2723,7 +2723,7 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 {
-	if (HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv))
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
 		dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
 	else if (HAS_PCH_SPLIT(dev_priv))
 		dev_priv->rawclk_freq = pch_rawclk(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f40b3342d82a..47857f96c3b1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -951,8 +951,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
 	regs->pp_off = PP_OFF_DELAYS(pps_idx);
 
 	/* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
-	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
-	    HAS_PCH_ICP(dev_priv))
+	if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
 		regs->pp_div = INVALID_MMIO_REG;
 	else
 		regs->pp_div = PP_DIVISOR(pps_idx);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index beca98d2b035..edd5540639b0 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1894,15 +1894,14 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
 		panel->backlight.set = bxt_set_backlight;
 		panel->backlight.get = bxt_get_backlight;
 		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
-	} else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv)) {
+	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) {
 		panel->backlight.setup = cnp_setup_backlight;
 		panel->backlight.enable = cnp_enable_backlight;
 		panel->backlight.disable = cnp_disable_backlight;
 		panel->backlight.set = bxt_set_backlight;
 		panel->backlight.get = bxt_get_backlight;
 		panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
-	} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
-		   HAS_PCH_KBP(dev_priv)) {
+	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_LPT) {
 		panel->backlight.setup = lpt_setup_backlight;
 		panel->backlight.enable = lpt_enable_backlight;
 		panel->backlight.disable = lpt_disable_backlight;
-- 
2.20.1

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✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/gen11+: First assume next platforms will inherit stuff

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/gen11+: First assume next platforms will inherit stuff
URL   : https://patchwork.freedesktop.org/series/57768/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/gen11+: First assume next platforms will inherit stuff
Okay!

Commit: drm/i915: Move PCH_NOP to -1
Okay!

Commit: drm/i915: Start using comparative INTEL_PCH_TYPE
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3553:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3559:16: warning: expression using sizeof(void)

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Re: [PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff

[Chris Wilson]

Quoting Rodrigo Vivi (2019-03-08 21:42:58)
> This exactly same approach was already used from gen9
> to gen10 and from gen10 to gen11. Let's also use it
> for gen11+.
> 
> Let's first assume that we inherit a similar platform
> and than we apply the differences on top.
> 
> Different from the previous attempts this will be
> done this time with coccinelle. We obviously need to
> exclude some case that is really exclusive for gen11
> like  PCH, Firmware, and few others. Luckly this was
> easy to filter by selecting the files we are touching
> with coccinelle as exposed below:
> 
> spatch -sp_file gen11\+.cocci --in-place i915_perf.c \
>        intel_bios.c intel_cdclk.c intel_ddi.c \
>        intel_device_info.c intel_display.c intel_dpll_mgr.c \
>        intel_dsi_vbt.c intel_hdmi.c intel_mocs.c intel_color.c
> 
> @noticelake@ expression e; @@
> -!IS_ICELAKE(e)
> +INTEL_GEN(e) < 11
> @notgen11@ expression e; @@
> -!IS_GEN(e, 11)
> +INTEL_GEN(e) < 11
> @icelake@ expression e; @@
> -IS_ICELAKE(e)
> +INTEL_GEN(e) >= 11
> @gen11@ expression e; @@
> -IS_GEN(e, 11)
> +INTEL_GEN(e) >= 11
> 
> No functional change.
> 
> v2: Remove intel_lrc.c per Tvrtko request since those were w/a
>     for ICL hw issuea and media related configuration.
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_perf.c         |  2 +-
>  drivers/gpu/drm/i915/intel_bios.c        |  4 ++--
>  drivers/gpu/drm/i915/intel_cdclk.c       |  6 +++---
>  drivers/gpu/drm/i915/intel_color.c       |  2 +-
>  drivers/gpu/drm/i915/intel_ddi.c         | 18 +++++++++---------
>  drivers/gpu/drm/i915/intel_device_info.c |  2 +-
>  drivers/gpu/drm/i915/intel_display.c     | 18 +++++++++---------
>  drivers/gpu/drm/i915/intel_dpll_mgr.c    |  2 +-
>  drivers/gpu/drm/i915/intel_dsi_vbt.c     |  6 +++---
>  drivers/gpu/drm/i915/intel_hdmi.c        |  4 ++--
>  drivers/gpu/drm/i915/intel_mocs.c        |  2 +-
>  11 files changed, 33 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index e19a89e4df64..9b0292a38865 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2881,7 +2881,7 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
>  
>         sysfs_attr_init(&dev_priv->perf.oa.test_config.sysfs_metric_id.attr);
>  
> -       if (IS_ICELAKE(dev_priv)) {
> +       if (INTEL_GEN(dev_priv) >= 11) {
>                 i915_perf_load_test_config_icl(dev_priv);
>         } else if (IS_CANNONLAKE(dev_priv)) {
>                 i915_perf_load_test_config_cnl(dev_priv);

Given that every platform so far has had different oa configurations,
that looks to be a hasty assumption that future platforms will be fixed.
-Chris
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Re: [PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff

[Rodrigo Vivi]

On Fri, Mar 08, 2019 at 10:23:20PM +0000, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2019-03-08 21:42:58)
> > This exactly same approach was already used from gen9
> > to gen10 and from gen10 to gen11. Let's also use it
> > for gen11+.
> > 
> > Let's first assume that we inherit a similar platform
> > and than we apply the differences on top.
> > 
> > Different from the previous attempts this will be
> > done this time with coccinelle. We obviously need to
> > exclude some case that is really exclusive for gen11
> > like  PCH, Firmware, and few others. Luckly this was
> > easy to filter by selecting the files we are touching
> > with coccinelle as exposed below:
> > 
> > spatch -sp_file gen11\+.cocci --in-place i915_perf.c \
> >        intel_bios.c intel_cdclk.c intel_ddi.c \
> >        intel_device_info.c intel_display.c intel_dpll_mgr.c \
> >        intel_dsi_vbt.c intel_hdmi.c intel_mocs.c intel_color.c
> > 
> > @noticelake@ expression e; @@
> > -!IS_ICELAKE(e)
> > +INTEL_GEN(e) < 11
> > @notgen11@ expression e; @@
> > -!IS_GEN(e, 11)
> > +INTEL_GEN(e) < 11
> > @icelake@ expression e; @@
> > -IS_ICELAKE(e)
> > +INTEL_GEN(e) >= 11
> > @gen11@ expression e; @@
> > -IS_GEN(e, 11)
> > +INTEL_GEN(e) >= 11
> > 
> > No functional change.
> > 
> > v2: Remove intel_lrc.c per Tvrtko request since those were w/a
> >     for ICL hw issuea and media related configuration.
> > 
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_perf.c         |  2 +-
> >  drivers/gpu/drm/i915/intel_bios.c        |  4 ++--
> >  drivers/gpu/drm/i915/intel_cdclk.c       |  6 +++---
> >  drivers/gpu/drm/i915/intel_color.c       |  2 +-
> >  drivers/gpu/drm/i915/intel_ddi.c         | 18 +++++++++---------
> >  drivers/gpu/drm/i915/intel_device_info.c |  2 +-
> >  drivers/gpu/drm/i915/intel_display.c     | 18 +++++++++---------
> >  drivers/gpu/drm/i915/intel_dpll_mgr.c    |  2 +-
> >  drivers/gpu/drm/i915/intel_dsi_vbt.c     |  6 +++---
> >  drivers/gpu/drm/i915/intel_hdmi.c        |  4 ++--
> >  drivers/gpu/drm/i915/intel_mocs.c        |  2 +-
> >  11 files changed, 33 insertions(+), 33 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> > index e19a89e4df64..9b0292a38865 100644
> > --- a/drivers/gpu/drm/i915/i915_perf.c
> > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > @@ -2881,7 +2881,7 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
> >  
> >         sysfs_attr_init(&dev_priv->perf.oa.test_config.sysfs_metric_id.attr);
> >  
> > -       if (IS_ICELAKE(dev_priv)) {
> > +       if (INTEL_GEN(dev_priv) >= 11) {
> >                 i915_perf_load_test_config_icl(dev_priv);
> >         } else if (IS_CANNONLAKE(dev_priv)) {
> >                 i915_perf_load_test_config_cnl(dev_priv);
> 
> Given that every platform so far has had different oa configurations,
> that looks to be a hasty assumption that future platforms will be fixed.

I know... But my hope is that at some point it gets stabilized.

Well, or at least start with this so any other gen11 could reuse and
gen12 would start with that and change later for >= gen12 and on...

> -Chris
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✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gen11+: First assume next platforms will inherit stuff

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/gen11+: First assume next platforms will inherit stuff
URL   : https://patchwork.freedesktop.org/series/57768/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5728 -> Patchwork_12426
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/57768/revisions/1/mbox/

Known issues
------------

  Here are the changes found in Patchwork_12426 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-compute:
    - fi-kbl-8809g:       NOTRUN -> FAIL [fdo#108094]

  * igt@gem_exec_basic@gtt-bsd2:
    - fi-byt-clapper:     NOTRUN -> SKIP [fdo#109271] +57

  * igt@gem_exec_basic@readonly-bsd2:
    - fi-pnv-d510:        NOTRUN -> SKIP [fdo#109271] +76

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@kms_busy@basic-flip-c:
    - fi-byt-j1900:       NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
    - fi-byt-clapper:     NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
    - fi-pnv-d510:        NOTRUN -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-byt-j1900:       NOTRUN -> SKIP [fdo#109271] +52

  * igt@kms_frontbuffer_tracking@basic:
    - fi-byt-clapper:     NOTRUN -> FAIL [fdo#103167]

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
    - fi-byt-clapper:     NOTRUN -> FAIL [fdo#107362]

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     NOTRUN -> FAIL [fdo#103191] / [fdo#107362]

  
#### Possible fixes ####

  * igt@amdgpu/amd_basic@userptr:
    - fi-kbl-8809g:       DMESG-WARN [fdo#108965] -> PASS

  * igt@kms_busy@basic-flip-a:
    - fi-gdg-551:         FAIL [fdo#103182] -> PASS

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          FAIL [fdo#103167] -> PASS

  
#### Warnings ####

  * igt@i915_selftest@live_contexts:
    - fi-icl-u3:          DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108569]

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278


Participating hosts (42 -> 43)
------------------------------

  Additional (3): fi-byt-j1900 fi-byt-clapper fi-pnv-d510 
  Missing    (2): fi-ilk-m540 fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5728 -> Patchwork_12426

  CI_DRM_5728: 78b288a16a32e8828f93c5e2e9eb3c1b73bfdce7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4877: d15ad69be07a987d5c2ba408201b287adae8ca59 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12426: c660e5a5a1de9783f0e810d09fbdd1e76b314e86 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c660e5a5a1de drm/i915: Start using comparative INTEL_PCH_TYPE
75e7e41e7d7a drm/i915: Move PCH_NOP to -1
8279af225dca drm/i915/gen11+: First assume next platforms will inherit stuff

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12426/
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✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/gen11+: First assume next platforms will inherit stuff

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/gen11+: First assume next platforms will inherit stuff
URL   : https://patchwork.freedesktop.org/series/57768/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5728_full -> Patchwork_12426_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12426_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live_coherency:
    - {shard-iclb}:       PASS -> DMESG-WARN +9

  * igt@i915_selftest@live_contexts:
    - {shard-iclb}:       DMESG-FAIL [fdo#108569] -> DMESG-WARN

  * igt@i915_selftest@live_gem:
    - {shard-iclb}:       PASS -> DMESG-FAIL +2

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu:
    - {shard-iclb}:       NOTRUN -> SKIP +30

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
    - {shard-iclb}:       NOTRUN -> FAIL +8

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
    - {shard-iclb}:       PASS -> FAIL +16

  * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
    - {shard-iclb}:       FAIL [fdo#108948] -> SKIP

  * igt@perf_pmu@busy-start-vecs0:
    - {shard-iclb}:       PASS -> INCOMPLETE

  * igt@runner@aborted:
    - {shard-iclb}:       ( 7 FAIL ) [fdo#106612] -> ( 4 FAIL )

  
Known issues
------------

  Here are the changes found in Patchwork_12426_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_userptr_blits@process-exit-gtt:
    - shard-glk:          NOTRUN -> SKIP [fdo#109271] +41

  * igt@i915_pm_lpsp@screens-disabled:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] +54

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-snb:          PASS -> SKIP [fdo#109271]

  * igt@i915_pm_rpm@gem-execbuf-stress-extra-wait:
    - shard-skl:          PASS -> INCOMPLETE [fdo#107803] / [fdo#107807] +1

  * igt@i915_pm_rpm@modeset-lpsp:
    - shard-skl:          PASS -> INCOMPLETE [fdo#107807] +1

  * igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
    - shard-apl:          PASS -> FAIL [fdo#109660]

  * igt@kms_atomic_transition@3x-modeset-transitions-nonblocking:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2

  * igt@kms_busy@basic-flip-d:
    - shard-glk:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
    - shard-hsw:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_color@pipe-a-ctm-max:
    - shard-glk:          NOTRUN -> FAIL [fdo#108147]

  * igt@kms_cursor_crc@cursor-128x42-random:
    - shard-glk:          NOTRUN -> FAIL [fdo#103232] +1

  * igt@kms_cursor_crc@cursor-64x64-dpms:
    - shard-apl:          PASS -> FAIL [fdo#103232] +1

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-glk:          PASS -> FAIL [fdo#103167] +2

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
    - shard-apl:          PASS -> FAIL [fdo#103167] +1

  * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#106885]

  * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
    - shard-skl:          NOTRUN -> FAIL [fdo#107815] / [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
    - shard-glk:          NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
    - shard-skl:          NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          PASS -> FAIL [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          PASS -> FAIL [fdo#107815]

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
    - shard-apl:          PASS -> FAIL [fdo#103166] +3

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
    - shard-glk:          PASS -> FAIL [fdo#103166]

  * igt@kms_rotation_crc@multiplane-rotation:
    - shard-kbl:          PASS -> FAIL [fdo#109016]

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-kbl:          PASS -> DMESG-FAIL [fdo#105763]

  * igt@kms_universal_plane@disable-primary-vs-flip-pipe-f:
    - shard-apl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-apl:          PASS -> FAIL [fdo#104894] +1

  * igt@prime_nv_api@i915_nv_import_vs_close:
    - shard-apl:          NOTRUN -> SKIP [fdo#109271] +31

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@vcs0-none:
    - {shard-iclb}:       DMESG-FAIL -> PASS

  * igt@gem_eio@wait-wedge-immediate:
    - {shard-iclb}:       WARN -> PASS

  * igt@gem_fence_thrash@bo-write-verify-y:
    - {shard-iclb}:       INCOMPLETE -> PASS +1

  * igt@gem_softpin@noreloc-s3:
    - {shard-iclb}:       FAIL [fdo#103375] -> PASS

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - shard-skl:          INCOMPLETE [fdo#107807] -> PASS

  * igt@kms_color@pipe-a-degamma:
    - shard-apl:          FAIL [fdo#104782] / [fdo#108145] -> PASS

  * igt@kms_color@pipe-a-legacy-gamma:
    - shard-skl:          FAIL [fdo#104782] / [fdo#108145] -> PASS

  * igt@kms_cursor_crc@cursor-128x42-random:
    - shard-skl:          FAIL [fdo#103232] -> PASS

  * igt@kms_cursor_crc@cursor-64x21-random:
    - shard-apl:          FAIL [fdo#103232] -> PASS

  * igt@kms_cursor_crc@cursor-alpha-opaque:
    - shard-apl:          FAIL [fdo#109350] -> PASS

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
    - {shard-iclb}:       FAIL [fdo#103355] -> PASS +1

  * igt@kms_flip@flip-vs-suspend:
    - shard-skl:          INCOMPLETE [fdo#109507] -> PASS

  * igt@kms_flip_tiling@flip-yf-tiled:
    - shard-skl:          FAIL [fdo#108145] -> PASS +2

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
    - shard-apl:          FAIL [fdo#103167] -> PASS +2

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-glk:          FAIL [fdo#103167] -> PASS +1

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
    - {shard-iclb}:       FAIL [fdo#105682] -> PASS

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite:
    - shard-skl:          FAIL [fdo#105682] -> PASS

  * igt@kms_frontbuffer_tracking@fbcpsr-slowdraw:
    - {shard-iclb}:       FAIL [fdo#103167] -> PASS +6

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite:
    - {shard-iclb}:       FAIL -> PASS +7

  * igt@kms_frontbuffer_tracking@psr-farfromfence:
    - shard-skl:          FAIL [fdo#103167] -> PASS

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-glk:          INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS +1
    - {shard-iclb}:       DMESG-WARN -> PASS

  * igt@kms_plane@plane-position-covered-pipe-c-planes:
    - shard-apl:          FAIL [fdo#103166] -> PASS +2

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
    - shard-glk:          FAIL [fdo#103166] -> PASS +2

  * igt@kms_psr2_su@frontbuffer:
    - {shard-iclb}:       SKIP [fdo#109642] -> PASS

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - {shard-iclb}:       SKIP [fdo#109441] -> PASS

  * igt@kms_psr@sprite_render:
    - {shard-iclb}:       FAIL [fdo#107383] -> PASS +3

  * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
    - shard-apl:          FAIL [fdo#104894] -> PASS

  
#### Warnings ####

  * igt@i915_pm_rpm@pc8-residency:
    - shard-skl:          INCOMPLETE [fdo#107807] -> SKIP [fdo#109271]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
  [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106612]: https://bugs.freedesktop.org/show_bug.cgi?id=106612
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
  [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
  [fdo#109052]: https://bugs.freedesktop.org/show_bug.cgi?id=109052
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109287]: https://bugs.freedesktop.org/show_bug.cgi?id=109287
  [fdo#109288]: https://bugs.freedesktop.org/show_bug.cgi?id=109288
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109502]: https://bugs.freedesktop.org/show_bug.cgi?id=109502
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#109559]: https://bugs.freedesktop.org/show_bug.cgi?id=109559
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644
  [fdo#109660]: https://bugs.freedesktop.org/show_bug.cgi?id=109660
  [fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
  [fdo#109677]: https://bugs.freedesktop.org/show_bug.cgi?id=109677
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts


Build changes
-------------

    * Linux: CI_DRM_5728 -> Patchwork_12426

  CI_DRM_5728: 78b288a16a32e8828f93c5e2e9eb3c1b73bfdce7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4877: d15ad69be07a987d5c2ba408201b287adae8ca59 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12426: c660e5a5a1de9783f0e810d09fbdd1e76b314e86 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12426/
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Re: [PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff

[Lucas De Marchi]

On Fri, Mar 08, 2019 at 02:39:36PM -0800, Rodrigo Vivi wrote:
>> Given that every platform so far has had different oa configurations,
>> that looks to be a hasty assumption that future platforms will be fixed.
>
>I know... But my hope is that at some point it gets stabilized.
>
>Well, or at least start with this so any other gen11 could reuse and
>gen12 would start with that and change later for >= gen12 and on...

If it's different, there's no harm in making this assumption now and
then later change to cover the differences. Making it consistent
everywhere allows to more easily add the next platform.

Lucas De Marchi

>
>> -Chris
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Re: [PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff

[Jani Nikula]

On Fri, 08 Mar 2019, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Fri, Mar 08, 2019 at 02:39:36PM -0800, Rodrigo Vivi wrote:
>>> Given that every platform so far has had different oa configurations,
>>> that looks to be a hasty assumption that future platforms will be fixed.
>>
>>I know... But my hope is that at some point it gets stabilized.
>>
>>Well, or at least start with this so any other gen11 could reuse and
>>gen12 would start with that and change later for >= gen12 and on...
>
> If it's different, there's no harm in making this assumption now and
> then later change to cover the differences. Making it consistent
> everywhere allows to more easily add the next platform.

At some point in time we deliberately made the if ladders and switch
cases avoid matching future platforms, and liberally sprinkled
MISSING_CASE() all over the place so we would catch each location that
needed updating. So we wouldn't miss any.

This is the opposite of that approach. I'm not against the new approach,
because we do have a lot of places where the existing code just works,
but if you do know something will break, or will need to be updated to
work, why not use the MISSING_CASE() there?

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff

[Rodrigo Vivi]

On Mon, Mar 11, 2019 at 11:12:06AM +0200, Jani Nikula wrote:
> On Fri, 08 Mar 2019, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> > On Fri, Mar 08, 2019 at 02:39:36PM -0800, Rodrigo Vivi wrote:
> >>> Given that every platform so far has had different oa configurations,
> >>> that looks to be a hasty assumption that future platforms will be fixed.
> >>
> >>I know... But my hope is that at some point it gets stabilized.
> >>
> >>Well, or at least start with this so any other gen11 could reuse and
> >>gen12 would start with that and change later for >= gen12 and on...
> >
> > If it's different, there's no harm in making this assumption now and
> > then later change to cover the differences. Making it consistent
> > everywhere allows to more easily add the next platform.
> 
> At some point in time we deliberately made the if ladders and switch
> cases avoid matching future platforms, and liberally sprinkled
> MISSING_CASE() all over the place so we would catch each location that
> needed updating. So we wouldn't miss any.
> 
> This is the opposite of that approach. I'm not against the new approach,
> because we do have a lot of places where the existing code just works,
> but if you do know something will break, or will need to be updated to
> work, why not use the MISSING_CASE() there?

If you know in advance and you don't have any internal patch handling that
a MISSING_CASE is useful indeed.

Notice that there were cases that I intentionally left ICL behind.

I will double check if I think this or any of those cases deserves
the MISSING_CASES, but my current guess is that we are fine without it.

Also I'm wondering if we should make some macros:

if GEN_GREATER_THAN(dev_priv, 11) {
	icl_func(); 
}

#define GEN_GREATER_THAN(dev_priv, n) \
        if n > latest_implemented_gen() \
	   MISSING_CASE()

or something like that...

hmm but this wouldn't help us later, when gen12 is
already defined in some internal and we might forget anyways...

so maybe something like

#define GEN_GREATER_THAN(dev_priv, g) \
        if g != .gen \
	   DRM_DEBUG_DRIVER("Reusing %s from gen %d\n", __FUNCTION__, g)


But for now let's please just use this approach to save internal little
patches here and there.

> 
> BR,
> Jani.
> 
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff

[Jani Nikula]

On Mon, 11 Mar 2019, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Mon, Mar 11, 2019 at 11:12:06AM +0200, Jani Nikula wrote:
>> On Fri, 08 Mar 2019, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> > On Fri, Mar 08, 2019 at 02:39:36PM -0800, Rodrigo Vivi wrote:
>> >>> Given that every platform so far has had different oa configurations,
>> >>> that looks to be a hasty assumption that future platforms will be fixed.
>> >>
>> >>I know... But my hope is that at some point it gets stabilized.
>> >>
>> >>Well, or at least start with this so any other gen11 could reuse and
>> >>gen12 would start with that and change later for >= gen12 and on...
>> >
>> > If it's different, there's no harm in making this assumption now and
>> > then later change to cover the differences. Making it consistent
>> > everywhere allows to more easily add the next platform.
>> 
>> At some point in time we deliberately made the if ladders and switch
>> cases avoid matching future platforms, and liberally sprinkled
>> MISSING_CASE() all over the place so we would catch each location that
>> needed updating. So we wouldn't miss any.
>> 
>> This is the opposite of that approach. I'm not against the new approach,
>> because we do have a lot of places where the existing code just works,
>> but if you do know something will break, or will need to be updated to
>> work, why not use the MISSING_CASE() there?
>
> If you know in advance and you don't have any internal patch handling that
> a MISSING_CASE is useful indeed.
>
> Notice that there were cases that I intentionally left ICL behind.
>
> I will double check if I think this or any of those cases deserves
> the MISSING_CASES, but my current guess is that we are fine without it.
>
> Also I'm wondering if we should make some macros:
>
> if GEN_GREATER_THAN(dev_priv, 11) {
> 	icl_func(); 
> }
>
> #define GEN_GREATER_THAN(dev_priv, n) \
>         if n > latest_implemented_gen() \
> 	   MISSING_CASE()
>
> or something like that...
>
> hmm but this wouldn't help us later, when gen12 is
> already defined in some internal and we might forget anyways...
>
> so maybe something like
>
> #define GEN_GREATER_THAN(dev_priv, g) \
>         if g != .gen \
> 	   DRM_DEBUG_DRIVER("Reusing %s from gen %d\n", __FUNCTION__, g)

This would spam dmesg everywhere it's used for normal cases.

As to this "greater than" business, there were macros to do
this... before 5bc0e89ff1be ("drm/i915: Kill GEN_FOREVER"). :/

> But for now let's please just use this approach to save internal little
> patches here and there.

Okay, let's see what happens.


BR,
Jani.



-- 
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Re: [PATCH 3/3] drm/i915: Start using comparative INTEL_PCH_TYPE

[Lucas De Marchi]

On Fri, Mar 08, 2019 at 01:43:00PM -0800, Rodrigo Vivi wrote:
>In order to make it easier to bring up new platforms
>without having to take care about all corner cases
>that was previously taken care for previous platforms
>we already use comparative INTEL_GEN statements.
>
>Let's start doing the same with PCH.
>
>The only caveats are:
> - less-than comparisons need to be avoided or done with
>   attention and check > PCH_NONE as well.
> - It is not necessarily a chronological order, but a matter
>   of south display compatibility/inheritance.
>
>v2: Rebased on top of Jani's clean-up which removed the
>    need for less-than comparison
>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

thanks
Lucas De Marchi


>---
> drivers/gpu/drm/i915/i915_drv.h    | 6 ++++++
> drivers/gpu/drm/i915/i915_irq.c    | 7 ++-----
> drivers/gpu/drm/i915/intel_cdclk.c | 2 +-
> drivers/gpu/drm/i915/intel_dp.c    | 3 +--
> drivers/gpu/drm/i915/intel_panel.c | 5 ++---
> 5 files changed, 12 insertions(+), 11 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 8a57cdde5385..9a93accbb2e1 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -523,6 +523,12 @@ struct i915_psr {
> 	u16 su_x_granularity;
> };
>
>+/*
>+ * Sorted by south display engine compatibility.
>+ * If the new PCH comes with a south display engine that is not
>+ * inherited from the latest item, please do not add it to the
>+ * end. Instead, add it right after its "parent" PCH.
>+ */
> enum intel_pch {
> 	PCH_NOP = -1,	/* PCH without south display */
> 	PCH_NONE = 0,	/* No PCH present */
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index 1f4e984ce42f..c823d2e76852 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -2831,9 +2831,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>
> 			if (HAS_PCH_ICP(dev_priv))
> 				icp_irq_handler(dev_priv, iir);
>-			else if (HAS_PCH_SPT(dev_priv) ||
>-				 HAS_PCH_KBP(dev_priv) ||
>-				 HAS_PCH_CNP(dev_priv))
>+			else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> 				spt_irq_handler(dev_priv, iir);
> 			else
> 				cpt_irq_handler(dev_priv, iir);
>@@ -4621,8 +4619,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> 		dev->driver->disable_vblank = gen8_disable_vblank;
> 		if (IS_GEN9_LP(dev_priv))
> 			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
>-		else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
>-			 HAS_PCH_CNP(dev_priv))
>+		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> 			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> 		else
> 			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
>diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
>index 7e5132772477..9d236e4ed26a 100644
>--- a/drivers/gpu/drm/i915/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/intel_cdclk.c
>@@ -2723,7 +2723,7 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv)
>  */
> void intel_update_rawclk(struct drm_i915_private *dev_priv)
> {
>-	if (HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv))
>+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
> 		dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
> 	else if (HAS_PCH_SPLIT(dev_priv))
> 		dev_priv->rawclk_freq = pch_rawclk(dev_priv);
>diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>index f40b3342d82a..47857f96c3b1 100644
>--- a/drivers/gpu/drm/i915/intel_dp.c
>+++ b/drivers/gpu/drm/i915/intel_dp.c
>@@ -951,8 +951,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
> 	regs->pp_off = PP_OFF_DELAYS(pps_idx);
>
> 	/* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
>-	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
>-	    HAS_PCH_ICP(dev_priv))
>+	if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
> 		regs->pp_div = INVALID_MMIO_REG;
> 	else
> 		regs->pp_div = PP_DIVISOR(pps_idx);
>diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
>index beca98d2b035..edd5540639b0 100644
>--- a/drivers/gpu/drm/i915/intel_panel.c
>+++ b/drivers/gpu/drm/i915/intel_panel.c
>@@ -1894,15 +1894,14 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
> 		panel->backlight.set = bxt_set_backlight;
> 		panel->backlight.get = bxt_get_backlight;
> 		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
>-	} else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv)) {
>+	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) {
> 		panel->backlight.setup = cnp_setup_backlight;
> 		panel->backlight.enable = cnp_enable_backlight;
> 		panel->backlight.disable = cnp_disable_backlight;
> 		panel->backlight.set = bxt_set_backlight;
> 		panel->backlight.get = bxt_get_backlight;
> 		panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
>-	} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
>-		   HAS_PCH_KBP(dev_priv)) {
>+	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_LPT) {
> 		panel->backlight.setup = lpt_setup_backlight;
> 		panel->backlight.enable = lpt_enable_backlight;
> 		panel->backlight.disable = lpt_disable_backlight;
>-- 
>2.20.1
>
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Re: [PATCH 3/3] drm/i915: Start using comparative INTEL_PCH_TYPE

[Rodrigo Vivi]

On Wed, Mar 13, 2019 at 10:30:52AM -0700, Lucas De Marchi wrote:
> On Fri, Mar 08, 2019 at 01:43:00PM -0800, Rodrigo Vivi wrote:
> > In order to make it easier to bring up new platforms
> > without having to take care about all corner cases
> > that was previously taken care for previous platforms
> > we already use comparative INTEL_GEN statements.
> > 
> > Let's start doing the same with PCH.
> > 
> > The only caveats are:
> > - less-than comparisons need to be avoided or done with
> >   attention and check > PCH_NONE as well.
> > - It is not necessarily a chronological order, but a matter
> >   of south display compatibility/inheritance.
> > 
> > v2: Rebased on top of Jani's clean-up which removed the
> >    need for less-than comparison
> > 
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> 
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Thanks, series pushed.

> 
> thanks
> Lucas De Marchi
> 
> 
> > ---
> > drivers/gpu/drm/i915/i915_drv.h    | 6 ++++++
> > drivers/gpu/drm/i915/i915_irq.c    | 7 ++-----
> > drivers/gpu/drm/i915/intel_cdclk.c | 2 +-
> > drivers/gpu/drm/i915/intel_dp.c    | 3 +--
> > drivers/gpu/drm/i915/intel_panel.c | 5 ++---
> > 5 files changed, 12 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 8a57cdde5385..9a93accbb2e1 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -523,6 +523,12 @@ struct i915_psr {
> > 	u16 su_x_granularity;
> > };
> > 
> > +/*
> > + * Sorted by south display engine compatibility.
> > + * If the new PCH comes with a south display engine that is not
> > + * inherited from the latest item, please do not add it to the
> > + * end. Instead, add it right after its "parent" PCH.
> > + */
> > enum intel_pch {
> > 	PCH_NOP = -1,	/* PCH without south display */
> > 	PCH_NONE = 0,	/* No PCH present */
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 1f4e984ce42f..c823d2e76852 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2831,9 +2831,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> > 
> > 			if (HAS_PCH_ICP(dev_priv))
> > 				icp_irq_handler(dev_priv, iir);
> > -			else if (HAS_PCH_SPT(dev_priv) ||
> > -				 HAS_PCH_KBP(dev_priv) ||
> > -				 HAS_PCH_CNP(dev_priv))
> > +			else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> > 				spt_irq_handler(dev_priv, iir);
> > 			else
> > 				cpt_irq_handler(dev_priv, iir);
> > @@ -4621,8 +4619,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> > 		dev->driver->disable_vblank = gen8_disable_vblank;
> > 		if (IS_GEN9_LP(dev_priv))
> > 			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> > -		else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
> > -			 HAS_PCH_CNP(dev_priv))
> > +		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> > 			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> > 		else
> > 			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > index 7e5132772477..9d236e4ed26a 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -2723,7 +2723,7 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv)
> >  */
> > void intel_update_rawclk(struct drm_i915_private *dev_priv)
> > {
> > -	if (HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv))
> > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
> > 		dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
> > 	else if (HAS_PCH_SPLIT(dev_priv))
> > 		dev_priv->rawclk_freq = pch_rawclk(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index f40b3342d82a..47857f96c3b1 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -951,8 +951,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
> > 	regs->pp_off = PP_OFF_DELAYS(pps_idx);
> > 
> > 	/* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
> > -	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> > -	    HAS_PCH_ICP(dev_priv))
> > +	if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
> > 		regs->pp_div = INVALID_MMIO_REG;
> > 	else
> > 		regs->pp_div = PP_DIVISOR(pps_idx);
> > diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> > index beca98d2b035..edd5540639b0 100644
> > --- a/drivers/gpu/drm/i915/intel_panel.c
> > +++ b/drivers/gpu/drm/i915/intel_panel.c
> > @@ -1894,15 +1894,14 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
> > 		panel->backlight.set = bxt_set_backlight;
> > 		panel->backlight.get = bxt_get_backlight;
> > 		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
> > -	} else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv)) {
> > +	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) {
> > 		panel->backlight.setup = cnp_setup_backlight;
> > 		panel->backlight.enable = cnp_enable_backlight;
> > 		panel->backlight.disable = cnp_disable_backlight;
> > 		panel->backlight.set = bxt_set_backlight;
> > 		panel->backlight.get = bxt_get_backlight;
> > 		panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
> > -	} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
> > -		   HAS_PCH_KBP(dev_priv)) {
> > +	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_LPT) {
> > 		panel->backlight.setup = lpt_setup_backlight;
> > 		panel->backlight.enable = lpt_enable_backlight;
> > 		panel->backlight.disable = lpt_disable_backlight;
> > -- 
> > 2.20.1
> > 
> _______________________________________________
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff

[Lucas De Marchi]

On Tue, Mar 05, 2019 at 05:43:15PM +0000, Tvrtko Ursulin wrote:
>>diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
>>index 331e7a678fb7..79913b06f455 100644
>>--- a/drivers/gpu/drm/i915/intel_mocs.c
>>+++ b/drivers/gpu/drm/i915/intel_mocs.c
>>@@ -252,7 +252,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
>>  {
>>  	bool result = false;
>>-	if (IS_ICELAKE(dev_priv)) {
>>+	if (INTEL_GEN(dev_priv) >= 11) {
>>  		table->size  = ARRAY_SIZE(icelake_mocs_table);
>>  		table->table = icelake_mocs_table;
>>  		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
>>
>
>Lucas should know if this is OK.

I prefer having it like this and later change if it's different for gen
12. It will make it more consistent on how to add a new one.

Lucas De Marchi
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Re: [PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff

[Tvrtko Ursulin]

On 04/03/2019 22:48, Rodrigo Vivi wrote:
> This exactly same approach was already used from gen9
> to gen10 and from gen10 to gen11. Let's also use it
> for gen11+.
> 
> Let's first assume that we inherit a similar platform
> and than we apply the differences on top.
> 
> Different from the previous attempts this will be
> done this time with coccinelle. We obviously need to
> exclude some case that is really exclusive for gen11
> like  PCH, Firmware, and few others. Luckly this was
> easy to filter by selecting the files we are touching
> with coccinelle as exposed below:
> 
> spatch -sp_file gen11\+.cocci --in-place i915_perf.c \
>         intel_bios.c intel_cdclk.c intel_ddi.c \
>         intel_device_info.c intel_display.c intel_dpll_mgr.c \
>         intel_dsi_vbt.c intel_hdmi.c intel_lrc.c intel_mocs.c intel_color.c
> 
> @noticelake@ expression e; @@
> -!IS_ICELAKE(e)
> +INTEL_GEN(e) < 11
> @notgen11@ expression e; @@
> -!IS_GEN(e, 11)
> +INTEL_GEN(e) < 11
> @icelake@ expression e; @@
> -IS_ICELAKE(e)
> +INTEL_GEN(e) >= 11
> @gen11@ expression e; @@
> -IS_GEN(e, 11)
> +INTEL_GEN(e) >= 11
> 
> No functional change.
> 
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_perf.c         |  2 +-
>   drivers/gpu/drm/i915/intel_bios.c        |  4 ++--
>   drivers/gpu/drm/i915/intel_cdclk.c       |  6 +++---
>   drivers/gpu/drm/i915/intel_color.c       |  2 +-
>   drivers/gpu/drm/i915/intel_ddi.c         | 18 +++++++++---------
>   drivers/gpu/drm/i915/intel_device_info.c |  2 +-
>   drivers/gpu/drm/i915/intel_display.c     | 18 +++++++++---------
>   drivers/gpu/drm/i915/intel_dpll_mgr.c    |  2 +-
>   drivers/gpu/drm/i915/intel_dsi_vbt.c     |  6 +++---
>   drivers/gpu/drm/i915/intel_hdmi.c        |  4 ++--
>   drivers/gpu/drm/i915/intel_lrc.c         |  4 ++--
>   drivers/gpu/drm/i915/intel_mocs.c        |  2 +-
>   12 files changed, 35 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 72a9a35b40e2..c81feb43da90 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2881,7 +2881,7 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
>   
>   	sysfs_attr_init(&dev_priv->perf.oa.test_config.sysfs_metric_id.attr);
>   
> -	if (IS_ICELAKE(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 11) {
>   		i915_perf_load_test_config_icl(dev_priv);

Ping Lionel if this is OK?

>   	} else if (IS_CANNONLAKE(dev_priv)) {
>   		i915_perf_load_test_config_cnl(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index b508d8a735e0..48c62bea92cd 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -2093,8 +2093,8 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
>   		dvo_port = child->dvo_port;
>   
>   		if (dvo_port == DVO_PORT_MIPIA ||
> -		    (dvo_port == DVO_PORT_MIPIB && IS_ICELAKE(dev_priv)) ||
> -		    (dvo_port == DVO_PORT_MIPIC && !IS_ICELAKE(dev_priv))) {
> +		    (dvo_port == DVO_PORT_MIPIB && INTEL_GEN(dev_priv) >= 11) ||
> +		    (dvo_port == DVO_PORT_MIPIC && INTEL_GEN(dev_priv) < 11)) {
>   			if (port)
>   				*port = dvo_port - DVO_PORT_MIPIA;
>   			return true;
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 5d266538036d..7e5132772477 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2560,7 +2560,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>    */
>   void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
>   {
> -	if (IS_ICELAKE(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 11) {
>   		if (dev_priv->cdclk.hw.ref == 24000)
>   			dev_priv->max_cdclk_freq = 648000;
>   		else
> @@ -2744,7 +2744,7 @@ void intel_update_rawclk(struct drm_i915_private *dev_priv)
>    */
>   void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>   {
> -	if (IS_ICELAKE(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 11) {
>   		dev_priv->display.set_cdclk = icl_set_cdclk;
>   		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
>   	} else if (IS_CANNONLAKE(dev_priv)) {
> @@ -2773,7 +2773,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>   			vlv_modeset_calc_cdclk;
>   	}
>   
> -	if (IS_ICELAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 11)
>   		dev_priv->display.get_cdclk = icl_get_cdclk;
>   	else if (IS_CANNONLAKE(dev_priv))
>   		dev_priv->display.get_cdclk = cnl_get_cdclk;
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index da7a07d5ccea..0173967ed593 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -841,7 +841,7 @@ void intel_color_init(struct intel_crtc *crtc)
>   
>   		dev_priv->display.color_commit = i9xx_color_commit;
>   	} else {
> -		if (IS_ICELAKE(dev_priv))
> +		if (INTEL_GEN(dev_priv) >= 11)
>   			dev_priv->display.load_luts = icl_load_luts;
>   		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>   			dev_priv->display.load_luts = glk_load_luts;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index d918be927fc2..5b132082a650 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -851,7 +851,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>   
>   	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>   
> -	if (IS_ICELAKE(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 11) {
>   		if (intel_port_is_combophy(dev_priv, port))
>   			icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
>   						0, &n_entries);
> @@ -1678,7 +1678,7 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
>   {
>   	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   
> -	if (IS_ICELAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 11)
>   		icl_ddi_clock_get(encoder, pipe_config);
>   	else if (IS_CANNONLAKE(dev_priv))
>   		cnl_ddi_clock_get(encoder, pipe_config);
> @@ -2225,7 +2225,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>   	enum port port = encoder->port;
>   	int n_entries;
>   
> -	if (IS_ICELAKE(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 11) {
>   		if (intel_port_is_combophy(dev_priv, port))
>   			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
>   						intel_dp->link_rate, &n_entries);
> @@ -2698,7 +2698,7 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp)
>   	struct intel_encoder *encoder = &dport->base;
>   	int level = intel_ddi_dp_level(intel_dp);
>   
> -	if (IS_ICELAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 11)
>   		icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
>   					level, encoder->type);
>   	else if (IS_CANNONLAKE(dev_priv))
> @@ -2867,7 +2867,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>   
>   	mutex_lock(&dev_priv->dpll_lock);
>   
> -	if (IS_ICELAKE(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 11) {
>   		if (!intel_port_is_combophy(dev_priv, port))
>   			I915_WRITE(DDI_CLK_SEL(port),
>   				   icl_pll_to_ddi_clk_sel(encoder, crtc_state));
> @@ -2909,7 +2909,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
>   	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   	enum port port = encoder->port;
>   
> -	if (IS_ICELAKE(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 11) {
>   		if (!intel_port_is_combophy(dev_priv, port))
>   			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
>   	} else if (IS_CANNONLAKE(dev_priv)) {
> @@ -3126,7 +3126,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
>   	icl_program_mg_dp_mode(dig_port);
>   	icl_disable_phy_clock_gating(dig_port);
>   
> -	if (IS_ICELAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 11)
>   		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
>   					level, encoder->type);
>   	else if (IS_CANNONLAKE(dev_priv))
> @@ -3175,7 +3175,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
>   	icl_program_mg_dp_mode(dig_port);
>   	icl_disable_phy_clock_gating(dig_port);
>   
> -	if (IS_ICELAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 11)
>   		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
>   					level, INTEL_OUTPUT_HDMI);
>   	else if (IS_CANNONLAKE(dev_priv))
> @@ -3711,7 +3711,7 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
>   void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
>   					 struct intel_crtc_state *crtc_state)
>   {
> -	if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
> +	if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
>   		crtc_state->min_voltage_level = 1;
>   	else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
>   		crtc_state->min_voltage_level = 2;
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 855a5074ad77..e34259989ead 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -740,7 +740,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   
>   	BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t));
>   
> -	if (IS_GEN(dev_priv, 11))
> +	if (INTEL_GEN(dev_priv) >= 11)
>   		for_each_pipe(dev_priv, pipe)
>   			runtime->num_sprites[pipe] = 6;
>   	else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7c5e84ef5171..fdefdc33a0de 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5036,10 +5036,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>   	/* range checks */
>   	if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
>   	    dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
> -	    (IS_GEN(dev_priv, 11) &&
> +	    (INTEL_GEN(dev_priv) >= 11 &&
>   	     (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
>   	      dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
> -	    (!IS_GEN(dev_priv, 11) &&
> +	    (INTEL_GEN(dev_priv) < 11 &&
>   	     (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
>   	      dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H)))	{
>   		DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
> @@ -6131,7 +6131,7 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
>   	if (port == PORT_NONE)
>   		return false;
>   
> -	if (IS_ICELAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 11)
>   		return port <= PORT_B;
>   
>   	return false;
> @@ -6139,7 +6139,7 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
>   
>   bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
>   {
> -	if (IS_ICELAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 11)
>   		return port >= PORT_C && port <= PORT_F;
>   
>   	return false;
> @@ -9550,7 +9550,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>   		to_intel_atomic_state(crtc_state->base.state);
>   
>   	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
> -	    IS_ICELAKE(dev_priv)) {
> +	    INTEL_GEN(dev_priv) >= 11) {
>   		struct intel_encoder *encoder =
>   			intel_get_crtc_new_encoder(state, crtc_state);
>   
> @@ -9693,7 +9693,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
>   	enum transcoder panel_transcoder;
>   	u32 tmp;
>   
> -	if (IS_ICELAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 11)
>   		panel_transcoder_mask |=
>   			BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
>   
> @@ -9826,7 +9826,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>   
>   	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
>   
> -	if (IS_ICELAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 11)
>   		icelake_get_ddi_pll(dev_priv, port, pipe_config);
>   	else if (IS_CANNONLAKE(dev_priv))
>   		cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
> @@ -9889,7 +9889,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>   		goto out;
>   
>   	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> -	    IS_ICELAKE(dev_priv)) {
> +	    INTEL_GEN(dev_priv) >= 11) {
>   		haswell_get_ddi_port_state(crtc, pipe_config);
>   		intel_get_pipe_timings(crtc, pipe_config);
>   	}
> @@ -14635,7 +14635,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
>   	if (!HAS_DISPLAY(dev_priv))
>   		return;
>   
> -	if (IS_ICELAKE(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 11) {
>   		intel_ddi_init(dev_priv, PORT_A);
>   		intel_ddi_init(dev_priv, PORT_B);
>   		intel_ddi_init(dev_priv, PORT_C);
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index e4ec73d415d9..b3fb221c2532 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -3259,7 +3259,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
>   	const struct dpll_info *dpll_info;
>   	int i;
>   
> -	if (IS_ICELAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 11)
>   		dpll_mgr = &icl_pll_mgr;
>   	else if (IS_CANNONLAKE(dev_priv))
>   		dpll_mgr = &cnl_pll_mgr;
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index 06a11c35a784..d1e00e4c7726 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -194,7 +194,7 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
>   		break;
>   	}
>   
> -	if (!IS_ICELAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) < 11)
>   		vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
>   
>   out:
> @@ -365,7 +365,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>   	/* pull up/down */
>   	value = *data++ & 1;
>   
> -	if (IS_ICELAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 11)
>   		icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
>   	else if (IS_VALLEYVIEW(dev_priv))
>   		vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
> @@ -890,7 +890,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>   
>   	intel_dsi->burst_mode_ratio = burst_mode_ratio;
>   
> -	if (IS_ICELAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 11)
>   		icl_dphy_param_init(intel_dsi);
>   	else
>   		vlv_dphy_param_init(intel_dsi);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index cd422a7b4da0..5ccb305a6e1c 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -2206,7 +2206,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
>   
>   	/* Display Wa_1405510057:icl */
>   	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
> -	    bpc == 10 && IS_ICELAKE(dev_priv) &&
> +	    bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
>   	    (adjusted_mode->crtc_hblank_end -
>   	     adjusted_mode->crtc_hblank_start) % 8 == 2)
>   		return false;
> @@ -2500,7 +2500,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool force)
>   
>   	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
>   
> -	if (IS_ICELAKE(dev_priv) &&
> +	if (INTEL_GEN(dev_priv) >= 11 &&
>   	    !intel_digital_port_connected(encoder))
>   		goto out;
>   
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 578c8c98c718..fb599e11e7b9 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2525,7 +2525,7 @@ u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *req_sseu)
>   	} else {
>   		ctx_sseu = intel_device_default_sseu(i915);
>   
> -		if (IS_GEN(i915, 11)) {
> +		if (INTEL_GEN(i915) >= 11) {

This one needs to stay since it is handling a specific Icelake hw issue 
and media related configuration.

>   			/*
>   			 * We only need subslice count so it doesn't matter
>   			 * which ones we select - just turn off low bits in the
> @@ -2565,7 +2565,7 @@ u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *req_sseu)
>   	 * subslices are enabled, or a count between one and four on the first
>   	 * slice.
>   	 */
> -	if (IS_GEN(i915, 11) &&
> +	if (INTEL_GEN(i915) >= 11 &&

This one needs to stay as well for now.

>   	    slices == 1 &&
>   	    subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
>   		GEM_BUG_ON(subslices & 1);
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index 331e7a678fb7..79913b06f455 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -252,7 +252,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
>   {
>   	bool result = false;
>   
> -	if (IS_ICELAKE(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 11) {
>   		table->size  = ARRAY_SIZE(icelake_mocs_table);
>   		table->table = icelake_mocs_table;
>   		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
> 

Lucas should know if this is OK.

Regards,

Tvrtko


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff

[Lucas De Marchi]

On Mon, Mar 04, 2019 at 02:48:28PM -0800, Rodrigo Vivi wrote:
>This exactly same approach was already used from gen9
>to gen10 and from gen10 to gen11. Let's also use it
>for gen11+.
>
>Let's first assume that we inherit a similar platform
>and than we apply the differences on top.
>
>Different from the previous attempts this will be
>done this time with coccinelle. We obviously need to
>exclude some case that is really exclusive for gen11
>like  PCH, Firmware, and few others. Luckly this was
>easy to filter by selecting the files we are touching
>with coccinelle as exposed below:
>
>spatch -sp_file gen11\+.cocci --in-place i915_perf.c \
>       intel_bios.c intel_cdclk.c intel_ddi.c \
>       intel_device_info.c intel_display.c intel_dpll_mgr.c \
>       intel_dsi_vbt.c intel_hdmi.c intel_lrc.c intel_mocs.c intel_color.c
>
>@noticelake@ expression e; @@
>-!IS_ICELAKE(e)
>+INTEL_GEN(e) < 11
>@notgen11@ expression e; @@
>-!IS_GEN(e, 11)
>+INTEL_GEN(e) < 11
>@icelake@ expression e; @@
>-IS_ICELAKE(e)
>+INTEL_GEN(e) >= 11
>@gen11@ expression e; @@
>-IS_GEN(e, 11)
>+INTEL_GEN(e) >= 11
>
>No functional change.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/i915_perf.c         |  2 +-
> drivers/gpu/drm/i915/intel_bios.c        |  4 ++--
> drivers/gpu/drm/i915/intel_cdclk.c       |  6 +++---
> drivers/gpu/drm/i915/intel_color.c       |  2 +-
> drivers/gpu/drm/i915/intel_ddi.c         | 18 +++++++++---------
> drivers/gpu/drm/i915/intel_device_info.c |  2 +-
> drivers/gpu/drm/i915/intel_display.c     | 18 +++++++++---------
> drivers/gpu/drm/i915/intel_dpll_mgr.c    |  2 +-
> drivers/gpu/drm/i915/intel_dsi_vbt.c     |  6 +++---
> drivers/gpu/drm/i915/intel_hdmi.c        |  4 ++--
> drivers/gpu/drm/i915/intel_lrc.c         |  4 ++--
> drivers/gpu/drm/i915/intel_mocs.c        |  2 +-
> 12 files changed, 35 insertions(+), 35 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>index 72a9a35b40e2..c81feb43da90 100644
>--- a/drivers/gpu/drm/i915/i915_perf.c
>+++ b/drivers/gpu/drm/i915/i915_perf.c
>@@ -2881,7 +2881,7 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
>
> 	sysfs_attr_init(&dev_priv->perf.oa.test_config.sysfs_metric_id.attr);
>
>-	if (IS_ICELAKE(dev_priv)) {
>+	if (INTEL_GEN(dev_priv) >= 11) {
> 		i915_perf_load_test_config_icl(dev_priv);
> 	} else if (IS_CANNONLAKE(dev_priv)) {
> 		i915_perf_load_test_config_cnl(dev_priv);
>diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>index b508d8a735e0..48c62bea92cd 100644
>--- a/drivers/gpu/drm/i915/intel_bios.c
>+++ b/drivers/gpu/drm/i915/intel_bios.c
>@@ -2093,8 +2093,8 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
> 		dvo_port = child->dvo_port;
>
> 		if (dvo_port == DVO_PORT_MIPIA ||
>-		    (dvo_port == DVO_PORT_MIPIB && IS_ICELAKE(dev_priv)) ||
>-		    (dvo_port == DVO_PORT_MIPIC && !IS_ICELAKE(dev_priv))) {
>+		    (dvo_port == DVO_PORT_MIPIB && INTEL_GEN(dev_priv) >= 11) ||
>+		    (dvo_port == DVO_PORT_MIPIC && INTEL_GEN(dev_priv) < 11)) {
> 			if (port)
> 				*port = dvo_port - DVO_PORT_MIPIA;
> 			return true;
>diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
>index 5d266538036d..7e5132772477 100644
>--- a/drivers/gpu/drm/i915/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/intel_cdclk.c
>@@ -2560,7 +2560,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>  */
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> {
>-	if (IS_ICELAKE(dev_priv)) {
>+	if (INTEL_GEN(dev_priv) >= 11) {
> 		if (dev_priv->cdclk.hw.ref == 24000)
> 			dev_priv->max_cdclk_freq = 648000;
> 		else
>@@ -2744,7 +2744,7 @@ void intel_update_rawclk(struct drm_i915_private *dev_priv)
>  */
> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> {
>-	if (IS_ICELAKE(dev_priv)) {
>+	if (INTEL_GEN(dev_priv) >= 11) {
> 		dev_priv->display.set_cdclk = icl_set_cdclk;
> 		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
> 	} else if (IS_CANNONLAKE(dev_priv)) {
>@@ -2773,7 +2773,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> 			vlv_modeset_calc_cdclk;
> 	}
>
>-	if (IS_ICELAKE(dev_priv))
>+	if (INTEL_GEN(dev_priv) >= 11)
> 		dev_priv->display.get_cdclk = icl_get_cdclk;
> 	else if (IS_CANNONLAKE(dev_priv))
> 		dev_priv->display.get_cdclk = cnl_get_cdclk;
>diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
>index da7a07d5ccea..0173967ed593 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -841,7 +841,7 @@ void intel_color_init(struct intel_crtc *crtc)
>
> 		dev_priv->display.color_commit = i9xx_color_commit;
> 	} else {
>-		if (IS_ICELAKE(dev_priv))
>+		if (INTEL_GEN(dev_priv) >= 11)
> 			dev_priv->display.load_luts = icl_load_luts;
> 		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> 			dev_priv->display.load_luts = glk_load_luts;
>diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>index d918be927fc2..5b132082a650 100644
>--- a/drivers/gpu/drm/i915/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/intel_ddi.c
>@@ -851,7 +851,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>
> 	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>
>-	if (IS_ICELAKE(dev_priv)) {
>+	if (INTEL_GEN(dev_priv) >= 11) {
> 		if (intel_port_is_combophy(dev_priv, port))
> 			icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
> 						0, &n_entries);
>@@ -1678,7 +1678,7 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
>-	if (IS_ICELAKE(dev_priv))
>+	if (INTEL_GEN(dev_priv) >= 11)
> 		icl_ddi_clock_get(encoder, pipe_config);
> 	else if (IS_CANNONLAKE(dev_priv))
> 		cnl_ddi_clock_get(encoder, pipe_config);
>@@ -2225,7 +2225,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
> 	enum port port = encoder->port;
> 	int n_entries;
>
>-	if (IS_ICELAKE(dev_priv)) {
>+	if (INTEL_GEN(dev_priv) >= 11) {
> 		if (intel_port_is_combophy(dev_priv, port))
> 			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
> 						intel_dp->link_rate, &n_entries);
>@@ -2698,7 +2698,7 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp)
> 	struct intel_encoder *encoder = &dport->base;
> 	int level = intel_ddi_dp_level(intel_dp);
>
>-	if (IS_ICELAKE(dev_priv))
>+	if (INTEL_GEN(dev_priv) >= 11)
> 		icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
> 					level, encoder->type);
> 	else if (IS_CANNONLAKE(dev_priv))
>@@ -2867,7 +2867,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>
> 	mutex_lock(&dev_priv->dpll_lock);
>
>-	if (IS_ICELAKE(dev_priv)) {
>+	if (INTEL_GEN(dev_priv) >= 11) {
> 		if (!intel_port_is_combophy(dev_priv, port))
> 			I915_WRITE(DDI_CLK_SEL(port),
> 				   icl_pll_to_ddi_clk_sel(encoder, crtc_state));
>@@ -2909,7 +2909,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	enum port port = encoder->port;
>
>-	if (IS_ICELAKE(dev_priv)) {
>+	if (INTEL_GEN(dev_priv) >= 11) {
> 		if (!intel_port_is_combophy(dev_priv, port))
> 			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
> 	} else if (IS_CANNONLAKE(dev_priv)) {
>@@ -3126,7 +3126,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> 	icl_program_mg_dp_mode(dig_port);
> 	icl_disable_phy_clock_gating(dig_port);
>
>-	if (IS_ICELAKE(dev_priv))
>+	if (INTEL_GEN(dev_priv) >= 11)
> 		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
> 					level, encoder->type);
> 	else if (IS_CANNONLAKE(dev_priv))
>@@ -3175,7 +3175,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> 	icl_program_mg_dp_mode(dig_port);
> 	icl_disable_phy_clock_gating(dig_port);
>
>-	if (IS_ICELAKE(dev_priv))
>+	if (INTEL_GEN(dev_priv) >= 11)
> 		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
> 					level, INTEL_OUTPUT_HDMI);
> 	else if (IS_CANNONLAKE(dev_priv))
>@@ -3711,7 +3711,7 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
> void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
> 					 struct intel_crtc_state *crtc_state)
> {
>-	if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
>+	if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
> 		crtc_state->min_voltage_level = 1;
> 	else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
> 		crtc_state->min_voltage_level = 2;
>diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>index 855a5074ad77..e34259989ead 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.c
>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>@@ -740,7 +740,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>
> 	BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t));
>
>-	if (IS_GEN(dev_priv, 11))
>+	if (INTEL_GEN(dev_priv) >= 11)
> 		for_each_pipe(dev_priv, pipe)
> 			runtime->num_sprites[pipe] = 6;
> 	else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 7c5e84ef5171..fdefdc33a0de 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -5036,10 +5036,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> 	/* range checks */
> 	if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
> 	    dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
>-	    (IS_GEN(dev_priv, 11) &&
>+	    (INTEL_GEN(dev_priv) >= 11 &&
> 	     (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
> 	      dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
>-	    (!IS_GEN(dev_priv, 11) &&
>+	    (INTEL_GEN(dev_priv) < 11 &&
> 	     (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
> 	      dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H)))	{
> 		DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
>@@ -6131,7 +6131,7 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
> 	if (port == PORT_NONE)
> 		return false;
>
>-	if (IS_ICELAKE(dev_priv))
>+	if (INTEL_GEN(dev_priv) >= 11)
> 		return port <= PORT_B;
>
> 	return false;
>@@ -6139,7 +6139,7 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
>
> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
> {
>-	if (IS_ICELAKE(dev_priv))
>+	if (INTEL_GEN(dev_priv) >= 11)
> 		return port >= PORT_C && port <= PORT_F;
>
> 	return false;
>@@ -9550,7 +9550,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> 		to_intel_atomic_state(crtc_state->base.state);
>
> 	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
>-	    IS_ICELAKE(dev_priv)) {
>+	    INTEL_GEN(dev_priv) >= 11) {
> 		struct intel_encoder *encoder =
> 			intel_get_crtc_new_encoder(state, crtc_state);
>
>@@ -9693,7 +9693,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
> 	enum transcoder panel_transcoder;
> 	u32 tmp;
>
>-	if (IS_ICELAKE(dev_priv))
>+	if (INTEL_GEN(dev_priv) >= 11)
> 		panel_transcoder_mask |=
> 			BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
>
>@@ -9826,7 +9826,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>
> 	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
>
>-	if (IS_ICELAKE(dev_priv))
>+	if (INTEL_GEN(dev_priv) >= 11)
> 		icelake_get_ddi_pll(dev_priv, port, pipe_config);
> 	else if (IS_CANNONLAKE(dev_priv))
> 		cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
>@@ -9889,7 +9889,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> 		goto out;
>
> 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
>-	    IS_ICELAKE(dev_priv)) {
>+	    INTEL_GEN(dev_priv) >= 11) {
> 		haswell_get_ddi_port_state(crtc, pipe_config);
> 		intel_get_pipe_timings(crtc, pipe_config);
> 	}
>@@ -14635,7 +14635,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> 	if (!HAS_DISPLAY(dev_priv))
> 		return;
>
>-	if (IS_ICELAKE(dev_priv)) {
>+	if (INTEL_GEN(dev_priv) >= 11) {
> 		intel_ddi_init(dev_priv, PORT_A);
> 		intel_ddi_init(dev_priv, PORT_B);
> 		intel_ddi_init(dev_priv, PORT_C);
>diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>index e4ec73d415d9..b3fb221c2532 100644
>--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>@@ -3259,7 +3259,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
> 	const struct dpll_info *dpll_info;
> 	int i;
>
>-	if (IS_ICELAKE(dev_priv))
>+	if (INTEL_GEN(dev_priv) >= 11)
> 		dpll_mgr = &icl_pll_mgr;
> 	else if (IS_CANNONLAKE(dev_priv))
> 		dpll_mgr = &cnl_pll_mgr;
>diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>index 06a11c35a784..d1e00e4c7726 100644
>--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>@@ -194,7 +194,7 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
> 		break;
> 	}
>
>-	if (!IS_ICELAKE(dev_priv))
>+	if (INTEL_GEN(dev_priv) < 11)
> 		vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
>
> out:
>@@ -365,7 +365,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> 	/* pull up/down */
> 	value = *data++ & 1;
>
>-	if (IS_ICELAKE(dev_priv))
>+	if (INTEL_GEN(dev_priv) >= 11)
> 		icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
> 	else if (IS_VALLEYVIEW(dev_priv))
> 		vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
>@@ -890,7 +890,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>
> 	intel_dsi->burst_mode_ratio = burst_mode_ratio;
>
>-	if (IS_ICELAKE(dev_priv))
>+	if (INTEL_GEN(dev_priv) >= 11)
> 		icl_dphy_param_init(intel_dsi);
> 	else
> 		vlv_dphy_param_init(intel_dsi);
>diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
>index cd422a7b4da0..5ccb305a6e1c 100644
>--- a/drivers/gpu/drm/i915/intel_hdmi.c
>+++ b/drivers/gpu/drm/i915/intel_hdmi.c
>@@ -2206,7 +2206,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
>
> 	/* Display Wa_1405510057:icl */
> 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
>-	    bpc == 10 && IS_ICELAKE(dev_priv) &&
>+	    bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
> 	    (adjusted_mode->crtc_hblank_end -
> 	     adjusted_mode->crtc_hblank_start) % 8 == 2)
> 		return false;
>@@ -2500,7 +2500,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool force)
>
> 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
>
>-	if (IS_ICELAKE(dev_priv) &&
>+	if (INTEL_GEN(dev_priv) >= 11 &&
> 	    !intel_digital_port_connected(encoder))
> 		goto out;
>
>diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>index 578c8c98c718..fb599e11e7b9 100644
>--- a/drivers/gpu/drm/i915/intel_lrc.c
>+++ b/drivers/gpu/drm/i915/intel_lrc.c
>@@ -2525,7 +2525,7 @@ u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *req_sseu)
> 	} else {
> 		ctx_sseu = intel_device_default_sseu(i915);
>
>-		if (IS_GEN(i915, 11)) {
>+		if (INTEL_GEN(i915) >= 11) {
> 			/*
> 			 * We only need subslice count so it doesn't matter
> 			 * which ones we select - just turn off low bits in the
>@@ -2565,7 +2565,7 @@ u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *req_sseu)
> 	 * subslices are enabled, or a count between one and four on the first
> 	 * slice.
> 	 */
>-	if (IS_GEN(i915, 11) &&
>+	if (INTEL_GEN(i915) >= 11 &&
> 	    slices == 1 &&
> 	    subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
> 		GEM_BUG_ON(subslices & 1);
>diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
>index 331e7a678fb7..79913b06f455 100644
>--- a/drivers/gpu/drm/i915/intel_mocs.c
>+++ b/drivers/gpu/drm/i915/intel_mocs.c
>@@ -252,7 +252,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
> {
> 	bool result = false;
>
>-	if (IS_ICELAKE(dev_priv)) {
>+	if (INTEL_GEN(dev_priv) >= 11) {
> 		table->size  = ARRAY_SIZE(icelake_mocs_table);
> 		table->table = icelake_mocs_table;
> 		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
>-- 
>2.20.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff

[Rodrigo Vivi]

This exactly same approach was already used from gen9
to gen10 and from gen10 to gen11. Let's also use it
for gen11+.

Let's first assume that we inherit a similar platform
and than we apply the differences on top.

Different from the previous attempts this will be
done this time with coccinelle. We obviously need to
exclude some case that is really exclusive for gen11
like  PCH, Firmware, and few others. Luckly this was
easy to filter by selecting the files we are touching
with coccinelle as exposed below:

spatch -sp_file gen11\+.cocci --in-place i915_perf.c \
       intel_bios.c intel_cdclk.c intel_ddi.c \
       intel_device_info.c intel_display.c intel_dpll_mgr.c \
       intel_dsi_vbt.c intel_hdmi.c intel_lrc.c intel_mocs.c intel_color.c

@noticelake@ expression e; @@
-!IS_ICELAKE(e)
+INTEL_GEN(e) < 11
@notgen11@ expression e; @@
-!IS_GEN(e, 11)
+INTEL_GEN(e) < 11
@icelake@ expression e; @@
-IS_ICELAKE(e)
+INTEL_GEN(e) >= 11
@gen11@ expression e; @@
-IS_GEN(e, 11)
+INTEL_GEN(e) >= 11

No functional change.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c         |  2 +-
 drivers/gpu/drm/i915/intel_bios.c        |  4 ++--
 drivers/gpu/drm/i915/intel_cdclk.c       |  6 +++---
 drivers/gpu/drm/i915/intel_color.c       |  2 +-
 drivers/gpu/drm/i915/intel_ddi.c         | 18 +++++++++---------
 drivers/gpu/drm/i915/intel_device_info.c |  2 +-
 drivers/gpu/drm/i915/intel_display.c     | 18 +++++++++---------
 drivers/gpu/drm/i915/intel_dpll_mgr.c    |  2 +-
 drivers/gpu/drm/i915/intel_dsi_vbt.c     |  6 +++---
 drivers/gpu/drm/i915/intel_hdmi.c        |  4 ++--
 drivers/gpu/drm/i915/intel_lrc.c         |  4 ++--
 drivers/gpu/drm/i915/intel_mocs.c        |  2 +-
 12 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 72a9a35b40e2..c81feb43da90 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2881,7 +2881,7 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
 
 	sysfs_attr_init(&dev_priv->perf.oa.test_config.sysfs_metric_id.attr);
 
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		i915_perf_load_test_config_icl(dev_priv);
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		i915_perf_load_test_config_cnl(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index b508d8a735e0..48c62bea92cd 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -2093,8 +2093,8 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
 		dvo_port = child->dvo_port;
 
 		if (dvo_port == DVO_PORT_MIPIA ||
-		    (dvo_port == DVO_PORT_MIPIB && IS_ICELAKE(dev_priv)) ||
-		    (dvo_port == DVO_PORT_MIPIC && !IS_ICELAKE(dev_priv))) {
+		    (dvo_port == DVO_PORT_MIPIB && INTEL_GEN(dev_priv) >= 11) ||
+		    (dvo_port == DVO_PORT_MIPIC && INTEL_GEN(dev_priv) < 11)) {
 			if (port)
 				*port = dvo_port - DVO_PORT_MIPIA;
 			return true;
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 5d266538036d..7e5132772477 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2560,7 +2560,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 {
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		if (dev_priv->cdclk.hw.ref == 24000)
 			dev_priv->max_cdclk_freq = 648000;
 		else
@@ -2744,7 +2744,7 @@ void intel_update_rawclk(struct drm_i915_private *dev_priv)
  */
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		dev_priv->display.set_cdclk = icl_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
 	} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2773,7 +2773,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 			vlv_modeset_calc_cdclk;
 	}
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		dev_priv->display.get_cdclk = icl_get_cdclk;
 	else if (IS_CANNONLAKE(dev_priv))
 		dev_priv->display.get_cdclk = cnl_get_cdclk;
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index da7a07d5ccea..0173967ed593 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -841,7 +841,7 @@ void intel_color_init(struct intel_crtc *crtc)
 
 		dev_priv->display.color_commit = i9xx_color_commit;
 	} else {
-		if (IS_ICELAKE(dev_priv))
+		if (INTEL_GEN(dev_priv) >= 11)
 			dev_priv->display.load_luts = icl_load_luts;
 		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
 			dev_priv->display.load_luts = glk_load_luts;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index d918be927fc2..5b132082a650 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -851,7 +851,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
 
 	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		if (intel_port_is_combophy(dev_priv, port))
 			icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
 						0, &n_entries);
@@ -1678,7 +1678,7 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		icl_ddi_clock_get(encoder, pipe_config);
 	else if (IS_CANNONLAKE(dev_priv))
 		cnl_ddi_clock_get(encoder, pipe_config);
@@ -2225,7 +2225,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 	enum port port = encoder->port;
 	int n_entries;
 
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		if (intel_port_is_combophy(dev_priv, port))
 			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
 						intel_dp->link_rate, &n_entries);
@@ -2698,7 +2698,7 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp)
 	struct intel_encoder *encoder = &dport->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
 					level, encoder->type);
 	else if (IS_CANNONLAKE(dev_priv))
@@ -2867,7 +2867,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 
 	mutex_lock(&dev_priv->dpll_lock);
 
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		if (!intel_port_is_combophy(dev_priv, port))
 			I915_WRITE(DDI_CLK_SEL(port),
 				   icl_pll_to_ddi_clk_sel(encoder, crtc_state));
@@ -2909,7 +2909,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		if (!intel_port_is_combophy(dev_priv, port))
 			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
 	} else if (IS_CANNONLAKE(dev_priv)) {
@@ -3126,7 +3126,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	icl_program_mg_dp_mode(dig_port);
 	icl_disable_phy_clock_gating(dig_port);
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
 					level, encoder->type);
 	else if (IS_CANNONLAKE(dev_priv))
@@ -3175,7 +3175,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
 	icl_program_mg_dp_mode(dig_port);
 	icl_disable_phy_clock_gating(dig_port);
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
 					level, INTEL_OUTPUT_HDMI);
 	else if (IS_CANNONLAKE(dev_priv))
@@ -3711,7 +3711,7 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
 					 struct intel_crtc_state *crtc_state)
 {
-	if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
+	if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 1;
 	else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 2;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 855a5074ad77..e34259989ead 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -740,7 +740,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t));
 
-	if (IS_GEN(dev_priv, 11))
+	if (INTEL_GEN(dev_priv) >= 11)
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_sprites[pipe] = 6;
 	else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7c5e84ef5171..fdefdc33a0de 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5036,10 +5036,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 	/* range checks */
 	if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
 	    dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
-	    (IS_GEN(dev_priv, 11) &&
+	    (INTEL_GEN(dev_priv) >= 11 &&
 	     (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
 	      dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
-	    (!IS_GEN(dev_priv, 11) &&
+	    (INTEL_GEN(dev_priv) < 11 &&
 	     (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
 	      dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H)))	{
 		DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
@@ -6131,7 +6131,7 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
 	if (port == PORT_NONE)
 		return false;
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		return port <= PORT_B;
 
 	return false;
@@ -6139,7 +6139,7 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
 
 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
 {
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		return port >= PORT_C && port <= PORT_F;
 
 	return false;
@@ -9550,7 +9550,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
 		to_intel_atomic_state(crtc_state->base.state);
 
 	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
-	    IS_ICELAKE(dev_priv)) {
+	    INTEL_GEN(dev_priv) >= 11) {
 		struct intel_encoder *encoder =
 			intel_get_crtc_new_encoder(state, crtc_state);
 
@@ -9693,7 +9693,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
 	enum transcoder panel_transcoder;
 	u32 tmp;
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		panel_transcoder_mask |=
 			BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
 
@@ -9826,7 +9826,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
 
 	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		icelake_get_ddi_pll(dev_priv, port, pipe_config);
 	else if (IS_CANNONLAKE(dev_priv))
 		cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
@@ -9889,7 +9889,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 		goto out;
 
 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
-	    IS_ICELAKE(dev_priv)) {
+	    INTEL_GEN(dev_priv) >= 11) {
 		haswell_get_ddi_port_state(crtc, pipe_config);
 		intel_get_pipe_timings(crtc, pipe_config);
 	}
@@ -14635,7 +14635,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv))
 		return;
 
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index e4ec73d415d9..b3fb221c2532 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -3259,7 +3259,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
 	const struct dpll_info *dpll_info;
 	int i;
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		dpll_mgr = &icl_pll_mgr;
 	else if (IS_CANNONLAKE(dev_priv))
 		dpll_mgr = &cnl_pll_mgr;
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 06a11c35a784..d1e00e4c7726 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -194,7 +194,7 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
 		break;
 	}
 
-	if (!IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) < 11)
 		vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
 
 out:
@@ -365,7 +365,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	/* pull up/down */
 	value = *data++ & 1;
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
 	else if (IS_VALLEYVIEW(dev_priv))
 		vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
@@ -890,7 +890,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 
 	intel_dsi->burst_mode_ratio = burst_mode_ratio;
 
-	if (IS_ICELAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 11)
 		icl_dphy_param_init(intel_dsi);
 	else
 		vlv_dphy_param_init(intel_dsi);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index cd422a7b4da0..5ccb305a6e1c 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2206,7 +2206,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
 
 	/* Display Wa_1405510057:icl */
 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
-	    bpc == 10 && IS_ICELAKE(dev_priv) &&
+	    bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
 	    (adjusted_mode->crtc_hblank_end -
 	     adjusted_mode->crtc_hblank_start) % 8 == 2)
 		return false;
@@ -2500,7 +2500,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool force)
 
 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
 
-	if (IS_ICELAKE(dev_priv) &&
+	if (INTEL_GEN(dev_priv) >= 11 &&
 	    !intel_digital_port_connected(encoder))
 		goto out;
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 578c8c98c718..fb599e11e7b9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2525,7 +2525,7 @@ u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *req_sseu)
 	} else {
 		ctx_sseu = intel_device_default_sseu(i915);
 
-		if (IS_GEN(i915, 11)) {
+		if (INTEL_GEN(i915) >= 11) {
 			/*
 			 * We only need subslice count so it doesn't matter
 			 * which ones we select - just turn off low bits in the
@@ -2565,7 +2565,7 @@ u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *req_sseu)
 	 * subslices are enabled, or a count between one and four on the first
 	 * slice.
 	 */
-	if (IS_GEN(i915, 11) &&
+	if (INTEL_GEN(i915) >= 11 &&
 	    slices == 1 &&
 	    subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
 		GEM_BUG_ON(subslices & 1);
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 331e7a678fb7..79913b06f455 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -252,7 +252,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 {
 	bool result = false;
 
-	if (IS_ICELAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
 		table->size  = ARRAY_SIZE(icelake_mocs_table);
 		table->table = icelake_mocs_table;
 		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
-- 
2.20.1

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